Embedded Systems Design, Spring 2023
Lecture 3
Sequential Logic: Latches and flip-flops
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Review from last time
§ ?
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Bistability
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Flip flops (latches)
§ 1918 – Eccles - Jordan triggered circuit
§ Latches can change their state at any time
§ Flip-flops can change their state only when a clocking signal is
changing
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Clock types
§ Clock types
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S-R latch
§ S-R latch:
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Typical operation
§ Metastable region: when the output is unpredictable
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§ Propagation delay: time need for an input signal change to generate an output
signal change
§ Recovery time: giving the minimum separation between S and R as to be not
simultaneous
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S-R latches
§ S’ and R’ are active low, therefore opposite operation
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S-R latch with enable
§ Why? To control when the inputs are active
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Typical operation
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D-latches
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Timing parameters
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Edge triggered D Flip Flop
§ Clk: dynamic input indicator – edge triggered behavior
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Shift registers
§ They produce a discrete delay for a specific digital signal. The
delay is given by “n” stages.
§ Conveyor belt similarity
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Shift registers
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Serial – in, parallel - out
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Parallel - in, serial - out
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Parallel - in, serial - out
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Parallel – in, parallel - out
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Example: 74x194, 4 bit shift register
Example:
S1:0
S0:1
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§ Example
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