Informática

Ing. Aeroespacial

Computers

C4: Computer organization (i):

Functional units of the computer

DISCA: Departamento de Informática de Sistemas y Computadores

Rev. 06
Introduction Informática

Do you know that a computer can be seen as a “Universal

Machine”?
but… what is a “Universal Machine”?
How can a computer execute any algorithm?
How can a computer “understand” any language program?

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Computer organization Informática

Introduction
Computer architecture
Memory organization
CPU organization

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Introduction Informática

Computers
A computer is a device that performs processes, calculations and operations
based on instructions provided by a software or hardware program. It is
designed to execute applications and provides a variety of solutions by
combining integrated hardware and software components.
- History of computers à see https://en.wikipedia.org/wiki/Computer
All modern computers are based on digital systems (0/1)
and the idea of “programmed logic”

Program
Machine
Data
(hardware)
(software)

Programmable machine

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Introduction Informática

Real computer
A computer is a machine designed to execute machine language
instructions

01001000
00110101
10010101
01111010
00101110

It is a sequence of 0’s and 1’s equivalent to simple tasks CrtCopyWin:

JC @@4
@@1: LODSW
Well, there is a “human readable” notation @@2:
MOV
IN
BX,AX
AL,DX
TEST AL,1
JNE @@2
CLI
@@3: IN AL,DX
TEST AL,1
RET
@@4: REP MOVSW
RET
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Computer organization Informática

Introduction
Computer architecture
Memory organization
CPU organization

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Computer architecture Informática

Functional units of a computer

Peripherals

Disk Video
Main Controller Controller
CPU Memory
I/O I/O

Bus

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Computer architecture Informática

Functional units of a computer

CPU (Central Processing Unit): responsible for executing programs: it
recognizes instructions in machine language and performs the proper
actions The CPU coordinates the rest of the computer subsystems.
Main Memory. It stores the programs in execution. Programs need to be
loaded from disks (secondary memory) into main memory before they can
be executed.
IO (Input/Output) Subsystem. responsible for the interaction of the
computer with the outer world. It includes peripherals and communication
links.

Bus
set of electrical lines for the interconnection of all the functional units of a
computer
there are single bus and multiple bus architectures

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Computer architecture Informática

Single bus / multiple bus architecture.

Single bus Multiple bus

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Computer architecture Informática

PC Motherboard

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Computer organization Informática

Introduction
Computer architecture
Memory organization
CPU organization

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Memory organization Informática

Memory
Memory: abstract device for storing information with two main operations:
- Write: storing, updating some information on the memory.
- Read: retrieving some previously stored information on the memory.
Memory property: a read operation always returns the value of the last write
operation.
Levels of storage
- Main memory: short-term memory. It stores the program(s) that the CPU is
currently executing and their associated data. In general, it is a volatile
memory: it loses its contents upon disconnection from the power supply.
- Secondary memory: includes disks, tapes, pen-drives, CD’s, and others. It
is a long-term storage for the programs and data that the computer may use.
It is a non-volatile memory.

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Memory organization Informática

Main memory organization

Organization: array of cells. A cell stores one bit.
Memory word: each row of the memory array. It has associated:
- Address: the row number or location of a word inside a memory.
- Value: is the memory contents
Example (16 byte memory)

Value at memory address F16 is B616 13

Memory organization Informática

Memory capacity
Volume of information it can store. Usually measured in bytes, KB, MB, GB, TB.
- It is the number of rows (memory words) x number of bytes per row.
‣ Example: 6 MB memory → 6 × 220 bytes ⋍ 6 million bytes.

Memory access modes

Main memory is Random-Access Memory or RAM
- Random access: any (random) memory word can be directly accessed by
providing its address.
- Sequential access: it is the access method of a tape. Accessing a given word
requires acessing all previous words.
Signals:
- Address lines: input lines to provide the address of the required word.
- Data lines: bidirectional lines to get/provide the value of a word.
- RD/WR: input lines to specify the operation RD (read) WR (write).
- CS: Chip Select. It enables the memory. If CS=0 its is isolated from the bus.
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Memory organization Informática

Memory accesses
Read: The CPU provides Address, RD/WR=1, CS=1 and waits to get Data
Write: The CPU provides Address, Data, RD/WR=0, CS=1

Read operation Write operation

Bus Bus
Address Address
RD/WR 1 RD/WR 0
16 byte 16 byte
CS CS
CPU 1 RAM CPU 1 RAM
Memory Memory

Data Data

Address: A3-A0 Address: A3-A0

Data: D7-D0 Data: D7-D0

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Memory organization Informática

Main memory Secondary memory

Volatile Non-volatile
Random access Sequential access (files)
Usual capacity: some GB Usual capacity: some TB
Speed: 1.000 times faster Speed: 1.000 times slower than
than secondary memory. main memory

Access times
- SRAM: 10 ns
- DRAM: 50-150 ns.

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Memory organization Informática

Memory hierarchy
Levels:
- Processor registers - internal to capacity speed
the processor. - +
- Cache memory - internal to the CPU
processor. regs.
- Main memory - stores programs cache
in execution and their associated memory
data.
main
- Virtual memory - simulates a memory
larger memory.
virtual
- Secondary memory - Disks and memory
similar devices.
Capacity increases top-down secondary
memory
while access speed increases + -
bottom-up.

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Computer organization Informática

Introduction
Computer architecture
Memory organization
CPU organization

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CPU organization Informática

CPU main features

The CPU (Central Processing Unit) is a computer functional unit that executes machine
language instructions
- Machine language instructions are processor specific, i.e., the Intel Pentium has a
different instruction set to the ARM Cortex.
- High level language (Matlab, C, C++,...) statements need to be transformed into
machine instructions for their execution
Processor word: number of bits of processor “native” data. An n-bit processor can
perform operations (additions, subtractions) using n-bit arithmetic
- It gives an idea of the processor power.
- A 16-bit processor has instructions to perform 16-bit additions natively, but it can also
perform 32-bit additions using a program (not natively) that decomposes 32-bit
additions into several 16-bit additions. This is much slower...
Addressing capacity: number of bits required to address the largest memory that it
supports.
- It determines important aspects, like the longest program that it can execute.
Instruction set: set of machine language instructions. Every processor architecture is
defined by its instruction set. (CISC/RISC next year)

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CPU organization Informática

CPU subsystems
Register bank: a very fast low capacity memory to keep the operands of
machine language instructions.
Arithmetic Logic Unit (ALU): is a combinational circuit that performs
arithmetic (like addition, subtraction, increment, ...) and logic operations
(AND, OR, NOT, ...).
Control Unit (CU): it fetches instructions in memory, decodes (identifies)
them and coordinates the rest of CPU subsystems to execute them.

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CPU organization Informática

A sample CPU: the SEP16

16-bit Simple Educational Processor
- There exists a simulator program
for this processor in Poliformat
Processor word: 16 bits
- 16-bit registers
- 16-bit arithmetic
Addressing capacity: 64 K x 16-bit
memory words = 128 KB
- 16-bit memory addresses
- Address space range: [0x0000, ...,
0xFFFF]
Register bank: 16 16-bit registers.
- R0, R1, ..., R15

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CPU organization Informática

The SEP16 ALU and register bank

Example of machine language instruction:

Register bank
1011011011101101
0x0001 R0
R1 Equivalent mnemonic

R2
0xFFFF ADD R2,R0
...
Description:
R14
R15/SP R2 ← R2 + R0

0xFFFF 0x0001 ALU inputs

temporary
ALU outputs
registers
opcode
ALU flags
V N Z C
...
0x0000 PSR: Processor Status Register
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CPU organization Informática

Example of machine language instructions (i)

ADD R2,R0 : Add the contents of register R0 to register R2 and store the
result in register R2 (R2← R2 +R0). Affect all the flags conveniently.
- Assuming R2=0xFFFF and R0=0x0001, the addition yields 0x0000 which is
transferred to R2.
- Temporal registers are used to avoid merging in R2 the initial and final value.
- The addition produces a register overflow: a carry from bit 15 to bit 16 (non-
existent).
‣ The ALU writes down overflows in a flag of a special register called the PSR.

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CPU organization Informática

Processor Status Register (PSR)

It contains a set of bits, called flags, where each bits
detects a special condition occurred when the ALU
performs an operation:
- N (Negative or less than): set when the result of an
arithmetical operation is a negative number
considering it as a 2’s complement signed number.
‣ It matches the value of bit 15 of the ALU.
- Z (Zero or equal to): set when the result of an
operation is zero.
- C (Carry or borrow or extend): set when the result
of an arithmetical operation or a shift operation
cannot be represented in 16 bits.
‣ It is set to the carry out of bit 15 of the ALU. As
a kind of bit 16 of the result.
- V (oVerflow): This may be ignored if the operands
were considered unsigned, but warns of a possible
error if the operands were 2’s complement signed.
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CPU organization Informática

The SEP16 CU (Control Unit) Main memory

Code
CPU Register bank
0x1200 ADD R2,R0
0x0001 R0
R1 0x1201 JNE 0x2000
0x0001
R2 ...
0xFFFF 0x2000 MOV R0,R1
...
...
R14
0x7FFD R15/SP
Data
0x4000 0xA7B1
0xFFFF 0x0001 0x7A7A
PSR ...
flags opcode
ALU

0x0000 Stack
0x7FFD

Control IR ADD R2,R0 0x8000

Unit (CU) PC 0x1201
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CPU organization Informática

The SEP16 CU (Control Unit)

Responsible for fetching machine language instructions from main memory,
decoding them, i.e. identifying each instruction, and giving the proper
orders to all CPU subsystems in order to execute them.
Two important registers related to instruction execution:
- Instruction Register (IR): It contains the instruction which the CPU is
currently executing.
‣ In this case, it contains the code of instruction ADD R2,R0.
‣ It has to be able to contain the longest memory instruction → 32 bits
- Program counter (PC) It points to the instruction in memory that will be
executed next.
‣ Before executing ADD R2,R0, the PC was pointing to memory location 0x1200.
Once it has been loaded into the IR register, it points to next instruction (JNE
0x2000), stored in location 0x1201.
‣ It has to be able to address the longest program → 16 bits

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CPU organization Informática

Executing machine language instructions

The CU performs the following actions:
It fetches the instruction from the memory location
where the PC points to, and moves it to the IR.
It sets the PC to point to the next instruction.
Normally it adds 1, but in some instructions it
can be 2.
It decodes the instruction, thus identifying it as an
“ADD” instruction with two operands stored in
registers R2 and R0.
It executes the instruction:
- It instructs R2 and R0 registers to output their
contents to the temporary input registers of the ALU.
- It orders the ALU to perform an addition and waits
until the ALU provides the result at the temporary
register at its output and sets the flags conveniently.
- It moves the ALU output to register R2.

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CPU organization Informática

Example of machine language instructions (ii)

Some instructions for control of flow cause the PC not to execute the next
instruction
JNE 0x2000 : Jump Not Equal to memory address 0x2000: it sets the PC to
the operand value (0x2000) if flag Z is not set. Otherwise the PC is
incremented to point to the next instruction. This can be algorithmically
expressed as:

if Z == 0
PC = 0x2000;
end

It is a conditional jump instruction: the action of jumping, or setting the PC to

some given value, depends on the flag values
It only has one operand (instead of two)
The operand data is stored in the PC, so it is a memory address
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CPU organization Informática

Cache memory
Current CPU technology allows
to access memory much faster
than main memory, specially Main
dynamic RAM (DRAM). Processor memory
- Due to this, memory can
significantly slow down the CPU
and reduce system
performance. CPU
The cache memory is a fast
memory whose goal is to Cache
improve memory average access memory ...
times.
Cache memory stores copies of
the most frequently used main
memory locations
- Its contents is a subset of the
main memory contents. 29
CPU organization Informática

Cache memory
The operation of cache memory is as follows: whenever the processor needs
to read or write a location in main memory it first checks whether that
memory location is in the cache.
- If the memory location is cached, we say that a cache hit has occurred.
‣ The processor immediately reads or writes the data in the cache line.
- Otherwise, we speak of a cache miss.
‣ The referenced memory location has to be cached. In order to make room for
the new entry, the cache has to evict one of the existing entries and replace it
with the required main memory location.
- The “victim” entry is selected using a replacement policy.
‣ Optimal policy: replacing the entry which is least likely to be used in the future.
However, predicting the future is difficult.
‣ LRU: replaces the Least Recently Used entry.
The performance of the cache memory depends on the percentage of
accesses that result in a cache hit is known as the hit rate.

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CPU organization Informática

Cache memory
Modern desktop and server CPUs have separated instruction and data
caches to increase performance.
- Instruction caches are read-only so they do not need to be refreshed on main
memory upon a miss
Data caches are usually multi-level, i.e. they are organized as a hierarchy of
more cache levels (L1, L2, etc.)

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CPU organization Informática

Microprocessors
Microprocessor: single chip CPU.
- Old CPUs were made of separated chips for registers, ALU, CU, etc.
‣ See again Megaprocessor: http://www.megaprocessor.com
- Actual CPUs are single chip
- They can include multiple cores (multicore) that basically are CPUs that
share memory and cache…

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CPU organization Informática

Microprocessors
The instruction set is considered as the
interface definition of a given
microprocessor
- The Intel Pentium has its own instruction
set different to, for example, the ARM
Cortex
- Two microprocessors with the same
instruction set are considered
compatibles
‣ Examples: Intel Pentium clones
manufactured by AMD or Cyrix, like AMD
K5 or K6.

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CPU organization Informática

Microprocessors
Evolution of the Intel family

Go to http://cpuboss.com/ for checking the performance of your PC computer

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CPU organization Informática

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CPU organization Informática

Computer power evolution

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 Informática
Ing. Aeroespacial

Computers

C4: Computer organization (ii):

Machine Language

DISCA: Departamento de Informática de Sistemas y Computadores

Computer organization Informática

Machine language
Machine language instructions
The stack
Translating into Assembly
Compilers and interpreters

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Machine language Informática

Machine language
Remember: the CPU only executes machine language instructions
• Then, your computer only runs machine instructions,
• but every processor architecture has its own instruction set
Instruction classification:
- Data movement
- Arithmetic and logic instructions
- Control of flow
- Stack handling

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Machine language Informática

Machine language instructions consist of:

- Opcode: the operation code. Its mnemonic reminds the operation functionality.
Examples: ADD
- Operands: the data that the operation is performed upon. Example: ADD R1,R2

Instructions encoding format for SEP16

Format 16 bits Example
6 4 2 4
1 opcode op1 op2 MOV reg1,reg2
6 4 6
2 opcode op1 INC reg
6 10
3 opcode RET
6 4 6
opcode op1
4 MOV reg,addr
op2 40
Machine language Informática

Instructions encoding format for SEP16 (Real examples)

Hex Bin Example
6 4 2 4
1 opcode op1 op2 MOV reg1,reg2
0x9885 100110 0010 00 0101 MOV R2,R5
6 4 6
2 opcode op1 INC reg
0x4680 010001 1101 000000 INC R10
6 10
3 opcode RET
0x8400 100001 0000000000 RET
6 4 6
opcode op1 MOV reg,addr
4
op2
0x0C80 000011 0011 000000 MOV R3,0x1F1F
0x1F1F 0001 1111 0001 1111 41
Machine language Informática

Instruction encoding
Instruction codes consist of the following fields:
- Opcode: in the SEP16 it is a fixed number of bits for all instructions.
‣ Encodes not only the type of instruction (MOV, INC, etc.) but also the addressing mode
‣ 6 bits: it allows up to 26=64 different instructions and addressing modes.
- Operands: each operand is reserved a number of bits that depends on the operand type
and addressing mode.
- Number of operands: instructions may have different number of operands:
‣ two operands: ADD R2,R0
‣ one operand: JNE 0x2000
‣ no operands: NOP
- Addressing modes: the way in which the operands of the instructions are obtained:
‣ Register addressing requires 4 bits (16 registers)
‣ Direct addressing requires 16 bits (64K word memory address space)
‣ Register indirect addressing requires 4 bits (16 registers)
‣ Immediate addressing requires 16 bits (16 bit data)
‣ Implicit addressing has no operands
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Machine language Informática

Addressing modes
Register addressing: the operand is a register.
- Examples: MOV R1,R2; ADD R3,R2; XOR R1,R2
Direct addressing: the operand is a memory location that is specified in the
instruction itself.
- Examples: MOV R0,0x4002; JNE 0x2002; CALL 0x7FE
Register indirect addressing: the operand is a memory location whose
address is given by (the contents of) a bracketed register identifier.
- Examples: MOV R0,[R2]; JEQ [R2]; CAL [R2]
Instruction: MOV R0,[R2]

CPU Main memory

Register
0xA7B1 R0 indirect
0x4000 0xA7B1 addresing

0x4000 R2
...
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Machine language Informática

Addressing modes
Immediate addressing: the operand is an immediate data specified in the
instruction itself.
- Examples: LDR R0,0xFF01; ADD R2,0xAB01
Implicit addressing: the operand is a predefined register which is not
specified as an operand.
- Examples: PUSHSR, POPSR

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Computer organization Informática

Machine language
Machine language instructions
The stack
Translating into Assembly
Compilers and interpreters

45
Machine language instructions Informática

Data movement instructions

MOV - move
- MOV reg1,reg2 - move register to register
‣ RTL: reg1← reg2 Ex: MOV R1,R2
- MOV reg1,[reg2] - move register to register indirect
‣ RTL: reg1←[reg2] Ex: MOV R1,[R2]
- MOV [reg1],reg2 - move register indirect to register
‣ RTL: [reg1]←reg2 Ex: MOV [R1],R2
- MOV reg,addr - move memory to register
‣ RTL: reg←[addr] Ex: MOV R1, 0x2000
- MOV addr,reg - move register to memory.
‣ RTL: [addr]←reg Ex: 0x2000,R1
LDR - load register
- LDR reg,data - load register with immediate data
‣ RTL: reg←data Ex: LDR R1,0xFF00
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Machine language instructions Informática

Arithmetic instructions
ADD - add SUB - subtract
- ADD reg1,reg2 - add register to register - SUB reg1,reg2
‣ RTL: reg1←(reg1+reg2), Ex: ADD R1, R2 ‣ RTL: reg1←(reg1-reg2)

- ADD reg,data - add immediate data to register - SUB reg,data

‣ RTL: reg1←(reg1+data), Ex: ADD R1, ‣ RTL: reg1←(reg1-data)
0x0003
SBC - subtract with carry
ADC - add with carry
- SBC reg1,reg2
- ADC reg1,reg2 - adc register to register
‣ RTL: reg1←(reg1-reg2-C)
‣ RTL: reg1←(reg1+reg2+C), Ex: ADC R1, R2
- SBC reg,data
- ADC reg,data - add immediate data to register
‣ RTL: reg←(reg-data-C)
‣ RTL: reg←(reg+data+C), Ex: ADC R1, 0x0003
DEC - decrement
INC - increment
- DEC reg
- INC reg - increment register
‣ RTL: reg←(reg-1)
‣ RTL: reg←(reg+1), Ex: INC R1
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Machine language instructions Informática

Logic instructions
CMP - compare and affect flags
- CMP reg1,reg2 - compare register to register.
‣ RTL: PSR←(reg1 ? reg2) Ex: CMP R1,R2
- CMP reg,data - compare register to immediate data.
‣ RTL: PSR←(reg ? data) Ex: CMP R1,0xFFFF
AND - logical and OR - logical or XOR - logical xor
- AND reg1,reg2 - and register to register.
‣ RTL: reg←(reg1 & reg2) Ex: AND R1,R2
- AND reg,data - compare register to immediate data.
‣ RTL: reg←(reg & data) Ex: AND R1,0xFF00
BIC - bit clear
- BIC reg1,reg2 - bit clear register to register.
‣ RTL: reg1←(reg1 & ∼ reg2) Ex: BIC R1,R2
- BIC reg,data - bit clear register to immediate data
‣ RTL: reg←(reg & ∼ data) Ex: BIC R1,0xFF00
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Machine language instructions Informática

Shift instructions
SHR - shift right SHL - shift left
- SHR reg,data4
‣ RTL:(C←reg31 ←reg30 ←···←reg1 ←reg0 ←0)*data4 times. Ex: SHR R1,0x0A

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Machine language instructions Informática

Control of flow instructions

Jcond - jump conditional
- Jcond,addr - jump to address
‣ RTL: if (cond) PC←addr; else PC←(PC+2); end Ex: JEQ 0x20FF
- Jcond,[reg] - jump register indirect
‣ RTL: if (cond) PC←reg; else PC←(PC+1); end Ex: JNE [R3]
Ccond - call subroutine conditional
- Ccond,addr - call address
‣ RTL: if (cond) [SP]←PC; SP←(SP-1); PC←addr; else PC←(PC+2); end
‣ Ex: CAL 0x27FF
- Ccond,[reg] - call register indirect
‣ RTL: if (cond) [SP]←PC; SP←(SP-1); PC←addr; else PC←(PC+2); end
‣ Ex: CNZ [R3]
RET - return from subroutine
- RET
‣ RTL: SP←(SP+1); PC←[SP]; Ex: RET
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Machine language instructions Informática

Conditions
AL: always
EQ / NE: equal / not equal
MI, PL: minus (negative) /
plus (positive or zero)

Unsigned:
HS / LO: ≥ / <
HI / LS: >/≤

Signed:
GE / LT: ≥/<
GT / LE: >/≤

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Computer organization Informática

Machine language
Machine language instructions
The stack
Translating into Assembly
Compilers and interpreters

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The stack Informática

The stack
A stack is a Last In, First Out (LIFO) data structure.
It has two associated operations:
- push: puts a new item onto the top of the stack
- pop: removes an item from the top-most position of the stack.

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The stack Informática

Stack handling instructions

PUSH - push onto the stack
- PUSH reg - push register onto the stack.
‣ RTL: [SP]←reg; SP←(SP-1); Ex: PUSH R3
- PUSHSR - push the PSR onto the stack.
‣ RTL: [SP]←PSR; SP←(SP-1); Ex: PUSHSR
POP - pop from the stack
- POP reg - pop the value on top of the stack onto register.
‣ RTL: SP←(SP+1); reg←[SP]; Ex: POP R3
- POPSR - pop the value on top of the stack onto the PSR.
‣ RTL: SP←(SP+1); PSR←[SP]; Ex: POPSR

Other instructions
NOP - no operation
STOP - stop the processor
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The stack Informática

Subroutines and functions

CAL 0x240A: call always (unconditionally) memory address 0x240A.
RET: return from a function.

CAL
[SP] ← PC;
SP ← SP-1;
PC ← 0x240A;

RET
SP ← SP+1;
PC ← [SP] ;

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The stack Informática

Nested subroutine calls

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The stack Informática

Global variables and local variables

Global

Local

57
Computer organization Informática

Machine language
Machine language instructions
The stack
Translating into Assembly
Compilers and interpreters

58
Translating from high-level into assembly Informática

Assembly language
//DATA segment
ORG 0x2000 SYMBOL TABLE
X: DWORD X ≡ 0x2000
Y: DBYTE
//STACK segment Y ≡ 0x2001
ORG 0x7000 STACK ≡ 0x7200
STACK: DWORD[512] START ≡ 0x4000
//CODE segment CASE2 ≡ 0x400A
ORG 0x4000
CASE1 ≡ 0x400E
START: LDR SP, STACK+512 //SP←Stack base - 0x4000
LDR R0, 200 //R0 ← 200 - 0x4002 END ≡ 0x4011
MOV X, R0 //0x2000 ← R0 - 0x4004
CMP R0, 100 //R0 > 100? - 0x4006
JGT CASE1 //Jump greater - 0x4008
//than (signed)
CASE2: LDR R1, 0 //R1←0 - 0x400A
JAL END //Jump always - 0x400C
CASE1: LDR R1, 1 //R1←1 - 0x400E
SHL R1, 1 //Shift left R1 - 0x4010
END: NOP //Do nothing - 0x4011 NOT TO STUDY-
MOV Y, R1 //0x2001 ← R1 - 0x4012 ONLY GIVEN AS EXAMPLES
OF ASSEMBLY CODE
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Translating from high-level into assembly Informática

Translating if-statements
ORG 0x2000 // DATA segment
x: DWORD
y: DWORD
ORG 0x4000 // CODE segment
START: LDR R0, 200 // R0 ← 200
MOV x, R0 // 0x2000 ← R0
LDR R1, 0 // R1 ← 0
MOV y, R1 // 0x2000 ← R1
CMP R0,100 // if R0>100?
JGT case1 //Jump signed GT case1
CMP R0,10 //if R0>10
JGT case2 //Jump signed GT case2
case3: MOV R2, 3 //else R2 ← 3
JAL END //Jump always END
case2: MOV R2, 2 //R2 ← 2
JAL END //Jump always END
case1: MOV R2, 1 //R2 ← 1
NOT TO STUDY-
END: MOV y, R2 //0x2001 ← R2 ONLY GIVEN AS EXAMPLES
OF ASSEMBLY CODE
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Translating from high-level into assembly Informática

Translating for-statements
ORG 0x2000 // DATA segment
y: DWORD[100] // y[0]...y[99]
// i assigned to R0
ORG 0x4000 // CODE segment
START: LDR R0, 0 // R0 ← 0
LDR R1, y // R1 points @ y[0]
loop: CMP R0,100 // R0>=100?
JGT END // if >= exit loop
ADD R1, 2 // R1 points @ y[i]
MOV [R1], RO // y[i] ← R0
INC R0 // i ← i+1
JAL loop // loop again
END: ...

NOT TO STUDY-
ONLY GIVEN AS EXAMPLES
OF ASSEMBLY CODE
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Translating from high-level into assembly Informática

Translating while-statements
ORG 0x2000 // DATA segment
x: DWORD //var x
ORG 0x4000 // CODE segment
START: MOV R0, x //R0 ← [x]
loop: CMP R0, 0 //x<0?
JLT END //exit loop
CMP R0,100 //x>=100?
JGE END //exit loop
INC R0 //x ← x+1
JAL loop //loop again
END: MOV x, R0 //[x] ← R0

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Translating from high-level into assembly Informática

Translating function calls (I)

ORG 0x2000 // DATA segment
z: DWORD // var z
ORG 0x7000 // STACK segment
STACK: DWORD [512]
ORG 0x4000 // CODE segment
// Main program
MAIN: LDR SP, STACK-512 // SP ← Stack base
LDR R0, 0 // R0 ← 0
MOV z, 0 // init z=0
LDR R0, 9 // push y
PUSH R0
LDR R0, 5 // push x
PUSH R0
CAL sum // call sum (always)
POP R0 // pop z
NOT TO STUDY-
END: MOV z, R0 // z ← R0 ONLY GIVEN AS EXAMPLES
OF ASSEMBLY CODE
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Translating from high-level into assembly Informática

Translating function calls (IU)

// CODE segment
// Function sum
sum: POP R14 //old PC
POP R1 // pop x
POP R0 // pop y
ADD R0, R1 // x=x+y
PUSH R0 // push z
PUSH R14
RET // end sum

NOT TO STUDY-
ONLY GIVEN AS EXAMPLES
OF ASSEMBLY CODE
64
Computer organization Informática

Machine language
Machine language instructions
The stack
Translating into Assembly
Compilers and interpreters

65
Languages and compilers Informática

Languages
High-level programming language: it is machine independent; it can be used for any
computer and may be ported across computers
- It makes abstraction of the computer architecture like the CPU registers, memory
addresses, stacks and, mostly, a particular machine language instruction set
Language components:
- Syntax (form): describes the possible combinations of symbols that form a syntactically
correct program
- Semantics: meaning
Programming language paradigms
- Structured programming:
‣ A program is a limited number of structures (sequences, selections, and repetitions).
The most important structuring elements are functions, which allow to decompose a
program into a set of well defined building blocks. It is used to build higher level
abstractions and hiding their details
‣ C, Matlab, ...
- Object oriented:
‣ Java, C++, ...
- Others...

66
Languages and compilers Informática

Compilers
Compiler: it is a computer program that transforms source code written in a
pro gramming language (source) into another language (target).
- Source: high level language (C, C++, Fortran...)
- Target: usually machine code

A same program can be compiled for

two different hardware targets:
- A Windows desktop on an Intel Pentium
- A mobile phone running IPhone OS on
an ARM processor.

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Languages and compilers Informática

Linkers
Large program consist of many source files and make use of external libraries
Library: file that contains code and data that can be used from independent
programs. They usually encapsulate a set of related functions useful in some
application domain
- Example: a matrix library, a graphic library, an I/O library,...
Generating an executable program consists of two steps:
- 1. Compiling: each source file separately. In this case the compiler does not
produce the executable file, but an intermediate file called an object file
- 2. Linking all the object files and libraries that the program comprises
together, in order to generate a single executable file
Linking process:
- The compiler generates a symbol table for each object file with symbols and
the location of this symbols into the object file
- Solving cross-references consists of associating each unsolved reference
with an external reference
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Languages and compilers Informática

Linkers

69
Languages and compilers Informática

Linkers

70
Languages and compilers Informática

Interpreters
An interpreter is a computer program that directly executes instructions
written in a programming language. No previous compiling or linking
process
- Examples: Matlab, Perl, Python
In compiled languages there are two important milestones in their life-cycle:
- Compile time
- Execution time
In interpreted language there is no compile time; everything is done at
execution time: program analysis, solving external references, translating
and performing instructions, etc.
- More inefficient
- Easily portable

71
Languages and compilers Informática

The Java language

Java uses a combination of compilation and interpretation:
- Compilation: the source program is first compiled to produce an
intermediate representation called bytecode for the “Java Virtual Machine”
(JVM).
- Interpretation: the bytecode is usually interpreted by the JVM which
produces machine code for the real CPU.

72
Languages and compilers Informática

The Java language

The Java bytecode is an instruction set
designed for a virtual or hypothetical CPU
called the “Java Virtual Machine” (JVM).
- The JVM is not a real hardware CPU, but
we can imagine it as it effectively was.
A virtual machine is a hypothetical machine
defined by an instruction set and usually
implemented as an interpreter.
Advantages of Java:
- Portability: programs can be executed on
any platform running the JVM.
- Code mobility: code can be sent from the
Internet.

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