ee UE eo eat gs Computer Science 9618 with Majid Tahir Syllabus Content: 1.4.1 CPU architecture © show understanding of the basic Von Neumann model for a computer system and the stored program concept ® show understanding of the roles carried out by registers, including the difference between general purpose and special purpose registers including: Program Counter Memory Data Register Memory Address Register Index Register Current Instruction Register © Status Register o0000 * show understanding of the roles carried out by the Arithmetic and Logic Unit (ALU), Control Unit and system clock, Immediate Access Store(IAS) * show understanding of how data are transferred between various components of the computer system using the address bus, data bus and control bus * show understanding of how the factors contribute to the performance of the computer system including: ‘0 processor types and cores X © bus width 0 clockspeed > cache memory ® show understanding of the need for ports, including © Universal Serial Bus (USB), to provide the connection to peripheral devices © High Definition Multimedia Interface (HDMI) © Video Graphics Array (VGA) © The fetch-execute cycle © describe the stages of the fetch-execute cycles how understanding of ‘register transfer’ notation © possible causes and applications of interrupts are handled Von Neumann Model: The earliest computers were not “programmable”. They were designed to do specific tasks only. Reprogramming when it was possible at all was a tedious process, starting with flowcharts and paper notes, followed by detailed engineering designs, and then the often process of physically re-wiring and re-building the machine. It could take three weeks to set up a program on ENIAC (a computer of 1940s) and get it working. ENIAC (Electronic Numerical Integrator and Computer) was the first electronic general-purpose computer. It was Turing-complete, digital, and capable of being reprogrammed to solve “a large class of numerical problems www.majidtahir.com Email: [email protected] |Contact: 03004003666 5The von Neumann architecture, also known as the von Neumann model and Princeton Architecture, is based on John von Neumann's (mathematician and physicist) research paper in 1945 and others in the First Draft of a Report on the EDVAC. EDVAC (Electronic Discrete Variable Automatic Computer) was one of the earliest electronic computers. This described design architecture for an electronic digital computer with parts consisting © Central Processing Unit containi © Control Unit © Arithmetic/Logic unit © Processor registers, © Memory to store data & instructions © Input / Output Mechanism ® External Storage This describes design architecture for an electronic digital computer with subdivisions of a central arithmetic part, a central control part, a memory to store both data and instructions, external storage, and input and output mechanisms. The meaning of the phrase has evolved to mean a stored-program computer. A stored-program digital computer is one that keeps its programmed instructions, as well as its data, in read-write, random-access memory (RAM) ‘So John Von Neumann introduced the idea of the stored program. Previously data and programs were stored in separate memories. Von Neumann realized that data and programs are indistinguishable and can, therefore, use the same memory ‘The Von Neumann architecture uses a single processor which follows a linear sequence of fetch-decode-execute. The Picture below shows difference between Von Neumann architecture and Harvard architecture (earliest computers) Von Neumann vs. Harvard Architecture Devices Enaitmajaanisiegnatcom || conscconouwssss |S) ©Features of a Von Neumann architecture The illustration shows the essential features of the Von Neumann or stored-program architecture Memory The computer will have memory that can hold both data and also the program proceso at dia.nmecer comps RU this memory is RAM. Es Control Unit EI The control unit will manage the process of moving data and program into and out of memory and also deal with carrying out (executing) program instructions - one at a time. This includes the idea of a ‘register’ to ° hold intermediate values. In the illustration above, the ‘accumulator’ is one such register. The ‘one-at-a-time’ phrase means that the Von Neumann architecture processing machine. a sequential Input - Output Central Processing Unit This architecture allows for the idea that a person needs to interact with Contre Unit the machine. Whatever values that is, assed to and forth is stored once again in some internal registers. Input Device ‘thetic / Logic Unit ouput Device Registers (ro ][ a Arithmetic Logic Unit This part of the architecture is solely fe Twa TL vee } involved with carrying out calculations upon the data. All the usual Add, Multiply, Divide and Subtract calculations will be available but also data comparisons such as ‘Greater Than’, ‘Less Than’, ‘Equal To' will be available. Registers: The Von Neumann architecture uses a single processor which follows a linear sequence of fetch-decode-execute. In order to do this, the processor has to use Emattmattahier@gmaticom || contac: esoosonsese Sysome special registers, which are discrete memory locations with special purposes. attached. Pc Program Counter- keeps track of where to find the next instruction so that a copy of the instruction can be placed in the current instruction register MAR Memory Address Register- to hold the memory address that contains either the next piece of data or an instruction tha is to be used MDR Memory Data Register: acts like a buffer and holds anything that is copied from the memory ready forthe processor to use it Current Instruction Register: The current instruction register holds the instruction that is cIR tobe executed Index Register: isa register used for modifying operand addresses during the run of a program, typically for doing vectoriarray operations. Index registers are used for a special kind IRIIX of indirect addressing. ‘Accumulator: This is simply the special register where data is worked on. Again, you can think of tas a box. If | wanted to add 4 to 7, for example, | would fetch 4 from RAM and put 4 in the Accumulator. | would then get 7 trom RAM and add that to whatever was in the ‘Accumulator. | would then store the result briefly in the Accumulator before moving it back to ‘somewhere in RAM to be used later. All calculations of any description are done using the ‘Accumulator. In fact, CPUs often have a few of these important registers, to help them Accumulator | process data quickly. ‘The Processor Status Register (abbreviated as P) is a hardware register which records the condition of the CPU as a result of arithmetic, logical or command operations. The purpose of the Processor Status Register is to hold information about the most recently performed ALU operation, control the enabling and disabling of interrupts and set the CPU operating mode. Special Purpose Register {A Special Function Register (or Special Purpose Register, or simply Special Register) is a register within a microprocessor, which controls or monitors various aspects of the microprocessors function. General Purpose Registers General purpose registers are available to store any transient data required by the program. For example, when a program is interrupted its state, ie: the value of the registers such as the program counter, instruction register or memory address register - may be saved into the general purpose registers, ready for recall when the program is ready to start again. In general www.majidtahir.com | | Email: [email protected] | Contact: 03004003666 Stalthe more registers a CPU has available, the faster it can work. Accumulator is a General Purpose Register. Bus Notice the arrows between components? This implies that information should flow between, various parts of the computer. In a modern computer built to the Von Neumann architecture, information passes back and forth along a ‘bus’. There are buses to identify locations in memory ~ an ‘address bus’ Address Bus: Address bus is unidirectional (single directional) bus that carries signals relating to memory addresses between processor and memory. Data Bus: This bi-directional (two way traffic) bus is used to exchange data between processor, memory and input/output devices Control bus: This bus that carries signals used to coordinate the computer's activities System bus Bus Width ‘A bus is a channel over which information flows. The wider the bus, the more information can flow over the channel, much as a wider highway can carry more cars than a narrow one. The original ISA bus on the IBM PC was 8 bits wide; the universal ISA bus used now is 16 bits. The other I/O buses (including VLB and PCI) are 32 bits wide. The memory and processor buses on Pentium and higher PCs are 64 bits wide. ‘The address bus width can be specified independently of the data bus width. The width of the address bus dictates how many different memory locations that bus can transfer information to or from. soonmisticcn | [Enanaidanriegotion || conaccowososeis |S 5 ~ ZSystem Clock: Every computer contains an internal clock that regulates the rate at which instructions are executed and synchronizes all the various computer components. The CPU requires a fixed number of clock ticks (or clock cycles) to execute each instruction. The faster the clock, the more instructions the CPU can execute per second. In order to synchronize all of a computer's operations, a system clock—a small quartz crystal located on the motherboard—is used. The system clock sends out a signal on a regular basis to all other computer components. (One full period is also called a clock cycle. On most modern systems, the system clock switches between zero and one at rates exceeding several million times per second, ‘The clock frequency is simply the number of clock cycles which occur each second. A typical 80486 chip runs at speeds of 66milion cycles per second. Clock rat The speed at which a micro-processor executes instructions. One clock cycle is expressed in herda(Hz). Clock speeds are expressed in megahertz (MHz) or gigahertz ((GHz). Clock Speed: In a computer, clock speed refers to the number of pulses per second generated by an oscillator that sets the tempo for the processor. Clock speed is usually measured in MHz (megahertz, of millions of pulses per second) or GHz (gigahertz, or billions of pulses per second), ‘The operating speed of a computer, or its microprocessor, expressed in cycles per second (Megahertz or Gigahertz) 4 Megahertz is exactly one million Hertz. 1 MHz = 1 x 10° Hz. 1 MHz = 1000000Hz. 1 Cycle per Second: A period of 1 second is equal to 1 Hertz frequency. Port: In computer hardware, a port serves as an interface between the computer and other computers or peripheral devices. In computer terms, a port generally refers to the female part of connection. Computer ports have many uses, to connect 2 monitor, webcam, speakers, or other peripheral devices. (On the physical layer, a computer port is a specialized outlet on a piece of equipment to which a plug or cable connects, Electronically, hardware ports can almost always be divided into two groups based on the signal transfer: www.majidtahir.com | | Email: [email protected] | Contact: 03004003666 2faitkX<After ports are connected, they typically require handshaking, where transfer type, transfer rate, and other necessary information is shared before data are sent. Universal Serial Bus (USB) ‘The UNIVERSAL SERIAL BUS (USB) is an asynchronous serial data transmissionmethod. © thas quickly become the standard method for transferring data between a computer and a number of devices. Essentially the USB cable consists of: ® a four-wire shielded cable © two of the wires are used for power and the earth © two of the wires are used in the data transmission, When a device is plugged into a computer using one of the USB ports: © the computer automatically detects that a device is present (this is due to a small change in the voltage level on the data signal wires in the cable) © the device is automatically recognized, and the appropriate DEVICE DRIVER is loaded up so that computer and device can communicate effectively © if anew device is detected, the computer will 00k for the device driver which matches the device; if this is not available, the user is prompted to download the appropriate software, z : Devices plugged into the computer are automatically detected; device drivers are automatically uploaded The connectors can only fit one way; this |The maximum cable length is prevents incorrect connections being made |presently about 5 metres This has become the industry standard; this means that considerable support is ‘Several different data transmission rates | The present transmission rate is limited to less than 500 megabits per second Newer USB standards are backward The older USB standard (e.g. compatible with older USB standards 1.1) may not be supported in the near future www.majidtahir.com Email: [email protected] |Contact: 03004003666Specialised multimedia ports Despite the widespread use of USB ports there are some peripheral devices that require a different port, one that is specialised for the type of device. Although computer systems come packaged with a monitor for screen display there is sometimes a requirement for a second screen to be used. The connection of the second screen can be through a Video Graphics Array (VGA) port. This provides high-resolution screen display which is suitable for most display requirements. However, if the screen is needed to display a video, the VGA port is not suitable because it does not transmit the audio component. High Definition Multimedia Interface (HDMI) A High Definition Multimedia Interface (HDMI) port will provide a connection to a screen andallow the transmission of high-quality video including the audio component. CPU and Fetch-Execute Cycle Fetch-Decode-Execute-Reset Cycle: t The program counter (PC) contains the address of the The following is an algorithm that shows the ‘memory location of the next instruction which has to steps in the cycle. At the end the cycle is reset peered and the algorithm repeated. 1 1. Load the address that is in the program | _addtess register (MAR this ts done using the adaress counter (PC) into the memory address ee register (MAR). 1 2. Load the instruction that is in the The contents insirucion) at the memory locaton memory address given by the MAR into | {acdress) contained in MAR are then copied temporarily the memory data register (MDR). eee eae 3. Load the instruction that is now in the MDR iinto the current instruction register [pz cayenugrsinions of he MOR we then copied (CIR). and placed into the current instruction register (CIR) 4. Increment the PC by 1. 5. Decode the instruction that is in the CIR. 6._ Ifthe instruction is a jump instruction Tho value Tn tw PCs then incremented by 150 ate then nom plist He at stn whch hes be a. Load the address part of the instruction into the PC ' b. Reset by going to step 1 Te ene aed ey eS 7. Execute the instruction. ‘sanding out signals (via the contr to the various 8. Reset by going to step 1 Sone are ee caren ree Steps 1 to 4 are the fetch part of the cycle. wweaumaidahiczom | [ Ema majétane6i@gmaticom || Contact 0308003666 |Steps 5, 6a and 7 are the execute part of the cycle and steps 6b and 8 are the reset part. Step 1 simply places the address of the next instruction into the memory address register so that the control unit can fetch the instruction from the right part of the memory, The program counter is then incremented by 1 so that it contains the address of the next instruction, assuming that the instructions are in consecutive locations. rec tig Arithmetic & Logic Copy ares from data Unit fiom 9 10 MAR memory an mmemocy 308 gy o MOR 09410 MOR Control Unit Copy tom MOR Ur uu) ‘The MDR memory data register is used whenever anything is to go from the central processing unit to main memory, or vice versa. Thus the next instruction is copied from memory into the MDR and is then copied into the current instruction register. Now that the instruction has been fetched the control unit can decode it and decide what has to be done. This is the execute part of the cycle. If itis an arithmetic instruction, this can be executed and the cycle restarted as the PC contains the address of the next instruction in order. However, if the instruction involves jumping to an instruction that is not the next one in order, the PC has to be loaded with Enaitmajatanisiegnatcom || consccossouwssss | Sy) ©the address of the instruction that is to be executed next. This address is in the address part of the current instruction, hence the address part is loaded into the PC before the cycle is reset and starts all over again. Register Transfer Notatio: Register Transfer Notation (or RTN) is a way of specifying the behavior of a digital ‘synchronous circuit. Operations involving registers can be described by register transfer notation. The simplest form of this can be illustrated by the following representation of the fetch stage of the fetch execute cycle MAR ¢«— [PC] PC <— [PC]+1; MDR<— [[MAR]] IR «— [MDR] The basic format for an individual data transfer is similar to that for variable assignment. The first item is the destination of the data. Here the appropriate abbreviation is used to identity the particular register. To the right of the arrow showing the transmission of data is the definition of this data. In this definition, the square brackets around a register abbreviation show that the content of the register is being moved possibly with some arithmetic operation being applied. When two data operations are placed on the same line separated by a semi-colon this means that the two transfers take place simultaneously. ‘The double pair of brackets around MAR on the second line needs careful interpretation. The content of the MAR is an address; itis the content of that address which is being transferred to the MDR. Interrupt handling There are many different reasons for an interrupt to be generated. Some examples are: fatal error in a program hardware fault need for 1/0 processing to begin user interaction a timer signal. wweaumaidahiczom | [ Ema majétane6i@gmaticom || Contact 0308003666 |There are a number of different approaches possible for the detailed mechanisms used to handle interrupts but the overriding principles are clearly defined, Each different interrupt needs to be handled appropriately and different interrupts might possibly have different priorities. Therefore, the processor must have a means of identifying the type of interrupt. (One way is to have an interrupt register in the CPU that works like the status register, with each individual bit operating as a flag for a specific type of interrupt. AAs the flowchart in Figure shows, the existence of an interrupt is only detected at the end of a fetch-execute cycle This allows the current program to be interrupted and left ina defined state which Fetch next can be returned to later. instruction The first step in handling the Transfer control to interrupt is to store the interrupt-handlin contents of the program ea counter and any other Leste registers somewhere safe in instruction memory. | Execute instruction k ‘ny interrupts to be processed? Following this, the appropriate interrupt handler or interrupt service routine (ISR) program is initiated by loading its start address into the program counter. When the ISR program has been executed there needs to be an immediate check to see if further interrupts need handling. if there are none, the safely stored contents of the registers are restored to the CPU and the originally running program is resumed. Enaitmajaanisiegnatcom || conscconsowwssss | Say) ©Interrupt handling There are many different reasons for an interrupt to be generated. Some examples are: ++ fatal eror in a program a hardware fault a need for JO processing to begin user interaction timer signal. Interrupts are handled by a number of different mechanisms, but there are some clear overriding principles. Each different interrupt needs to be handled appropriately. Different interrupts might have different priorities. Therefore, the processor must have a means of identifying the type of interrupt. (One way is to have an interrupt register in the CPU that works like the status register, with each individual bit operating as a flag for a specific type of interrupt. AAs the flowchart in Figure above shows, the existence of an interrupt is only detected at the end of a fetch-execute cycle. This allows the current program to be interrupted and left in a defined state which can be returned to later. An interrupt is handled by the following steps. *- The contents of the program counter and any other registers are stored somewhere safe in memory. +: The appropriate interrupt handler or interrupt Service Routine (ISR) program is initiated by loading its start address into the program counter. ‘When the ISR program has been executed there is an immediate check to see if further interrupts need handling. ++ Further interrupts are dealt with by repeated execution of the ISR program + If there are no further interrupts, the safely stored contents of the registers are restored to the CPU and the originally running program is resumed. Past paper Question June 2015 7\(a) Bus Description ‘Three buses and three descriptions are shown is bus carries signals used below. address bus ‘coordinate the computer's activites Draw a line to connect each bus to its correct this bi-directional bus is used description to exchange data between processor, memory and inpu/ output devices control bus this uni-directional bus carries signals relating to. memory oe addresses betwoen processor ‘and memory [2] Enaitmajaanisiegnatcom || conscconsouwssss | Sap) ©(b) The seven stages in a von Neumann fetch-execute cycle are shown in the table below. Put each stage in the correct sequence by writing the numbers 1 to 7 in the right hand column, oe ‘Sequence The first one has been ‘number done for you. the instruction Is then copied from the memory location contained in the MAR (memory address register) and is placed in the MDR (memory data register) the instruction is finally decoded and is then executed the PC (program counter) contans the address of the nextinstucton |g to be fetched the entire instruction is then copied from the MDR (memory data register) and placed in the CIR (current instruction register) Refrences: 151 suo address contained in the PC (program counter) is copied to the Gomputer Science book by _| MAR (memory adcress register via the address bus Sylvia Langfield & Dave Duddell, www.wikipedia.com | the address part of the instruction, IGCSE Computer Science by _| (memory address register) Hodder Education, VCN — ICT I any, is placed in the MAR Deparment 2013 Prepared bY vay n he PC (rogram court then ncemeried ota it PAPERS points to the next instruction to be fetched www.majidtahir.com | | Email: majidtahir61@gmailcom | Contact: 08004003666 2Ce T<