KHULNA UNIVERSITY OF ENGINEERING AND TECHNOLOGY

Department of Electronics & Communication Engineering

Project Report On: Verilog HDL

Course Name: Digital Electronics and Logic Design Laboratory
Course No: ECE 2104

Name: Abdullah Al Hasib Sikder Naymur Rahman

Roll:2009050
Year:2nd Lecturer
Semester: 1st Department of ECE,KUET
Submission Date: 8 May,2023
Khulna
Table of project report contents:

No Contents Page

1 Objectives 2

2. Introduction 2

3. Theory 2-17

4. Problem statement 18

5. K-map simplification 20-21

6. Programe (Verilog Code) 22-24

7. Test bench code 25-28

8. Result and discussion 28-32

9. Conclusion 33

10. References 34

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Objectives :

1.To know about the SOP and POS form and write down the truth table from
product of sum (POS) form.
2. To learn how K-map works and simplify Boolean expression using K-map.
3. To learned about Verilog coding and write three separate Verilog design
programs for the simplified Boolean expression in gate level, data flow level, and
behavioral level modeling.
4. To write the Verilog testbench programs to determine the truth table and to
obtain the timing diagram for your designed system.

Introduction :

Verilog is a hardware description language (HDL) used to model digital circuits and
systems. Verilog code describes the behavior and structure of digital circuits using
modules, which can contain inputs, outputs, registers, and combinational logic.
Verilog can also describe more complex circuits and systems, including sequential
logic and finite state machines. With its powerful constructs and wide range of
modeling abilities, Verilog is widely used in digital design and verification.
It is commonly used in the design and implementation of digital systems, such as
microprocessors, memory chips, and communication systems. The Verilog code is
used to describe the functionality of the digital system, and it can be used to
simulate and synthesize the system to produce a physical implementation.
And It is not typically used to generate time graphs directly, but it can be used to
simulate a circuit's behavior over time, and the resulting simulation data can be
visualized as a time graph.

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Theory :

● SOP and POS form:

SOP (Sum of Products) and POS (Product of Sums) are two standard forms of
representing Boolean functions in digital logic.

●SOP Form:
In SOP form, a Boolean function is expressed as the sum of multiple product
terms. Each product term is made up of the product of one or more literals
(variables or their complements). For example, the Boolean function
F(A, B, C) = ∑(1, 3, 5, 7)
This can be represented in SOP form as
F(A,B,C) = A'B'C' + A'B'C + AB'C' + ABC.

●POS Form:
In POS form, a Boolean function is expressed as the product of multiple sum
terms. Each sum term is made up of the sum of one or more literals (variables or
their complements).
For example, the Boolean function
F(A, B, C) = Π(0, 2, 4, 6)
This can be represented in POS form as
F(A,B,C) = (A+B+C')(A+B'+C)(A'+B+C)(A'+B'+C).

Both SOP and POS forms are used in digital logic design for simplification of
Boolean functions and implementation of digital circuits

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● K-map:

K-map, short for Karnaugh map, is a graphical representation of a truth table for a
Boolean function. It is a tool used in digital logic design to simplify Boolean
algebra expressions by grouping together adjacent cells in a two-dimensional grid.

The K-map consists of cells arranged in a grid, with each cell representing a
possible combination of inputs for the Boolean function. The cells are arranged
so that cells that differ by only one input are adjacent to each other. This allows
for easy grouping of cells with the same output value.

K-maps are particularly useful in simplifying Boolean expressions with up to 6

variables. To use a K-map, the truth table for the Boolean function is first written
out, and the output values for each combination of inputs are placed in the
corresponding cell in the K-map. The cells are then grouped together in groups of
1, 2, 4, 8, etc., until all cells with the same output value are grouped together.

The resulting groups are then used to create a simplified Boolean expression for
the function. K-maps can significantly simplify complex Boolean expressions and
reduce the number of logic gates required to implement a circuit, resulting in a
more efficient and cost-effective design.

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Some Possible grouping of K-map:

CD
AB 00 01 11 10
00 a Group of 4
1 0 1 1 values

01
0 1 1 0 As K map is assumed
to be connected,so
11
we can make group
0 1 1 0 this way[22]

10
As K map is assumed to
be connected,so we can
1 0 1 1 make group this way[22]

Fig-01: 4 Variable k Map Grouping

00 01 11 10
00
0 1 1 0
01
0 1 1 0 As K map is assumed
to be connected,so
we can make group
this way[23] (group of
11 0 1 1 0 8 values)

10
0 1 1 0

Fig-02: 4 Variable k Map Grouping

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 CD
AB 00 01 11 10
00 Group of two
1 0 0 1 values

01 As K map is assumed to
0 1 1 0 be connected,so we can
make group this way[21]

11
0 1 0 0 Two Group of
two values
10
0 0 0 1 Group of a
single value

Fig-03: 4 Variable k Map Grouping

Group 1 Group 5

000 001 011 010 100 101 111 110

0
0 1 1 0 0 0 0 1
00
01

0 1 1 0 0 1 1 0
1 0 0 1 0 0 1 0
11
10

0 1 1 0 0 0 0 0

Group 2 Group 3 Group 4

Fig-04: 5 Variable k Map Grouping

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Example : Simplify the given 4 variable Boolean using the karnaugh map.

F(a,b,c,d = ∑(0, 2, 5, 7, 8, 10, 13, 15)

cd
ab 00 01 11 10

1 0 0 1
00

01 0 1 1 0

11 0 1 1 0 Group 2

10
1 0 0 1 Group 1

Fig-05: 4 Variable k Map Grouping

●Group:1
Positions = 0,2,8,10
Simplified Expression = b'd'
●Group:2
positions=5,7,13,15
Simplified Expression = bd
Final Expression = b'd' + bd

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Verilog Code:

The Verilog language is based on two main concepts: modules and signals. A
module is a building block of a digital circuit and is defined by a set of input and
output signals. Signals are used to represent electrical signals in the digital circuit,
such as clock signals, data signals, and control signals.
Verilog code typically consists of two main sections: module declaration and
module instantiation. In the module declaration section, the inputs and outputs of
the module are defined, along with any internal signals and variables that are
used in the module. In the module instantiation section, instances of other
modules are instantiated and connected to the inputs and outputs of the current
module.
Verilog also includes constructs for behavioral modeling, such as if-else
statements, case statements, and loops, which can be used to define the behavior
of the digital circuit. Verilog also supports gate-level modeling, where logic gates
and flip-flops are explicitly specified in the code.
Overall, the theory of Verilog code revolves around the description of digital
circuits and systems using a set of predefined constructs and syntax. The Verilog
code is used to model and simulate the behavior of the digital circuit and is
synthesized to generate the physical circuit.

STRUCTURE OF VERILOG CODE:

module name_of_the_module (port1, port2,…..);
input port1, port2,……; //declare input ports
output port5, port6, port7,…..; //declare output ports
…………………….................... // statements
………………………………….. // statements
endmodul

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In Verilog code there are different types of data. Data types are divided into NETS
and Registers.

Data types in Verilog:

● NET
- Connect between hardware entities.
- Do not store any value.
- Value changes continuously by the driving circuit.

- Commonly used net is wire which carries simple data from one port to another.

●REGISTER
- Stores the last value that was assigned to it.

VERILOG OPERATORS:
Verilog includes a variety of operators that are used to perform operations on
signals in digital circuits. These operators can be categorized into different groups
based on the type of operation they perform. Here are some of the main
categories of Verilog operators:
1. Arithmetic Operators:
●Addition (+)
●Subtraction (-)
●Multiplication (*)
●Division (/)
●Modulo (%)
●Unary Plus (+)
●Unary Minus (-)

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 2. Bitwise Operators:
●Bitwise AND (&)
●Bitwise OR (|)
●Bitwise XOR (^)
●Bitwise XNOR (~^)
●Bitwise NOT (~)
●Bitwise NAND (~&)
●Bitwise NOR (~|)
●Bitwise Reduction AND (&&)
●Bitwise Reduction OR (||)
3. Relational Operators:
●Equal to (==)
●Not equal to (!=)
●Less than (<)
●Greater than (>)
●Less than or equal to (<=)
●Greater than or equal to (>=)
4. Logical Operators:
●Logical AND (&&)
●Logical OR (||)
●Logical NOT (!)
5. Shift Operators:
●Left shift (<<)
●Right shift (>>)

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 ●Arithmetic right shift (>>>)
6. Conditional Operators:
●Conditional operator (?:)

These are some of the main categories of Verilog operators. Verilog also includes
other operators such as concatenation operator ({ }), replication operator ({ }),
and assignment operators (<=, =). Understanding the Verilog operators is
essential for writing Verilog code to model digital circuits and systems.

VERILOG CONDITIONAL STATEMENTS:

● if-else-if:
1. if-else statement: The if-else statement is used to execute a block of code if
a specific condition is true. If the condition is false, then the code in the else
block is executed. Here's an example:

if (condition) begin
// code to execute if condition is true
end else begin
// code to execute if condition is false
End

● case :
- Use of if-else may is inconvenient if number of conditions to be checked is quite
high.

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- The case statement checks if the given expression matches one among the other
expressions inside the list and branches.
- A case statement begins with the case keyword and closes with the endcase
keyword.

Example:

case (<expression>)
case_item1 : begin
// code to execute if expression is equal to item 1
case_item2: begin
// code to execute if expression is equal to item 2

case_item3 : begin
// code to execute if expression is equal to item 3

case_item4 : begin
//multiple statement for case 4
end
default: begin
// code to execute if signal does not match any of the above values
endcase

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VERILOG LOOPING:
● The statements are controlled by the for loop in three steps:
1. Initialization of counter variable
2. Condition check
3. Update counter variable

Syntax:
for ( initialize; condition; update) begin [statements]
end

TYPES OF MODELLING:

There are four types of modeling in Verilog code .

1. Switch Level Modeling (for MOSFET and BJT)
2. Gate Level Modeling (for AND, OR, NOT, etc.)
3. Data Flow Modeling (for Logical expression)
4. Behavioral Modeling (for the Behavior of the system)

●GATE LEVEL MODELING:

Gate-level modeling in Verilog is a style of hardware description that focuses on
the lowest level of abstraction in the design hierarchy, namely, the individual logic
gates and their interconnections. In this style of modeling, the design is described
in terms of the gates that make it up, and their interconnections are specified
using structural Verilog.
In short:
- Verilog supports a few basic logic gates known as primitives.

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- Predefined modules which can be instantiated in the code if needed.
- For example, not, and, nand, or, nor, xor, and xnor.

Example:
not n1 (y, x); // y is the output, x is the input
and a1 (y, a, b); //y is the output, a and b are inputs
or o1 (y, a, b, c); //y is the output, a, b and c are inputs

●Data flow modeling:

Data flow modeling in Verilog is a style of digital circuit design that emphasizes
the flow of data through a circuit rather than the control of that data. In data flow
modeling, a circuit is represented as a set of interconnected modules or gates,
each of which performs a specific data processing operation.
In Verilog, data flow modeling is implemented using the "assign" statement. The
"assign" statement is used to specify the logical connection between a module's
input and output ports. The syntax of the assign statement is as follows:

assign <output> = <expression>;

Here, the "<output>" represents the output port of the module, and
"<expression>" represents the expression that is evaluated to produce the
output. The expression can be a simple expression, such as a Boolean function, or
a more complex expression, such as a combination of Boolean functions and
arithmetic operations.

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For example, consider the following Verilog code that implements a simple AND
gate using data flow modeling:

module and_gate(input a, input b, output c);

assign c = a & b;
endmodule

In this code, the "assign" statement connects the input ports "a" and "b" to the
output port "c" using the Boolean AND operator. When both inputs are high, the
output will be high, and when either input is low, the output will be low.
Data flow modeling is particularly useful for designing combinational circuits,
where the output is solely dependent on the input. However, it is not suitable for
designing sequential circuits, where the output depends on both the input and
the circuit's previous state. For sequential circuits, Verilog provides other
modeling styles, such as behavioral and structural modeling.

●BEHAVIORAL MODELING:

Behavioral modeling in Verilog describes the function of a digital circuit in terms

of its behavior or operation, rather than its implementation details. It is a high-
level description of a digital system, typically used in the early stages of design to
validate its functionality before moving to more detailed descriptions.
Verilog's behavioral modeling constructs include:

1. Continuous assignments: These are assignments that execute continuously,

i.e., whenever the right-hand side (RHS) changes, the left-hand side (LHS) updates
immediately. It is used to model combinational logic.

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Example:

module my_module (input a, input b, output c);

assign c = a & b;
endmodule

2. Procedural assignments: These are assignments that execute only when the
block they are contained in executes. It is used to model sequential logic.
Example:

module my_module (input a, input clk, output reg b);

always@(posedge clk)
b <= a;
endmodule

3.Conditional statements: These are used to execute different code depending

on the value of a variable.
Example:

module my_module (input a, input b, output c);

always@(a or b)
begin
if (a == 1)
c = b;
else
c = 0;
end
endmodule

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4. Case statements: These are used to select from a number of choices based on
the value of a variable.
Example:

module my_module (input [1:0] a, output reg [3:0] b);

always@*
begin
case(a)
2'b00: b = 4'b0001;
2'b01: b = 4'b0010;
2'b10: b = 4'b0100;
2'b11: b = 4'b1000;
default: b = 4'b0000;
endcase
end
endmodule

Behavioral modeling is a useful technique for simulating and testing digital

systems before they are implemented in hardware. By providing a high-level
description of the system, it allows for easier verification of its functionality and
can help identify potential design flaws early in the design process.

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Problem Satement:
Write down the truth table of the given product of sum (POS) form of
the given Boolean expression, and then find out its simplified Boolean
expression using K-map. After these, write down three separate Verilog
design programs for the simplified Boolean expression in gate level,
data flow level, and behavioral level modeling (use the "case"
statement) respectively). Write Verilog testbench programs to
determine the truth table and to obtain the timing diagram for your
designed system

Given expression:
𝐹(𝑎, 𝑏, 𝑐, 𝑑, 𝑔) = 𝛱(2,4,7,13,19,24,26)

Solution:
Here the function is presented in the maxtems.So it will be a 5 variable (inputs) k
map.We can easily make the truth table as the position given will be 0.Other
position will hold 1.
Table -01 : truth table for the expression 𝐹(𝑎, 𝑏, 𝑐, 𝑑, 𝑔) = 𝛱(2,4,7,13,19,24,26)
a b c d g F

0 0 0 0 0 1

0 0 0 0 1 1

0 0 0 1 0 0

0 0 0 1 1 1

0 0 1 0 0 0

0 0 1 0 1 1

0 0 1 1 0 1

a b c d g F

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 0 0 1 1 1 0

0 1 0 0 0 1

0 1 0 0 1 1

0 1 0 1 0 1

0 1 0 1 1 1

0 1 1 0 0 1

0 1 1 0 1 0

0 1 1 1 0 1

0 1 1 1 1 1

1 0 0 0 0 1

1 0 0 0 1 1

1 0 0 1 0 1

1 0 0 1 1 0

1 0 1 0 0 1

1 0 1 0 1 1

1 0 1 1 0 1

1 0 1 1 1 1

1 1 0 0 0 0

1 1 0 0 1 1

1 1 0 1 0 0

1 1 0 1 1 1

1 1 1 0 0 1

1 1 1 0 1 1

1 1 1 1 0 1

1 1 1 1 1 1

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 Simplification of the expression using Karnaugh Map :

Maxterm = ΠM(2,4,7,13,19,24,26)
Variable = a,b,c,d,g.
Solution:

3rd group 6th group 2nd group

c+d+g c+d+g’ c+d’+g’ c+d’+g c’+d’+g c’+d’+g’ c’+d+g’ c’+d+g

000 001 011 010 110 111 101 100

00 1 1 1 0 1 0 1 0
a+b

01 1 1 1 1 1 1 0 1
a+b’

11 0 1 1 0 1 1 1 1
a’+b’

10 1 1 0 1 1 1 1 1
a’+b

1st group 4th group 5th group

Fig-06: K-Map Grouping for given expression

Group 1:
Positions = 24,26
Simplified Expression = a'+b'+c+g

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Group 2:
Positions = 4
Simplified Expression = a+b+c'+d+g

Group 3:
Positions = 2
Simplified Expression - a+b+c+d'+g

Group 4:
Positions = 19
Simplified Expression = a'+b+c+d'+g'

Group 5:
Positions = 13
Simplified Expression= a+b'+c'+d+g'

Group 6:
Positions = 7
Simplified Expression = a+b+c'+d'+g'

Final Expression = (a'+b'+c+g) (a+b+c'+d+g) (a+b+c+d'+g)

(a'+b+c+d'+g') (a+b'+c'+d+g') (a+b+c'+d'+g')

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● Program for gate level modeling,data flow modeling and
behavioral modeling:

code-1: code for gate level modeling

module delc_project_1(a,b,c,d,g,out); //declaring all variables

input wire a,b,c,d,g; //inputs are declared as wire

output out;

wire or1, or2, or3, or4, or5, or6, A, B, C, D, G;

//declaring some internal wire used in

circuit for OR gate or1, or2, or3, or4,
or5, or6 wire is used and for NOT gate
A, B, C, D, G wire is used.

not(A,a); // assigning all the required gate

not(B,b);
not(C,c);
not(D,d);
not(G,g);

or(or1,A,B,c,g);
or(or2,a,b,C,d,g);
or(or3,a,b,c,D,g);
or(or4,A,b,c,D,G);
or(or5,a,B,C,d,G);
or(or6,a,b,C,D,G);

and(or1,or2,or3,or4,or5,or6,out); //final output assigned

endmodule //end of the module body

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code-2: code for data flow modeling

module delc_project_2(a,b,c,d,g,out); // here all variables are declared

input a,b,c,d,g; //declaring inputs output out;

output out; //declaring output

wire or1,or2,or3,or4,or5,or6; //internal wires are declared

assign or1=~a|~b|c|d|g; //here ‘|’ symbol represents the
bitwise OR and ’~’ symbol
assign or2=a|b|~c|d|g; represents the bitwise NOT.
assign or3=a|b|c|~d|g;

assign or4=~a|b|c|~d|~g;

assign or5=a|~b|~c|d|~g;

assign or6=a|b|~c|~d|~g;

assign out= or1 & or2 & or3 & or4 & or5 & or6 //assigning the final output and
here ‘&’ symbol represent
the bitwise AND.

endmodule

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Code-3: code for behavioral modeling(using case statement)

module delc_project_3( a,b,c,d,g,out); //here all variables are declared

input wire a,b,c,d,g; //declaring inputs as wire

//declaring output as register
output reg out;

always @(a,b,c,d,g) //always loop

//begin of always loop
begin

case ({a, b, c, d, g})

//case statements

5'b00010,
5'b00100, //here 5’b means 5 bits binary value and
5'b00111, each bit represent one of the inputs, as we
5'b01101, mentioned in the case header the inputs
5'b10011, are a,b,c,d,g
5'b11000,
5'b11010: out = 0;

default: out = 1;
//default case statements

endcase
end //end of the case

endmodule //end of loop

//end of the module

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Test bench code :

module DELC_project;

reg a, b, c, d, g; //inputs

wire out;

delc_project_3 fp(.a(a), .b(b), .c(c), .d(d), .g(g), .out(out));

// the module ports are connected here

initial begin

$dumpfile("dump.vcd");
$dumpvars(1);

// Initializing Inputs
// Waiting 100 time units between each

a = 0; b = 0; c = 0; d = 0; g = 0;#100
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 0; c = 0; d = 0; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 0; c = 0; d = 1; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 0; c = 0; d = 1; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 0; c = 1; d = 0; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

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a = 0; b = 0; c = 1; d = 0; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 0; c = 1; d = 1; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 0; c = 1; d = 1; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 1; c = 0; d = 0; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 1; c = 0; d = 0; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 1; c = 0; d = 1; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 1; c = 0; d = 1; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 1; c = 1; d = 0; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 1; c = 1; d = 0; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 1; c = 1; d = 1; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 0; b = 1; c = 1; d = 1; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 0;c = 0; d = 0; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 0; c = 0; d = 0; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

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a = 1; b = 0; c = 0;d = 1; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 0; c = 0; d = 1; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 0; c = 1; d = 0; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 0; c = 1; d = 0; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 0; c = 1; d = 1; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 0; c = 1; d = 1; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 1; c = 0; d = 0;g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 1; c = 0; d = 0; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 1; c = 0; d = 1; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 1; c = 0; d = 1; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 1; c = 1; d = 0; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 1; c = 1; d = 0; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

a = 1; b = 1; c = 1; d = 1; g = 0;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

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a = 1; b = 1; c = 1; d = 1; g = 1;#100;
$display("a=%b,b=%b,c=%b,d=%b,g=%b,F=%b",a,b,c,d,g,out);

end

endmodule //end of the module and test bench code.

Result and discussion:

In this project a expression of maxterm was given and our task was to find tha
truth table and simplify the expression with K-map. I have solved our given
expression using the truth table (table-01) and using the figure-06 .and my
simplified expression was:
F(out)= (a'+b'+c+g) (a+b+c'+d+g) (a+b+c+d'+g) (a'+b+c+d'+g')
(a+b'+c'+d+g') (a+b+c'+d'+g')

After that I have write down three separate Verilog design programs for the
simplified Boolean expression in gate level, data flow level, and behavioral level
modeling. And then using then I have Write the Verilog testbench programs to
determine the truth table and to obtain the timing diagram for my designed
system.

Fig-07: Timing diagram of the designed circuit at input 00010 (2)

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Then I run the programs in EDA playground (online simulator and
synthesizing System Verilog) to obtain the timing diagrams(as example fig-07) and
the console window(fig-16).
In fig-07 I have selected the input a=0,b=0,c=0,d=1,g=0 and got the output which
is defined as out is 0. That’s means at binary equivalent 00010 or decimal 2 my
output is 0 , and in my given given expression I have also a maxterm in 00010 or in
2. It proves that this input have given the correct output.

Fig-08: Timing diagram of the designed circuit at input 00100 (4)

In fig-08 I have selected the input a=0,b=0,c=1,d=,g=0 and got the output 0. That’s
means at binary equivalent 00100 or decimal 4 my output is 0.

Fig-09: Timing diagram of the designed circuit at input 00111 (7)

In fig-09 I have selected the input a=0,b=0,c=1,d=1,g=1 and got the output 0.
That’s means at binary equivalent 00111 or decimal 7 my output is 0.

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 Fig-10: Timing diagram of the designed circuit at input 01101 (13)
In fig-10 I have selected the input a=0,b=1,c=1,d=0,g=1 and got the output 0.
That’s means at binary equivalent 01101 or decimal 13 my output is 0.

Fig-11: Timing diagram of the designed circuit at input 10011 (19)

In fig-11 I have selected the input a=1,b=0,c=0,d=1,g=1 and got the output 0.
That’s means at binary equivalent 10011 or decimal 19 my output is 0.

Fig-12: Timing diagram of the designed circuit at input 11000 (24)

In fig-12 I have selected the input a=1,b=1,c=0,d=0,g=0 and got the output 0.
That’s means at binary equivalent 11000 or decimal 24 my output is 0.

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 Fig-13: Timing diagram of the designed circuit at input 11010 (26)

In fig-13 I have selected the input a=1,b=1,c=0,d=1,g=0 and got the output 0.
That’s means at binary equivalent 11010 or decimal 26 my output is 0.

Fig-14: Timing diagram of the designed circuit at a random input 11100(28)

In fig-14 I have selected the input a=1,b=1,c=1,d=0,g=0 and got the output 1.
That’s means at binary equivalent 11100 or decimal 28 my output is 1.
28 was a random input and in this case I shouldn’t gate the maxterm and the
output also says that there is no maxterm as I’ve got the output 1.

Fig-15: Timing diagram of the designed circuit at a random input 01110(14)

In fig-15 I have selected the input a=0,b=1,c=1,d=1,g=0 and got the output 1.
That’s means at binary equivalent 01110 or decimal 14 my output is 1. Also 14
was a random input and in this case I shouldn’t gate the maxterm and the output
also says that there is no maxterm as I’ve got the output 1.

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From those Timing Diagrams (from fig-07 to fig-15) it is clear that the output is 0
only when the inputs are : 00010, 00100, 00111, 01101,10011,11000, 11010. And
for other inputs its output is 1.
This outputs satisfies the truth table (table-01).

In the fig-16 the console window has been shown.For all the possible combination
of the input consist here along with their corresponding output. From the truth
table(table-01) we can see that the output is 0 only when the input is: 00010,
00100, 00111, 01101,10011,11000, 11010 . So the truth table satisfied all the
required cases.

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 Fig-16:Console window containing truth table

Our timing diagram outputs satisfies the truth table (table-01).And the console
window (fig-16) also contain the truth table which justifies our output and also
indicates that our codes are written successfully and also executes successfully.

Conclusion:

In this Verilog HDL project, we’ve been given separate problems which was Given
in SOP form. In theory I’ve given a brief explanation of SOP and POS form. And as
I’ve to solve or simplify the expression with K-map, I’ve given a brief explanation
of k-map solving process. And most important part of the theory was to explain
the Verilog code briefly and I tried to explain all the important parts of the Verilog
HDL and also give some examples in theory part. And then obtain the truth table
of the given expression and then simplify the expression with k-map. Using the
simplified expression I’ve write the Verilog program of gate level, data flow level,
and behavioral level modeling. And then I have Write the Verilog testbench
programs using the truth table.

After that I’ve run them in online simulator (EDA playground).And obtain the
timing diagrams and Console window containing truth table. After analyzing the
timing diagrams and Console window I get that my programs were successfully
executing and my outputs also satisfies the truth table. And this result was
satisfactory to me.

As Verilog is an essential tool for microcontroller designers, as it enables them to

design and verify complex digital systems in a highly efficient and reliable manner.
By using Verilog to describe and simulate their designs, microcontroller designers
can ensure that their final products meet the high standards of performance,
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reliability, and functionality that are expected in today's fast-paced and ever-
evolving technological landscape. Hope this project work will help us in future to
work with microcontroller designs.

References:

1.Digital Logic And Computer Design.

- M.Morris Mano.
2.Modern Digital Electronics.
- R.P. Jain.
3.https://chat.openai.com/
4.https://en.wikipedia.org/
5.https://www.allaboutcircuits.com/
6.https://youtube.com/playlist?list=PLAC_jmBddcjTPEh1UV_ojRJmsx2D9sQXH
7.https://www.geeksforgeeks.org/
8.https://edaplayground.com/x/AU2T

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