ABHISHEK [Link].2,[Link].
13A, Meethapur New Delhi 110044 India
+91-8800445933
abhishekchaubey523@[Link]
CHAUBEY [Link]/in/chaubeyabhishek523
CAREER SUMMARY
Highly passionate professional with ability to analyze real time emir issues with static/dynamic IR droop/bounce & thermal hotspot
flows. Also, working on 2 patents first one is to model the vectorless events which can cause highest dynamic ir drop & second one
on thermal hotspot mitigation with help of density analysis . Good leadership qualities with desire to explore & build new things and
tackle challenges.
Driving & Validation of various Voltus flows at multiple customers.
Proficient technical knowledge of PDN.
Outstanding problem solving and presentation skills.
Hands on python automation helps in providing WA to customer on urgent basis.
Hands on in custom IC EMIR analysis using the Virtuoso Layout Lsuite.
EXPERIENCE
Product Engineer | Cadence Design Systems Inc. (Noida, India)
August 2021 – Present
Developing specifications for new product features.
Debugging tool issues, providing workarounds, file & track code change requests.
Writes & execute testing plans, protocols & helps validate specific products on customer test cases and evaluates it results.
Well versed with Voltus from basic to advanced flows like static/dynamic power & EMIR analysis, Chip Package co-analysis, ESD
analysis, Rush current analysis, xPGV modelling, selfheat analysis, effective resistance analysis and lot more.
Practiced numerous small designs creation inhouse: Multi-die, Custom IC, Low Power digital designs having clock & power gates.
Patent & Research
Vectorless new_modelling algorithm.(under progress)
-Algorithm to detect the worst events which can cause highest dynamic ir drop, use it to detect the weakness of grid asap.
Thermal hotspot Mitigation.(under progress)
-Idenifying the early thermal hotspot & then apply the mitigation techniques based on feedback from voltus to innovus.
Flows /Tools Exposure
• Thermal Analysis(VOLTUS (EMIR TOOL))
- Root level analysis of temperature impact on Resistance & EM on various customer designs
- Developing Spec for supporting merging of powermap & Enabling Early stage Chip Temperature Map identification.
- Created Python Scripts to mantain the quality of results builds to builds with TAT to process 10M lines in 5min.
- Setup regression flows for features coverage of thermal & Self Heating flows with their automated validation with python.
• Vectorless_power
2
-Validated power & rail results identifying the scheduling & corresponding switching time for multiple_user_defined_activity & twf.
-Created scripts to get cyclewise_instance_switching report for every type of cells(i.e seq,comb,clkcomb etc) process 10M lines in 5min
• 3DIC_Validation
-Converted single_die designs into multi_die with interposer & die_stack_mapping_file.
-Validation of reff & rlrp path tracing of multi_die designs with pkg substrate.
• Automation
-Created multiple python scripts to improve TAT for debugging.
-Thermal_power_map & metal_density QA
-SelfHeat reports QA
-n number macro_based_deisgn creation script with mention -n <number> it can create rtl2gds processs with design having n macros
. -Cycle_wise_coverage script helps in giving instance switching info cyclewise with each category differentiated based on cell types.
-avgToggleRate script to get each instance avg toggle_rate.
• RTL2GDS & PDN(genus-innovus-voltus)
-Synthesis, floor-planning (place-route, power grid creation) and simulation (vectors - vcd, shm, fsdb, phy, saif) of digital blocks
. integrated clock gating cells to experiment and develop the functionalities of static and transient power.
- Created CPF based 2 power_domain designs & done power & rail analysis on it.
- Evaluating switching, power reporting and dynamic current waveforms, instances voltage drops of inst ances in digital chip by
. computation of energy tables in Non Linear Delay Models (NLDM), Effective Current Source Model (ECSM) and Composite Current .
. Source Model (CCS-P) liberties based on factor of input slew and output load.
- Analyzing violations reported based on current density during electromigration (EM) analysis in signal and power/ground nets of . .
. design chip w.r.t to EM rules mentioned in technology file & created scripts to get the layerwise worst resistor segments.
• Virtuoso_layout_editor
-Created Custom layouts to improve extraction on RDL Layer to debug false em violation & false resistor fracturing
EDUCATION
B. Tech. in Electronics & Communication| JC Bose University of science and technology (YMCAUST ), Faridabad,
Haryana
AUG 2017 – MAY 2021, GRADE: 8.28
During my undergrad, my major area of work was embedded system design. I worked on various small/medium scale projects collaboratively.
Participated in various national-level competitions to outperform/enhance my skills and knowledge. Conducted numerous free workshops on
system design & embedded programming (Altium PCB editor, Arduino, Python, Network analysis).
SKILLS
Research Grep, Sed & AWK C (ANSI C99) Python
Linux Shell scripting TCL Verilog
Software tools
VOLTUS INNOVUS VIRTUOSO TEMPUS
LANGUAGES KNOWN
English (Professional), Hindi (native)
HOBBIES
Table Tennis, Knowledge sharing via Teaching, Singing
