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Lecture 3 VLSI Technology

VLSI process for MOSFETs involves growing a thick field oxide on the substrate, then doping the source and drain regions. Originally, P-MOSFETs were fabricated first due to process limitations in controlling threshold voltages, but with advances like ion implantation, N-MOSFETs became possible. Polysilicon-based MOSFETs were developed using a self-aligned gate technique that simplified processing compared to metal-gate designs.

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0% found this document useful (0 votes)
86 views27 pages

Lecture 3 VLSI Technology

VLSI process for MOSFETs involves growing a thick field oxide on the substrate, then doping the source and drain regions. Originally, P-MOSFETs were fabricated first due to process limitations in controlling threshold voltages, but with advances like ion implantation, N-MOSFETs became possible. Polysilicon-based MOSFETs were developed using a self-aligned gate technique that simplified processing compared to metal-gate designs.

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VLSI Technology

Lecture 3

VLSI process for MOSFET

Dr. Brajendra Singh Sengar (PhD, IIT Indore)


Assistant Professor
Department of Electronics and Communication Engineering
National Institute of Technology Srinagar
Email id: [email protected]
VLSI Technology

BJT
• High speed

MOSFET
• High density

BICMOS
MOSFET

Field S, D Gate Metal


Oxide Doping Doping Contacts
• Take a Substrate.
Field Oxide • Grow a thick oxide

n
Using Photolithography
• Opening of window
Source and Drain
• Doped region extend laterally as well (precise doping is
doping difficult)

P+
Further Oxidation

P+
• Already oxide?, why we need oxide
Gate Oxidation

1. Field oxide is very thick (>800 nm).


2. Gate oxide is very thin (<100 nm).
3. Role of filed oxide is Masking so quality is not important.
4. Gate oxide quality is very important.
Gate
Oxidation

P+
Metal Contacts

P+
In comparison to BJT. MOSFET are very simple
but the controlling is very difficult
Why we made P-MOSFET?

MOSFET

Depletion mode Enhancement mode


(normally on) (normally off)

P MOSFET fabricated first in the integrated circuit technology?


Why we made P-MOSFET?

Depletion mode Enhancement mode


(normally on) (normally off)

N type,-Ve P type,+Ve N type,+Ve P type,-Ve


threshold threshold threshold threshold
needed for needed for needed for needed for
turning off turning off turning ON turning ON
Why we made P-MOSFET?
For Digital circuits we want enhancement MOSFET

Enhancement mode
(normally off)

N type,+Ve P type,-Ve threshold


threshold needed needed for turning
for turning ON ON
Why we made P-MOSFET?

Threshold voltage depends on the gate oxide thickness, on the


substrate doping concentration, Type of metals, so many things.

Controllable to some extent

During process, which are very difficult to control and there are
unwanted charges in the oxide (+ve charges).

How to counter this charge (by applying negative threshold).


Why we made P-MOSFET?

Example: Vth of n type enhancement MOSFET = 0.7.

Due to charge oxide, Vth of nMosfet become = -0.7.

This works as a n-type Depletion device.


Why we made P-MOSFET?

Example: Vth of p type enhancement Mosfet = - 0.7.

Due to charge oxide, Vth of nMosfet become = -1.7.

This still works as a p-type enhancement device.


N-MOSFET

With the advancement of technology, it was possible to make quality oxide then it
become possible to fabricate N-MOSFET

New doping techniques comes as well. ION Implantation

Threshold tailoring implant

Possible to change threshold easily

Impossible to realize MOSFET without Ion implantation. BJT is possible without Ion
implantation
Polysilicon based MOSFET

Gate Gate
Field CVD +
Oxide
Oxide + Pattern +
Metal
Poly S and D
Polysilicon based MOSFET

Field
Oxide

n
Polysilicon based MOSFET
Gate
Oxide +
Poly

p
Polysilicon based MOSFET
Etching
of Poly
except at
Gate

p
Polysilicon based MOSFET

S and D

Do not even need a masking step, because you see your field oxide is
much thicker than your gate oxide. So, just a quick dip in hydrofluoric
acid will remove the thin oxide from these regions, while it will not
materially affect the thicker field oxide.

Mask not needed in order to realize your source and drain.

Self aligned technique where the source and drain are automatically aligned
to the channel region of the MOSFET
Mask Design for Metal Vs Polysilicon based
MOSFET

S D
Mask Design for Metal Vs Polysilicon based
MOSFET
Gate Oxide Mask must Overlap with the Source and Drain

S D
Mask Design for Metal Vs Polysilicon based
MOSFET
Problem with this Design

1. As we shrink the device dimension


alignment becomes very difficult S G D
Metal Vs Polysilicon based MOSFET

Problem with Metal Gate Technology

1. The Gate oxidation should be pre final Steps (need to deposit S and D
before Gate): Aluminium (low melting point)

2. After Al deposition no high temp processing is allowed.

3. All the IC process has high temp requirement.

4. By replacing Metal with Poly this disadvantage can be prevented.


Thanks

27

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