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Virtex-II Pro and Virtex-II Pro X FPGA User Guide

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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. 20022007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

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Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v4.2) 5 November 2007
The following table shows the revision history for this document. All revision publications are electronic only (PDF) unless otherwise noted. Version 01/31/02 10/14/02 12/04/02 01/23/03 1.0 2.0 2.1 2.2 (Print Edition.) Initial Xilinx release. (Print Edition.) Updated and reprinted. New Virtex-II Pro family members and packages. Revised I/O support information. Added full support for 3.3V I/O standards PCI-X, LVTTL, and LVCMOS33. Added wire-bond package FG676 for XC2VP20, 30, and 40. New package diagram (Figure 5-66) and pinout diagrams (Figure 5-11 through Figure 5-15). Revised Table 5-6. Removed pinout diagrams and other references for XC2VP40FF1517. Revised material in, and added Figure 4-4 to, section Mixed Voltage Environments, page 298. Clariified explanation of banks 4/5 VCCO settings for configuration vs. operation in section Special VCCO Requirements during Configuration and Readback, page 299. Table 3-37, Table 3-38: Corrected package type FG672 to FF672, and added package type FG676. Deleted (former) Table 3-3, Power-Up Timing Characteristics, and replaced it with a hyperlink to Data Sheet Module 3. Deleted (former) Table 1-5, Multiplier Switching Characteristics, and replaced it with a hyperlink to Data Sheet Module 3. Changed attribute CLOCK_FEEDBACK to CLK_FEEDBACK. Clarifying text added to section Phase Shift Enable - PSEN in Chapter 3. Additional implementation rule added to section DCI in Virtex-II Pro/Virtex-II Pro X Hardware in Chapter 3. Corrections made in command line, key file, and key file command line equivalent in section Creating Keys in Chapter 3. Added device-specific parameters to step 16 of Single Device Configuration Sequence in Chapter 4. Section Master SelectMAP Data Loading in Chapter 4: Corrected maximum frequency for SelectMAP configuration without BUSY handshaking to 5 MHz. Table 4-8: Corrected maximum SelectMAP frequency (FCC_SELECTMAP ) to 50 MHz. Appendix A, BitGen and PROMGen Switches and Options: Updated all commandline options to correlate with development tools and their documentation. Table 3-58: Added numerous LVDS primitives to this table, including new differential termination primitives. Added new section LVDS Input HDL Examples. Changed Figure 3-119 to show internal rather than external differential input termination. Various minor edits. Revision

04/11/03

2.3

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Version 06/30/03 2.4

Revision Corrected Location Constraints syntax, multiple instances. Added Figure 3-23, page 91 and associated explanatory text. Added HDL code for resetting the DCM after configuration in section External Feedback, page 93. Modified Banking Rules in section DCI in Virtex-II Pro/Virtex-II Pro X Hardware, page 236. Added reference to Answer Record 13012 in section SSTL2_ I_DCI, SSTL2_II_DCI, page 238. Corrected command-line equivalent statements for bitstream encryption key files in section Creating Keys, page 270. Added new section SelectMAP ABORT Sequence and ABORT Recovery, page 316, to section Master SelectMAP Programming Mode. Corrected shading property of GND pin in symbol key, all diagrams, section Pinout Diagrams, page 397. Numerous additional minor edits. Figure 3-59, page 158: Added missing connection between second LUT of Slice 3 and first LUT of Slice 2. Figure 3-72, page 180: Corrected bit numbers on inputs to adder. Section Routing with BlockRAM, page 184 added. Table 3-36, page 202: Added SSO parameters for HSTL18 I/O standards. Figure 3-90, page 215: Correct VREF from 0.75V to 0.9V. Section DCI I/O Buffer Library Components, page 231, added IBUFG_LVDS components to list. Section Location Constraints, page 251: Added constraint on locating a DDR register next to an SDR register using a different clock. Appendix C, Choosing the Battery for VBATT added, with linked reference in section VBATT, page 272. Page 292: added paragraph at end of Introduction to Configuration chapter specifying a fixed voltage tie for mode pins M0-M2, and warning not to toggle these pins during or after configuration. Table 4-2, page 292: Reduced configuration bitstream lengths for all devices by 64 bits. Section Configuration Pins, page 296: Added warning and constraints regarding application of 3.3V signals to dedicated configuration pins. Table 4-3, page 297: Corrected directionality of BUSY/DOUT to Output, INIT_B to Input/Output. Updated with data from XAPP659. Former Table 4-6, Master/Slave Serial Mode Programming Switching, and former Table 4-8, SelectMAP Write Timing Characteristics, removed. See the Virtex-II Pro / Virtex-II Pro X Data Sheet, DC and Switching Characteristics for these and all other timing parameter specifications. Table 4-6, page 302: Corrected FCC_SERIAL from 66 MHz to 50 MHz. Added footnote to Figure 4-9, page 305, and Figure 4-11, page 307, clarifying that DOUT transitions on the falling edge of CCLK. Second paragraph below Figure 4-13, page 311: Corrected maximum no-handshake SelectMAP configuration speed from 5 MHz to 50 MHz. Section Master SelectMAP Data Loading, page 311: Changed wording to emphasize that if RDWR_B is toggled while CS_B is still asserted, a configuration abort will occur.

02/02/04

2.5

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Version 02/02/04 (contd) 2.5 (contd)

Revision Section Express-Style Loading, page 308: Added new text to clarify the sequencing of signals before, during, and after data loading. Page 322: added text to TDO paragraph indicating that pin is open-drain and should be pulled up externally. Table 4-13, page 331: Updated Total No. of Bits column with new numbers. Figure 5-53, page 457; Figure 5-54, page 458; Figure 5-55, page 459; and Figure 5-56, page 460: Corrected banking assignments for pins AB12 and AB31. Now shows these pins in Banks 2 and 7 respectively. Table 5-1, page New Thermal Data Table 5-3: Changed Theta-JC to 0.5C/Watt for all FF packages. Section Crosstalk, page 488: Clarified wording of PCB trace routing guidelines to minimize crosstalk onto VREF lines. Section Digital Clock Managers (DCMs) in Chapter 3: Removed all referrals to CLK2X as an option in implementing a clock feedback loop for the DCM, including: Removed former Figures 3-25, 3-27, and 3-39, which showed schematics of CLK2X feedback implementation. Section Attributes, page 97: Removed section Feedback Input discussing the CLK_FEEDBACK attribute, which was used to designate CLK2X as the feedback clock. Table 3-9, page 114: Removed CLK_FEEDBACK from the table of attributes. Section VHDL and Verilog Instantiation, page 115: Removed BUFG_ CLK2X_SUBM, BUFG_CLK2X_FB_SUBM, and BUFG_PHASE_CLK2X_SUBM from the list of available DCM submodules. Page 179: Added registered multiplier primitive to table Table 3-26, new schematic of both multiplier primitives (Figure 3-71), and explanatory text. Table 3-36, page 202: Added LVPECL_25 and BLVDS_25 to table. Table 3-38, page 206: Added referral to XAPP689 for managing ground bounce. Section DCI I/O Buffer Library Components, page 231: Removed all LVDS_33_DCI and LVDSEXT_33_DCI components from listing. Section Creating a Bidirectional LVDS Buffer, page 264, and Creating an LVPECL Output Buffer, page 267: Added referral to Table 3-36 for SSO guidelines. Section Bitstream Encryption, page 269: Added referral to Appendix C, Choosing the Battery for VBATT. Section Creating Keys (end): Added material discussing use of CBC initial value to safeguard bitstream security. Table 4-3, page 297: Mode pins (M0, M1, M2) not to be connected to 3.3V unless through a 100 resistor. VBATT pin to be connected to GND or VCCAUX when bitstream encryption not used. Section Frame Length Register (FLR), page 333: Added minus one word to the description of the value to be loaded into this register. Former Table 4-3, Power-Up Timing Configuration Signals, removed. See the Virtex-II Pro Platform FPGA Data Sheet, DC and Switching Characteristics for these and all other timing parameter specifications. Section Test Access Port, page 321: Added mention of implementation tool pull-up, pull-down, and float options on TMS and TDI pins. Updated DS026 in Appendix B, Platform Flash Family PROMs to v5.0. Various edits and deletions in Glossary.

04/19/04

2.6

UG012 (v4.2) 5 November 2007

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Product Not Recommended for New Designs

Version 04/19/04 (contd) 2.6 (contd)

Revision Edits throughout to synchronize/align User Guide with Data Sheet Table 1. Updated DS026 in Appendix B, Platform Flash Family PROMs to v5.0. Various edits and deletions in Glossary. Edits throughout to synchronize/align User Guide with Data Sheet Table 1.

06/02/04

2.6.1

Table 4-3, page 297: Corrected BUSY/DOUT from Input to Output. Corrected INIT_B from Input to Input/Output. Removed redundant entries for CCLK and PROG_B. Revised throughout with updated tables, text, pinout diagrams, and hyperlinks to include two new devices, Virtex-II Pro X XC2VPX20 and XC2VPX70, which feature the RocketIO X 10.3125 Gb/s MGT. Revised throughout with updated tables, text, and package diagrams to include new Pb-free packaging options FGG256, FGG456, and FGG676. Section Frequency Synthesized Clock Output - CLKFX, page 101: Added text indicating no CLKFX phase alignment when the CLKIN frequency is below 24 Mhz. Section Phase Shift Characteristics, page 105: Added substantial detailed material related to calculating and controlling the desired phase shift. Table 3-29, page 187: Added clarifying example to Footnote (2) regarding GTL/GTLP VCCO lower limit. Section Daisy-Chain Configuration, page 303: Revised text to clarify daisy-chain options for strings of different Xilinx FPGA devices. Section RDWR_B, page 305: Revised text to clarify the status of the data bus when RDWR_B is High and Low. Table 4-16, page 331: Revised step 5 to give XC2VP2 its own TDI code, and step 6 to correct the TDI code from 1 to 0. Corrected Footnote (1) to say data and instruction. Chapter 4, Configuration: This chapter has been expanded and completely updated with new material. Since most of the material is newly written, specific changes in this chapter are not recorded in the Revision History. Section BUFG Exclusivity, page 75: Corrected numbering of exclusive buffer pairs. Figure 3-23, page 91: Added note on when to reset the DCM. Section Fixed-Mode Phase Shifting in Certain Virtex-II Pro Devices, page 106: Added link to Solution Record 13349. Table 3-9, page 114: From Description for CLKIN_DIVIDE_BY_2, removed text specifying an upper frequency limit for using this attribute to divide the DCM input clock by 2. Section Embedded Multipliers, page 178: Deleted subsection Two Multipliers in a Single Primitive. Deleted references to DUAL_MULT_* templates. Section Output Drive Source Voltage (VCCO) Pins, page 199: Added text recommending that VCCO be powered for all I/O standards. Table 3-36, page 202: Corrected number of SSOs for the following standards: GTL_DCI, GTLP_DCI, HSTLII_DCI, SSTL18_II, LVPECL_25, BLVDS_25. Added the following standards: DIFF_HSTL_II, DIFF_HSTL_II_DCI, DIFF_HSTL_II_18, DIFF_HSTL_II_18_ DCI, DIFF_SSTL_II, DIFF_SSTL_II_DCI, DIFF_SSTL_II_18, DIFF_SSTL_II_18_ DCI. Section DCI in Virtex-II Pro/Virtex-II Pro X Hardware, page 236: Added step 8. Added Figure 3-109, page 242.

08/05/04

3.0

03/07/05

4.0

Virtex-II Pro and Virtex-II Pro X FPGA User Guide

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Version 03/07/05 (contd) 4.0 (contd)

Revision Code template DDR_input.v, page 253: Removed assign data_out = q1 & q2 just before endmodule. Section LVDS I/O, page 258: Replaced Table 3-58, Available LVDS Primitives with new Table 3-58, Available LVDS Standards. Section Loading Encrypted Bitstreams, page 272: Corrected reference to JTAG JSTART instruction to JTAG JPROG_B. Added new section Temperature-Sensing Diode (DXP/DXN), page 273. Corrected pinout diagram FF672 Composite Pinout Diagram (XC2VP4) (Figure 5-19, page 420). Previously, this figure had shown the composite pinout diagram for the FF672/XC2VP7 device. Section Design Examples, page 521 (Appendix C): Deleted text and illustration that incorrectly suggested different battery voltage compliance requirements for Virtex-II and Virtex-II Pro BBRAM power pin. Added new section Cascading DCMs, page 95. Feedback Clock Input CLKFB, page 96: Added information regarding when CLK_FEEDBACK must be set to NONE. Reset Input RST, page 101 andReset Input RST, page 111 : Corrected hold time from 2 ns to 3 clock cycles. Port Signals, page 108: Corrected paragraph regarding DUTY_CYCLE_CORRECTION attribute. Data Flow, page 123: Added paragraph requiring block RAM address setup/hold times to be met if port is enabled, even if data is of no interest. Table 3-54 (LVCMOS15) and Table 3-55, page 222 (LVCMOS18): Updated voltage level definitions and values. Xilinx DCI, page 224: Added material clarifying the effect on DCI outputs of leaving VRN/VRP disconnected. Xilinx DCI, page 224: Removed reference to FreezeDCI. DCI in Virtex-II Pro/Virtex-II Pro X Hardware, page 236: Modified point 3 detailing when VRP/VRN reference resistors are not required. Location Constraints, page 251: Deleted last paragraph, incorrect. Differential Termination LVDS Input HDL Examples, page 260: Replaced VHDL and Verilog instantiation examples. Chapter 4, Configuration: Corrected various typographical errors. Device Startup, page 295: Added requirement of 5-10 CCLK cycles after DONE is released. Figure 4-5: Added pull-up resistor to INIT_B signal. Deleted section Using XC17V00 PROMs. Obsolete. Table 5-3: Added Pb-free package names. Corrected errors in row/column headings. (No change to values.) Figure 5-65, Figure 5-70: Replaced FG456/FGG456 and FF1148/FFG1148 package drawings with updated versions.

03/28/07

4.1

UG012 (v4.2) 5 November 2007

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Virtex-II Pro and Virtex-II Pro X FPGA User Guide

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Version 11/05/07 4.2

Revision Added footnote regarding LVDS receiver differential termination to _DT standards in Table 3-58 and Table 3-59. Table 4-28: Corrected bit assignments for MATCH_CYCLE and LOCK_CYCLE. Table 4-16: Added new Step 13. Configuration Memory Read Procedure (1149.1 JTAG), page 374: Added new steps 5(b) and 5(c); corrected step 5(g) [formerly 5(e)]. Updated legal disclaimer. Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1149.1, page 321: Updated IEEE 1149.1 compliance statement.

Virtex-II Pro and Virtex-II Pro X FPGA User Guide

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Table of Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 1: The Virtex-II Pro / Virtex-II Pro X FPGA Family

The Next Logical Revolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Built for Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Legacy of Leadership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packets Everywhere . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge, Anyone? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplifying Complexity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Is Money . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flexibility Is Money . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Not Being Discrete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21 21 22 23 23 24 24 25 25

Chapter 2: Timing Models

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CLB / Slice Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
General Slice Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Slice Distributed RAM Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 31 Slice SRL Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Block SelectRAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded Multiplier Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 IOB Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IOB Input Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 IOB Output Timing Model and Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 IOB 3-State Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Pin-to-Pin Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Global Clock Input to Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Global Clock Setup and Hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Digital Clock Manager Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Operating Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Clock Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous DCM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 62 63 63

Additional Timing Models in Other Publications: PPC405 Processor Block and RocketIO/RocketIO X Transceivers . . . . . . . . . . 65

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R

IBM PPC405 Processor Block Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 RocketIO Transceiver Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 RocketIO X Transceiver Timing Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Chapter 3: Design Considerations

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RocketIO and RocketIO X Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Distribution Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 67 68 68 68 68 69 78 79 83 84 84 84

Digital Clock Managers (DCMs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Clock De-Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Legacy Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Frequency Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DCM Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Block SelectRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Dual-Port and Single-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization in VHDL or Verilog Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ports Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization in VHDL or Verilog Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 123 127 127 130 130 132 132 134 134 134 135 141 143 143 144 145 145 146 146 148 149

Distributed SelectRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Look-Up Tables as Shift Registers (SRLs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

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Shift Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization in VHDL and Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fully Synchronous Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static-Length Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-II Pro/Virtex-II Pro X CLB Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wide-Input Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-II Pro/Virtex-II Pro X CLB Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Twos-Complement Signed Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing with BlockRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of Supported I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx DCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCI in Virtex-II Pro/Virtex-II Pro X Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

151 153 153 156 156 157 157 158 159 160 162 162 166 166 167 167 168 168 172 172 173 174 174 178 179 179 183 183 183 184 185 186 186 187 188 190 199 207 224 224 231 236 243 243 249 249

Large Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Sum of Products (SOP) Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Embedded Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Single-Ended SelectIO-Ultra Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Digitally Controlled Impedance (DCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Double-Data-Rate (DDR) I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

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VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization in VHDL or Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an LVDS Input/Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an LVDS Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an LVDS Output 3-State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Bidirectional LVDS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDT Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

250 250 251 251 251 252 258 258 262 263 264 265 265

LVDS I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

LVPECL I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Creating an LVPECL Input/Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Creating an LVPECL Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Bitstream Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

What DES Is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How Triple DES is Different. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classification and Export Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading Encrypted Bitstreams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature-Sensing Diode (DXP/DXN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The CORE Generator System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORE Generator Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Core Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx IP Solutions and the IP Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORE Generator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-II Pro/Virtex-II Pro X IP Cores Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 269 270 270 272 272 272 273 274 274 276 276 278 281 281

CORE Generator System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Chapter 4: Configuration
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Process and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed Voltage Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System ACE CF (CompactFlash) Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash PROMs With a CPLD Configuration Controller. . . . . . . . . . . . . . . . . . . . . . . . . Embedded Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM and System ACE CF Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 293 296 298 299 300 301 302 303

Configuration Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Software Support and Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

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Programming Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Boundary Scan Interconnect Testing for Virtex-II Pro Devices. . . . . . . . . . . . . . . . . . 304 In-System Programming Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Serial Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Master Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Slave Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

SelectMAP Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Master SelectMAP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Slave SelectMAP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

SelectMAP ABORT Sequence and ABORT Recovery . . . . . . . . . . . . . . . . . . . . . . . 316

Triggering an ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 ABORT Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 ABORT Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Internal Configuration Access Port (ICAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 JTAG / Boundary-Scan Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1149.1 . . . . . . . . . . . Using Boundary Scan in Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1532 . . . . . . . . . . . . Configuration Flows Using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory: Columns and Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPC405 and MGT Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bitstream Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing a Design for Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying Readback Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using ChipScope ILA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 321 329 335 337 339 341 341 342 343 356 361 367 368 379 379 382 383

Configuration Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Chapter 5: PCB Design Considerations

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Pinout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 FG256/FGG256 Fine-Pitch BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

FG256/FGG256 Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG456/FGG456 Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG676/FGG676 Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF672 Flip-Chip Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . FF896 Flip-Chip Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . FF1152 Flip-Chip Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . FF1148 Flip-Chip Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . FF1517 Flip-Chip Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 399 403 411 417 425 433 445 451

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FF1704 Flip-Chip Fine-Pitch BGA Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

FG256/FGG256 Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . . FG456/FGG456 Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . . FG676/FGG676 Fine-Pitch BGA Package (1.00mm pitch) . . . . . . . . . . . . . . . . . . . . . . FF672 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . . FF896 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . . FF1152 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . FF1148 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . FF1517 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . FF1704 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . FF1696 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) . . . . . . . . . . . . . . . . . . . . 470 471 472 473 474 475 476 477 478 479

Flip-Chip Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

Advantages of Flip-Chip Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 Thermal Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Printed Circuit Board Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 VCC Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

Board Routability Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Board-Level BGA Routing Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Board Routing Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

XPower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

Using IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBIS Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advantages of IBIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBIS File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBIS I/V and dV/dt Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ramp and dV/dt Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx IBIS Package Parasitic Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBIS Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IBIS Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx IBIS Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANSI/EIA IBIS Official Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 496 496 496 497 497 498 498 499 500 500

BSDL and Boundary Scan Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

BSDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

Appendix A: BitGen and PROMGen Switches and Options

Using BitGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
BitGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 BitGen Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 BitGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Using PROMGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

PROMGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROMGen Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROMGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 510 511 514

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Appendix B: Platform Flash Family PROMs

PROM Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
FS48 Package Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 VO48 Package Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 VO20 Package Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Appendix C: Choosing the Battery for VBATT

Battery Types and Chemistry Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Primary or Secondary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Battery Cost and Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 Battery Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Case #1: Case #2: Case #3: Case #4: ................................................................ ................................................................ ................................................................ ................................................................ 521 521 521 522 523 553

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Preface

About This Guide

This document, the Virtex-II Pro and Virtex-II Pro X FPGA User Guide, describes the function and operation of Virtex-II Pro and Virtex-II Pro X devices, and also includes information on FPGA configuration techniques and PCB design considerations. It comprises the following main sections:

Guide Contents
Chapter 1, The Virtex-II Pro / Virtex-II Pro X FPGA Family Chapter 2, Timing Models Chapter 3, Design Considerations Chapter 4, Configuration Chapter 5, PCB Design Considerations Appendix A, BitGen and PROMGen Switches and Options Appendix B, Platform Flash Family PROMs Appendix C, Choosing the Battery for VBATT Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet

For Virtex-II Pro device specifications, refer to the Virtex-II Pro Data Sheet:

The following documents offer in-depth technical design information about the RocketIO and RocketIO X multi-gigabit transceivers and PowerPC 405 processor, which are not covered in this User Guide: RocketIO Transceiver User Guide RocketIO X Transceiver User Guide PowerPC Processor Reference Guide PowerPC 405 Processor Block Reference Guide

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Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource Data Sheets Description/URL Xilinx data sheets describe device-specific operating characteristics, architecture, and pinouts/packaging. http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp Xilinx user guides contain detailed, device-specific operating theory and generic design examples for various device functions. http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?categor y=User+Guides Application Notes Xilinx application notes describe design techniques and approaches to general design as well as specific applications. Many application notes feature complete reference designs including source code. http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?categor y=Application+Notes Xcell Journals Tech Tips This site contains quarterly journals for Xilinx programmable logic users. http://www.xilinx.com/xcell/xcell.htm See this site for the latest news, design tips, and patch information on the Xilinx design environment. http://www.xilinx.com/support/techsup/journals/index.htm Answers Database This database provides a current listing of solution records for Xilinx software tools. Search this database using the search function at: http://www.xilinx.com/support/searchtd.htm

User Guides

Conventions
This document uses the following conventions. An example illustrates each convention.

Typographical
The following typographical conventions are used in this document: Convention Courier font Meaning or Use Messages, prompts, and program files that the system displays Literal commands that you enter in a syntactical statement Commands that you select from a menu Keyboard shortcuts Example speed grade: - 100

Courier bold

ngdbuild design_name File Open Ctrl+C

Helvetica bold

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Convention

Meaning or Use Variables in a syntax statement for which you must supply values. (In angle brackets.)

Example

ngdbuild <design_name>

Italic font

References to other manuals

See the Development System Reference Guide for more information. If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. ngdbuild [option_name] design_name

Emphasis in text An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required. A list of items from which you must choose one or more | Separates items in a list of choices

Square brackets

[ ]

Braces

{ }

lowpwr ={on|off} lowpwr ={on|off} IOB #1: Name = QOUT IOB #2: Name = CLKIN . . . allow block block_name loc1 loc2 ... locn;

Vertical bar

Vertical ellipsis . . . Horizontal ellipsis . . .

Repetitive material that has been omitted

Repetitive material that has been omitted

Online Document
The following conventions are used in this document: Convention Meaning or Use Cross-reference link to a location in the current document Cross-reference link to a location in another document Hyperlink to a website (URL) Example See the section Additional Resources for details. Refer to Title Formats in Chapter 1 for details. See Figure 2-5 in the Virtex-II Handbook. Go to http://www.xilinx.com for the latest speed files.

Blue text

Red text Blue, underlined text

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Chapter 1

The Virtex-II Pro / Virtex-II Pro X FPGA Family

The Next Logical Revolution
The Virtex-II Pro/Virtex-II Pro X Platform FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry. The goal was to revolutionize system architecture "from the ground up." To achieve that objective, the best circuit engineers and system architects from IBM, Mindspeed, and Xilinx co-developed the world's most advanced Platform FPGA silicon product. Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled this new system architecture paradigm. The result is the first Platform FPGA solution capable of implementing high performance system-on-a-chip designs previously the exclusive domain of custom ASICs, yet with the flexibility and low development cost of programmable logic. The Virtex-II Pro/Virtex-II Pro X family marks the first paradigm change from programmable logic to programmable systems, with profound implications for leading-edge system architectures in networking applications, deeply embedded systems, and digital signal processing systems. It allows custom user-defined system architectures to be synthesized, next-generation connectivity standards to be seamlessly bridged, and complex hardware and software systems to be co-developed rapidly with insystem debug at system speeds. Together, these capabilities usher in the next programmable logic revolution.

Built for Bandwidth

The Virtex-II Pro/Virtex-II Pro X family consists of eleven members. The nine Virtex-II Pro devices contain four to twenty RocketIO multi-gigabit transceivers (MGTs), while the two Virtex-II Pro X devices contain eight or twenty RocketIO X MGTs. Each Xilinx RocketIO/RocketIO X transceiver block contains a complete set of user-configurable supporting circuitry that addresses real-life, system-level challenges. These include standard 8B/10B encode/decode (plus 64B/66B encode/decode in the RocketIO X), programmable signal integrity adjustments for varying PCB trace lengths and materials, support for synchronization of multiple channels, and programmable support for channel control commands. In addition, the RocketIO and RocketIO X blocks are the first FPGAembedded transceivers to reach baud rates of 3.125 Gbps and 10.3125 Gbps, respectively. Four RocketIO transceivers, employing sixteen PCB traces, can be used to support a fullduplex 10 Gbps channel by way of the RocketIO channel-bonding featureor, a single RocketIO X transceiver can implement the same speed with just four PCB traces. This is equivalent to 256 traces of typical LVTTL buses, or 68 traces of a high-speed, sourcesynchronous parallel LVDS bus. It allows a PCB trace reduction of up to 64X over conventional parallel buses, resulting in significant reductions in PCB complexity and EMI

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system noise. The RocketIO/RocketIO X technology fulfills higher bandwidth system requirements than currently possible, with cost savings coming from faster time-tomarket, reduced printed circuit board (PCB) complexity, and lower component count. Each of the larger devices incorporates one or two small yet powerful IBM PowerPC 405 processor cores, each capable of more than 300 MHz clock frequency and 420 Dhrystone MIPS. While the processor cores occupy a small area of the die, they provide tremendous system flexibility where they are used. The PowerPC 405 cores are fully embedded within the FPGA fabric, where all processor nodes are controlled by the FPGA routing resources. This provides the utmost architectural capability, where complex applications may be efficiently divided between high-speed logic implementation and high-flexibility software implementations. For example, a packet processing application using only the FPGA logic today for high-speed packet routing may be augmented to include a slave high-performance processor for exception handling or in-system statistics monitoring. In contrast, using a separate processor externally requires hundreds of additional interface pins, which degrades system performance and significantly increases FPGA I/O requirements and overall board costs. The Virtex-II Pro/Virtex-II Pro X products are based on the most advanced FPGA fabric available: the Virtex-II architecture with IP-Immersion technology, which was developed to offer significant improvements in engineering productivity, silicon efficiency, and system flexibility. Unique features common in the Virtex-II Seriesconsisting of the Virtex-II and Virtex-II Pro familiesinclude powerful SystemIO system connectivity solutions, digitally controlled impedance (DCI) technology, comprehensive clocking solutions, high-speed Active Interconnect routing architecture, and bitstream encryption. These features together constitute the most complete Platform FPGA solution available, optimized for high performance system-level applications. The upward compatibility of the Virtex Series of products ensures benefits in engineering productivity, performance, design longevity, and continuing cost reduction.

Legacy of Leadership
Each of the Virtex families of FPGAs has been the most successful programmable product family in its class, starting with the introduction of the original Virtex family in 1998. The Virtex and Virtex-E families were recognized by the industry as the highest technology products available when they were first introduced. The Virtex-II family, which again achieved technology leadership in density, performance, and features, ushered in the era of Platform FPGAsprogrammable devices with the system-level capability and performance to implement systems functionality. The Virtex-II Pro family continues the tradition of technology leadership as the most sophisticated Platform FPGA yet, again breaking the technology barrier for the benefit of leading-edge system architects. The Virtex-II Pro/Virtex-II Pro X family is the first FPGA family to incorporate both serial transceiver technology and a hard processor core within a general-purpose FPGA device. This is significant for new high-bandwidth embedded processing applications such as packet processing, where both high device I/O bandwidth and high performance processor cores are needed together. The Virtex-II Pro/Virtex-II Pro X devices are the industry's first FPGAs in a 0.13-micron process. The nine-layer metal, all-copper, low-k process technology is among the most advanced in the semiconductor industry. The combination of advanced Active Interconnect architecture and advanced process technology makes the Virtex-II Pro/Virtex-II Pro X family the highest performance FPGA in the world. The RocketIO/RocketIO X multi-gigabit MGTs are the highest performance, most complete embedded serial transceivers available. They are user-configurable for up to

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Packets Everywhere
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3.125 Gbps or 10.3125 Gbps baud rate per channel, which is many times the performance of other embedded transceivers at 1.25 Gbps. Each RocketIO/RocketIO X transceiver provides a complete set of common functionality available in standard SerDes transceivers. In contrast, "programmable ASSP" products with clock/data recovery (CDR) provide only the most basic transceiver capability. The IBM PowerPC 405 processor core used in the Virtex-II Pro/Virtex-II Pro X family is the highest performance embedded core available in FPGAs. The PowerPC architecture is used in many markets including communications, industrial control, test and measurement systems, and other performance-oriented markets. It is currently the most popular processor architecture in embedded applications.

Packets Everywhere
The Virtex-II Pro/Virtex-II Pro X family provides a powerful new paradigm for network processing where low latency is required, such as storage area networks, wireless infrastructure, and voice-over-IP networks. The digital convergence phenomenon drives the need for packet routing based on type and priority. For example, live voice and video data packets require significantly lower latency than data file packets. New data networking applications must now handle higher bandwidth traffic as well as more complex types of prioritized packets. In many cases, Virtex-II Pro/Virtex-II Pro X devices can offer higher overall performance than other solutions, including specialized network processors (NPs). Using the Virtex-II Pro architecture, the most common packets may be quickly read and routed using FPGA logic, without incurring the lengthy software runtime needed by NPs. The FPGA logic interrupts the PowerPC processor core only when processor instructions are needed for special packet types. For example, packets may be stored into a 16 KB dual-port memory area accessible by both the FPGA logic and the PowerPC 405 on-chip memory (OCM) port, allowing rapid change of control and packet disposition. By using the FPGA logic to process the most common packet types while the processor core handles the more specialized ones as a slave to the logic, the Virtex-II Pro architecture can provide higher overall performance than NPs, as well as more sophisticated processing capabilities than FPGA logic alone.

Bridge, Anyone?
Powerful protocol bridges for tying together disparate data stream formats are well-suited for the Virtex-II Pro/Virtex-II Pro X solution. New interface standards and protocols include PCI Express, Infiniband, Gigabit Ethernet, XAUI/10 Gigabit Ethernet, RapidIO, and HyperTransport. These must interface seamlessly to one another, as well as to other standards such as PCI, Fibre Channel, POS Phy Level 4, Flexbus 4, and others. This presents a significant challenge to system developers because of changing standards, scarcity of off-the-shelf interface components, and the inflexibility of available solutions. System designers have had to assemble their own blend of FPGAs, discrete physical transceivers, and discrete communications processors to solve their complex system challenges. Even newer "programmable ASSPs" (application-specific standard products) with built-in serial transceivers fall short, because they frequently require companion FPGAs to supplement their logic capacity. The Virtex-II Pro solution, using the powerful Xilinx SystemIO capability to fully integrate silicon, software, and IP capabilities, provides the most flexible pre-engineered protocol bridge solutions available for fast timeto-market and low development cost.

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Simplifying Complexity
The Virtex-II Pro/Virtex-II Pro X solution offers a powerful paradigm for complex embedded systems found in signal processing, industrial control, image processing, networking, communications, and aeronautic applications. For the first time, complex embedded systems traditionally involving sophisticated hardware and software may be developed concurrently, emulated in actual hardware at speed, debugged in-system, and re-architected for performance within weeks, rather than months or years. In addition, full systems can be remotely upgraded as easily as software-only upgrades are performed today, using Compact Flash, CDROM, Internet, wireless transmission, or other flexible means. Hardware design is simplified using powerful development software and a large soft IP library to assemble logic- and processor-based platforms. Software development may be started earlier using the actual device in preconfigured sample platforms, without waiting for the new system board to be developed. In many cases, higher density Virtex-II Pro components may be used for early system development, whereby extra resources (including additional PowerPC processor cores) may be used to easily emulate board-level components yet to be developed. This flexibility, obviously unavailable in custom ASICs or ASSPs, allows systems to be emulated at speed, rather than simulated using software simulators at 100 or 1000 times slower. In-system debugging is further enhanced by the Xilinx ChipScope Pro tool, which provides comprehensive logic analysisfrom probing internal nodes to full bus analysis with bus protocol adherence checks using an external logic analyzer via the IEEE 1149.1 (JTAG) test access port. Using ChipScope Pro can result in orders of magnitude of improvement in engineering productivity. Complex systems can be optimally repartitioned between FPGA logic and processor cores, allowing a continuum of possible trade-offs between the speed of logic and the flexibility of software code. For example, a first implementation of an ec