MODEL QUESTIONS
Flip Flops
1) Draw the logic diagram of clocked „D‟ flip-flop. Write its truth table, characteristic equation,
state diagram and excitation table. What is the drawback of SR flip-flop?
2) Using behavioural model, write Verilog HDL code for a „D‟ flip-flop.
3) With the help of a block diagram Explain the working of a JK Master-Slave flip-flop.
4) Show how a SR flip-flop can be converted to a JK flip-flop.
5) Explain the different types of flip flops along with their truth table.
6) Explain basic SR flip-flop by using NOR gate. What is the drawback of SR flip flop? How JK
flip flop is obtained from SR flip flop?
7) Find out characteristic equations of JK flip-flop and D flip-flop.
8) Explain the working of a JK flip-flop. Write its truth table, state diagram and excitation table.
9) Draw a switch debouncer using a SR latch and show the waveforms of switch bounce and
debounce.
10) Describe
i)Master-slave JK-flip flop
ii)Edge triggered flip flop.
11) Explain the advantages of an edge triggered flip flop over a pulse triggered flip flop.
12) Give state transition diagram of SR,D,JK and T flip flops.
13) What do you mean by characteristic equation of a flip-flop? Derive characteristic equation for
SR flip-flop
.
Registers
14) Draw the logic diagram of a 4 bit serial in serial out shift register using J-K flip flop and explain.
15) Explain briefly serial adder with a neat sketch.
16) Write Verilog code for switched tail counter.
17) With a neat logic and timing diagram explain the working of a SISO register.
18) Design two 4 bit serial Adder.
19) Write the Verilog code for switched tail counter using “assign” and “always” statement.
20) What is a shift register? Draw the logic diagram of a 4 bit serial in serial out shift register using
negative edge triggered JK or D flip flops and explain its operation with the waveform to shift
the binary number 1010 into the register.
21) Explain with logic diagram the use of 8bit SISO shift register in serial addition of two 8bit
numbers.
22) Write verilog HDL code for 4 bit SIPO shift register when all the flip flop outputs are available
externally.
23) Using negative edge trigger JK flip flop, draw the logic diagram of a 4 bit serial in serial out
shift register. Draw the waveform to shift the binary number 1010 into this register. Also draw
the waveform for 4 clock transistor when J=K=0.
24) Explain the working of mod 4 ring counter.
25) Explain with a neat diagram, how shift register can be applied for serial addition.
26) Design 3 bit PISO (Use D flip flop).
27) Design two 4 bit serial adder.
28) Design 4 bit Johnson counter with state table.
29) Using positive edge triggered D flip flops draw the logic diagram for a 4 bit parallel in serial out
shift register and explain its working to load 1001 into it and shift the same.
30) With neat diagram, explain how shift registers can be applied for serial addition.
31) How long will it take to shift an 4 bit PISO shift register that operates at clock frequency of
5MHz. Also what is the time required to extract 4 bit number from PISO operates at %MHz
clock?
32) Write Verilog/VHDL code for Johnson counter.
33) With a neat diagram, explain the working of a 4 bit SISO register.
34) With neat diagram, explain how 7495 can be connected to function as switched tail counter.
35) Write Verilog code for Johnson counter.
36) Using negative edge triggered JK flip flop s draw the logic diagram of a 4 bit serial in serial out
shift register. Draw the waveform to shift the binary number 1010 into this register. Also draw
the waveforms for 4 clock transitions when J=K=0 (assuming the register has stored 1010 in it)
37) How long will it take to shift the hex decimal number „AB‟ into the 54/74164 (SIPO) if 5 MHz
clock is connected to it? Also mention the time required to extract an 8 bit number from the
same register.
38) With the neat diagram explain a 4 bit universal shift register.
39) Write the Verilog code for switched tail counter using “assign” and “always” statement.
