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Memory Interfacing for 8086 CPU

This document discusses memory interfacing with a microprocessor. It describes that memory is characterized by its size and number of data bits. An interface is needed for communication between the memory and microprocessor so they can read and write registers. Memory is organized as arrays that can only access one location at a time, requiring an address of at least log2N bits to access N locations. The document provides an example of interfacing 4KB of RAM and ROM chips with an 8086 microprocessor using address lines and control signals to select the proper bytes or chips.

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Harisankar R N R 21BRS1524
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116 views7 pages

Memory Interfacing for 8086 CPU

This document discusses memory interfacing with a microprocessor. It describes that memory is characterized by its size and number of data bits. An interface is needed for communication between the memory and microprocessor so they can read and write registers. Memory is organized as arrays that can only access one location at a time, requiring an address of at least log2N bits to access N locations. The document provides an example of interfacing 4KB of RAM and ROM chips with an 8086 microprocessor using address lines and control signals to select the proper bytes or chips.

Uploaded by

Harisankar R N R 21BRS1524
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

21-12-2022

 Memory is usually described by its size of storage


and number of data bits
 For example,
 A 32K bytes memory chip is represented by 32K x 8
 A 64K bits memory is represented by 64K x 1

 Interface is the path for communication between two


components. Interfacing is of two types, memory
interfacing and I/O interfacing.
 When we are executing any instruction, we need the
microprocessor to access the memory for reading
instruction codes and the data stored in the memory.
 For this, both the memory and the microprocessor
requires some signals to read from and write to
registers.
 The interfacing circuit therefore should be designed in
such a way that it matches the memory signal
requirements with the signals of the microprocessor.

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21-12-2022

 Semiconductor memories are organized as two


dimensional arrays of memory locations, for
example 4K X 8 , 4K byte memory which contains
4096 locations, where each location contains 8-bit
data. Only one of the 4096 locations can be
selected at a time.
 In general, to address a memory location out of 'N'
memory locations, one would require at least 'n’
bits of address i.e. 'n' address lines where n = log2N
 Hence if the microprocessor has 'n' address lines,
then it is able to address at most N locations of
memory where 2n = N

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21-12-2022

 Arrange the available memory chips so as to obtain 16-bit


data bus width.
 Upper 8-bit bank is called as the "odd address memory
bank" and the lower 8-bit bank is referred to as the "even
address memory bank".
 Now one must connect the available memory address
lines of memory chips with those of the 8086
microprocessor and connect the memory RD and WR
inputs to the corresponding processor control signals.
 BHE, A0 and the rest of the address lines left are used for
decoding the required chip select signals for the odd and
even memory banks.

 G1, G2A and G2B are


enable signals
 To enable 74LS138,
G1 should be high
and G2A and G2B
should be low
 A, B and C are select
lines
 Y0, Y1, ……..Y7 are
output lines
 An output lines goes
low when it is
selected, Other
output lines remain
high

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21-12-2022

 Interface two 4KB EPROMS and two 4KB RAM


chips with 8086, microprocessor and draw the
suitable circuit showing their interfacing.
 The address of the RAM may be selected anywhere
in the 1MB address space of 8086.
 We must first calculate the total number of
address lines required for 8Kbytes of EPROM which
is 13, as we have seen earlier that we have N = 2n
hence, we get 213 = 8K = 23 * 210

 The memory system here contains in total four 4K X 8


memory chips. The two 4K X 8 chips of RAM and ROM
are arranged in parallel to obtain16-bit data bus
width.
 If A0 is 0 i.e. the address is even and is in RAM, then
the lower RAM chip is selected indicating 8-bit
transfer at an even address.
 If A0 is 1, i.e. the address is odd and is in RAM the
BHE goes low , the upper RAM chip is selected,
further indicating that the 8-bit transfer is at an odd
address. If the selected addresses are in ROM, the
respective ROM chips are selected.
 If at a time A0 and BHE both are 0, both the RAM or
ROM chips are selected i.e. the data transfer is of 16-
bits.

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21-12-2022

 Address lines A13-A19 are used for decoding to generate the chip
select.
 BHE and A0 signals are used to select the proper byte or bytes of
memory or I/O word to be read or write.

FE000H
FD000H

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21-12-2022

 Design an interface between CPU 8086 and two


chips of 32KB ROM and four chips of 32 KB RAM
according to the following memory map.

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21-12-2022

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