Introduction to Digital VLSI

Design
‫ ספרתי‬VLSI ‫מבוא לתכנון‬

Verilog – Logic Synthesis with Verilog HDL

Lecturer: Gil Rahav

Semester B’ , EE Dept. BGU.
Freescale Semiconductors Israel

1 09/03/07
 Objectives

Define logic synthesis and explain the benefits of logic synthesis

Identify Verilog HDL constructs and operators accepted in logic

synthesis. Understand how the logic synthesis tool interprets
these constructs

Explain the typical design flow, using logic synthesis. Describe
the components in the logic synthesis-based design flow

Describe verification of the gate-level netlist produced by logic
synthesis

Understand techniques for writing efficient RTL description

Describe partitioning techniques to help logic synthesis provide

the optimal gate-level netlist

Design combinational and sequential circuits, using logic
synthesis
2 Introduction to Digital VLSI 09/03/07
Gil Rahav
Freescale Semiconductor Israel
 Impact of Logic Synthesis

Logic synthesis always existed even in the days of schematic gate-
level design, but it was always done inside the designer’s mind
 For large design, manual conversion was prone to human error
 The designer could never be sure that the design constraints were
going to be met until the gate-level implementation was completed and
tested
 A significant portion of the design-cycle was dominated by the time
taken to convert a high-level design into gates
 The turnaround time for redesign of blocks was very high
 What-if scenarios were hard to verify
 Each designer would implement design blocks differently
 If a bug was found in the final, gate-level design, this would sometimes
require redesign of thousands of gates
 Timing, area, and power dissipation in library cells are fabrication-
technology specific
 Design reuse was not possible (technology specific, hard to port, …)

3 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Impact of Logic Synthesis

The advent of computer-aided logic synthesis tools has
automated the process of converting the high-level description to
logic gates
 High-level design is less prone to human error
 High-level design is done without significant concern about design
constraints
 Conversion from high-level design to gates is fast
 Turnaround time for redesign of blocks is shorter
 What-if scenarios are easy to verify
 Logic synthesis tools optimize the design as a whole
 If a bug was found in the final, gate-level design, the designer goes
back and changes the high-level description to eliminate the bug
 Logic synthesis tools allow technology-independent design
 Design reuse is possible for technology-independent descriptions

4 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Verilog HDL Synthesis

For the purpose of logic synthesis, designs are currently written

in an HDL at a register transfer level (RTL)
 The term RTL is used for an HDL description style that utilizes a
combination of dataflow and behavioral constructs

Verilog and VHDL are the two most popular HDLs used to
describe the functionality at the RTL level

Logic synthesis tools take the register transfer-level HDL

description and convert it to an optimized gate-level netlist
 RTL-based synthesis is currently the most popular design method

5 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Verilog HDL Synthesis: Verilog Constructs

In general, any construct that is used to define a cycle-by-cycle

RTL description is acceptable to the logic synthesis tool

Construct Type Keyword of Description Notes

ports input, inout, output
parameters parameter
module definition module
signals & variables wire, reg, tri Vectors are allowed
instantiation module & primitive instances mymux m1(out, i0, i2, s); nand (out, a, b);
functions & tasks function, task Timing constructs ignored
procedural always, if, then, else, case(x/z) initial is not supported
procedural blocks begin, end, named blocks, disable Disabling of named blocks allowed
data flow assign Delay information is ignored
while and forever loops must contain
loops for, while, forever
@(posedge clk) or @(negedge clk)

6 Introduction to Digital VLSI 09/03/07

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 Verilog HDL Synthesis: Think Hardware!!!

Remember that we are providing a cycle-by-cycle RTL description

of the circuit

There are restrictions on the way these constructs are used for the
logic synthesis tool. For example:
 The while and forever loops must be broken by a @(posedge clock) or
@(negedge clock) statement to enforce cycle-by-cycle behavior and to
prevent combinational feedback
 Logic synthesis ignores all timing delays specified by #<delay>
construct. Therefore, pre- and post-synthesis Verilog simulation results
may not match. The designer must use a description style that
eliminates these mismatches
 The initial construct is not supported by logic synthesis tools. Instead,
the designer must use a reset mechanism to initialize the signals in the
circuit
 …
7 Introduction to Digital VLSI 09/03/07
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Freescale Semiconductor Israel
 Verilog HDL Synthesis: Timing Delays

Pre- and post-synthesis Verilog

simulation results may not match
 Logic synthesis ignores all timing
module code11 (out1, out2, in);
delays specified by #<delay> output out1, out2;
construct input in;
 In RTL simulation the outputs will reg out1, out2;
always @(in)
not be updated on every input (in begin
signal) change if changes happen #25 out1 = ~in;
more frequently than the delay in #40 out2 = ~in;
the logic (65 time units in the end
endmodule
example)

The designer must use a

description style that eliminates
these mismatches
8 Introduction to Digital VLSI 09/03/07
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Freescale Semiconductor Israel
 Verilog HDL Synthesis: Verilog Operators

Almost all operators in Verilog are allowed for logic synthesis

Operators Type Operator Symbol Operation Performed

Arithmetic * / + - % Multiply, divide, add, subtract, modulus
Logical ! && || Logical negation, and, or

Greater than, Less than, Greater than or equal

Relational > < >= <=
to, Less than or equal to

Equality == != Equality, inequality

Bit-wise ~ & | ^ ~^ ^~ Bitwise negation, and, or, nor, xor, xnor
Reduction & ~& | ~| ^ ~^ ^~ Reduction and, nand, or, nor, xor, xnor
Shift << >> Left shift, right shift
Concatenation {} Concatenation
Conditional ?: Conditional

Only operators such as “===“ and “!==“ that are related to “x” and
“z” are not allowed (equality with “x” and “z” does not have much
meaning in logic synthesis)

9 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel
 Verilog HDL Synthesis: Top-Down Design

Model entire system architecturally, in
Requirements Analysis
Verilog or some other high-level language

Partition your design based on functionality
System Partitioning
or path length

Behavioral/Functional
Write a behavioral Verilog model for each

Specification partition as an executable bus-functional
specification of the design
Behavioral/Functional
Write or generate the same models at the
Verification RTL level, using synthesizable constructs.
Assemble and verify entire RTL system

Translate the functional models to gate-
Synthesis & Optimization
level netlists using synthesis and
optimization tool

Gate Level Verification
Mixed-level logic simulation allows you to

verify the design at all levels
10 Introduction to Digital VLSI 09/03/07
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Freescale Semiconductor Israel
 Verilog HDL Synthesis: Design Partitioning

Design partitioning is another important factor for efficient

logic synthesis
 The way the designer partitions the design can greatly affect the
output of the logic synthesis tool

Various partitioning techniques can be used

 Hierarchical partitioning
 Horizontal partitioning
 Vertical partitioning
 Parallelizing design structure

11 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Hierarchical Design Partitioning

Module statements create hierarchical design blocks (see part III

of this course)

Continuous assignments (assigns) and procedural blocks (always)

do not create hierarchy

ADR_BLK

module ADR_BLK (. . .); Dec

DEC U1 (ADR, CLK, INST);
OK U2 (ADR, CLK, AS, OK);
endmodule;
Ok

12 Introduction to Digital VLSI 09/03/07

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 Hierarchical Design Partitioning

While writing the RTL, the designer has to decide if to keep the
hierarchy of the design or to write a flat code

Flattened synthesis optimization
 Can take longer to execute
 Saves from calculating timing budgets between blocks (uses
synthesis tools’ strengths in optimizing for timing)

Hierarchical synthesis optimization

 Speed up optimization times
 Requires partitioning designs to optimize smaller blocks.
 Requires management of timing budgets between blocks.
 Simplify the synthesis process (incremental design updates, is
easier to debug, multi- engineer teams)
 Supports a mix of options for different modules
13 Introduction to Digital VLSI 09/03/07
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Freescale Semiconductor Israel
 Horizontal Design Partitioning

Horizontal partitioning: use bit slices to give the logic synthesis

tool a smaller block to optimize
 It reduces complexity of the problem and produces more optimal
results for each block

The downsize of horizontal partitioning is that global minima can

often be different local minima
 Each block is optimized individually, but there may be some global
redundancies that the synthesis tool may not be able eliminate

14 Introduction to Digital VLSI 09/03/07

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 Horizontal Design Partitioning Example

Instead of directly designing a 16-bit ALU,
design a 4-bit ALU and build the 16-bit ALU a[15:0] b[15:0]
with four 4-bit ALUs

Logic synthesis tool has to optimize only 16-bit ALU

control flags
the 4-bit ALU, which is a smaller problem
than optimizing the 16-bit ALU
output
a[15:0] b[15:0]

4-bit ALU 4-bit ALU 4-bit ALU 4-bit ALU

control flags

output

15 Introduction to Digital VLSI 09/03/07

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 Vertical Design Partitioning

Vertical partitioning implies that the functionality of the block is

divided into smaller sub-modules

This is different from horizontal partitioning

 In horizontal partitioning, all blocks do the same function
 In vertical partitioning each block does a different function

For logic synthesis it is important to create hierarchy by

partitioning a large block into separate functional sub-blocks
 A design is best synthesized if levels of hierarchy are created and
smaller blocks are synthesized individually
 Creating modules that contain a lot of functionality can cause logic
synthesis to produce sub-optimal designs. Instead, divide the
functionality into smaller modules and instantiate those modules.

16 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Vertical Design Partitioning Example

The 4-bit ALU is a four-function ALU with functions add, subtract,

shift right, and shift left

Vertical partitioning of 4-bit ALU: each block is distinct in function

a[3:0] b[3:0]
a[3:0] b[3:0]

Add Shift-left
4-bit ALU
flags control flags
control Subtract Shift-right

output
output

17 Introduction to Digital VLSI 09/03/07

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 Parallelizing Design Structure

In this technique we use more

resources to produce faster
a[3:0]
design Carry summ[3:0]
b[3:0] Look-
 We convert sequential operations ahead c_out
into parallel operations by using c_in Adder
more logic

a[0] b[0] a[1] b[1] a[2] b[2] a[3] b[3]

 Contrast the “carry
c_in c_1 c_2 c_3 c_out lookahead” adder (4
full full full full gate delays, more logic
adder adder adder adder gates) with a “ripple
fa_0 fa_1 fa_2 fa_0
carry” adder (9 gate
delays, less logic gate)
summ[0] summ[1] summ[2] summ[3]

18 Introduction to Digital VLSI 09/03/07

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 Partitioning Rules for Synthesis

No hierarchy in combinational paths

No glue logic between blocks

Register all outputs

Separate designs with different goals

Isolate state machines

Maintain a reasonable block size

Separate logic, pads, clocks and non-synthesizable structures

19 Introduction to Digital VLSI 09/03/07

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 Partitioning Rules for Synthesis

No hierarchy in combinational paths

Reg Logic Logic Logic Reg

No glue logic between blocks

Logic Reg Logic Reg

 Merge glue logic into the related combinational logic description of the
lower-level architectural statements

20 Introduction to Digital VLSI 09/03/07

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 Partitioning Rules for Synthesis

Register all outputs

Logic Reg Logic Reg Logic Reg

 Related combinational logic is grouped into the same block that contains
the destination register for the combinational logic path
 Allows improved sequential mapping during optimization (no hierarchical
boundaries between combinational and sequential logic)
 Simplifies the description of the timing interface

21 Introduction to Digital VLSI 09/03/07

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 Partitioning Rules for Synthesis

Separate designs with different goals

Critical Critical
Reg Path
Reg
Path

No No
Critical Reg Critical Reg
Path Path

 Optimization is limited because the  Designer can now perform

designer cannot isolate parts of a appropriate optimization
block and optimize them solely for techniques on each module
area or for speed

22 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Design Constraints Specification

Design constraints are as important as efficient HDL description

in producing optimal design

Accurate specification of timing, area, power, and environmental

parameters, such as input drive strengths, output loads, input
arrival times, etc., are critical to produce a gate-level netlist that
is optimal

A deviation from the correct constraints or omission of a

constraint can lead to non-optimal designs

Careful attention must be given to specifying design constrains

23 Introduction to Digital VLSI 09/03/07

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 Verilog HDL Synthesis: Modeling Style

There is a modeling style for each synthesis tool

 It is possible to write Verilog descriptions for which there are no digital
hardware
 Synthesis results are sensitive to the input description

Goals of the modeling style

 Efficiency
 Predictability
 Synthesizability

Two basic guidelines for writing synthesizable Verilog descriptions:

 The gate-level simulation should match the functional (RTL) simulation
 Sequential design should work independent of technology-specific
propagation delays

24 Introduction to Digital VLSI 09/03/07

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 Modeling Style Basics

Use meaningful names for signals and variables
 Names of signals and variables should be meaningful so that the code
becomes self-commented and readable

Avoid mixing positive and negative edge-triggered flip-flops

 Mixing negative and positive edge-triggered flip-flops may introduce
inverters and buffers into the clock tree

Be careful with multiple assignments to the same variable

Multiple assignments to the same variable can cause undesired logic to be
generated (the previous assignment might be ignored, and only the last
assignment would be used
 The synthesis tool infers two flip-
// Two assignments to the same variable flops with the outputs anded
always @(posedge clk) if(load1) q <= a1;
together to produce the q output
always @(posedge clk) if(load2) q <= a2;  The designer needs to be careful
about such situation!!!

25 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Modeling Style Basics

Multiply, divide, and modulo operators are very expensive to

implement in terms of logic and area
 These arithmetic operators can be used to implement the desired
functionality concisely and in a technology-independent manner
 On the other hand, designing custom blocks to do multiplication,
division or modulo operation can take a longer time to design, and
the module becomes more technology dependent

Use parentheses to optimize logic structure

 The designer can control the final

// Translates to three adders in series
structure of logic by using
out = a + b + c+ d; parentheses to group logic
/* Translates to two adders in parallel
 Using parentheses also improves
with one final adder to sum results*/ readability of the Verilog
out = (a + b) + (c+ d); description

26 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Modeling Style: Combinational Logic

For logic to be combinational, the output must have only one

possible value for any combination of inputs
 There must be no timing or order dependencies
 If the description meets this definition, it can be synthesized as a
combinational logic

There are three modeling styles that meet these requirements

 A netlist structure of combinational primitives with no feedback loops
 A continuous assignment statement with no feedback loops
 A procedural block with an event sensitivity list consisting of all nodes
to which assignments are made

You can group the combinational logic in a function

 This guarantees that the logic will be interpreted as combinational,
eliminating the risk of generating latches in a data path

27 Introduction to Digital VLSI 09/03/07

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 Combinational Logic

 Method 1: A netlist structure of

combinational primitives with no
A
feedback loops
B
E OUT // Method 1
C or (or1, A, B);
D or (or2, C, D);
and (OUT, or1, or2, E);

module orand (OUT, A, B, C, D, E);  Method 2: A continuous

input A, B, C, D, E; assignment statement with no
feedback loop
output OUT;
// Use one of four methods // Method 2
endmodule assign OUT = E & (A | B) & (C | D);

28 Introduction to Digital VLSI 09/03/07

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Freescale Semiconductor Israel
 Combinational Logic

 Method 3: Since a function have no

timing control, it is interpreted as
A combinational logic
B
// Method 3
E OUT
function out;
C
input A, B, C, D, E;
D
out = E & (A | B) & (C | D);
endfunction

 Method 4: Procedural blocks with

complete event sensitivity list
module orand (OUT, A, B, C, D, E);
input A, B, C, D, E; // Method 4
output OUT; reg OUT;
// Use one of four methods always @(A or B or C or D or E)
endmodule if (E) OUT = (A | B) & (C | D);
else OUT = 0;

29 Introduction to Digital VLSI 09/03/07

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 Combinational Logic

4
A module mux (A, B, C, D, OUT, SEL);
input [3:0] A, B, C, D;
B 4 input [1:0] SEL;
OUT output [3:0] OUT;
C
reg [3:0] OUT;
D
always @(SEL or A or B or C or D)
2
case(SEL)
2’b00: OUT = A;
SEL 2’b01: OUT = B;
2’b10: OUT = C;
 If you desire combinational logic, 2’b11: OUT = D;
specify all branches of a case default: OUT = 4’bx;
endcase
statement, including the default
branch endmodule
 If the assignments are not complete
in all brunches of the decision, the
synthesizer adds latches to maintain
the state of the circuit
30 Introduction to Digital VLSI 09/03/07
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 Functions in Synthesis

Functions always synthesize to combinational logic

A problem can occurs when

engineers make a mistake in the
combinational function code and module code3b (o, a, nrst, en);
output o;
create simulation code that input a, nrst, en;
behaves like a latch. reg o;
always @(a or nrst or en)
module code3a (o, a, nrst, en);
o = latch(a, nrst, en);
output o;
input a, nrst, en; function latch;
reg o; input a, nrst, en;
if (!nrst) latch = 1'b0;
always @(a or nrst or en)
else if (en) latch = a;
if (!nrst) o = 1'b0;
else if (en) o = a; endfunction
endmodule endmodule

31 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Efficient Comparison

Equality operators are implemented more efficiently

if (a <= b) @ (posedge clk) if (a != b) @ (posedge clk) a = a + 1;
a = a + 1;

Avoid threshold comparison, except where resources can be shared

 In general, threshold comparisons are less efficiently implemented

if (a <= b) do_1; if (a < b+1) do_1;

When there are few branches consisting of many consecutive

cases, using a “case value” is more efficient
case (a) case (a)
(1 < a) && (a < 11): do_A; 2, 3, 4, 5, 6, 7, 8, 9, 10: do_A;
(11 <= a) && (a < 18): do_B; 11, 12, 13, 14, 15, 16, 17: do_B;
(a == 20): do_C; 20: do_C;
default: do_D; default: do_D;
endcase endcase

32 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Latched Logic

Latched logic describes storage  Method 1: Using a simple feedback

devices independent from clock
// Method 1
8 wire [7:0] OUT;
in D assign OUT = ENABLE ? IN : OUT;
8
out
en G
 Method 2: Using an unspecified
branch in if or case statement
// Method 2
module latch (OUT, IN, ENABLE); reg [7:0] OUT;
input [7:0] IN; always @(ENABLE or IN);
input ENABLE; if (ENABLE) OUT = IN;
output [7:0] OUT; // no else statement !!!
// Use one of two methods
endmodule
Be careful of unintentional latches!

Try to avoid using latches => use FFs

33 Introduction to Digital VLSI 09/03/07

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Modeling Style: Inferring Latches & Flip-Flops

An always block, without all its module dffn (q, data, clk);
conditions specified, leads to a latch input data, clk;
output q;

In the example below, is a false case, reg q;
the value of data must be held and always @( negedge clk)
the synthesizer must use a storage q <= data;
element. endmodule

module latch (q, data, enable);

A flip-flop is inferred
input data, enable;
when the procedural
output q;
block is entered into
reg q;
always @(enable or data)
only on a single edge
if (enable)
of the control signal
q <= data;
(clk).
endmodule

34 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Simple Sequential Logic

module mux_dff (A, B, C, D, OUT, SEL,

CLK);

The output of a block is stored
input [3:0] A, B, C, D;
with a flip-flop when it is output [3:0] OUT;
triggered by an edge-sensitive input [1:0] SEL;
event control input CLK;
reg [3:0] OUT;

always @(posedge CLK)

4
A case(SEL)
B
2’b00: OUT <= A;
4
D 2’b01: OUT <= B;
C 4
out 2’b10: OUT <= C;
D 2’b11: OUT <= D;
2 // use default if not full case
SEL CLK endcase

endmodule

35 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Simple Sequential Logic

inputs R outputs
Combinational
E
Logic
G

Modeling style rules for sequential logic:

 Each always block can have only one edge of one clock (unless
you are modeling asynchronous reset with the
asynchronous/synchronous brunch modeling style)
 Each stored variable may be assigned from only one clock-edge-
triggered procedural block

36 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Registers

The reg variables in a sequential block are implemented as

hardware registers if they are assigned a value in one clock cycle
and sampled in another

If the sampling and assignment of the reg does not cross clock
boundaries then the reg may be optimized away

The reg variable does not necessarily imply a hardware register in

the final synthesized output (reg variables do exist in RTL logic
that is combinational)

If the reg variable is also a primary output, it will appear in the

final netlist regardless of the type of logic produced

37 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Register Examples

module ex1reg (data, clk, module ex2reg (data, clk,

out); out);
input data, clk; input data, clk;
output out; Blocking output out;
reg out; assignment. reg out;
Don’t ever
reg rega; reg rega;
use!
always @( posedge clk) always @( posedge clk)
begin begin Two clock
rega = data; One clock rega <= data; edges imply
out = rega; edge imply out <= rega; two storage
two storage elements
end elements end and rega is
endmodule and rega is endmodule not
optimized optimized
away away

38 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Asynchronous Reset

You can model reset for any type of edge or level sensitive
storage device

Asynchronous reset can be modeled in a single block, sensitive

to the active clock edge and the active reset edge
 There must be exactly one synchronous branch in the conditional
statement
 The default (else) branch is typically the synchronous one

39 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Asynchronous Reset

Flip-flop
Latch

module dffsetclr (q, clk, reset, d); module latch (q, enable, set, clr, d);
input clk, d, reset; input enable, d, set, clr;
output q; output q;
reg q; reg q;
always @(posedge clk or posedge always @(enable or set or clr or d)
reset) begin
begin if (set)
if (reset) q <= 1;
q <= 0; else if (clr)
else q <= 0;
q <= d; else if (enable)
end q <= d;
end
endmodule endmodule

40 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Synchronous Reset

Check the status of the reset

module dffsetclr (q, clk, reset,
signal at every clock edge d);
input clk, d, reset;

If your target library does not output q;
contain a storage device with reg q;
synchronous reset, the reset is always @(posedge clk)
implemented in the data path begin
if (reset)
q <= 0;
else
q <= d;
end
endmodule

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 Modeling Style: Complex Operators

Complex operators are operations that can be recognized as

high-level operations and mapped to existing cells in a
vendor’s library directly:
out = a * b;

 Most tools know enough to map this to a multiplier

 This multiplier may exist in a special macro library that has
components at a higher level of complexity than the regular cell
library
 Macro libraries can include parts for design reuse such as
FIFOs, adders, substractors, shift registers, counters, decoders,
etc., of a various architectures
 The macro library may also contain user-defined blocks that are
designed and synthesized by the user and intended or re-use

42 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Resource Sharing

Resource sharing is the sharing of a group of logic by more than

one section of RTL code
 Some synthesizers do resource sharing automatically
 You can control some resource sharing from within your RTL code
 You can force resource sharing by changing the coding style

b c b d c d

always @(a or b or c or d) b a
if (a) temp = a ? c :
out = b + c; d;
a
else out = b + temp;
out = b + d;
out out

43 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Sensitivity List

Inputs to a procedural block should be included in its sensitivity list

 Some synthesis tools produce a warning when encountering an
incomplete sensitivity list; others produce an error. The tools that
produce a warning proceed with the assumption that you meant to have
a complete list

/* In this example, a, b, and c are inputs to the block;a and b are

conditions, and c is contained in the RHS of the procedural
assignment d = c */
always @( a or b or c)
begin
if (a and b) d = c;
end

44 Introduction to Digital VLSI 09/03/07

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 Modeling Style: Incomplete Sensitivity List

As a result of incomplete sensitivity list (input b is not specified)

the RTL and gate-level simulations will produce different results

// In this example, a and b are inputs to the block and c is an

output
always @( a ) // Incomplete sensitivity list
begin
c = a || b;
end

RTL Synthesis results Gate-Level

A A
A
B C B
B
C C

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Freescale Semiconductor Israel
Modeling Style: (Non-) Blocking Assignments

Use non-blocking assignments when
 modeling sequential logic
 modeling latches
 modeling both sequential and combinational logic within the same
"always" block

Use blocking assignments when
 modeling combinational logic with an "always" block

General guidelines
 Do not mix blocking and non-blocking assignments in the same
"always" block
 Do not make assignments to the same variable from more than one
"always" block
 Use $strobe to display values that have been assigned using non-
blocking assignments
 Do not make assignments using #0 delays

46 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel
 Modeling Style: Finite State Machine (FSM)
Mealy vs. Moore
Finite State Machines (FSM) types

A Mealy machine has outputs that are a function of the present state registers
and of the machine inputs.

A Moore machine has output that are function of the present state only, the
outputs are not directly dependent on the machine inputs

It is always possible to model an FSM specification as either Mealy or Moore

machine, the difference is the output timing
A Moore machine has output that settle directly after active clock edge and
remain stable for the duration of the clock cycle.
In Mealy machine changes on the input are seen a cycle earlier than in the
Moore machine

47 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel
Finite State Machine: Implicit vs. Explicit FSMs

There are two distinct types of Finite State Machines (FSMs):

explicit and implicit

Implicit machines use multiple always @(posedge clk)
statements to indicate state transitions
 exist at a higher level of abstraction than explicit machines and in
general are not synthesizable
 In implicit FSMs, registers are created whenever data is written in
one clock cycle and read in another

Explicit machines use case statements to define each possible

state explicitly
 explicit machines are used in code meant for synthesis

All FSMs must have a reset, and their state changes must be
synchronous to one edge of a single clock
48 Introduction to Digital VLSI 09/03/07
Gil Rahav
Freescale Semiconductor Israel
Finite State Machine: Implicit vs. Explicit FSMs

Implicit FSMs:
state A
 Do not need a state register
 Handle only linear state changes well
 Each state is separated by clock state B1 state B2
boundaries
 Are not handled by most synthesis state C
tools
state D
state 1

Explicit FSMs:
 Are clearer and more well-defined
state 2
 Can handle default conditions
 Handle complex (nonlinear) state
state 3
changes
 You specify a state variable that define
state 4
the state of the state machine

49 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel
 Implicit Style of FSM

module imp (out, datain, clk, rst);
From each always block that
output out; models sequential logic, synthesis
input clk, datain, rst; extracts a single FSM
reg out;
always @(posedge clk or posedge rst)
If the always block has only one
if (rst) out <= 1’b0; // asynchronous clock cycle (a degenerate FSM), it
// reset
is implemented with combinational
else
begin logic plus a register
if (!out) // state out == 0
Registers are created whenever
begin
if (datain) out <= 1’b0;
data is written in one clock cycle
else out <= 1’b1; and read in another clock cycle for
end the stored variables
else // state out == 1
out <= 1’b0;
If the FSM has more than one
end cycle, the synthesis tool
endmodule datain = 0 generates control logic,
including a state variable, and
0 1
datain = 1
adds registers for the stored
variables
50 Introduction to Digital VLSI 09/03/07
Gil Rahav
Freescale Semiconductor Israel
 Explicit Style of FSM

FSM can be described explicitly in a

procedural block with a single clock module exp (out, datain, clk, rst);
edge and a case statement output out;
input clk, datain, rst;

A state variable that defines the state reg out, state; // state variable
of the FSM must be specified always @(posedge clk or posedge rst)
if (rst) {state,out} <= 2’b00;

To change the current state, the value else
of the state variable must be changed case (state) // case statement
synchronous to the clock edge 1’b0: begin
Not required out <= 1’b0;

It is a good practice to specify a In Verilog if (datain) state <= 1’b1;
default action for conditions that else state <= 1’b0;
end
normally do not occur
datain = 0 1’b1: begin

Assignments of the out <= datain;
state variable and 0 1 state <= 1’b0;
output signals to datain = 1 end
default: {state, out} = 2’b00;
constant expressions endcase
are optimized efficiently endmodule

51 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel
 Explicit Style of FSM (con.)

module exp (out, datain, clk, rst);

output out;
input clk, datain, rst;
reg out, state; // state variable
always @(posedge clk or posedge rst) datain state
if (rst) {state,out} <= 2’b00; Logic Reg
else
case (state) // case statement
1’b0: begin
out <= 1’b0;
if (datain) state <= 1’b1;
end
1’b1: begin
out
out <= datain;
Logic Reg
state <= 1’b0;
end
default: {state, out} = 2’b00;
endcase
endmodule

52 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel
 Explicit Style of FSM (con.)

module exp (my_out, datain, clk, rst, my_in);

output my_out;
input clk, datain, rst;
input my_in;
reg out, state; // state variable
wire my_out;
datain state assign my_out = out & my_in;
Logic Reg always @(posedge clk or posedge rst)
if (rst) {state,out} <= 2’b00;
my_in else
case (state) // case statement
1’b0: begin
out <= 1’b0;
if (datain) state <= 1’b1;
my_out end
Logic Reg Logic 1’b1: begin
out out <= datain;
state <= 1’b0;
end
default: {state, out} = 2’b00;
endcase
clk rst endmodule

53 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel
 Logic Synthesis with Verilog HDL Summary

Logic synthesis is the process of converting a high-level description of

the design into an optimized, gate-level representation, using the cells in
the technology library

Computer aided logic synthesis tools have greatly reduced the design
cycle time and improved productivity. They allow designers to write
technology-independent, high-level descriptions and produce technology-
dependent, optimized, gate-level netlists. Both combinational and
sequential RTL descriptions can be synthesized

Logic synthesis tools accept high-level descriptions at the register

transfer level (RTL). Thus, not all Verilog constructs are acceptable to a
logic synthesis tool. We discussed the acceptable Verilog constructs and
operators and their interpretation in terms of digital circuit elements

54 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel
 Logic Synthesis with Verilog HDL Summary

A logic synthesis tool accepts an RTL description, design constraints,

and technology library, and produces an optimized gate-level netlist.
Translation, logic optimization, and technology mapping are the internal
processes in a logic synthesis tool and are normally invisible to the user

Proper Verilog coding techniques must be used to write efficient RTL

descriptions, and various design trade-off must be evaluated. Guidelines
for writing efficient RTL descriptions were discussed

Design partitioning is an important technique used to break the design

into smaller blocks. Smaller blocks reduce the complexity of optimization
for the logic synthesis tool

Accurate specification of design constraints is an important part of logic

synthesis

55 Introduction to Digital VLSI 09/03/07

Gil Rahav
Freescale Semiconductor Israel