ICC2 (1) import design —— MCMM
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1.1 What is MCMM?
MCMM ( multi -corner multi-mode) defines the combination of all modes and corners
into several scenarios, simultaneously analyzes and optimizes the timing of effective
scenarios, and can selectively optimize the area and power consumption at the same time,
thus greatly reducing the timing The number of iterations and design time to
convergence.
1.2.1 Multi Corner
remove_corners
creare_corner slow_1; creare_corner fast_1
current_corner slow_1
set_temperature -40 -corner {slow_1}
set_voltage 0.81 -corner slow_1 -object_list VDD *
set_voltage 0 -corner {slow_1} -object_list VSS *
current_corner fast_1
set_temperature 125 -corner {fast_1}
set_voltage 0 -corner {fast_1} -object_list VSS*
1.2.1.1 RC corners
Specifies the RC model corresponding to the corner.
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read_parasitic_tech -tluplus cmax.tluplus -layer_map layer.map -name tluplus_max
read_parasitic_tech -tluplus cmin.tluplus -layer_map layer.map -name tluplus_min
//tluplus and layer map are provided by foundry, among which tluplus can be converted by
itf file, and the layer map will correspond to the layer name of techfile and tluplus.
set_parasitic_parameters -corners {slow_1} -early_spec tluplus_max -late_spec tluplus_max
set_parasitic_parameters -corners {fast_1} -early_spec tluplus_min -late_spec tluplus_min
1.2.1.2 Delay corner
Specifies the PVT corresponding to the corner.
current_corner slow_1
set_process_label ssg_cworst_max_0p81v_m40c -corner slow_1
current_corner fast_1
set_process_label ffg_cbest_max_0p99v_125c -corner fast_1
1.2.2 Multi Mode
Define multiple modes, the common ones are func and scan.
remove_modes
create_mode func_1
create_mode scan_1
1.2.3 Scenarios
Combine Corner and Mode into Scenario.
There are many commands pointing to -corner -mode -scenario, how to specify refer to
the figure below.
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remove_scenarios -all
create_scenario -mode func_1 -corner slow_1 -name func_slow_1
current_scenario func_slow_1
read_sdc func_1.sdc
set_max_transition 0.5 [current_design]
set_max_transition 0.15 [get_clocks *] -clock_path
set_max_capacitance 0.15 [get_clocks *] -clock_path
set_false_path …
set_disable_timing …
sdc: Synopsys Design Constraints, which constrain timing, area, and power consumption,
and generate multiple modes through switches of different sdc and signals.
set_scenario_status func_slow_1 -leakage_power true -setup true -hold true -
max_capacitance true -max_transition true -min_capacitance false -active true
set_scenario_status //Tell the tool whether to perform the analysis of setup /hold
/
leakage_power / dynamic_power and the analysis of default DRC such as
transition/capacitance, is true.
1.3 Reports report
report_parasitic_parameters
report_pvt // Check the match between the set pvt and the pvt applied by the actual tool.
report_corners
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