Anubhuti Navin Contact:

Email id: anubhuti11navin@[Link]

Mob. No.: 7783047192/9148015107

Professional Experience Summary

● About 4 years 4 months of experience from PNR to GDSII.

● Worked on Different technology Node like 7nm, 12nm,14nm, 28nm, and 153nm using ICC, ICC2,
Innovus, Prime Time, tempus, Calibre, Star-RC , Tweaker etc.

● Good in STA, Floorplan understanding.

● Worked on Low Power design.

Offering Area Experience Description

Physical Design 4 years 4 months PnR & Sign-Off

Technical Skills
Primary Skills Physical Design Implementation

Development Tools ● PnR: Synopsys (ICC, ICC2, formality), Cadence (Innovus).

● Signoff: synopsys (PrimeTime, Star-RC, Laker), Cadence (Tempus),

Tweaker.

● DRC: Calibre,ICV
Languages Perl, Tcl, & Shell scripting

Secondary skills Prime Time, Conformal LEC, Calibre, Tweaker, Tempus

Project1 MOET[6nm TSMC] INNOVUS

Role & Description Currently Ongoing Project
Responsible for Complete Physical Implementation
of the netlist ,floorplan, congestion fixes, timing
fixes, DRV fixes, Skew & latency fixes ,DRC fixes ,CLP
fixes and PI fixes along with ECO’S.

Description  Owner of low power block named

imgsys1_top_par_wrap.
 Responsible for Complete PNR, STA and PV
closure.
 Blocks has 2.2 million instances .Its a low
power block.
 Macro Dominant Block having 113 Macros.
 Currenlty in TDI STAGE.
 Facing congestion as well as Timing issues.
Project2 Cygnus (12nm TSMC) INNOVUS
Role & Description
Responsible for Complete Physical Implementation
of the netlist ,floorplan, congestion fixes, timing
fixes, DRV fixes, Skew & latency fixes ,DRC fixes ,CLP
fixes and PI fixes along with ECO’S.

Description ● Owner of a low power Block named

camsys_rawa_par_wrap.
● Responsible for Complete PNR, STA and PV
closure.
● Blocks has 1.8 million instances .Its a low
power block.
● Macro Dominant Block having 142 Macros .
● Block have 5k feedthroughs
● Have Power switches in the block.
● Frequency of Block is 546Mhz.
● It’s a Congestion and area critical design.
● Cleaned CONGESTION in the block with
multiple floorplan trials.
● Timing fixes using manual eco’s based on
analysis as well as tweaker.
● Also Did clock tweaking for huge hold
violations.
● Static and Dynamic IR fixes.
● Closed Block at 73% utilisation post route.
● Fixed DRC’S/ERC/ANT/LVS as well as CLP.

TOOLS USED INNOVUS,Primtime, ICV,Laker,Star-PEX,

Tweaker

Project 3 Lagrange (12nm TSMC) INNOVUS

Role & Description

● PnR – Complete Physical Implementation

of the netlist, low power fixes, timing fixes,
DRC fixes congestion fixes and PI fixes

● Timing Closure – Generated ECOs using

path-based analysis and clock tweaks.
Description ● Owner of 1 Block named
camsys_rawa_par_wrap.

● Responsible for Complete PNR RUN and

integration.

● Blocks has 1.8 million instances .Its a low

power block.
● Macro Dominant Block having 142 Macros .

● Responsible for Complete PNR, STA and PV

closure.

● Have Power switches and Voltage Area in

the block.

● Cleaned CONGESTION in the block with

multiple floorplan trials.

● Timing fixes using manual eco’s based on

analysis as well as tweaker.

● Static and Dynamic IR fixes.

● Closed Block at 72% utilisation.

● Responsible for complete PV , PI and

signoff fixes.

● Project Tapedout successfully.

ISSUES FACED ● CONGESTION :

Block is congestion critical along with area
[Link] macro dominant ,had
congestion [Link] congestion using
multiple floorplans as well as
bounds/blockages.
 IR ISSUES.
 Timing issues.
 LVS/ERC issues.

TOOLS USING INNOVUS,Primtime, ICV,Laker,Star-PEX,

Tweaker
Project4 MARGAUX (7nm TSMC) LOW POWER DESIGN

Role

● PnR – Complete Physical Implementation of

the netlist, low power fixes, timing fixes, DRC
fixes and congestion fixes in INNOVUS.

● Timing Closure – Generated ECOs using

path-based analysis.

Description ● Owner of block named imgsys1.

● Responsible for Complete PNR RUN and

integration and closure of the block.

● Block has 3million instances and one power

domain

● Macro Dominant design [having 132 Macros]

.

● It’s a low power Switchable domain

blockwith approx. 8K power switch cells.

● Responsible for Complete STA and PV

closure.

● Scripted ECOs and Used Tweaker for setup

hold critical paths for timing closures

● Solved Critical 7 nm Lower node drc’s.

● LVS and Static IR cleaned.

ISSUES FACED ● Congestion: Solved Congestion issue with

Proper Macros placement [according to its
module and ports connection] and also by
providing Channels blockages, and Bounds.
● Hold Violation: Addition of Hold buffers in a
particular module cased Thousands of
SHORTS violation. Solved Hold paths using
clock push –pull .Also Spreaded the cells of
 the module for hold [Link] fixed Hold
paths as well as Shorts.
● ERC Violation and Antenna Violation.
● Critical 7nm drc’s: Fixed drc’s based on 7nm
rules .

Tools INNOVUS,Prime time, Calibre,Laker,Star-RC,

Tweaker.

Project5 Mercury [12nm FFC TSMC] LOW POWER DESIGN

Role ● PnR –Complete Physical Implementation of

the netlist, DRC fixes and Congestion fixes in
INNOVUS.

● Timing closure.

● Clock Skew balancing.

Description ● Owner of Analog Block named Digbb_serdes.

● Block has 0.9 million instances ,33macros

and 1 Analog Macro.

● Switchable block with 1900 power switch

cells.

● Preplacement of cells near ANALOG MACRO

according to designer requirement.

● Created Bounds for clock cells for proper

clock tree building.

● Did skew and latency balancing in CTS stage

as well as at post_route stage to meet the
skew and latency criteria decided by
Designer.

● Static and Dynamic IR fixes.

● Timing fixes using manual eco’s based on

analysis as well as tweaker.

Issues Faced ● Preplacement of cells: Prepared script to

preplace the required cells near to its
ANALOG PINS causing straight connections.

● LEC FAIL: Solved LEC issue with proper

 connection and disconnection of LEC failed
cells.

● SKEW and LATENCY Requirements: Balanced

skew and latency of the 12 clocks to meet its
required criteria.

● LVS FAIL: Manually created

POWER/GROUND nets to connect with
ANALOG POWER/GROUND PINS.

● Fixed Critical 12nm DRC’S like

H384.M0,OD.L, etc.

Tools INOVUS,Prime time, Calibre,Laker,Star-RC,

Tweaker.

Project 6 Wisteria (28nm TSMC)

Role & Description

● PnR – Complete Physical Implementation

of the netlist, low power fixes, timing fixes,
DRC fixes congestion fixes and PI fixes

● Timing Closure – Generated ECOs using

path-based analysis and clock tweaks.

Description ● Owner of 2 Blocks named infra_safety and

rtap.

● Responsible for Complete PNR RUN and

integration.

● Blocks has 3million and 1.5 million

instances [Link] are Always ON
HPM blocks.
● Macro Dominant Blocks having 102 and
294Macros respectively.

● Responsible for Complete PNR, STA and PV

closure.

● Scripted ECOs for setup hold critical paths

for timing closures

● Used clock pull-push for fixing HOLD paths.

● Solved DRC’S , static and dynamic IR fixes.
 ● Cleaned LVS,ERC and ANT violations.

TOOLS USED ICC2,primetime,Tweaker,Calibre, Laker,Star-RC

Project7 AEOLIAN (28nm) Low power Design

Role Responsible for complete PnR, Timing Closure, LVS and DRC fixes

Description ● Handled two Blocks ldpc and ldpc_t having approx 2 M and 1M instances
respectively

● Responsible for complete PnR from netlist to GDSII.

● Responsible for handling the timing closure.

● Owned multiple blocks with more than 1 million instances each and more than
90 macros.

● Responsible for Physical verification. Handled responsibility of cleaning LVS and

DRC for both the block

● The design is a 28nm processor.

● Design frequency is 500MHz

Tools ICC2, LEC, Calibre,Tweaker,PrimeTime.

Project8 LAUREAL (14nm TSMC)

Role & Description Responsible for PV and PI closure of CHIP TOP.

Tools ICC2, Calibre.

EDUCATIONAL BACKGROUND:
Year Degree Major Subject Institutions Full time/Part time Marks%/CGPA

2012-16 Bachelor of E.C.E RVS College of Engineering and Full time 8.43
Technology Technology, Jamshedpur,Jharkhand

2010- 10+2 Physics,Chemistry,Math Tender Heart Senior secondary 2years 88.6%

2012 s school,Ranchi,Jhanrkhand

2010 10th - ST. THOMAS Full time 87%

 SCHOOL,Ranchi,Jhanrkhand

Other Details:

Currently working in Client Company MEDIATEK [Deployed as contractor from May,2017-present]

Rmz ecoworld,building 4AB,bellandur,Banglore-560103,Karnataka

Current Company Name: Synapse Techno Design Innovations Private Limited [01/04/2017 – Present]

Prestige Shantineketan, 8th Floor, Tower `C` Commercial Complex, Gate No. 2, Near ITPL, Whitefield Main
Road, Thigalarapalya, Krishnarajapura, Bengaluru, Karnataka 560066