JSCOE 210257: Microprocessor Laboratory 2019
ASSIGNMENT NO: 7
TITLE: Write X86/64 ALP to switch from real mode to protected mode and display the
values of GDTR, LDTR, IDTR, TR and MSW Registers.
OBJECTIVES:
1. To be familiar with the format of assembly language program structure and
instructions.
2. To study GDTR, LDTR and IDTR.
PROBLEM DEFINITION:
Write X86/64 ALP to switch from real mode to protected mode and display the values of
GDTR, LDTR, IDTR, TR and MSW Registers.
INPUT: system file
OUTPUT: contents of GDTR, LDTR and IDTR.
THEORY:
Four registers of the 80386 locate the data structures that control segmented memory
management called as memory management registers:
1. GDTR: Global Descriptor Table Register
These registers point to the segment descriptor tables GDT. Before any segment register
is changed in protected mode, the GDT register must point to a valid GDT. Initialization
of the GDT and GDTR may be done in real-address mode. The GDT (as well as LDTs)
should reside in RAM, because the processor modifies the accessed bit of descriptors.
The instructions LGDT and SGDT give access to the GDTR.
2. LDTR: Local Descriptor Table Register
These registers point to the segment descriptor tables LDT. The LLDT instruction loads
a linear base address and limit value from a six-byte data operand in memory into the
LDTR. The SLDT instruction always stores all 48 bits of the six-byte data operand.
3. IDTR: Interrupt Descriptor Table Register
JSCOE 210257: Microprocessor Laboratory 2019
This register points to a table of entry points for interrupt handlers (the IDT). The LIDT
instruction loads a linear base address and limit value from a six-byte data operand in
memory into the IDTR. The SIDT instruction always stores all 48 bits of the six-byte
data operand.
4. TR: Task Register
This register points to the information needed by the processor to define the current task.
These registers store the base addresses of the descriptor tables (A descriptor table is
simply a memory array of 8-byte entries that contain Descriptors and the descriptor
stores all the information about segments) in the linear address space and store the
segment limits.
SLDT: Store Local Descriptor Table Register
Operation: DEST ← 48-bit BASE/LIMIT register contents;
Description: SLDT stores the Local Descriptor Table Register (LDTR) in the two-byte register
or memory location indicated by the effective address operand. This register is a selector that
points into the Global Descriptor Table. SLDT is used only in operating system software. It is
not used in application programs.
Flags Affected: None
SGDT: Store Global Descriptor Table Register
Operation: DEST ← 48-bit BASE/LIMIT register contents;
Description: SGDT copies the contents of the descriptor table register the six bytes of memory
indicated by the operand. The LIMIT field of the register is assigned to the first word at the
effective address. If the operand-size attribute is 32 bits, the next three bytes are assigned the
BASE field of the register, and the fourth byte is written with zero. The last byte is undefined.
Otherwise, if the operand-size attribute is 16 bits, the next 4 bytes are assigned the 32-bit BASE
field of the register. SGDT and SIDT are used only in operating system software; they are not
used in application programs.
Flags Affected: None
SIDT: Store Interrupt Descriptor Table Register
Operation: DEST ← 48-bit BASE/LIMIT register contents;
JSCOE 210257: Microprocessor Laboratory 2019
Description: SIDT copies the contents of the descriptor table register the six bytes of memory
indicated by the operand. The LIMIT field of the register is assigned to the first word at the
effective address. If the operand-size attribute is 32 bits, the next three bytes are assigned the
BASE field of the register, and the fourth byte is written with zero. The last byte is undefined.
Otherwise, if the operand-size attribute is 16 bits, the next 4 bytes are assigned the 32-bit BASE
field of the register. SGDT and SIDT are used only in operating system software; they are not
used in application programs.
Flags Affected: None
ALGORITHM:
1. Display welcome message on terminal using macro disp.
2. Store the most significant bit of CR0 in the eax register.
3. Check the PE bit of CR0.
4. If PE=1 then display the message “Processor is in Protected mode”. 5. And if
PE=0 then display the message “Processor is in Real mode”. 6. Then copies/stores
the contents of GDT, IDT, LDT using sgdt, sidt, sldt instruction. 7. Display their contents
using macro function disp and disp_num.
FLOWCHART:
JSCOE 210257: Microprocessor Laboratory 2019
CONCLUSION:
In this way, we use GDTR, LDTR and IDTR in Real mode.
JSCOE 210257: Microprocessor Laboratory 2019
QUESTIONS:
Oral Question Bank
1. Different types of operating modes?
2. State the difference between different operating modes? 3.
Explain descriptor and descriptor table?
4. What is CR0 and what are its contents?
5. Explain different types of descriptor tables?
6. Explain how to load and store the contents of the descriptor table?
