TH E ANALOG M IN D

Behzad Razavi

The Design of an Equalizer—Part One

E
Equalizers are widely used in broad-
band wireline systems. At high data
rates, the imperfections of the medium
through which the signal travels (the
“channel”) become more critical, mak-
therefore assume certain character-
istics for the channel. We employ a
“scalable” model that reflects the
physical loss mechanisms in cop-
per media [1]. Shown in Figure 1(a)
those computed by electromagnetic
field simulations of a 50-Ω channel.
Cascading 12 such sections yields
the loss profile depicted in Fig-
ure  1(b) and a value of 21 dB at
ing equalization an essential function is one section of the model, with 28 GHz. Note that the line is driven
in receivers (Rxs). its horizontal and vertical branches by a 50-Ω source and is terminated
In this two-part article, we study the representing frequency-dependent with a 50-Ω load.
transistor-level design of a high-speed copper and dielectric losses, respec- In addition to loss, copper media
equalizer in 28-nm CMOS technology. tively [1]. The component values can also suffer from impedance dis-
The first part describes channel mod- are obtained by fitting the circuit’s continuities. For example, a connec-
eling and linear equalizer design. The magnitude and phase responses to tor attaching a cable to a line card
second part deals with decision-feed-
back equalizers (DFEs). We target the
470 pH
following performance: 77.3 pH
■■ Data format: nonreturn to zero

■■ Data rate = 56 Gb/s

2 kΩ 100 Ω
■■ Channel loss at 28 GHz = 20 dB
5.55 Ω
30.9 fF
■■ Input differential swing = 800 mVpp 200 fF 80 fF
■■ Bit error rate (BER) <10 −12

■■ Power consumption = 10 mW
(a)
■■ V DD = 1 V.
0
It is customary to specify the chan-
nel loss at the “Nyquist frequency,” –5
fNyq, i.e., the frequency equal to half
Channel Response (dB)

of the data rate. The reader is re­­ –10

ferred to several background arti-
–15
cles [1]–[3] and the vast literature on
the subject [4]–[17]. The simulations –20
are carried out with VDD = 1 V - 5%
–25
in the slow-slow corner of the pro-
cess and at T = 75 °C. –30

General Considerations –35

The purpose of equalization in an Rx is –40
to compensate for channel nonideali- 108 109 1010 1011
ties and reproduce the transmitted data Frequency (Hz)
with a low error rate. The design must (b)

Digital Object Identifier 10.1109/MSSC.2021.3111426 FIGURE 1: (a) One section of a scalable channel model and (b) the loss profile for 12
Date of current version: 17 November 2021 cascaded sections.

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may exhibit an impedance that has ponents of the received data. In tal frequency of (1/rb) /2 = fNyq . This
a real component different from practice, however, various tradeoffs periodic segment experiences the
50 Ω as well as a finite imaginary in CTLE design allow only partial greatest degradation in the chan-
value. As a result, the frequency res­­ flattening of the response, thereby nel, as illustrated by the differential
ponse experiences a deep notch, an requiring that the DFE perform fur- waveforms in Figure 3(b) for a loss of
effect that can be compensated by a ther equalization. 12 dB at fNyq . But we also recognize
DFE but not by a linear equalizer. The significance of the Nyquist that the worst case occurs for the
Analog equalization in Rxs is real- frequency, fNyq, is better appre- first transition, which arrives after
ized by a continuous-time linear equal- ciated by examining the channel 5.25 ns, i.e., after the channel has
izer (CTLE) and a DFE [Figure 2(a)]. response in the time domain. Con- “relaxed.” As the periodic segment
The CTLE ideally “inverts” the chan- sider a random sequence of ones proceeds, the output reaches the
nel, i.e., it provides the inverse of and zeros arriving at a rate of rb bits steady state and a greater swing.
the channel’s frequency response per second, i.e., with a bit period of
so that the product of their transfer 1/rb = Tb . As depicted in Figure 3(a), Basic CTLE Stage
functions has a relatively flat magni- such a sequence can follow a 0–1– The most common approach to cre-
tude up to the Nyquist frequency 0–1 pattern for some time, e.g., from ating a boost at high frequencies
[Figure 2(b)]. We say that the CTLE 5.3 to 5.4 ns, which we consider a incorporates resistive and capaci-
“boosts” the high-frequency com- periodic signal having a fundamen- tive degeneration in a differential

Channel Din
Continuous-Time Decision−Feedback
Dout
Linear Equalizer Equalizer

CK
(a)

Channel CTLE Cascade

Response Response Response

f f fNyq f
(b)

FIGURE 2: (a) A typical equalizer architecture and (b) an illustration of its overall frequency response.

0.9 0.85
0.85
0.8
0.8
0.75
0.75
Voltage (V)
Voltage (V)

0.7 0.7
0.65
0.65
0.6
0.6
0.55

5.25 5.3 5.35 5.4 5.25 5.3 5.35 5.4

Time (ns) Time (ns)
(a) (b)

FIGURE 3: (a) The input and (b) output waveforms of a lossy channel.

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pair, as shown in Figure 4(a). It can a greater C1 and hence a lower ~ p ity, however, the situation is more com-
be readily proved that the circuit’s reduce the frequency at which the plex. With the low available boost factor
transfer function, H (s) = Vout /Vin, is peak occurs. These points encour- per stage, the Bode plot of | H (j~) | in
given by age us to apply inductive peaking Figure 4(b) proves inaccurate because
so as to approach the first case. ~ z and ~ p are separated by a factor
- g m R D (R S C S s + 1)
H (s) = , (1) To raise the boost factor, we can of only 2 to 3. The actual behavior is
R S C S s + 1 + g m R S /2
cascade multiple CTLE stages, but depicted in Figure 6 and can be quan-
where gm denotes the transconduc- at the cost of reduced small-signal tified as follows. We express | H (j~) | 2
tance of M 1 and M 2 and channel- bandwidth and greater power con- from (1) as
length modulation is neglected. The sumption. If each stage’s bandwidth 2 2
stage exhibits a zero and a pole, limitation is approximated by a single | H (j~) | 2 = K 2 ~ 2 + ~ 2z , (5)
~ + ~p
respectively: pole at 2rf0, then n identical stages
yield a total bandwidth of where K = g m R D, and evaluate it at
| ~z | = 1 (2) ~ = ~ p = (1 + g m R S /2) ~ z:
RS CS
BW tot = 2 1/n - 1 f0 .(4)
1 + g m R S /2 2
1
| ~p | = , (3) | H (j~ p) | 2 = K 1 +
2 > gm RS 2 H
RS CS .
For example, two stages lower the (6) c1 + m
2
and the magnitude of its response bandwidth by 35%. These constraints
varies from g m R D / (1 + g m R S /2) at imply that it is difficult to use more
low frequencies to g m R D at high than two CTLE stages, and that the That is,
frequencies [Figure 4(b)]. The cir- DFE in Figure 2(a) must shoulder the
cuit thus provides a boost factor of remainder of the equalization. | H (j~ p) | = K 1+ 1 .
c1 + m
2 gm RS 2
1 + g m R S /2. Note that the zero and (7) 2
pole frequencies are separated by Pole-Placement Considerations
the same factor. In the CTLE stage studied previously, If the boost factor, 1 + g m R S /2, ranges
The CTLE stage of Figure 4(a) merits we may naturally conclude that the from 2 to 3, then | H (j~ p) | falls between
two remarks. First, the boost factor trades degeneration pole, ~ p , should be placed 0.79K and 0.74K, i.e., roughly 2 to 2.5 dB
with the low-frequency gain (also called around the Nyquist frequency. In real- below the maximum value. The key
the dc gain), g m R D / (1 + g m R S /2) . We
wish to maintain this gain around
unity so that the received data swings VDD
are not attenuated. With low supply RD RD
|H(jω)|
voltages and channel-length modu-
lation, the boost factor typically Vout
gmRD
does not exceed 6 dB. Second, we Vin M1 M2
surmise that ~ p should be placed
roughly around the Nyquist frequency, RS gmRD
but as indicated by the red plot in
gmRS
Figure 4(b), the limited bandwidth 1+
CS 2
at the output makes it difficult to do ωz ωp ω
so. For this reason, high-speed CTLEs
often employ inductive peaking. (a) (b)
The output pole, ~ 0 , in Figure 4(a)
results from the load resistance FIGURE 4: (a) A basic CTLE stage and (b) its approximate response.
and capacitance, presenting sig-
nificant challenges in high-speed
CTLE design. The relative magni- |H(jω)| |H(jω)|
tudes of this pole and that due to
gmRD gmRD
source degeneration lead to differ-
ent responses and dependencies CS CS
gmRD gmRD
upon CS . As shown in Figure 5(a),
if ~ 0 2 ~ p, then increasing CS sim- gmRS gmRS
1+ 1+
ply shifts the high-pass response 2 2
ωz ω p ω0 ω ωz ω0 ω p ω
to the left. On the other hand, if
~ 0 1 ~ p [Figure 5(b)], then two effects (a) (b)
emerge. First, | H | fails to reach its
maximum value of g m R D . Second, FIGURE 5: The CTLE response for (a) ~ 0 2 ~ p and (b) ~ 0 1 ~ p .

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point here is that, to create maxi- realize a programmable boost fac- to approximately 20 GHz. The dc
mum boost at fNyq, the pole frequ­­ tor. We can then design the DFE and gain is about unity. The bandwidth
ency should be chosen well below study the performance of the over- falls short of fNyq = 28 GHz and can
this frequency. For example, to obtain all equalizer. be increased by lowering RD but at
| H (j2rfNyq) | = 0.95K, (7) indicates We begin the design of our two- the cost of dc gain. This tradeoff
that ~ p must be chosen according to stage CTLE with a power budget of must eventually be studied when
5 mW, leaving the other 5 mW for the the CTLE-DFE chain is formed.
0.312 (2rfNyq) DFE. Biased at 2.5 mW, each stage We now cascade two such stages
~p = .(8)
0.95 2 - 1 then allows a current of 1.25 mA so as to raise the boost factor [see
c1 + m S m
g R 2
per transistor. We then select the Figure 8(a)]. As an approximation
2
as­­pect ratio, W/L, of M1 and M2 in of t he input ca­­pacit a nce of the
For a boost factor of 2 to 3, ~ p ranges Figure 4(a) according to two require- next stage, two NMOS devices with
from 0.39 (2rfNyq) to 0.35 (2rfNyq), ments, namely, the desired trans- W/L = 10 nm/30 nm are attached
i.e., the pole frequency should be conductance and an acceptable to t he out put no des . Plot ted in
roughly 2.5 to 3 times less than fNyq . gate-source overdrive voltage. The Fig ­­ure 8(b), the overall res­­p onse
former plays a role in the boost fac- exhibits a boost of 14 dB at 25 GHz.
CTLE Design tor while the latter determines the Preceding the CTLE with the channel
CTLE design proceeds in four steps. voltage headroom for the tail cur- yields the behavior in Figure 8(c) and
1) We place the degeneration pole rent sources and across the drain hence, roughly 8 dB of loss at fNyq .
around one-third of fNyq and imple- resistors. According to simulations, a Unlike the first stage, the second
ment the CTLE. 2) We precede the W/L of 10 nm/30 nm gives a gm of does not see Miller capacitance
CTLE with the channel and examine 10 mS and an overdrive of 170 mV, multiplication, thus achiev ing a
the flatness of the cascade response. both reasonable values. We then tar- wider bandwidth.
3) We study and optimize the eye get a boost factor of 1 + g m R S /2 = 3, The next step is to study the eye
diagram at the CTLE output. 4) We obtaining R S = 400 X. We also place diagrams. Depicted in Figure 9(a)
~ p at 2r (28 GHz) /3 and arrive at a and (b) are the channel and CTLE
value of 150 fF for CS. The drain resis- outputs, respectively. We observe a ver-
tors are constrained by the voltage tical opening of 250 mV and a horizon-
|H(jω)| headroom; we select R D = 400 X for tal opening of 13 ps.
~2.5 dB a voltage drop of 500 mV. As mentioned prev iously, the
gmRD
Figure 7(a) depicts the design tradeoff between the dc gain and the
of the first stage. We load the cir- boost factor should be examined in
cuit by an identical stage for now. a given design. Specifically, does the
Figure 7(b) plots the response with vertical eye opening in Figure 9(b)
ωz ωp ω L D  =  0 and L D  =  600 pH, suggesting increase if the dc gain is raised and
that inductive peaking raises the the boost is, inevitably, reduced? For
FIGURE 6: An illustration of an actual CTLE boost from 5.4 to 6.2 dB and its cor- example, we can choose R S = 300 X
response. responding frequency from 15 GHz and C S = 200 f F. But simulations

6
5 LD = 0
VDD LD = 600 pH
4
LD LD
Magnitude (dB)

3
400 Ω 400 Ω
2
1
Vin M1 M2
0
400 Ω W 10 µm
= –1
L 30 nm
–2
1.25 mA 150 fF 1.25 mA 108 109 1010 1011
Frequency (Hz)
(a) (b)

FIGURE 7: (a) The design of the first CTLE stage and (b) its frequency response.

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 VDD

Channel
Stage 1 Stage 2
VDD

(a)

14 5

12 0
10
–5
Magnitude (dB)

Magnitude (dB)
8
–10
6
–15
4
–20
2

0 –25

–2 –30
108 109 1010 1011 108 109 1010 1011
Frequency Frequency
(b) (c)

FIGURE 8: (a) The two-stage CTLE, (b) its frequency response, and (c) the channel-CTLE cascade response.

0.4 0.5

0.3 0.4
0.3
0.2
0.2
0.1 0.1
VCTLE (V)

VCTLE (V)

0 0

–0.1 –0.1
–0.2
–0.2
–0.3
–0.3 –0.4
–0.4 –0.5
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Time (ps) Time (ps)
(a) (b)

FIGURE 9: The output eyes of (a) the channel and (b) the CTLE.

reveal that the eye suffers further assumption at this point is that the data if the loss is lower. As a result,
closure in this case. Conversely, DFE will further improve the eye. significant intersymbol ­ interference
R S = 600 X and C S = 100 fF increase appears at the CTLE output. For this
the boost factor but do not improve The Need for Programmable Boost reason, the boost must be ­ variable.
the output eye. Broadband Rxs must operate proper­ This is typically accomplished by
Whether the eye opening depict­ ­ly with different channel responses. implementing the degeneration capaci-
­ed in Figure 9(b) is adequate for The CTLE developed thus far is opti- tors as programmable units. A lower
a BER < 10 -12 or not is ultimately mized for a loss of approximately
de­­termined by the DFE design. Our 20 dB at fNyq, and “overequalizes” the (continued on p. 160)

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FIGURE 9: The Best Demo Paper Award was given to two papers at the VLSI 2021: “Energy-Efficient Reliable HZO FeFET Computation-in-Mem-
ory with Local Multiply and Global Accumulate Array for Source-Follower and Charge-Sharing Voltage Sensing” by the University of Tokyo,
and “A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge” by CSEM and ETH Zürich.

online contents and industry sys- Society of Applied Physics in coopera- the Japan Society of Applied Physics in
tems session. For further information, tion with the Institute of Electronics, cooperation with SSCS.
please visit www.vlsisymposium.org. Information, and Communication Engi- —Sugako Otani
The Symposium on VLSI Circuits is neers and the IEEE Electron Devices Publicity Chair, Symposium
sponsored by the IEEE Solid-State Society (EDS). The Symposium on VLSI on VLSI Circuits
Circuits Society (SSCS) and the Japan Technology is sponsored by EDS and 

TH E ANALOG M IN D (continued from p. 11)

value pushes the pole to higher fre- Conf. (ISSCC), Feb. 2019, pp. 118–120. doi: [12] J. Han, N. Sutardja, Y. Lu, and E. Alon, “De-
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