PART-1

Mastering Microcontroller with

Embedded Driver Development
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GPIO Must Know
Concepts !
Section Takeaways !

 This section has totally 7 lectures

 You will learn about behind the scene implementation about
GPIO pin and GPIO port
 GPIO Input mode configurations like HIGH-Z , pull-up,pull-down
state
 You will learn about different GPIO output Configurations like
Open drain, pushpull , etc.
 You will learn about I/O power optimization
GPIO Pin and GPIO Port
General
Purpose
Input
Output
GPIOs typically used for
Let‟s begin with some of the must know concepts in
GPIO. These concepts are generic and can be
applied to any microcontroller you have !
PA.0

GPIO Port A

PA.1 PA.15

Port „A‟ having many pins Port „Soller Town‟ having many boats
Each port have Each port have Each port have
8 i/o pins 32 i/o pins 16 i/o pins
GPIO Pin Behind the Scene
How does a GPIO pin is actually
implemented inside the MCU?
 Enable Line

Output buffer Pin

Input buffer

YOUR MCU
 +VCC
Enable Line
source
Output buffer gate
PMOS
T1
Pin
Pin
drain

T2
NMOS
Input buffer gate

source

MCU GND
 Enable Line
Output buffer +VCC
Pin S

T1 P Pin
G
D
Input buffer
T2 N
S

MCU
 Enable Line +VCC
Output buffer +VCC
Pin S

T1 P Pin
G
D
Input buffer
T2 N
S

MCU
 Enable Line
Output buffer +VCC
Pin S

T1 P Pin
G
D
Input buffer
T2 N
S

MCU
GPIO INPUT MODE
High Impedance(HI-Z) State
Let‟s understand, what exactly is this High
Impedance state, that people talk about when
the pin is in input mode ??

High impedance is also called as HI-Z state

 +VCC

S
T1 P
Pin Floating=Hi-Z
D G

T2 N Input Not Fixed

S

GND
GND
GPIO INPUT MODE
Pull-Up/Pull-Down State
 +Vcc
Input Buffer
Pin
Input Buffer Ri Re
Pin

GND
GPIO OUTPUT MODE
Open-drain State
 +VCC
S

P T1 Pin
G
D

N T2
S

GND
 +VCC
S

P T1 Pin
G
D

N T2
S

GND
GPIO OUTPUT MODE
Open drain with Pull-Up
 +VCC +VCC

Ri Re
Pin Pin
D D
G
P G P
S S

GND GND
Open drain with internal pull up Open drain with External pull up
Practical Usage -1

How to drive a LED from

Open drain GPIO Pin ??
Driving LED‟s
+VCC +VCC

R
R
Pin Pin
D D
LED LED
G N G N
S S

GND GND GND GND

Using Internal Pull-up Using External Pull-up

Practical Usage -2

Driving I2C bus

 +Vcc

I2C Bus SDA SCL

Pull-Up
Pull-Up
Serial Data Line(SDA)

Pin Serial Clock line(SCL)

Pin
MCU
SCL Rx
SDA Rx

SCL Tx D
SDA Tx D G
N
G
N
S
S

GND GND
GPIO OUTPUT MODE
Push-Pull State
Output Mode with Push-Pull
Configuration +VCC

S
P T1 Pin
G D

N T2
S

GND
 +VCC +VCC

Ri Re
Pin Pin
D D
G
P G P
S S

GND GND
Open drain with internal pull up Open drain with External pull up
How to drive a LED from
Push-Pull GPIO Pin ??
 +VCC

S
P T1
G D Pin
N T2
S
R
GND
LED

GND
Discovery Board LED Connection
+VCC

S
P T1
G D PD12
Pin
N T2
S R
GND LED_GREEN
Optimizing IO Power
Consumption
Leakage Mechanism By Input Pin Floating
 Fixed to High
MCU +VCC +VCC MCU +VCC

S S
T1 P T1
Pin P
Pin
D D
G G
T2 N T2 GND
N
S
S

Fixed to Low
GND GND
 Voltage of input
MCU is not fixed
+VCC
May be 0.5Vcc Input Logic Level
or 0.3Vcc
S
T1 P Pin
D G

T2 N
S

GND
GND
 Valve opened
Valve Closed partially

No water flows
Water Tickles out
GPIO Programming Structure
 Port Direction(Mode)
register

Port Speed Register

Port output type

Register MCU
I/O I/0 Pins
BUS
Some other PORT
configuration Register

Port OutPut Data

Register
Port Input Data
Register
In STM32F4xx series of microcontrollers, each GPIO
port is governed by many configuration registers.
Exploring GPIO Port and Pins
On the Discovery board
STM32F407VG
GPIOA
GPIOA
GPIOB
GPIOB
GPIOC
Each port will have its GPIOC
GPIOD Own set of configuration GPIOD
GPIOE registers
GPIOE
GPIOF
GPIOG
GPIOH
GPIOI
GPIO Driver
development
GPIO Port MODE Register
 32 bit reg. 32 bit reg.
32 bit reg.

GPIOA_MODER GPIOB_MODER GPIOC_MODER

32 bit reg. 32 bit reg.

32 bit reg.

GPIOD_MODER GPIOE_MODER GPIOF_MODER

32 bit reg.
32 bit reg. 32 bit reg.

GPIOG_MODER GPIOH_MODER GPIOI_MODER

Before using any GPIO, you must decide its MODE.
Whether you want to use it as an Input, Output or
for any analog purposes
A GPIO Pin can be used for many purposes as shown here . That‟s why it
is called as “General” Purpose.
Some pins of the MCU can not be used for all these purposes. So those
are called as just pins but not GPIOs

An MCU GPIO Pin

INPUT OUTPUT ALT. FUN. ANALOG

INTERRUPT
When MCU pin is in INPUT
mode it can be configured to
issue an interrupt to the
processor
Input configuration
Input mode : Summary

 When the I/O port is programmed as Input:

 the output buffer is disabled
 the Schmitt trigger input is activated
 the pull-up and pull-down resistors are activated depending
on the value in the GPIOx_PUPDR register
 The data present on the I/O pin are sampled into the input
data register every AHB1 clock cycle
 A read access to the input data register provides the I/O
State
Floating input
Output configuration
Output configuration ( Push pull)
Output configuration ( Push pull)
Output configuration ( Open Drain)
Alternate function configuration
GPIO Port Output Type Register
When a GPIO pin is in the output
mode, this register is used to select the
output type of that pin
GPIO Port Speed Register
By using speed register you can
configure “how quick the GPIO transitions
from H to L and L to H”
In other words you can control the slew rate of a pin
 LOW

Slew rate
 MEDIUM

Slew rate
 HIGH

Slew rate
 VERY HIGH

Slew rate
 VERY HIGH

Slew rate
Applicability of SPEED register
configuration

Pin Mode = Applicable

OUTPUT
Applicability of SPEED register
configuration

Don‟t care
Pin Mode =
INPUT

So, Speed setting is only applicable when the pin is in output mode
GPIO Port Pull-Up/Pull-Down
Register
GPIO Port Input Data Register
GPIO Port Output Data
Register
 GPIO Functional Summary
By taking various modes and pull up /pull down resistors combinations
below configurations can be obtained for a GPIO pin

Input floating
Input pull-up
Input-pull-down
Analog
Output open-drain with pull-up or pull-down capability
Output push-pull with pull-up or pull-down capability
Alternate function push-pull with pull-up or pull-down capability
Alternate function open-drain with pull-up or pull-down capability
 Alternate Functionality
configuration of a GPIO pin
 An MCU GPIO Pin

INPUT OUTPUT ALT. FUN. ANALOG

When a GPIO is in Alternate

INTERRUPT functionality mode it can be
used for 16 different
functionalities .
A GPIO Pin‟s 16 possible alternate
functionalities
Exercise :
List out all the 16 possible alternation functionalities supported by GPIO
port „A‟ pin number 8 (GPIOA.8)

MODE(Afx) Functionality
AF0 MCO1
AF1 TIM1_CH1
AF2 Not Supported
AF3 Not Supported
AF4 I2C3_ SCL
AF5 Not Supported
AF6 Not Supported
AF7 USART1_ CK
Exercise :
List out all the 16 possible alternation functionalities supported by GPIO
port „A‟ pin number 8 (GPIOA.8)

MODE(Afx) Functionality
AF8 Not Supported
AF9 Not Supported
AF10 OTG_FS_ SOF
AF11 Not Supported
AF12 Not Supported
AF13 Not Supported
AF14 Not Supported
AF15 EVENT OUT
Exercise :
List out all the alternation functionalities supported by GPIO port „C‟ pin
number 6 (GPIOC.6)
Solution :
List out all the alternation functionalities supported by GPIO port „C‟ pin
number 6 (GPIOC.6)

MODE(Afx) Functionality
AF0 Not Supported
AF1 Not Supported
AF2 TIM3_CH1
AF3 TIM8_CH1
AF4 Not Supported
AF5 I2S2_MCK
AF6 Not Supported
AF7 Not Supported
Solution :
List out all the alternation functionalities supported by GPIO port „C‟ pin
number 6 (GPIOC.6)

MODE(Afx) Functionality
AF8 USART6_TX
AF9 Not Supported
AF10 Not Supported
AF11 Not Supported
AF12 SDIO_D6
AF13 DCMI_D0
AF14 Not Supported
AF15 EVENT OUT
GPIO Alternate
Function Register
Example

Find out the alternate functionally mode(AFx) and

AFR(Alternate Function Register) settings to make
PA0 as UART4_TX
PA1 as UART4_RX
PA10 as TIM1_CH3
Solution: PA0 as UART4_TX

AFx = AF8
( This info you can only get from datasheet of the MCU not from
RM in the case of ST‟s MCUs)
Solution: PA0 as UART4_TX
AFR settings

GPIOA_AFRL
Solution: PA1 as UART4_RX
AFx = AF8

GPIOA_AFRL
Solution: PA10 as TIM1_CH3
AFx = AF1

GPIOA_AFRH
Enabling /Disabling GPIO Port
Peripheral Clock
RCC Peri. Clock Enable Registers

RCC_AHB1ENR

RCC_AHB2ENR

RCC_AHB3ENR

RCC_APB1ENR

RCC_APB2ENR
Peripheral Driver
Development
High level project
architecture
 Sample Applications

Driver Layer
(Device header)
gpio_driver.c , .h i2c_driver.c , .h Stm3f407xx.h

spi_driver.c , .h uart_driver.c , .h

GPIO SPI I2C UART

STM3F407x MCU
 3 Sample Applications

Driver Layer
(Device header)
gpio_driver.c , .h i2c_driver.c , .h Stm3f407xx.h
2
1
spi_driver.c , .h uart_driver.c , .h

GPIO SPI I2C UART

STM3F407x MCU
What is Device Header file and what it
contains ?
This is a header file („C‟ header file in our case) which contains Microcontroller
specific details such as

1) The base addresses of various memories present in the microcontroller such

as (Flash, SRAM1,SRAM2,ROM,etc)
2) The base addresses of various bus domains such as (AHBx domain, APBx
domain)
3) Base addresses of various peripherals present in different bus domains of the
microcontroller
4) Clock management macros ( i.e clock enable and clock disable macros)
5) IRQ definitions
6) Peripheral Register definition structures
7) Peripheral register bit definitions
8) Other useful microcontroller configuration macros
 (Device header)

Stm3f407xx.h

Application Driver files

Application and Driver source files can #include device

specific header file to access MCU specific details
In the next lecture lets create
MCU Device specific header file
step by step
New project creation
Define base addresses of MCU
embedded memories using „C‟ macros
Defining base addresses of various bus
domains (AHBx , APBx)
Different bus domains of PERIPH_BASE
the stm32f4x MCU .

APB1PERIPH_BASE APB2PERIPH_BASE AHB1PERIPH_BASE AHB2PERIPH_BASE

•Different peripherals are hanging on different busses .

•AHB bus is used for those peripherals which need high speed data communication (ex. Camera
interfaces, GPIOs)
•APB bus is used for those peripherals for which low speed communication would suffice .
Full Memory map of the MCU 0xFFFF_FFFF

From here onwards peripheral

register addresses start

(APB1PERIPH_BASE) 32 bits wide 0x40000000 (PERIPH_BASE)

32 bits wide 0x0000_0004 Offset between 2

memory addresses is 4
32 bits wide 0x0000_0000 bytes
Full Memory map of the MCU 0xFFFF_FFFF

Find out 0x4000_0000 is the

address of which register of which
peripheral ????

From here onwards peripheral

register addresses start

(APB1PERIPH_BASE) 32 bits wide 0x40000000 (PERIPH_BASE)

32 bits wide 0x0000_0004 Offset between 2

memory addresses is 4
32 bits wide 0x0000_0000 bytes
 Figure shows Peripheral base addresses of different bus domains
In stm32f407xx MCU
0x40000000
PERIPH_BASE
(APB1PERIPH_BASE)

Offset : 0x00010000 Offset : 0x00020000 Offset:0x10000000

APB2PERIPH_BASE AHB1PERIPH_BASE AHB2PERIPH_BASE

0x40010000 0x40020000 0x50000000

This simply means that registers of peripherals hanging on APB2 bus will appear
on address 0x40010000 onwards in the memory map of the MCU.
Defining base addresses of AHB1
peripherals, APB1 and APB2 peripherals
 AHB1

GPIOA GPIOB GPIOC GPIOD GPIOE …. GPIOI

APB1

I2C1 I2C2 I2C3 SPI2 SPI3 USART2 USART3 UART4 UART5

APB2

SPI1 USART1 USART6 EXTI SYSCFG

Addresses of the peripheral registers
Determining addresses of 0x40000000
various registers of a
peripheral PERIPH_BASE

0x40020000

APB1PERIPH_BASE APB2PERIPH_BASE AHB1PERIPH_BASE AHB2PERIPH_BASE

GPIOA 0x4002 0000

MODE Reg. OUTPUT TYPE Reg. SPEED Reg. PUPDR Reg. IDR Reg. ODR Reg. BSRR Reg.

Offset:0x00 0x04 0x08 0x0C 0x10 0x14 0x18

0x40020000 0x40020004 0x40020008 0x4002000C 0x40020010 0x40020014 0x40020018
Exercise:
Find out the addresses of below registers of SPI1 peripheral .

Register Name Address

control register 1 ??
control register 2 ??
status register ??
data register ??
CRC polynomial register ??
RX CRC register ??
TX CRC register ??
configuration register ??
prescaler register ??
Structuring Peripheral register details
Example : „C‟ Structure for registers
of GPIO peripheral

Variable(Place holder) to hold values for GPIOx_MODE register and so on

Address of MODER variable(&MODER) will be (0x40020000+0x00)
Address of OTYPER variable(&OTYPER ) will be (0x40020000+0x04) and so on

Base address of GPIOA

Base address of GPIOA
Base address of GPIOA
Peripheral clock enable and disable macros
Macros for IRQ(Interrupt Request) Numbers
of the MCU
Creating GPIO Driver .c and .h files
GPIO Handle and
Configuration structures
 GPIO Port Name

GPIO Pin number

GPIO mode
GPIOx
Peripheral Configurable items
For user application
GPIO speed

GPIO outputtype

GPIO Pullup-pulldown

GPIO Alt.function mode

GPIO Driver APIs requirements
Driver API Requirements
GPIO initialization

Enable/Disable GPIO port

clock

Read From a GPIO Pin

GPIO Driver
APIs

Write to GPIO Pin

Configure alternate
functionality

Interrupt Handling
GPIO Pin Interrupt Configuration

1. Pin must be in input configuration

2. Configure the edge trigger (RT,FT,RFT)
3. Enable interrupt delivery from peripheral to the processor (on
peripheral side)
4. Identify the IRQ number on which the processor accepts the
interrupt from that pin
5. Configure the IRQ priority for the identified IRQ number (Processor
side)
6. Enable interrupt reception on that IRQ number (Processor side)
7. Implement IRQ handler
STM32f4x GPIO Pins interrupt delivery to the
Processor
Processor side
MCU Peripheral side
6
GPIO port is decided by 7
SYSCFG_EXTICR register
configuration 8
EXTI0 9
GPIOx_PIN0
10
GPIOx_PIN1 EXTI1
23
GPIOx_PIN2 EXTI2 N
40
GPIOx_PIN3
EXTI EXTI3 V
GPIOx_PIN4 EXTI4 I Processor core
GPIOx_PIN5_9 EXTI5_9 5 C
GPIOx_PIN10_15
EXTI10_15 6
EXTI block does
Edge
detection(FT,RT) ,
Enable/Disable of
interrupt delivery to Enable/Disable of IRQs are
the processor configured in NVIC registers
Interrupt Set-enable Registers

NVIC_ISER0

IRQ31 IRQ16

IRQ15 IRQ9 IRQ2 IRQ1 IRQ0

0 has no effect
1 enables the interrupt
Interrupt Set-enable Registers

NVIC_ISER1

IRQ63 IRQ48

IRQ47 IRQ41
IRQ34 IRQ33 IRQ32

0 has no effect
1 enables the interrupt
Interrupt Set-enable Registers

NVIC_ISER2

IRQ95 IRQ80

IRQ66 IRQ65 IRQ64

0 has no effect
1 enables the interrupt
Interrupt Clear-enable Registers

NVIC_ICER0

IRQ31 IRQ16

IRQ15 IRQ9 IRQ2 IRQ1 IRQ0

0 has no effect
1 disable interrupt
Interrupt Priority Registers
NVIC_IPR0-NVIC_IPR59
Exercise
Write a program to toggle the on board LED with some delay .
Case 1 : Use push pull configuration for the output pin
Case 2 : Use open drain configuration for the output pin
Discovery Board LEDs
 CH3

CH1
USB Logic
Analyzer
CH2

CH0

GND GND
Probing LED Toggling using USB Logic Analyzer

CH0
USB Logic analyzer
CH1

To PC
GND
Exercise
Write a program to toggle the on board LED whenever the on board button is pressed
Exercise
Write a program to connect external button to the pin number PB12 and external LED to PA14
Toggle the LED whenever the external button is pressed
Exercise
Toggle a GPIO pin with no delay between
GPIO high and GPIO low and measure the
frequency of toggling using logic analyzer
Exercise
Connect an external button to PD5 pin and toggle the
led whenever interrupt is triggered by the button press.

Interrupt should be triggered during falling edge of

button press.
In the next lecture lets understand input
mode of a pin
Introduction to SPI
Serial
Peripheral
Interface
 SPI Bus
Serial Clock
SCLK SCLK
Master Out Slave In Slave
MOSI MOSI
Master
( Sensor, EEPROM,
Master In Slave Out
MISO MISO SDCARD,
Display,
Bluetooth,etc )
Slave Control
gpio1 ss

The SPI bus allows the communication between one master

device and one or more slave devices.
 Serial Clock
SCLK SCLK
Master Out Slave In Slave
Master MOSI MOSI
( Sensor, EEPROM,
Master In Slave Out
MISO MISO SDCARD,
Display,
Slave Control Bluetooth,etc )
gpio1 ss

1. Four I/O pins are dedicated to SPI communication with external devices.
2. MISO: Master In / Slave Out data. In the general case, this pin is used to
transmit data in slave mode and receive data in master mode
3. MOSI: Master Out / Slave In data. In the general case, this pin is used to
transmit data in master mode and receive data in slave mode.
4. SCK: Serial Clock output pin for SPI master and input pin for SPI slaves.
5. NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be
used to select an individual slave device for communication
 SCLK SCLK
MOSI MOSI Slave1
MISO MISO
Master gpio1 ss
gpio2
gpio3 SCLK
MOSI Slave2
MISO
ss

SCLK
MOSI Slave3
MISO
ss
Protocol Type Max distance(ft.) Max Speed Typical usage
(bps)
USB 3.0 dual simplex 9 (typical) 5G Mass storage,
serial (up to 49 video
with 5 hubs)

USB 2.0 half duplex 16 (98 ft. 1.5M, 12M, Keyboard,

serial with 5 hubs) 480M mouse, drive,
speakers, printer,
camera

Ethernet serial 1600 10G network

communications
I2C synchronous 18 3.4 M in High-speed Microcontroller
serial mode. communications
RS-232 asynchronous 50–100 20k Modem, mouse,
serial instrumentation

RS-485 asynchronous 4000 10M Data acquisition

serial and control
systemsSPI

SPI synchronous 10 fPCLK/2

serial
You can use CAN, ETHERNET ,
RS485, RS232 or combination of
them , when you have to cover
larger distances and want to
achieve better quality of service.
 SCLK SCLK
MOSI MOSI Slave1
MISO MISO
Master gpio1 ss
gpio2
gpio3 SCLK
MOSI Slave2
MISO
ss

SCLK
MOSI
MISO Slave3
ss
 SCLK
Master SCLK
Send
MOSI
MOSI
Receive
MISO MISO

gpio ss
 MINIMAL SPI BUS​
The SPI bus allows the communication between one master device and
one or more slave devices. In some applications SPI bus may consists of just
two wires - one for the clock signal and the other for synchronous data
transfer. Other signals can be added depending on the data exchange
between SPI nodes and their slave select signal management.​
Serial Clock
SCLK SCLK
Master Out Slave In Slave
Master MOSI MOSI
MISO MISO
gpio ss
SPI Hardware :Behind the scenes
SPI Hardware :Behind the scenes

SCLK

Shift Register Shift Register

A A A A A A A A MOSI
B7 B6 B5 B4 B3 B2 B1 B0
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
SPI Hardware :Behind the scenes
1

SCLK

Shift Register Shift Register

A A A A A A A MOSI A
B0 B7 B6 B5 B4 B3 B2 B1
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
SPI Hardware :Behind the scenes
1 2

SCLK

Shift Register Shift Register

A A A A A A MOSI A A
B1 B0 B7 B6 B5 B4 B3 B2
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
SPI Hardware :Behind the scenes
1 2 3

SCLK

Shift Register Shift Register

A A A A A MOSI A A A
B2 B1 B0 B7 B6 B5 B4 B3
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
SPI Hardware :Behind the scenes
1 2 3 4

SCLK

Shift Register Shift Register

A A A A MOSI A A A A
B3 B2 B1 B0 B7 B6 B5 B4
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
SPI Hardware :Behind the scenes
1 2 3 4 5

SCLK

Shift Register Shift Register

A A A MOSI A A A A A
B4 B3 B2 B1 B0 B7 B6 B5
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
SPI Hardware :Behind the scenes
1 2 3 4 5 6

SCLK

Shift Register Shift Register

A A MOSI A A A A A A
B5 B4 B3 B2 B1 B0 B7 B6
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
SPI Hardware :Behind the scenes
1 2 3 4 5 6 7

SCLK

Shift Register Shift Register

A MOSI A A A A A A A
B6 B5 B4 B3 B2 B1 B0 B7
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
SPI Hardware :Behind the scenes
1 2 3 4 5 6 7 8

SCLK

Shift Register Shift Register

MOSI A A A A A A A A
B7 B6 B5 B4 B3 B2 B1 B0
7 6 5 4 3 2 1 0

SPI clock
SCLK
generator
Master Slave

MISO
CUSTOMIZING SPI BUS : BUS CONFIGURATIONS​

The SPI allows the MCU to communicate using different configurations, depending
on the device targeted and the application requirements.
FULL-DUPLEX COMMUNICATION ​
Master Slave
MSBit LSBbit MSBit LSBbit
Up to 16-bit shift MISO MISO Up to 16-bit shift
register register

MOSI MOSI

SPI Clock SCK SCK

generator By default, the SPI is
NSS NSS configured for full-
duplex communication

In this configuration, the shift registers of the master and slave are linked using two unidirectional
lines between the MOSI and the MISO pins. During SPI communication, data is shifted
synchronously on the SCK clock edges provided by the master. The master transmits the data to
be sent to the slave via the MOSI line and receives data from the slave via the MISO line.
Remember that in SPI communication ,slave will not
initiate data transfer unless master produces the
clock.
HALF -DUPLEX COMMUNICATION ​
Master Slave
MSBit LSBbit MSBit LSBbit
MISO MISO
8-bit shift register 8-bit shift register
R
MOSI MOSI

SPI Clock SCK SCK

generator
NSS NSS

In this configuration, one single cross connection line is used to link the shift registers of the
master and slave together. During this communication, the data is synchronously shifted
between the shift registers on the SCK clock edge in the transfer direction selected
reciprocally by both master and slave
SIMPLEX COMMUNICATION ​
Master Slave
MSBit LSBbit MSBit LSBbit
MISO MISO
8-bit shift register 8-bit shift register

MOSI MOSI

SPI Clock SCK SCK

generator
NSS NSS

Simplex single master, single slave application (master in transmit-only/slave in receive-only mode)

Transmit-only , Receive Only mode :

The configuration settings are the same as for full- duplex. The application has to ignore the
information captured on the unused input pin. This pin can be used as a standard GPIO​
STM32 SPI FUNCTIONAL BLOCK DIAGRAM
 SLAVE SELECT (NSS) PIN MANAGEMENT ​
When a device is slave mode:​
In slave mode, the NSS works as a standard “chip select” input and
lets the slave communicate with the master.​
​
When a device is master:​
In master mode, NSS can be used either as output or input. As an
input it can prevent multi-master bus collision, and as an output it can
drive a slave select signal of a single slave. ​
 Master Slave
MSBit LSBbit MSBit LSBbit
MISO MISO
8-bit shift register 8-bit shift register

MOSI MOSI

SCK SCK
SPI Clock
generator
NSS NSS

Scenario of single master and single slave

2 Types of slave managements

Hardware slave management

Software slave management
 Scenario of single master and single slave
Master Slave
MSBit LSBbit MSBit LSBbit
MISO MISO
8-bit shift register 8-bit shift register

MOSI MOSI

SCK SCK
SPI Clock
generator
NSS NSS
Software NSS management (SSM = 1): in this
configuration, slave select information
is driven internally by the SSI bit value in
register SPIx_CR1. The external NSS pin is
free for other application uses.
Hardware or software slave select management can
be set using the SSM bit in the SPIx_CR1 register:
 Scenario of single master and single slave
Master Slave
MSBit LSBbit MSBit LSBbit
MISO MISO
8-bit shift register 8-bit shift register

MOSI MOSI

SCK SCK
SPI Clock
generator
NSS NSS
Hardware NSS management (SSM = 0):
Hardware NSS management (SSM = 0): Nss pin must be pulled low to active salve
Nss pin must be in output mode. to communicate with master
The NSS pin is managed by the
hardware

Hardware or software slave select management can be set using the SSM bit in the
SPIx_CR1 register:
In this application you
cannot use software slave
management . You have
to use hardware slave
management
SPI Communication Format
 SPI Communication Format

SCLK PHASE(CPHA) SCLK POLARITY(CPOL) Data frame format(DFF)

•During SPI communication, receive and transmit operations are performed

simultaneously​.

•The serial clock (SCK) synchronizes the shifting and sampling of the information on
the data lines​

•The communication format depends on the clock phase, the clock polarity and
the data frame format. To be able to communicate together, the master and
slaves devices must follow the same communication format. ​
CPOL(CLOCK POLARITY)​

 The CPOL (clock polarity) bit controls the idle state value of
the clock when no data is being transferred​
 If CPOL is reset, the SCLK pin has a low-level idle state. If
CPOL is set, the SCLK pin has a high-level idle state. ​
CPOL =0

CPOL =1
CPHA(CLOCK PHASE)

 CPHA controls at which clock edge of the SCLK( 1st or 2nd )

the data should be sampled by the slave.
 The combination of CPOL (clock polarity) and CPHA
(clock phase) bits selects the data capture clock edge. ​
Data toggling means, data transition to the next bit.

Data line 1 0 1

Data sampling means, sampling the data line to

capture the data.
Clock

Data line 1 0 1
CPHA=1
1 Data will appear on the lines during first edge of the SCLK
CPHA=1
2 Slave captures the data here ( 2nd edge of the SCLK)
CPHA=1 1
Data will appear on the lines during first edge of the SCLK

L
CPHA=0 1 Data will appear on the lines during 2nd edge of the lock
 2 Slave captures the data here ( 1st edge of the SCLK)
CPHA=0
Different SPI Modes
If CPHASE=1
Data will be sampled on the trailing edge of the
clock.

If CPHASE=0
Data will be sampled on the leading edge of the
clock.
SPI peripherals of your MCU

AHB1

GPIOA GPIOB GPIOC GPIOD GPIOE …. GPIOI

APB1

I2C1 I2C2 I2C3 SPI2 SPI3 USART2 USART3 UART4 UART5

APB2

SPI1 USART1 USART6 EXTI SYSCFG

SPI serial clock (SCLK)
What is the maximum SCLK speed of SPIx peripheral
which can be achieved on a given microcontorller ?

First you have to know the speed of the APBx bus on which
the SPI peripheral is connected
HSI
16MHz
HSE

PLL

/ APB1 bus prescalar

APB 1 bus ( 42 Mhz Max)

Min Prescalar fpclk = 16MHz

=2
8MHz / SPI2/SPI3
SCLK
HSI
16MHz
HSE

PLL

/ APB2 bus prescalar

APB 2 bus ( 84 Mhz Max)

Min Prescalar fpclk = 16MHz

=2
8MHz / SPI1
SCLK
So, if we use the internal RC oscillator of 16Mhz as our
system clock then SPI1/SPI2/SPI3 peripherals can able
to produce the serial clock of maximum 8MHz.
Remember that in SPI communication ,slave will not
initiate data transfer unless master produces the
clock.
SPI Driver Development
Driver API requirements and
user configurable items
 Sample Applications

Driver Layer
(Device header)
gpio_driver.c , .h i2c_driver.c , .h Stm3f407xx.h

spi_driver.c , .h uart_driver.c , .h

GPIO SPI I2C UART

STM3F407x MCU
 SPI Initialization / peripheral clock
control

SPI TX

SPI RX
APIs
SPI Driver
SPI Interrupt config. &
handling

Other SPI management APIs

 SPI_DeviceMode

SPI_BusConfig

SPI_DFF
SPIx Peripheral Configurable items
For user application
SPI_CPHA

SPI_CPOL

SPI_SSM

SPI_Speed
SPI handle structure and
configuration structure
SPI Configuration Structure

SPI Handle Structure

Exercise :

1. Complete SPI register definition structure and other

macros ( peripheral base addresses, Device definition ,
clock en , clock di , etc) in MCU specific header file
2. Complete SPI Configuration structure and SPI handle
structure in SPI header file
Writing API prototypes
Send data Start

Yes
Len=0 ? Exit from the function

No
Wait until the Tx buffer is empty End

16 bit
DFF ? 1
0
8Bit
Load DR with 1 byte of data Load DR with 1 byte of data
And increment the buffer address And increment the buffer adress

Len-- Len--
Receive data Start

Yes
Len=0 ? Exit from the function

No
Wait until the Rx Buffer is non
empty End

16 bit
DFF ? 1
0
8Bit
Read DR for 1 byte of data Read DR for 2 bytes of data
And increment the rx buffer address And increment the rx buffer address

Len-- Len--
Exercise :

1. Test the SPI_SendData API to send the string “Hello

world” and use the below configurations
1. SPI-2 Master mode
2. SCLK = max possible
3. DFF = 0 and DFF = 1
 Exercise :
SPI Master(STM) and SPI Slave(Arduino) communication .
When the button on the master is pressed , master should send string of data to the Arduino slave
connected. The data received by the Arduino will be displayed on the Arduino serial port.

1 .Use SPI Full duplex mode

2. ST board will be in SPI master mode and Arduino will be configured for SPI slave mode
3. Use DFF = 0
4. Use Hardware slave management (SSM = 0)
5. SCLK speed = 2MHz , fclk = 16MHz

In this exercise master is not going to receive anything for the slave. So you may not configure the
MISO pin

Note.
Slave does not know how many bytes of data master is going to send. So master first sends the
number bytes info which slave is going to receive next.
Things you need
1 .Arduino board
2. ST board
3. Some jumper wires
4. Bread board

ST board Arduino board PC ( Arduino

SPI USB
Serial Monitor )
STEP-1
Connect Arduino and ST board SPI pins as shown
STEP-2
Power your Arduino board and download SPI
Slave sketch to Arduino
Sketch name : 001SPISlaveRxString.ino
Find out the GPIO pins over which SPI2 can
communicate
 Exercise :
SPI Master(STM) and SPI Slave(Arduino) command & response based communication .

When the button on the master is pressed, master sends a command to the slave and
slave responds as per the command implementation .

1 .Use SPI Full duplex mode

2. ST board will be in SPI master mode and Arduino will be configured for SPI slave
mode
3. Use DFF = 0
4. Use Hardware slave management (SSM = 0)
5. SCLK speed = 2MHz , fclk = 16MHz
STEP-1
Connect Arduino and ST board SPI pins as shown
STEP-2
Power your Arduino board and download SPI
Slave sketch to Arduino
Sketch name : 002SPISlaveCmdHandling.ino
Master & Slave communication

Master Slave
Master sends a command
NACK 0xA5
Slave response ACK or NACK BYTE
ACK 0xF5
IF ACK 1 or more Command Arguments

Take action
IF NACK
according to
command
Display error
message

Slave response for data read command

Command formats

< command_code(1) > <arg1 > <arg2>

This command is used to turn on/off led connected to specified arduino pin
number
ON/OFF
1)CMD_LED_CTRL <pin no(1)> <value(1)>
2)CMD_SENOSR_READ <analog pin number(1) >
3) CMD_LED_READ <pin no(1) >
4) CMD_PRINT <len(2)> <message(len) >
5) CMD_ID_READ
CMD_LED_CTRL <pin no> <value>

<pin no > digital pin number of the arduino board ( 0 to 9) ( 1 byte)

<value> 1 = ON , 0 = OFF (1 byte)

Slave Action : control the digital pin ON or OFF

Slave returns : Nothing

Remove the
connection made
here

Download the code

Then, connect it
back
CMD_SENOSR_READ <analog pin number >

<analog pin number > Analog pin number of the Arduino board ( A0 to A5)
(1 byte)

Slave Action : Slave should read the analog value of the supplied pin

Slave returns : 1 byte of analog read value

CMD_LED_READ <pin no >

<pin no > digital pin number of the arduino board ( 0 to 9)

Slave Action : Read the status of the supplied pin number

Slave returns : 1 byte of led status . 1 = ON , 0 = OFF

CMD_PRINT <len> <message >

<len> 1 byte of length information of the message to follow

<message> message of „len‟ bytes

Slave Action : Receive the message and display via serial port

Slave returns : Nothing

CMD_ID_READ

No arguments for this command

Slave returns : 10 bytes of board id string

Application flow chart
START

Enter main()

All inits

Wait till button is pressed

Execute CMD_LED_CTRL

Wait till button is pressed

Execute CMD_SENSOR_READ

Wait till button is pressed

Execute CMD_LED_READ
Firmware Write 0xAB Data Register

APB1/APB2

Read

Rx buffer

Shift Register

TX buffer

Write
Firmware Write 0xAB Data Register

APB1/APB2

Read

Rx buffer

Shift Register

TX buffer

Write
Firmware Read Data Register

APB1/APB2

Read

Rx buffer
0xAB

Shift Register

TX buffer

Write
SPI interrupts
During SPI communication , interrupts can be generated by the following
events:
• Transmit Tx buffer ready to be loaded
• Data received in Rx buffer
• Master mode fault ( in single master case you must avoid this error
happening )
• Overrun error

Interrupts can be enabled and disabled separately.

SPI interrupts
SPI Interrupting the Processor

SPI_1

NVIC Processor
SPI_2 Core

ARM Cortex M4
SPI_3

MCU
Exercise-1

 Complete SPI IRQ number definition macros in MCU

specific header file
Exercise-2

 Complete the SPI IRQ Configuration APIs

Implementation (reuse code from GPIO driver)
SPI send data API (Interrupt mode)
API to send data with interrupt mode
API to send data with interrupt mode

So first we have to create some place holder

variables to save application‟s Tx address, len
and SPI state.
Handle Structure modification
Possible SPI Application States

#define SPI_READY 0
#define SPI_BUSY_IN_RX 1
#define SPI_BUSY_IN_TX 2
SPI receive data API (Interrupt mode)
SPI receive data with interrupt
SPI ISR Handling Implementation
Handling SPI interrupt in the Code

Enter ISR

Understand which event

caused interrupt to
trigger(check SR)

Interrupt is due to Interrupt is due to Interrupt is due Setting

setting of RXNE flag setting of TXE flag of ERROR flag

Handle RXNE event Handle TXE flag Handle Error

Handling TXE interrupt
Handle TXE interrupt

8 bit or 16 bit mode?

8bit 16bit

Write one byte to SPI Write 2 byte to SPI Data

Data register(DR) register(DR)

Len-- Len -= 2

No Transmission Not over

Len = 0 ?
Transmission over Yes
Close the SPI TX Wait till another TXE
interrupt
Configuring NSS
 SCLK SCLK
MOSI MOSI

MISO MISO

Master
Slave
gpio1 Nss
In STM32F4xx based microcontroller, the NSS pin can be
handled by 2 ways

 Software Slave Management

 Hardware Slave Management
Software Slave Management

NSS Pin state is handled by „SSI‟ bit in the CR1 register SCLK

MOSI
If SSI bit = 1 , then NSS goes HIGH

+VCC MISO
SSI=1
Slave
Nss
Software Slave Management

NSS state is handled by „SSI‟ bit in the CR1 register SCLK

MOSI
If SSI bit = 1 , then NSS goes HIGH
If SSI bit = 0, then NSS goes LOW
MISO
SSI=0
Slave
Nss
Software Slave Management

NSS state is handled by „SSI‟ bit in the CR1 register SCLK

MOSI
If SSI bit = 1 , then NSS goes HIGH
If SSI bit = 0, then NSS goes LOW
MISO

SSI bit is the handle for the software to Slave

control the NSS pin ! Nss
So, What is the advantage of using
Software Slave Management(SSM) ?
 Saves PIN
SCLK SCLK
MOSI MOSI

MISO MISO
Master
Sla
gpio1 Nss
ve

Master need not use its NSS pin is handled by SSI bit
another pin to drive the NSS of Control register by software
pin low, that saves one pin for
master.
What is Hardware slave Management?
 SCLK SCLK
MOSI MOSI Slave1
Master MISO MISO
gpio1 Nss
gpio2
gpio3 SCLK
MOSI Slave2
MISO
Nss

SCLK
MOSI Slave3
MISO
Nss
Implementing Master rx API

If master wants read something form the slave, it has to

produce clock , and to produce clock Master has to place
some data in to the tx buffer by writing some dummy bytes.
Implementing slave tx api

Slave can not do Tx, until master produces clock

Whenever you are in SPI slave mode and want

to send some data, then slave must be ready
with the data before master produces the clock.
Master Sending Write CMD and Data
Stream to Slave
Master Slave
Master Send Write CMD

Master gets ACK bytes

Verify ACK
Master Sends Data Stream
Pass

Fail Blink RED LED

Verify Data
Stream

Blink BlueLED Pass

Fail
Blink RED LED
Master Sending Read CMD and
Receiving Data Stream From Slave
Master Slave
Send Read CMD

Master gets ACK bytes from slave

Verify ACK
Master gets data stream from slave
Pass

Fail Blink RED LED

Verify Data
Stream
Pass Blink BlueLED

Fail Blink RED LED

Master Write CMD Execution
 Master sends out the Write CMD
 Slave ACK back for the command
 If ACK is valid, then Master sends out the Data stream of known
length

Master Read CMD Execution

 Master sends out the Read CMD
 Slave ACK back for the command
 If ACK is valid , then Master gets the data stream from the slave of
known length.
We selected spi2 device,
The clock will run at 500KHz
Data format is 8bit MSbfirst
Spi mode is 0, because CPOL and CPHASE are 0
The peripheral acts as master device.
SPI Master Initialization
 We selected SPI2 device.
 SPI serial line clock will run at 500KHz
 Data format is 8bit msb first
 SPI mode is 1, because CPO=0 and CPHASE=1
 The peripheral acts as master device

SPI peripheral clock is 16Mhz, because we are running MCU at

16Mhz Internal RC Oscillator
Common Debugging Steps

 Master mode bit must be enabled in the configuration

register if you are making peripheral to work in MASTER
mode.

 SPI peripheral enable bit must be enabled

 SPI peripheral clock must be enabled

Common Problems in SPI and
Debugging Tips
Case 1

Master Can not able to produce clock and data

Case 1: Master cannot able to produce
clock and data

Reason-1:
Non-Proper Configuration of I/O lines for Alternate
functionality

Debug Tip:
Recheck the GPIO Configuration registers to see what values
they have
Case 1: Master cannot able to produce
clock and data

Reason-2:
Configuration Overriding

Debug Tip:
Dump out all the required register contents just before you begin
the transmission
Case 2

Master is sending data, but slave is not receiving data !

Case 2: Master is sending data but
slave is not receiving data !

Reason-1:
Not pulling down the slave select pin to ground before sending data to
the slave

Debug Tip:
Probe through the logic analyzer to confirm slave select line is
really low during data communication
Case 2: Master is sending data but
slave is not receiving data !

Reason-2 :
Non-Proper Configuration of I/O lines for Alternate functionality

Debug Tip:
Probe the alternate function register
Case 2: Master is sending data but
slave is not receiving data !

Reason-3 :
Non enabling the peripheral IRQ number in the NVIC

Debug Tip:
Probe the NVIC Interrupt Mask register to see whether the bit
position corresponding to the IRQ number is set or not
Case 3

SPI interrupts are not getting triggered

Case 3: SPI interrupts are not getting triggered

Reason-1 :
Not enabling the TXE or RXNE interrupt in the SPI configuration register

Debug Tip:
Check the SPI configuration register to see TXEIE and RXNEIE bits
are really set to enable the interrupt !
Case 3: SPI interrupts are not getting triggered

Reason-2:
Non enabling the peripheral IRQ number in the NVIC

Debug Tip:
Probe the NVIC Interrupt Mask Register to see whether the bit
position corresponding to the IRQ number is set or not
Case 4

Master is producing right data but slave is

receiving the different data
Case 4: Master is producing right data
but slave is receiving the different data

Reason-1 :
Using Long Wires in high frequency communication

Debug Tip:
use shorter wires or reduce the SPI serial frequency to 500KHz to
check things work well
 SCLK SCLK
MOSI MOSI Slave1
MISO MISO
Master gpio1 Nss
gpio2
gpio3 SCLK
MOSI Slave2
MISO
Nss

SCLK
MOSI Slave3
MISO
Nss
Cross Check These Settings

 Master mode bit must be enabled in the configuration register if you

are configuring the peripheral as master
 SPI peripheral enable bit must be enabled .
 SPI peripheral clock must be enabled. By default clocks to almost all
peripheral in the microcontroller will be disabled to save power.
Clock Sources in the MCU

• High Speed Internal (HSI) oscillator

• High Speed External (HSE) oscillator
• Phase Locked Loop (PLL)
• Low Speed Internal (LSI) clock
• Low Speed External (LSE) clock
Clock Sources in the MCU

PLLN
HSI
X SysClk AHB
16MHz PLLM PLLP AHB
/
HSE / VCO / APB1
8 – 26 MHz /
PLLQ

/
APB2
PLL /

USB OTG,SDIO,etc
The HSI RC oscillator which is inside the MCU has the advantage of
providing a clock source at low cost . Because there is no external
components required to use this clock. It also has a faster start-up
time than the external crystal oscillator however, the frequency is
less accurate than an external crystal oscillator.
STM32F4xx Discovery board
STM32F411RE Nucleo-64
Connection Diagram
SPI2 SPI2
SCLK(PB13) SCLK(PB13)

MISO(PB14) MISO(PB14)

MOSI(PB15) MOSI(PB15)
NSS
USER button

GND GND
STM32F4 discovery STM32F4 discovery
Master Slave
 How to enable the High Speed
External Crystal Oscillator and use it
as System Clock ?
Let‟s measure the frequency of
different clock sources like
HSI,HSE,PLL by using USB logic
Analyzer !
Connection between USB Logic
Analyzer and Discovery board
Understanding Connection
Diagram
 To PC
USB Logic analyzer
GND CH2 CH1 CH0

SPI2 SPI2
SCLK(PB13) SCLK(PB13)

MISO(PB14) MISO(PB14)

MOSI(PB15) MOSI(PB15)

USER button

GND GND
STM32F4 discovery STM32F4 discovery
Master Slave
PART-2

Mastering Microcontroller with

Embedded Driver Development
FastBit Embedded Brain Academy
Check all online courses at
www.fastbitlab.com
 About FastBit EBA
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We leverage the power of internet to bring online courses at your fingertip in the domain of
embedded systems and programming, microcontrollers, real-time operating systems, firmware
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​
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Introduction to I2C
Inter–Integrated Circuit(I2C) Protocol

Pronounced as
“I squared C “ or “ I two C “
What is I2C ?
It is just a protocol to achieve serial data communication between
integrated circuits(ICs) which are very close to each other. (but more
serious protocol than SPI because companies have come forward to
design a specification ) ​

I2C protocol details ( how data should sent, how data

should received, how hand shaking should happen between sender
and receiver, error handling, ) are complex than SPI. ( In other words SPI
is simple protocol compared to I2C)​
Difference between SPI and I2C ​
How different than SPI ?
Specification

I2c is based on dedicated specification. The spec you

can download from here
https://www.nxp.com/docs/en/user-guide/UM10204.pdf
For SPI there is no dedicated spec but TI and Motorola have their
own spec
How different than SPI ?
Multi-Master Capability

I2C protocol is multi-master capable ,

whereas SPI has no guidelines to achieve this, but depends
on MCU designers . STM SPI peripherals can be used in
multi master configurations but arbitration should be
handled by software code.
How different than SPI ?

ACK

I2C hardware automatically ACKs every byte received.

SPI does not support any automatic ACKing.
How different than SPI ?

Pins

I2C needs just 2 pins for the communication

whereas SPI may need 4 pins and even more than that
if multiple slaves are involved
SPI Consumes more
pins when more slaves
are involved
In I2C, you just need 2 pins to connect all the slaves and masters

+vcc

R1 R2

SCL

SDA

Master-1 Slave Slave Slave Master-2

STM32 Accelerometer ADC EEPROM Rasp PI
How different than SPI ?

Addressing

I 2C master talks to slaves based on slave addresses,

whereas in SPI dedicated pin is used to select the slave.
How different than SPI ?
Communication

I2C is half duplex, where is SPI is full duplex

How different than SPI ?
Speed

For I2C the max speed is 4MHz in ultra speed plus .

For some STM microcontrollers the max speed is just 400KHz​.
For SPI max speed is its Fpclk/2 . That means if
the peripheral clock is 20MHz, then speed can be 10MHz ​
How different than SPI ?
Slave‟s control over serial clock

In I2C slave can make master wait by holding the clock

down if it's busy , thanks to clock stretching feature of I2C.
But in SPI, slave has no control over clock, programmers
may use their own tricks to overcome this situation .
Data rate
Data rate ( number of bits transferred from sender to receiver in 1
sec ) is very much lesser in I2C compared to SPI. ​

For example in STM32F4X if you have peripheral clock of 40MHz,

then in I2C you can achieve data rate of 400Kbps but in SPI it is
20Mbps. ​

So in the above scenario SPI is 50 times faster than I2C. ​

In I2C, you just need 2 pins to connect all the slaves and masters

+vcc

R1 R2 Pull up resistors

SCL

SDA

Master-1 Slave Slave Slave Master-2

STM32 Accelerometer ADC EEPROM Rasp PI
SDA and SCL signals
Both SDA and SCL are bidirectional lines connected to a positive
supply voltage via pull-up resistors. When the bus is free, both lines are
held at HIGH.

The output stages of devices connected to the bus must have an

open-drain or open-collector configuration

The bus capacitance limits the number of interfaces connected to the

bus.
I2C: Pin Configuration
 For proper functioning
of the I2C bus , pull up
Enable Pull up Resistor resistor value has to be
calculated according
to the I2C formula ( will
discuss later)
OD

SCL
 For proper functioning
Enable Pull up Resistor of the I2C bus , pull up
resistor value has to be
calculated according
to the I2C formula ( will
discuss later)
OD

SDA

Trouble shooting tip : When the bus is idle, both SDA and SCL are pulled to +Vdd
GND SDA & SCL Tip
Whenever you face
3.3V
problems in I2C , probe
the SDA and SCL line
after I2C initialization.
It must be held at HIGH
(3.3 V or 1.8V
depending up on IO
voltage levels of your
board)
I2C Modes

Mode Data rate Notes

Standard Mode Up to100 Kbits/sec Supported by STMf2F4x

Fast Mode Up to 400Kbits/sec Supported by STMf2F4x

Fast Mode + Up to 1Mbits/sec Supported by some

STMf2F4x MCUs (refer RM)

High Speed mode Up to 3.4 Mbits/sec Not supported by F4x

Fast Mode/Standard Mode
Standard Mode
 In standard mode communication data transfer rate can reach up
to maximum of 100kbits/sec.
 Standard mode was the very first mode introduced when first i2c
spec was released.
 Standard-mode devices, however, are not upward compatible;
They cant communicate with devices of Fast mode or above.
Fast Mode
 Fast mode is a mode in i2c protocol, where devices can receive and
transmit data up to 400 kbits/s.
 Fast-mode devices are downward-compatible and can
communicate with Standard-mode devices in a 0 to 100 kbit/s I2C-
bus system
 Standard-mode devices, however, are not upward compatible; they
should not be incorporated in a Fast-mode I2C-bus system as they
cannot follow the higher transfer rate and unpredictable states
would occur.
 To achieve data transfer rate up to 400kbits/sec, you must put the
i2c device in to fast mode
Basics of I2C Protocol
 R/nW = „1‟ indicates R/nW = „0‟ indicates a
request for data (READ) transmission (WRITE),

S A7 A6 A5 A4 A3 A2 A1 R/𝑊 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK P

Every byte put on the SDA line must be eight bits long.
Each byte must be followed by an Acknowledge Bit
Data is transferred with the Most Significant Bit (MSB) first
START and STOP conditions
All transactions begin with a START (S) and are terminated by a STOP (P)

A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
I2C Protocol: Start condition timings
Min. Setup Time For a Start Condition (tSU;STA)

Min. Hold Time For Start Condition (tHD;STA)

I2C Protocol: stop condition timings
Min.Setup Time for Stop Condition (tSU;STO)

Setup Time for Stop Condition (tSU;STO) is measured as the time between 70%
amplitude of the rising edge of SCL and 30% amplitude of a rising SDA signal
during a stop condition.
Points to Remember
 START and STOP conditions are always generated by the master. The bus
is considered to be busy after the START condition.
 The bus is considered to be free again a certain time after the STOP
condition.
 When the bus is free another master(if present) can get the chance to
claim the bus.
 The bus stays busy if a repeated START (Sr) is generated instead of a STOP
condition.
 Most of the MCU‟s I2C peripherals support both master and slave mode.
You need not to configure the mode because when the peripheral
generates the start condition it automatically becomes the master and
when it generates the stop condition it goes back to slave mode.
I2C Protocol: Address Phase
I2C Protocol: Address Phase
I2C Protocol: ACK/NACK
I2C Protocol: ACK
The Acknowledge signal is defined
as follows:
The transmitter releases the SDA line
during the acknowledge clock pulse
so the receiver can pull the SDA line
LOW and it remains stable LOW
during the HIGH period of this clock
pulse

The acknowledge takes place after every byte.

The acknowledge bit allows the receiver to signal the transmitter that the byte was
successfully received and another byte may be sent.
The master generates all clock pulses, including the acknowledge ninth clock pulse
I2C Protocol: NACK

When SDA remains HIGH during this ninth clock pulse, this is defined as the Not
Acknowledge signal.

The master can then generate either a STOP condition to abort the transfer, or a
repeated START condition to start a new transfer.
Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The
HIGH Or LOW state of the data line can only change when the clock signal on the
SCL line is LOW . One clock pulse is generated for each data bit transferred.
Master Writing data to slave
SCL

SDA
SCL
1 2 3 4 5 6 7 8

SDA

A7 A6 A5 A4 A3 A2 A1
SCL
1 2 3 4 5 6 7 8 9

SDA

A7 A6 A5 A4 A3 A2 A1
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8

SDA

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Master Reading
data from slave
SCL

SDA
SCL 7
1 2 3 4 5 6

SDA

A7 A6 A5 A4 A3 A2 A1
SCL 7 8
1 2 3 4 5 6

SDA

A7 A6 A5 A4 A3 A2 A1
SCL 7 8 9
1 2 3 4 5 6

SDA

A7 A6 A5 A4 A3 A2 A1
SCL 7 8 9 2 7 8
1 2 3 4 5 6 1 3 4 5 6

SDA

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0
SCL 7 8 9 2 7 8 9
1 2 3 4 5 6 1 3 4 5 6

SDA

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0
SCL 7 8 9 2 7 8 9
1 2 3 4 5 6 1 3 4 5 6

SDA

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 7 8 9 2 7 8 9
1 2 3 4 5 6 1 3 4 5 6

SDA

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Repeated Start(Sr)
(Start again without Stop)
 I2C
0x45
MCU EEPROM
(Master) (Slave)

Master reading the contents of EEPROM at address 0x45

Without repeated start
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0
With repeated start
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0
I2C peripherals of your MCU

AHB1

GPIOA GPIOB GPIOC GPIOD GPIOE …. GPIOI

APB1

I2C1 I2C2 I2C3 SPI2 SPI3 USART2 USART3 UART4 UART5

APB2

SPI1 USART1 USART6 EXTI SYSCFG

I2C Driver Development
 Sample Applications

Driver Layer
(Device header)
gpio_driver.c , .h i2c_driver.c , .h Stm3f407xx.h

spi_driver.c , .h uart_driver.c , .h

GPIO SPI I2C UART

STM3F407x MCU
Driver API requirements and
user configurable items
 I2C Initialization

I2C Master TX

I2C Driver
I2C Master RX

APIs I2C Slave TX

I2C Slave RX

I2C Error Interrupt handling

I2C Event Interrupt handling

 I2C_SCLSpeed

I2C_DeviceAddress
I2Cx
Peripheral Configurable items
I2C_ACKControl For user application

I2C_FMDutyCycle
Exercise:

1. Create stm32f407xx_i2c_driver.c and

stm32f407xx_i2c_driver.h
2. Add I2Cx related details to MCU specific header file
I. I2C peripheral register definition structure
II. I2Cx base address macros
III. I2Cx peripheral definition macros
IV. Macros to enable and disable I2Cx peripheral clock
V. Bit position definitions of I2C peripheral
I2C handle structure and
configuration structure
Create Configuration and Handle structure
 check comments
Implementation
I2C_Init() API
Steps for I2C init (Generic)
1. Configure the Mode (standard or fast )
2. Configure the speed of the serial clock (SCL)
3. Configure the device address (Applicable when device is slave)
4. Enable the Acking
5. Configure the rise time for I2C pins (will discuss later )

All the above configuration must be done when the peripheral is

disabled in the control register
I2C Serial clock (SCL) control settings
In STM32F4x I2C peripheral, CR2 and CCR registers are used to control the I2C
serial clock settings and other I2C timings like setup time and hold time
HSI
16Mhz
HSE

PLL

/ APB1 prescaler

16Mhz

APB 1 bus ( 42 Mhz Max)

16Mhz
CR2_FREQ I2C1
CCR Settings

Up to 100KHz in SM SCL
Up to 400Khz in FM
Example :
In SM Mode , generate a 100 kHz SCL frequency
APB1 Clock (PCLK1) = 16MHz

1) Configure the mode in CCR register (15th bit )

2) Program FREQ field of CR2 with the value of PCLK1
3) Calculate and Program CCR value in CCR field of CCR register

Thigh(scl) = CCR * TPCLK1

Tlow(scl) = CCR * TPCLK1
Example :
In FM Mode , generate a 200 kHz SCL frequency
APB1 Clock (PCLK1) = 16MHz

1) Configure the mode in CCR register (15th bit )

2) Select the duty cycle of Fast mode SCL in CCR register (14th bit)
3) Program FREQ field of CR2 with the value of PCLK1
4) Calculate and Program CCR value in CCR field of CCR register

If DUTY = 0:
Thigh = CCR * TPCLK1
Tlow = 2 * CCR * TPCLK1
If DUTY = 1: (to reach 400 kHz)
Thigh = 9 * CCR * TPCLK1
Tlow = 16 * CCR * TPCLK1
 I2C Duty Cycle
SM
In STM32f4x I2C
thigh tlow
For SM
(Tlow may be equal to Thigh )
For FM
Tlow = 2Thigh
2thigh Or
FM thigh tlow Tlow = 1.8 Thigh

1.7thigh
thigh tlow
 I2C Duty Cycle
Thigh(scl) = CCR * TPCLK1
Tlow(scl) = CCR * TPCLK1

SM

thigh tlow
 If DUTY = 0:
I2C Duty Cycle Thigh = CCR * TPCLK1
Tlow = 2 * CCR * TPCLK1
If DUTY = 1: (to reach 400 kHz)
Thigh = 9 * CCR * TPCLK1
Tlow = 16 * CCR * TPCLK1
2thigh
FM thigh tlow

1.7thigh
thigh tlow
Implementation
I2C_MasterSendData API
Master sending data to slave
 Exercise :
I2C Master(STM) and I2C Slave(Arduino) communication .
When button on the master is pressed , master should send data to the Arduino slave
connected. The data received by the Arduino will be displayed on the Arduino serial
port.

1 . Use I2C SCL = 100KHz(Standard mode )

2. Use internal pull resistors for SDA and SCL lines
Things you need
1 .Arduino board
2. ST board
3. Some jumper wires
4. Bread board
5. 2 Pull up resistors of value 4.4K Ω( only if your pin doesn't
support internal pull up resistors )

ST board Arduino board PC ( Arduino

I2C USB
Serial Monitor )
STEP-1 Connect Arduino and ST board SPI pins as shown

To PC USB Logic analyzer

GND CH1 CH0

SCL(PB6) A5

I2C1 I2C

SDA(PB9) A4

USER button

GND GND
STM32F4 discovery Arduino
Master Slave
STEP-2
Power your Arduino board and download I2C
Slave sketch to Arduino
Sketch name : 001I2CSlaveRxString.ino
Find out the GPIO pins over which I2C1 can
communicate
I2C pull up resistance , Rise time and
Bus capacitance discussion
Pull-up Resistor(Rp ) Calculation
VOL = LOW-level output voltage
Rp (min) is a function of VCC, VOL (max), and IOL:
IOL = LOW-level output current
tr = rise time of both SDA and SCL
signals

Cb = capacitive load for each bus

line

The maximum pullup resistance is a function of the maximum rise time (tr ):
Image taken from :
http://www.ti.com/lit/an/slva704/slva704.pdf
Rise (tr) and Fall (tf) Times
tr is defined as the amount of
time taken by the rising edge to
SDA or SCL reach 70% amplitude from 30%
amplitude for either SDA and
SCL

I2C spec cares about tr value and you have to respect it while calculating the pull up resistor
value.

Higher value of pull up resistors(weak pull-ups) increases tr value. ( not acceptable if tr crosses
max. limit mentioned in the spec )

Lower value of pull up resistors ( strong pull-ups) decreases tr value ( good) but they also lead
higher current consumption (bad)
 Using very high value of pull up resistors may
cause issues like this where the pin may not
able to cross the VIH limit (Input Level High
Voltage)

VDD

VIH

VIL
I2C Bus Capacitance(Cb )

capacitance means that the voltage level on the signal line

(data or clock) can‟t change instantaneously

accidental capacitors
I2C Bus Capacitance(Cb )

Bus capacitance is a collection of individual pin capacitance wrt gnd ,

capacitance between the sda and scl , parasitic capacitance,
capacitance added by the devices hanging on the bus , bus length (wire) ,
dielectric material etc.

Bus capacitance limits how long your i2c wiring can be and how many
devices you can connect on the bus.

For maximum allowed bus capacitance check the spec.

Exercise
For Fast-mode I2C communication with the following parameters,
calculate the pullup resistor value. Cb = 150 pF, VCC = 3.3 V
TRISE calculation
Clock Stretching
Clock Stretching
 Clock stretching pauses a transaction by holding the SCL line LOW.
 The transaction cannot continue until the line is released HIGH again. Clock
stretching is optional and in fact, most slave devices do not include an SCL
driver so they are unable to stretch the clock.
 Slaves can hold the SCL line LOW after reception and acknowledgment of a
byte to force the master into a wait state until the slave is ready for the next byte
transfer in a type of handshake procedure
 If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, for example servicing an internal interrupt, it
can hold the clock line SCL LOW to force the master into a wait state. Data
transfer then continues when the slave is ready for another byte of data and
releases clock line SCL.
 1 2 3 4 5 6 7 8 9 1
SCL

SDA

1 2 3 4 5 6 7 8 9 1
SCL

SDA
The slave is not ready for more data, so it buys
time by holding the clock low.
The master will wait for the clock line to be
released before proceeding to the next frame
Implementation
I2C_MasterReceiveData API
Master Receiving data from slave
Master Receiving 1 byte from slave
Master Receiving more than 1 byte
 Exercise :
I2C Master(STM) and I2C Slave(Arduino) communication .

When button on the master is pressed , master should read and display data from
Arduino Slave connected. First master has to get the length of the data from the
slave to read subsequent data from the slave.
1 . Use I2C SCL = 100KHz(Standard mode )
2. Use internal pull resistors for SDA and SCL lines
Things you need
1 .Arduino board
2. ST board
3. Some jumper wires
4. Bread board
5. 2 Pull up resistors of value 4.7K Ω( only if your pin doesn't
support internal pull up resistors )

ST board I2C Arduino board

Print received data using semihosting

STEP-1 Connect Arduino and ST board SPI pins as shown

To PC USB Logic analyzer

GND CH1 CH0

SCL(PB6) A5

I2C1 I2C

SDA(PB9) A4

USER button

GND GND
STM32F4 discovery Arduino
Master Slave
STEP-2
Power your Arduino board and download I2C
Slave sketch to Arduino
Sketch name : 002I2CSlaveTxString.ino
Procedure to read the data from Arduino Slave

1 2

Master sends command Master sends command

code 0x51 to read the code 0x52 to read the
length(1 byte) of the complete data from the
data from the slave slave
I2C transactions to read the 1 byte
length information from slave
I2C transactions to read “length”
bytes of data from the slave
 START

Reset both the boards

Wait for button press on the master

Master first sends command code 0x51

to slave (to read length)
Master reads “length” from slave
( 1 byte)

Master reads “length” number of bytes

from the slave

Master display the data received using

printf (semihosting)

END
I2C Functional
block and
Peripheral Clock
fpclk (Peripheral Clock Frequency ) must be at least 2MHz
to achieve standard mode I2c frequencies that are up to
100khz
fpclk must be at least 4Mhz to achieve FM mode i2c
frequencies. that is above 100khz but below 400Khz

fpclk must be a multiple of 10Mhz to reach the 400khz

max i2c fm mode clock frequency
I2C Interrupts
I2C IRQs and Interrupt mapping
I2C1 interrupts

Peripheral Processor

I2C1_EV_IRQ_LINE IRQn
31

Processor
NVIC Core

I2C1_ER_IRQ_LINE
32

ARM Cortex M4
I2C Interrupting the Processor

31
32

33

34

79
80

IRQ numbers are specific to MCUs. Please check the vector table of your RM
Bus Error
This error happens when the interface detects an SDA rising or falling
edge while SCL is high, occurring in a non-valid position during a byte
transfer

Arbitration Loss Error

This error can happen when the interface loses the arbitration of the
bus to another master
ACK Failure Error
This error happens when no ACK is returned for the byte sent

Overrun Error
Happens during reception, when a new byte is received and the data
register has not been read yet and the New received byte is lost.
Under-run Error
Happens when In transmission when a new byte should be sent and
the data register has not been written yet and the same byte is sent
twice

PEC Error
Happens when there is CRC mismatch, if you have enabled the CRC
feature
Time-Out Error
Happens when master or slave stretches the clock , by holding it
low more than recommended amount of time.
BTF flag in TX and preventing underrun

During Txing of a data byte, if TXE=1, then that means

data register is empty.

And if the firmware has not written any byte to data

register before shift register becomes empty(previous
byte transmission), then BTF flag will be set and clock
will be stretched to prevent the under run.
BTF flag in RX and preventing overrun

If RXNE =1, Then it means new data is waiting in

the data register, and if the firmware has not read
the data byte yet before Shit register is filled with
another new data, then also the BTF flag will be set
and clock will be stretched to prevent the overrun.
I2C sending and receiving
data in interrupt mode
I2C_MasterSendDataIT API

I2C_MasterReceiveDataIT API
Modifying handle structure to store
place holder variables
Implementing
I2C_MasterSendDataIT API
Implementing
I2C_MasterReceiveDataIT API
Adding I2C IRQ number macros
Implementing
I2C_IRQInterruptConfig();
I2C_IRQPriorityConfig();
I2C ISR handling

ISR1 ISR2

Interrupt handling for Interrupt handling for

interrupts generated by I2C interrupts generated by I2C
events errors

I2C_EV_IRQHandling I2C_ER_IRQHandling
When BTF flag is set

TXE=1 RXNE=1

SR DR SR DR
EMPTY EMPTY FULL FULL

During Transmission During Reception

I2C Slave Programming
 STM32 Arduino
I2C
(Master) (Slave)
Arduino
STM32
(Master) I2C
(Slave)
I2C Master I2C I2C Slave

START Request for data

STOP
Receive data
Read
Write
 Callback events
I2C Driver Slave
ACK Failure
(Slave mode) Application

STOP generation

Request for data

Receive data
 Exercise :
I2C Master(Arduino) and I2C Slave(STM32) communication .

Master should read and display data from

STM32 Slave connected. First master has to get the length of the data from the
slave to read subsequent data from the slave.
1 . Use I2C SCL = 100KHz(Standard mode )
2. Use internal pull resistors for SDA and SCL lines
Things you need
1 .Arduino board
2. ST board
3. Some jumper wires
4. Bread board
5. 2 Pull up resistors of value 4.7K Ω( only if your pin doesn't
support internal pull up resistors )

Arduino(M) I2C STM32(Slave)

Print received data on to Arduino serial port

STEP-1 Connect Arduino and ST board SPI pins as shown

To PC USB Logic analyzer

GND CH1 CH0

SCL(PB6) A5

I2C1 I2C

SDA(PB9) A4

USER button

GND GND
STM32F4 discovery Arduino
Master Slave
STEP-2
Power your Arduino board and download I2C
Slave sketch to Arduino
Sketch name: 003I2CMasterRxString.ino
Procedure to read the data from STM32 Slave

1 2

Master sends command Master sends command

code 0x51 to read the code 0x52 to read the
length(1 byte) of the complete data from the
data from the slave slave
I2C transactions to read the 1 byte
length information from slave
Master : Arduino
Master : Arduino
I2C transactions to read “length”
bytes of data from the slave
Master : Arduino
Master : Arduino
I2C transactions to read the 4
bytes of length information from
the slave
Master : Arduino
I2C transactions to read “length”
bytes of data from the slave
If length is <= 32 then only one “READ” Transaction
READ Transaction -1

READ Transaction -2

READ Transaction -3
Common Problems in I2C and
Debugging Tips
GND SDA & SCL

Tip
3.3V
Whenever you face
problem in I2C , probe
the SDA and SCL line
after I2C initialization.
It must be held at HIGH
level.
Problem-1: SDA and SCL line not held HIGH
Voltage after I2C pin initialization

Reason-1:
Not activating the pullup resistors if you are using the internal
pull up resistor of an I/O line

Debug Tip:
worth checking the configuration register of an I/O line to see
whether the pullups are really activated or not, best way is to
dump the register contents.
Problem-2: ACK failure

Reason-1:
Generating the address phase with wrong slave address

Debug Tip:
verify the slave address appearing on the SDA line by using
logic analyser.
Problem-2: ACK failure

Reason-2:
Not enabling the ACKing feature in the I2C control register

Debug Tip:
Cross check the I2C Control register ACK enable field
Problem-3: Master is not producing the clock

Debug Tip 1 :
First Check whether I2C peripheral clock is enabled and set to
at least 2MHz to produce standard mode i2c serial clock
frequency

Debug Tip 2 :
Check whether GPIOs which you used for SCL and SDA
functionality are configured properly for the alternate
functionality
 To PC
USB Logic analyzer
GND CH1 CH0

SCL(PB6) SCL(PB6)

I2C1 I2C1

SDA(PB9) SDA(PB9)

USER button

GND GND
STM32F4 discovery STM32F4 discovery
Master Slave
 To PC
USB Logic analyzer
GND CH1 CH0

SCL(PB6)

I2C1

SDA(PB9)

USER button

GND
STM32F4 discovery
Master Slave
I2C Clock Stretching

Clock Stretching simply means that holding the clock

to 0 or ground level.

The moment clock is held at low, then the whole I2C

interface pauses until clock is given up to its normal
operation level.
So, What is the use of clock stretching ?
I2C devices, either Master or Slave, uses this feature to slow down the
communication by stretching SCL to low, which prevents the clock to
Rise high again and the i2c communication stops for a while

There are situations where an I2C slave is not able to co-operate with
the clock speed given by the master and needs to slow down a little.

If slave needs time, then it takes the advantage of clock stretching , and
by holding clock at low, it momentary pauses the I2C operation.
Modifying I2C application to
send/receive more than 32 bytes
Introduction :UART vs USART
Exploring UART Interrupt
Mapping
UART USART
Universal Universal
Asynchronous Synchronous
Receiver Asynchronous
Transmitter Receiver
Transmitter
UART Peripheral supports only asynchronous mode

USART supports both asynchronous and synchronous modes.

You can use USART module both in synchronous mode as

well as in asynchronous mode

There is no specific port for USART communication. They are

commonly used in conjugation with protocols like RS-232, RS-
434, USB etc.

In synchronous transmission, the clock is sent separately from

the data stream and no start/stop bits are used
USART hardware components

 Baud rate generator

 TX and RX shift registers
 Transmit/Receive control blocks
 Transmit/Receive buffers
 First-in, First-out (FIFO) buffer memory
USART is just a piece of hardware in your microcontroller
which transmits and receives data bits either in
Synchronous mode or in Asynchronous mode.

If it is Asynchronous mode, then clock will not be sent

along with the data, instead we use synchronization bits
like start and stop along with the useful data.
Understanding UART pins
Understanding UART pins

TX

RX
UART1
RTS

CTS
Understanding UART pins

10101110101 TX

RX
UART1
RTS

CTS
Understanding UART pins

TX TX

UART1 RX RX UART2
RTS RTS

CTS CTS
UART frame formats
9-bit word Length, 1 stop bit
Optional
Parity Next Next Data Frame
Start Data Frame Bit Start
bit
Bit0 Bit1 Bit 2 Bit 3 Bit4 Bit5 Bit6 Bit7 Bit8 Stop bit
bit

8-bit word Length, 1 stop bit Optional

Parity Next
Data Frame Next Data Frame
Start Bit Start
bit bit
Bit0 Bit1 Bit 2 Bit 3 Bit4 Bit5 Bit6 Bit7 Stop
bit
UART Baudrate
The significance of baud rate is how fast the data is
sent over a serial line. It‟s usually expressed in units of
bits-per-second (bps). If you invert the baud rate, you
can find out, just how long it takes to transmit a single
bit. This value determines how long the transmitter
holds a serial line high or low .
UART Synchronization bits
 1 Stop Bit
Start 5 to 9 data bits
bit

1.5 Stop Bit

Start
bit 5 to 9 data bits

2 Stop Bit
Start
bit 5 to 9 data bits
UART Parity
Adding Parity bit is a simplest method of error detection. Parity is
simply the number of ones appearing in the binary form of a number.

55(Decimal) 0b00110111

Parity = 5

Parity

Even Parity Odd parity

Even parity
Binary
55 0 0 1 1 0 1 1 1 1

Odd number of ones Make Parity bit =1

In the data byte

That becomes, Even

number of ones
including parity bit
Even parity
Binary
54 0 0 1 1 0 1 1 0 0

even number of ones Parity bit =0

Even number of ones

including parity bit
Odd parity
Binary
55 0 0 1 1 0 1 1 1 0

Odd number of ones Parity bit =0

Maintain odd number

of ones including parity
bit
Odd parity
Binary
54 0 0 1 1 0 1 1 0 1

even number Parity bit =1

of ones

Maintain odd number

of ones including parity
bit
 Simply remember
Even parity results in even number of 1s, whereas odd
parity results in odd number of 1s, when counted
including the parity bit.
Why use the Parity Bit?
 Represents EVEN parity
. i.e even number of 1s
1101011 1 including the parity bit

Data gets corrupted

during transmission
Here it has a odd number
of 1s including the parity

1100011 1 bit. Which implies that

data is corrupted and has
to be discarded.
UART Functional block
UART Peripheral Clock
HSI
16MHz
HSE
PLL

16MHz
APB 2 bus ( 84 MHz Max)

16MHz
USART1/USART6
FPCLK
HSI
16MHz
HSE
PLL

16MHz
APB1 bus ( 42 MHz Max)

USART2
16MHz USART3
FPCLK UART4
UART5
UART Transmitter
Steps to do Data Transmission
Steps to do Data Transmission
 Program the M bit in USART_CR1 to define the word length
 Program the number of stop bits in USART_CR2 register.
 Select the desired baud rate using the USART_BRR register
 Set the TE bit in USART_CR1 to enable the transmit block. .
 Enable the USART by writing the UE bit in USART_CR1
 Now if txe flag is set , then Write the data byte to send , in the
USART_DR register .
 After writing the last data into the USART_DR register, wait until
TC=1
 Line idle Frame 1 Frame 2 Frame 3
TX Line

Set by hardware Set by hardware

TXE Flag Cleared by software Cleared by software

DR F1 F2 F3

Set by hW
TC Flag

Software Software waits TC is not set TC is not set TC is set

enables until TXE=1 and because because because
the UART writes F2 to DR TXE=0 TXE=0 TXE=1

Software waits Software waits

until TXE=1 and until TXE=1 and Software waits until TC=1
writes F1 to DR writes F3 to DR
UART Receiver
Steps to do Data Reception
Steps to do Data Reception
 Program the M bit in USART_CR1 to define the word length
 Program the number of stop bits in USART_CR2 register.
 Select the desired baud rate using the USART_BRR register
 Enable the USART by writing the UE bit in USART_CR1
 Set the RE bit in the USART_CR1 register , which enables the
receiver block of the usart peripheral
 When a character is received, wait till The RXNE bit is set and read
the data byte from the data register
 The RXNE bit must be cleared by reading the data register ,
before the end of the reception of the next character to avoid
an overrun error.
 Line idle Frame 1 Frame 2 Frame 3 Line idle
RX Line

Set by hardware Set by hardware

Cleared by Cleared by
RXNE Flag software
software

DR F1 F2 F3

Reception RXNE is set when RXNE is set when RXNE is set when
started F1 fully received F2 fully received F3 fully received

Software reads Software reads

F1 from DR F2 from DR Software reads
register register F3 from DR
register
UART Interrupts
Over sampling

 What is oversampling
 How does it effect the baudrate
Connecting UART Pins to PC
 Using TTL to USB Converter
 Using RS232 cable with DB9 Connector
 Using TTL to USB Converter
 Using RS232 cable with DB9 Connector
Overview
 Sample Applications

Startup &
UART Driver
CMSIS APIs

USART1 USART2 USART3 USARTx

STM32F4xx Microcontroller
Understanding the
Requirements
 UART initialization

UART Transmission
UART Driver APIs
UART Reception

Interrupt Handling
Exploring different UART
Peripherals and pins of the
MCU
U(S)ARTs Pin Pack 1 Pin pack 2 Pin pack 3 Bus
TX RX TX RX TX RX
USART1 PA9 PA10 PB6 PB7 APB2

USART2 PA2 PA3 PD5 PD6 APB1

USART3 PB10 PB11 PC10 PC11 PD8 PD9 APB1

UART4 PA0 PA1 PC10 PC11 APB1

UART5 PC12 PD2 APB1

USART6 PC6 PC7 PG14 PG9 APB2

UART Data Register
Firmware Write 0xAB Data Register
USART_DR

APB1/APB2

RDR

RX shift register

TX shift register

TDR
Firmware Write 0xAB Data Register
USART_DR

APB1/APB2

RDR

RX shift register

TX shift register
Write
TDR
 Firmware Read Data Register
USART_DR

Read

APB1/APB2

RDR

0xAB
RX shift register

TX shift register

TDR
UART Status Register
 Got interrupt from UART

Decode the interrupt using

Status register

Interrupt is due
Interrupt is due to Interrupt is due to Interrupt is due to Setting of ERROR
setting of RXNE flag setting of TXE flag setting of TC flag flag

Handle RXNE Handle TXE Handle TC

interrupt interrupt Handle Error
interrupt
 Handle TXE interrupt

Write one byte to

USART_DR

Tx Count--

Tx Count = 0 ?
No
Yes
Disable TXE interrupt
Enable TC interrupt

Wait till TC interrupt to

confirm of last byte sent Wait till another TXE
interrupt
 Handle TC interrupt

Disable TC interrupt

Make tx_state = READY

Call Application callback to

indicate TX completed
 Handle RXNE interrupt

Yes No
Is parity used ?

Read USART_DR register Read USART_DR register

With out msb With msb

RX Count--
N
Is RX count = 0 ?? Wait till another RXNE
interrupt
y
Disable RXNE interrupt
Disable Error interrupts

Make RX_State = READY

Call Application
callback to indicate RX
completed
Debug strings TX

USART2

LED commands RX

MCU
Commands Function

LEDOH Turn ON LED Orange

LEDOL Turn OFF LED Orange
LEDBH Turn ON LED Blue
LEDBL Turn OFF LED Blue
LEDRH Turn ON LED Red
LEDRL Turn OFF LED Red
LEDGH Turn ON LED Green
LEDGL Turn OFF LED Green
LEDAH Turn ON ALL LEDs
LEDAL Turn OFF ALL LEDs
Different USART Peripherals and Associated Pin Packs

U(S)ARTs Pin Pack 1 Pin pack 2 Pin pack 3 Bus

TX RX TX RX TX RX
USART1 PA9 PA10 PB6 PB7 APB2
USART2 PA2 PA3 PD5 PD6 APB1
USART3 PB10 PB11 PC10 PC11 PD8 PD9 APB1
UART4 PA0 PA1 PC10 PC11 APB1
UART5 PC12 PD2 APB1
USART6 PC6 PC7 PG14 PG9 APB2
USB to TTL USB UART
serial port
converter
module
 TX
RX PA2

USB
CP2102 USB to
USART2
PC UART Convertor

TX PA3
GND RX

GND MCU
 TX
RX PB10

USB
CP2102 USB to
USART Master Application
PC UART Convertor
With
uartprintf library
TX PB11
GND RX

GND

Uartprintf library uses USART3 to output debug messages

Implementing UART_PRINTF

By using this printf function you can able to print debug

messages over UART, just like standard printf
write a code for uart
create a static
printf
library
uartprintf.c
uartprintf.lib

Use uartprintf.lib in any

application to enable
the prints over UART
Both transmitting as well as receiving devices should operate at the
same rate.

2400 4800 9600 19200 38400

57600 115200
Fpclk = 16MHz OVER8=0

Desired baudrate USARTDIV value Hex conversion

(USART_BRR)
9600bps 104.1875 0x683

115200 bps 8.6875 0x8A

921600 bps(Max) 1.0625 0x11

USART and UART peripherals of your MCU

AHB1

GPIOA GPIOB GPIOC GPIOD GPIOE …. GPIOI

APB1

USART USART
I2C1 I2C2 I2C3 USART2 USART3 UART4 UART5
2 3

APB2

USART
USART1 USART6 EXTI SYSCFG
1
USART Driver Development
 Sample Applications

Driver Layer
(Device header)
gpio_driver.c , .h i2c_driver.c , .h Stm3f407xx.h

USART_driver.c , .h usart_driver.c , .h

GPIO USART I2C UART

STM3F407x MCU
Driver API requirements and
user configurable items
 USART_Mode

USART_Baud

USART_NoOfStopBits
USARTx
Peripheral Configurable items
For user application
USART_WordLength

USART_ParityControl

USART_HWFlowControl
 USART Initialization / peripheral
clock control

USART TX

USART RX
APIs
USART Driver
USART Interrupt config. &
handling

Other USART management

APIs
USART handle structure and
configuration structure
USART Configuration Structure

USART Handle Structure

Exercise :

1. Create USART driver header file and source file

2. Complete USART register definition structure and other
macros ( peripheral base addresses, Device definition ,
clock en , clock di , etc) in MCU specific header file
3. Also add USART register bit definition macros in MCU
specific header file
4. Add USART Configuration structure and USART handle
structure in USART header file
Writing API prototypes
Implementing USART_Init
USART: Oversampling ​
USART: Oversampling ​
 The receiver implements different user-configurable oversampling
techniques (except in synchronous mode) for data recovery by
discriminating between valid incoming data and noise.
 The oversampling method can be selected by programming the OVER8
bit in the USART_CR1 register and can be either 16 or 8 times the baud
rate clock
 Configurable oversampling method by 16 or by 8 to give flexibility
between speed and clock tolerance
Receiver block sampling the
Rx line during reception
when oversampling by 16 is
used

Receiver block sampling the

Rx line during reception
when oversampling by 8 is
used
Sampled values Vs Noise
Noise Error
When noise is detected in a frame:
The NF flag bit is set by hardware when noise is
detected on a received frame
The invalid data is transferred from the Shift register
to the USART_DR register
The application may consider or discard the frame
based on application logic
Selecting the proper oversampling method

The receiver implements different user-configurable oversampling techniques (except in

synchronous mode) for data recovery by discriminating between valid incoming data and
noise.

If you select oversampling by 8 (OVER8=1) then you can achieve max baudrate up
to FPCLK/8, but In this case the maximum receiver tolerance to clock deviation is
reduced

If you select oversampling by 16 (OVER8=0) then you can achieve max baudrate
up to FPCLK/16, In this case the maximum receiver tolerance to clock deviation is
increased.
UART Baudrate Calculation
 Peripheral Clock

Divide factor to generate different baud rates

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same
value as programmed in the Mantissa and Fraction values of USARTDIV.
OVER8 =1 , if Oversampling by 8 is used
OVER8=0, if Oversampling by 16 is used
 Fck= 16MHz Tx/Rx baud = 9600 bps OVER8=0
(USART Peripheral Clock) (Desired Baudrate) (Oversampling by 16)

USARTDIV = 16M /(8 * 2 * 9600)

=104.17
Programming USART Baudrate register
(USART_BRR)
 USARTDIV = 104.1875
(For baudrate 9600bps with Fck = 16MHz and OVER8=0)

Now this value we have to convert in to hex and then program the
USART_BRR register to achieve desired baud rate.

USART uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit fraction

USART_BRR

Fraction part of 4 bits Mantissa part of 12 bits

 USARTDIV = 104.1875
(For baudrate 9600bps with Fck = 16MHz and OVER8=0)

DIV_Fraction = 0.1875 X 16 = 3

Div_Mantissa = 104= 0x68

USARTDIV = 0x683
(Program this value into USART_BRR register to generate baudrate of 9600bps)
Now lets take another example of generating baud
rate of 115200 bps.

For , FCK = 16MHz and OVER8=1

 USARTDIV = 17.361
(For baudrate 115200bps with Fck = 16MHz and OVER8=1)

DIV_Fraction = 0.361 X 8 = 2.88 = 3

Div_Mantissa = 17

USARTDIV = 0x113
(Program this value into USART_BRR register to generate baudrate of 115200bps)
Overrun Error
 An overrun error occurs when a character is received when RXNE
has not been reset. Data can not be transferred from the shift
register to the RDR register until the RXNE bit is cleared.
 When an overrun error occurs:
 The ORE bit is set.
 The RDR content will not be lost. The previous data is
available when a read to USART_DR is performed
 The shift register will be overwritten. After that point, any data
received during overrun is lost.
 An interrupt will be generated if enabled.
Firmware Read Data Register
USART_DR

Read

APB1/APB2

RDR

RX shift register

TX shift register

TDR
USB to UART Converter cable
USB to UART Converter module
 TX
RX PA2

USB
CP2102 USB to
USART2
PC UART Convertor

TX PA3
GND RX

GND MCU
Exercise
Write a program to send some message over UART from STM32
board to Arduino board. The Arduino board will display the
message (on Arduino serial monitor) sent from the ST board.

Baudrate : 115200 bps

Frame format : 1 stop bits, 8 bits , no parity
Exercise
Write a program for stm32 board which transmits different messages
to the Arduino board over UART communication.

For every message STM32 board sends , arduino code will change
the case of alphabets(lower case to upper case and vice versa)
and sends message back to the stm32 board .

The stm32 board should capture the reply from the arduino
board and display using semi hosting.
Arduino Sketch

001UARTRxString.ino

Download the Arduino sketch into Arduino board