INTERRUPTS IN 8085

Nayana Shenvi, ETC, GEC 1

 NEED FOR INTERRUPTS
❖ Interrupt is a signal send by an external device to the processor, to perform a
particular task or work.
❖ Any external device which seeks the attention of the microprocessor interrupts
it.
❖ The process starts from the I/O device and is asynchronous.
❖ Mainly, the interrupts are used for data transfer between the peripheral and the
microprocessor.
❖ When a peripheral is ready for data transfer, it interrupts the processor by
sending an appropriate signal to the interrupt pin of the processor.
❖ If the processor accepts the interrupt then the processor suspends its current
activity and executes an interrupt service subroutine to complete the data
transfer between the peripheral and processor.
❖ After executing the interrupt service routine the processor resumes its current
activity. This type of data transfer scheme is called interrupt driven data transfer
scheme.
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 Classification of Interrupts
❖ Software interrupts vs hardware interrupts:
❖ Software interrupts are program instructions. These
instructions are inserted at desired locations in a program.
While running a program, If a software interrupt
instruction is encountered, then the processor executes an
interrupt service routine (ISR).
❖ Hardware interrupts are initiated by an external device
at the interrupt pin of the processor. If the interrupt is
accepted, then the processor executes an interrupt service
routine (ISR).

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 Classification of Interrupts
❖ Maskable v/s Non-maskable Interrupts:
❖ Maskable: can be delayed or rejected by µP
❖ Non-Maskable: cannot be delayed or rejected
❖ Microprocessor can ignore or delay a maskable interrupt
request, if it is performing some critical task; however it
has to respond to a non-maskable interrupt request
immediately.
❖ Vectored v/s Non-vectored Interrupts:
❖ Vectored: The address of the service routine is
hardwired.
❖ Non-vectored: the address of the service routine
needs to be supplied by the external device.
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 8085 Interrupts
❖ 8085 has a total of 5 hardware interrupt pins

Interrupts in Maskable Vectored Priority

8085
TRAP NO YES Highest
RST 7.5 YES YES
RST 6.5 YES YES
RST 5.5 YES YES
INTR YES NO Lowest

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 Interrupt Vectors and the Vector Table

❖ An Interrupt vector is a pointer to the memory location where the

Interrupt Service routine is stored.
❖ The interrupt vector table (IVT) is usually located in memory page
00H (0000H-00FFH)
❖ The purpose of the IVT is to hold the vectors that redirect the
microprocessor to the right place when an interrupt arrives.
❖ Vectored interrupts TRAP, RST 7.5, RST 6.5 and RST 5.5 have
interrupt vectors are 0024H, 003CH,0034H and 002CH respectively.
❖ INTR is a non vectored interrupt. However the microprocessor
would be directed to some memory location on page 00H,
depending upon the RST instruction which is hardwired.

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 INTR
❖ INTR is a non-vectored interrupt and a maskable interrupt.
❖ A high on this pin interrupts the processor.
❖ The Interrupt enable F/F must be set to ‘1’ before this interrupt occurs.
❖ The Interrupt enable F/F can be set by EI instruction and can be reset
by DI instruction.
❖ The interrupt signal input INTR is not
affected by SIM instruction.
❖ INTR is a non vectored interrupt, hence
depending upon the RST instruction, the
microprocessor would execute ISR from
a pre-determined hard-wired memory location.

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 Instructions related to Interrupts
Opcode Description No of bytes/
Machine
cycles/T-
states
EI Enable Interrupt: 1/1/4
• The instruction sets the Interrupt enable flip-
flop and enables the interrupt process.
• After a system reset or acknowledgement of an
interrupt, the Interrupt Enable flip-flop is reset,
thus disabling the interrupts.
• EI instruction is needed to re-enable interrupts.
DI Disable Interrupt: 1/1/4
• The instruction resets the Interrupt enable flip-flop
and disables all the interrupts (except TRAP)
• It should be included in a program segment
where an interrupt from an outside source
cannot be tolerated

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 Steps to initiate and implement Interrupt
process in 8085 (INTR)
❖ Interrupt process is enabled by writing EI instruction in the main
program.
❖ The µP checks the INTR line during the execution of every
instruction.
❖ If INTR=1, the µP completes the current instruction, disables IEN,
sends INTA (Interrupt Acknowledge) signal.
❖ An RST instruction is inserted by INTA through external hardware.
❖ This instruction will transfer the program control to specific memory
location on page 00H.
❖ When µP receives RST instruction, it saves the address of the next
instruction on the stack.
❖ Program control is transferred to CALL location of the RST
instruction.
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❖ The µP executes the task stored as ISR (which starts at CALL
location).
❖ At the end of the subroutine Interrupt Enable flag is enabled
again by EI instruction.
❖ The last instruction of the subroutine is RET, which
transfers back the program control to its original address.

Nayana Shenvi, ETC, GEC

RST instructions
❖ 8085 has eight RST instructions.
❖ These are one byte call instructions that transfer the program
execution to a specific location on page 00H.
❖ They are executed in a similar way to that of CALL instructions.
❖ When the RST instruction is encountered the return address is stored
on the stack, before the program execution is transferred to the RST
location (ISR)
❖ When the processor encounters a Return instruction in the subroutine
associated with the RST instruction, the program returns to the address
that was stored on the stack.
❖ In case of a hardware interrupt, an RST instruction is used to restart
program execution.

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 Binary code Call
Mnemonics Hex
D7 D6 D D4 D3 D2 D1 D0 Location
RST0 1 1 0 0 0 1 1 1 C7 0000H
RST1 1 1 0 0 1 1 1 1 CF 0008H
RST2 1 1 0 1 0 1 1 1 D7 0010H
RST3 1 1 0 1 1 1 1 1 DF 0018H
RST4 1 1 1 0 0 1 1 1 E7 0020H
RST5 1 1 1 0 1 1 1 1 EF 0028H
RST6 1 1 1 1 0 1 1 1 F7 0030H
RST7 1 1 1 1 1 1 1 1 FF 0038H

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 +5v

1
1
EF to data bus

1 Note that DI4 is grounded and rest

0 pins are connected to +5V, Hence
1
data on data bus is EFH.
1
1
1

Instruction RST 5 is built using resistors and a tri-state buffer.

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 8085 Vectored Interrupts

❖ Interrupts RST 7.5, 6.5 and 5.5 and TRAP are automatically transferred
to specific locations on memory page 00H without any external
hardware.
❖ They do not need the 𝐼𝑁𝑇𝐴 signal.
❖ TRAP has the highest priority, followed by RST 7.5, RST 6.5 and RST
5.5 and then INTR.
❖ However, TRAP has got lower priority than the HOLD signal used for
DMA transfer.

Interrupt Vector Address

RST 7.5 003CH

RST 6.5 0034H
RST 5.5 002CH
TRAP 0024H
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Interrupt Scheme in 8085 µP

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 TRAP
❖ TRAP is a non-maskable vectored interrupt.
❖ The TRAP input is both edge sensitive and level sensitive interrupt.
❖ It means that TRAP input must make a low to high transition and
remain high until it is acknowledged.
❖ This is why the TRAP is both edge and level sensitive. This also
avoids false triggering caused by noise and transients.
❖ The program control is transferred to location 0024H without any
external hardware or the interrupt enable instruction EI.
❖ TRAP is generally used for critical events as power failure and
emergency shut-off.

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 RST7.5, RST6.5 & RST5.5

❖ These are maskable vectored interrupts.

❖ RST 7.5 has the highest priority among these & RST5.5 has the lowest
priority.
❖ RST6.5 & RST5.5 are HIGH level sensitive interrupt inputs.
❖ Whenever RST6.5 is recognized, the control is transferred to 0034H &
whenever RST5.5 is recognized, the control is transferred to 002CH.
❖ RST7.5 control signal input is a rising edge sensitive interrupt.
❖ Whenever LOW to HIGH transition occurs, it can interrupt the
microprocessor.
❖ RST 7.5 is vectored to 003CH.

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 SIM instruction

The contents in the Accumulator register are interpreted as follows by the SIM instruction.

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Nayana Shenvi, ETC, GEC
Write the instructions to
(a) enable all interrupts in an 8085 system,
(b) reset RST 7.5
a.
EI ; Enable interrupts
MVI A, 08H ; Load bit pattern to enable RST 7.5, 6.5 and 5.5
SIM ; enable RST 7.5, 6.5 and 5.5

b.
EI ; Enable interrupts
MVI A, 18H ; Reset 7.5 interrupt flip-flop
SIM

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RIM instruction

• RIM Instruction is 1-byte instruction that can be used:

• To read interrupt masks. This instruction loads the accumulator with
8-bits indicating the current status of the interrupt masks.
• To identify pending interrupts (bits D4, D5, D6)
• To receive serial data (bits D7, D5, D6)

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 Assuming the microprocessor is completing an RST 7.5 interrupt request,
check to see if RST 6.5 is pending. If it is pending, enable RST 6.5 without
affecting any other interrupts; otherwise return to the main program.

• Instructions:

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