LTC3891

Low IQ, 60V Synchronous

Step-Down Controller

FEATURES DESCRIPTION
n Wide VIN Range: 4V to 60V (65V Abs Max) The LTC®3891 is a high performance step-down switching
n Low Operating IQ: 50μA regulator DC/DC controller that drives an all N-channel
n Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 24V synchronous power MOSFET stage. A constant fre-
n RSENSE or DCR Current Sensing quency current mode architecture allows a phase-lockable
n Phase-Lockable Frequency (75kHz to 750kHz) frequency of up to 750kHz.
n Programmable Fixed Frequency (50kHz to 900kHz)
n
The 50μA no-load quiescent current extends operating run
Selectable Continuous, Pulse-Skipping or Low Ripple
time in battery-powered systems. OPTI-LOOP® compensa-
Burst Mode® Operation at Light Load
n
tion allows the transient response to be optimized over
Selectable Current Limit
n
a wide range of output capacitance and ESR values. The
Very Low Dropout Operation: 99% Duty Cycle
n
LTC3891 features a precision 0.8V reference and power
Adjustable Output Voltage Soft-Start or Tracking
n
good output indicator. A wide 4V to 60V input supply range
Power Good Output Voltage Monitor
n
encompasses a wide range of intermediate bus voltages
Output Overvoltage Protection
n
and battery chemistries. The output voltage of the LTC3891
Low Shutdown IQ: < 14μA
n
can be programmed between 0.8V to 24V.
Internal LDO Powers Gate Drive from VIN or EXTVCC
n No Current Foldback During Start-Up The TRACK/SS pin ramps the output voltages during
n Small 20-Pin 3mm × 4mm QFN and TSSOP Packages start-up. Current foldback limits MOSFET heat dissipation
during short-circuit conditions. The PLLIN/MODE pin se-
lects among Burst Mode operation, pulse-skipping mode,
APPLICATIONS or continuous conduction mode at light loads.
n Automotive Always-On Systems L, LT, LTC, LTM, OPTI-LOOP, Burst Mode, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
n Battery Powered Digital Devices respective owners. Patents, including 5481178, 5705919, 6611131, 6498466, 6580258,
7230497.
n Distributed DC Power Systems

TYPICAL APPLICATION
Efficiency and Power Loss vs
High Efficiency 3.3V Step-Down Converter Output Current
VIN
100 10000
4V TO 60V VIN = 12V
22µF 90 VOUT = 3.3V
VIN INTVCC
LTC3891 2.2µF 80 1000
70
POWER LOSS (mW)
EFFICIENCY (%)

41.2k TG 60 100
FREQ 0.1µF
2200pF BOOST 50
10k 4.7µH 8mΩ
ITH VOUT 40 10
SW 3.3V
100pF
150µF 5A 30
BG
20 1
0.1µF
TRACK/SS SENSE+ 10
0 0.1
SENSE– 100k 0.0001 0.001 0.01 0.1 1 10
SGND OUTPUT CURRENT (A)
VFB 3891 TA01b
100k
PGOOD INTVCC 31.6k

3891 TA01a

3891fa

1
LTC3891
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (VIN).......................... –0.3V to 65V ITH, VFB Voltages.......................................... –0.3V to 6V
Topside Driver Voltage (BOOST)..................–0.3V to 71V PGOOD Voltage............................................. –0.3V to 6V
Switch Voltage (SW)...................................... –5V to 65V TRACK/SS Voltage........................................ –0.3V to 6V
(BOOST-SW)................................................. –0.3V to 6V Operating Junction Temperature Range (Notes 2, 3)
RUN.............................................................. –0.3V to 8V LTC3891E, LTC3891I........................... –40°C to 125°C
Maximum Current Sourced into Pin from LTC3891H........................................... –40°C to 150°C
Source > 8V.......................................................100μA LTC3891MP........................................ –55°C to 150°C
SENSE+, SENSE– Voltages.......................... –0.3V to 28V Maximum Junction Temperature (Notes 2, 3)
PLLIN/MODE, INTVCC Voltages.................... –0.3V to 6V LTC3891E, LTC3891I.......................................... 125°C
ILIM, FREQ Voltages............................... –0.3V to INTVCC LTC3891H, LTC3891MP..................................... 150°C
EXTVCC....................................................... –0.3V to 14V Storage Temperature Range................... –65°C to 150°C

PIN CONFIGURATION
TOP VIEW
TRACK/SS

TOP VIEW
FREQ

ILIM

TRACK/SS 1 20 ILIM
VIN

20 19 18 17 FREQ 2 19 VIN

PLLIN/MODE 1 16 PGND PLLIN/MODE 3 18 PGND

SGND 2 15 EXTVCC SGND 4 17 EXTVCC
SGND 3 21 14 INTVCC SGND 5 21 16 INTVCC
RUN 4 SGND 13 BG SGND
RUN 6 15 BG
SENSE– 5 12 BOOST SENSE– 7 14 BOOST
SENSE+ 6 11 SW
SENSE + 8 13 SW
7 8 9 10 VFB 9 12 TG
VFB
ITH
PGOOD
TG

ITH 10 11 PGOOD

FE PACKAGE
UDC PACKAGE 20-LEAD PLASTIC TSSOP
20-LEAD (3mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 38°C/W
TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3891EUDC#PBF LTC3891EUDC#TRPBF LFXV 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3891IUDC#PBF LTC3891IUDC#TRPBF LFXV 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3891HUDC#PBF LTC3891HUDC#TRPBF LFXV 20-Lead (3mm × 4mm) Plastic QFN –40°C to 150°C
LTC3891MPUDC#PBF LTC3891MPUDC#TRPBF LFXV 20-Lead (3mm × 4mm) Plastic QFN –55°C to 150°C

3891fa

2
 LTC3891
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3891EFE#PBF LTC3891EFE#TRPBF LTC3891FE 20-Lead Plastic TSSOP –40°C to 125°C
LTC3891IFE#PBF LTC3891IFE#TRPBF LTC3891FE 20-Lead Plastic TSSOP –40°C to 125°C
LTC3891HFE#PBF LTC3891HFE#TRPBF LTC3891FE 20-Lead Plastic TSSOP –40°C to 150°C
LTC3891MPFE#PBF LTC3891MPFE#TRPBF LTC3891FE 20-Lead Plastic TSSOP –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Operating Voltage Range 4 60 V
VFB Regulated Feedback Voltage (Note 4); ITH Voltage = 1.2V
–40°C to 85°C 0.792 0.800 0.808 V
LTC3891E, LTC3891I l 0.788 0.800 0.812 V
LTC3891H, LTC3891MP l 0.786 0.800 0.812 V
IFB Feedback Current (Note 4) ±5 ±50 nA
VREFLNREG Reference Voltage Line Regulation (Note 4); VIN = 4.5V to 60V 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4) l 0.01 0.1 %
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 0.7V
(Note 4) l –0.01 –0.1 %
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 2V
gm Transconductance Amplifier gm (Note 4); ITH = 1.2V; Sink/Source 5µA 2 mmho
IQ Input DC Supply Current (Note 5)
Pulse Skip or Forced Continuous Mode VFB = 0.83V (No Load) 2 mA
Sleep Mode VFB = 0.83V (No Load) 50 75 µA
Shutdown RUN = 0V 14 25 µA
UVLO Undervoltage Lockout INTVCC Ramping Up l 3.92 4.2 V
INTVCC Ramping Down l 3.6 3.80 4.0 V
VOVL Feedback Overvoltage Protection Measured at VFB Relative to Regulated VFB 7 10 13 %
ISENSE + SENSE+ Pin Current ±1 µA
ISENSE– SENSE– Pins Current VSENSE– < INTVCC – 0.5V ±2 µA
VSENSE– > INTVCC + 0.5V 700 µA
DFMAX Maximum Duty Factor In Dropout 98 99 %
ITRACK/SS Soft-Start Charge Current VTRACK = 0V 7 10 14 µA
VRUN On RUN Pin On Threshold VRUN Rising l 1.15 1.21 1.27 V
VRUN Hyst RUN Pin Hysteresis 50 mV
VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE– = 3.3V, ILIM = 0 l 22 30 36 mV
VFB = 0.7V, VSENSE– = 3.3V, ILIM = INTVCC l 43 50 57 mV
VFB = 0.7V, VSENSE– = 3.3V, ILIM = FLOAT l 64 75 85 mV

3891fa

3
LTC3891
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Driver
TG Pull-Up On-Resistance 2.5 Ω
Pull-Down On-Resistance 1.5 Ω
BG Pull-Up On-Resistance 2.4 Ω
Pull-Down On-Resistance 1.1 Ω
TG tr TG Transition Time: (Note 6)
TG tf Rise Time CLOAD = 3300pF 25 ns
Fall Time CLOAD = 3300pF 16 ns
BG tr BG Transition Time: (Note 6)
BG tf Rise Time CLOAD = 3300pF 25 ns
Fall Time CLOAD = 3300pF 13 ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF 30 ns
Synchronous Switch-On Delay Time
BG/TG t1D Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF 30 ns
Top Switch-On Delay Time
tON(MIN) Minimum On-Time (Note 7) 95 ns
INTVCC Linear Regulator
VINTVCCVIN Internal VCC Voltage 6V < VIN < 60V, VEXTVCC = 0V 4.85 5.1 5.35 V
VLDOVIN INTVCC Load Regulation ICC = 0mA to 50mA, VEXTVCC = 0V 0.7 1.1 %
VINTVCCEXT Internal VCC Voltage 6V < VEXTVCC < 13V 4.85 5.1 5.35 V
VLDOEXT INTVCC Load Regulation ICC = 0mA to 50mA, 0.6 1.1 %
VEXTVCC = 8.5V
VEXTVCC EXTVCC Switchover Voltage ICC = 0mA to 50mA, 4.5 4.7 4.9 V
EXTVCC Ramping Positive
VLDOHYS EXTVCC Hysteresis 250 mV
Oscillator and Phase-Locked Loop
f25kΩ Programmable Frequency RFREQ = 25k; 105 kHz
PLLIN/MODE = DC Voltage
f65kΩ Programmable Frequency RFREQ = 65k; 375 440 505 kHz
PLLIN/MODE = DC Voltage
f105kΩ Programmable Frequency RFREQ =105k; 835 kHz
PLLIN/MODE = DC Voltage
fLOW Low Fixed Frequency VFREQ = 0V; 320 350 380 kHz
PLLIN/MODE = DC Voltage
fHIGH High Fixed Frequency VFREQ = INTVCC; 485 535 585 kHz
PLLIN/MODE = DC Voltage
fSYNC Synchronizable Frequency PLLIN/MODE = External Clock l 75 750 kHz
PGOOD1 Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.2 0.4 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative –13 –10 –7 %
Hysteresis 2.5 %
VFB Ramping Positive 7 10 13 %
Hysteresis 2.5 %
tPG Delay for Reporting a Fault 25 µs
3891fa

4
 LTC3891
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: The LTC3891 is tested in a feedback loop that servos VITH to a
may cause permanent damage to the device. Exposure to any Absolute specified voltage and measures the resultant VFB. The specification at
Maximum Rating condition for extended periods may affect device 85°C is not tested in production and is assured by design, characterization
reliability and lifetime. and correlation to production testing at other temperatures (125°C for
Note 2: The LTC3891 is tested under pulsed load conditions such that the LTC3891E/LTC3891I, 150°C for the LTC3891H/LTC3891MP). For the
TJ ≈ TA. The LTC3891E is guaranteed to meet performance specifications LTC3891MP, the specification at –40°C is not tested in production and is
from 0°C to 85°C. Specifications over the –40°C to 125°C operating assured by design, characterization and correlation to production testing
junction temperature range are assured by design, characterization and at –55°C.
correlation with statistical process controls. The LTC3891I is guaranteed Note 5: Dynamic supply current is higher due to the gate charge being
over the –40°C to 125°C operating junction temperature range, the delivered at the switching frequency. See Applications Information.
LTC3891H is guaranteed over the –40°C to 150°C operating junction Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
temperature range and the LTC3891MP is tested and guaranteed over times are measured using 50% levels
the –55°C to 150°C operating junction temperature range. High junction Note 7: The minimum on-time condition is specified for an inductor
temperatures degrade operating lifetimes; operating lifetime is derated peak-to-peak ripple current ≥ 40% of IMAX (See Minimum On-Time
for junction temperatures greater than 125°C. Note that the maximum
Considerations in the Applications Information section).
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 3: The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD • θJA), where θJA is 43°C/W for the QFN or 38°C/W for the
TSSOP.

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency and Power Loss vs
Output Current Efficiency vs Output Current Efficiency vs Input Voltage
100 10000 100 100
VIN = 12V BURST EFFICIENCY VOUT = 8.5V
90 VOUT = 3.3V 90 98
VOUT = 3.3V
80 1000 80 96 VOUT = 8.5V

70 FCM LOSS 70 94
POWER LOSS (mW)

EFFICIENCY (%)

EFFICIENCY (%)
EFFICIENCY (%)

60 100 60 92
50 BURST LOSS 50 90
PULSE-SKIPPING
40 LOSS 10 40 88 VOUT = 3.3V
30 30 86
20 FCM EFFICIENCY 1 20 84
Burst Mode OPERATION
10 PULSE-SKIPPING 10 82
EFFICIENCY VIN = 12V ILOAD = 2A
0 0.1 0 80
0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 0 5 10 15 20 25 30 35 40 45 50 55 60
OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V)
FIGURE 12 CIRCUIT 3891 G01
FIGURES 12, 14 CIRCUITS 3891 G02
FIGURES 12, 14 CIRCUITS 3891 G03

3891fa

5
LTC3891
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step Load Step Load Step
Burst Mode Operation Pulse-Skipping Mode Forced Continuous Mode

VOUT VOUT VOUT

100mV/DIV 100mV/DIV 100mV/DIV
AC- AC- AC-
COUPLED COUPLED COUPLED

IL IL IL
2A/DIV 2A/DIV 2A/DIV
3891 G04 3891 G05 3891 G06
50µs/DIV 50µs/DIV 50µs/DIV
LOAD STEP = 100mA TO 3A LOAD STEP = 100mA TO 3A LOAD STEP = 100mA TO 3A
VIN = 12V VIN = 12V VIN = 12V
VOUT = 3.3V VOUT = 3.3V VOUT = 3.3V
FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT

Inductor Current at Light Load Soft Start-Up Tracking Start-Up

FORCED
CONTINUOUS
MODE VOUT = 8.5V MASTER
2V/DIV 2V/DIV

Burst Mode
OPERATION VOUT = 3.3V VOUT 2V/DIV
1A/DIV 2V/DIV

PULSE-SKIPPING
MODE
3891 G07 3891 G08
5µs/DIV 2ms/DIV 2ms/DIV
3891 G09

VIN = 12V FIGURES 12, 14 CIRCUITS

VOUT = 3.3V
ILOAD = 200µA

Total Input Supply Current vs EXTVCC Switchover and INTVCC

Input Voltage Voltages vs Temperature INTVCC Line Regulation
300 6.0 5.5
FIGURE 12 CIRCUIT
5.8
250
EXTVCC AND INTVCC VOLTAGE (V)

5.6 5.0
SUPPLY CURRENT (µA)

5.4
INTVCC VOLTAGE (V)

200
300µA LOAD 5.2 INTVCC 4.5
150 5.0
EXTVCC RISING
4.8 4.0
100 EXTVCC FALLING
4.6
NO LOAD
4.4 3.5
50
4.2
ILOAD = 10mA
0 4.0 3.0
5 10 15 20 25 30 35 40 45 50 55 60 65 –75 –50 –25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V) TEMPERATURE (°C) INPUT VOLTAGE (V)
3891 G10 3891 G12
3891 G11

3891fa

6
 LTC3891
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense Voltage Maximum Current Sense
vs ITH Voltage SENSE– Pin Input Bias Current Threshold vs Duty Cycle
80 800 80
5% DUTY CYCLE

MAXIMUM CURRENT SENSE VOLTAGE (mV)

700
CURRENT SENSE THESHOLD (mV)

60 70 ILIM = FLOAT
600
PULSE-SKIPPING MODE

SENSE– CURRENT (µA)

40 Burst Mode 500 60
OPERATION 400 ILIM = INTVCC
20 50
300
ILIM = GND
0 200 40
ILIM = INTVCC
100 ILIM = GND
–20 ILIM = FLOAT 30
0
FORCED CONTINUOUS MODE
–40 –100 20
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 5 10 15 20 25 0 10 20 30 40 50 60 70 80 90 100
VITH (V) VSENSE COMMON MODE VOLTAGE (V) DUTY CYCLE (%)
3891 G13 3891 G14 3891 G15

Foldback Current Limit Quiescent Current vs Temperature INTVCC vs Load Current

80 80 5.50
VIN = 12V VIN = 12V
MAXIMUM CURRENT SENSE VOLTAGE (mV)

ILIM = FLOAT
70 75
5.25
70 EXTVCC = 0V
QUIESCENT CURRENT (µA)

60
65

INTVCC VOLTAGE (V)

ILIM = INTVCC 5.00 EXTVCC = 8.5V
50
60
40 55 4.75

30 50
4.50 EXTVCC = 5V
ILIM = GND 45
20
40
4.25
10 35
0 30 4.00
0 100 200 300 400 500 600 700 800 –75 –50 –25 0 25 50 75 100 125 150 0 20 40 60 80 100
FEEDBACK VOLTAGE (MV) TEMPERATURE (°C) LOAD CURRENT (mA)
3891 G16 3891 G17 3891 G18

TRACK/SS Pull-Up Current Shutdown (RUN) Threshold Regulated Feedback Voltage

vs Temperature vs Temperature vs Temperature
12.0 1.30 808
REGULATED FEEDBACK VOLTAGE (mV)

11.5 806

11.0 1.25
TRACK/SS CURRENT (µA)

804
RUN PIN VOLTAGE (V)

10.5 RUN RISING 802

10.0 1.20 800

9.5 798
RUN FALLING
9.0 1.15 796

8.5 794

8.0 1.10 792

–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3891 G19 3891 G20 3891 G21

3891fa

7
 LTC3891
TYPICAL PERFORMANCE CHARACTERISTICS
SENSE– Pin Input Bias Current Shutdown Current vs Input Oscillator Frequency
vs Temperature Voltage vs Temperature
800 30 600
700
VOUT > INTVCC + 0.5V 25 FREQ = INTVCC
550
600

SHUTDOWN CURRENT (µA)

SENSE– CURRENT (µA)

500 20 500

FREQUENCY (kHz)
400
15 450
300

200 10 400
100 FREQ = GND
VOUT < INTVCC – 0.5V 5 350
0

–100 0 300
–75 –50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30 35 40 45 50 55 60 65 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C)
3891 G22 3891 G23 3891 G24

Undervoltage Lockout Threshold Oscillator Frequency vs Input

vs Temperature Voltage Shutdown Current vs Temperature
4.2 356 22
FREQ = GND VIN = 12V

4.1 354 20
OSCILLATOR FREQUENCY (kHz)

SHUTDOWN CURRENT (µA)

18
INTVCC VOLTAGE (V)

4.0 352
RISING
16
3.9 350
14
FALLING
3.8 348
12

3.7 346 10

3.6 344 8
–75 –50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30 35 40 45 50 55 60 65 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C)
3891 G25 3891 G26 3891 G27

3891fa

8
 LTC3891
PIN FUNCTIONS (QFN/eTSSOP)

PLLIN/MODE (Pin 1/Pin 3): External Synchronization PGOOD (Pin 9/Pin 11): Open-Drain Logic Output. PGOOD
Input to Phase Detector and Forced Continuous Mode is pulled to ground when the voltage on the VFB pin is not
Input. When an external clock is applied to this pin, the within 10% of its set point.
phase-locked loop will force the rising TG signal to be
TG (Pin 10/Pin 12): High Current Gate Drives for Top
synchronized with the rising edge of the external clock,
N-channel MOSFET. This is the output of floating driver
and the regulator operates in forced continuous mode.
with a voltage swing equal to INTVCC superimposed on
When not synchronizing to an external clock, this input
the switch node voltage SW.
determines how the LTC3891 operates at light loads. Pull-
ing this pin to ground selects Burst Mode operation. An SW (Pin 11/ Pin 13): Switch Node Connection to Induc-
internal 100k resistor to ground also invokes Burst Mode tor.
operation when the pin is floated. Tying this pin to INTVCC BOOST (Pin 12/Pin 14): Bootstrapped Supply to the Top-
forces continuous inductor current operation. Tying this side Floating Driver. A capacitor is connected between the
pin to a voltage greater than 1.2V and less than INTVCC BOOST and SW pin and a Schottky diode is tied between
–1.3V selects pulse-skipping operation. the BOOST and INTVCC pins. Voltage swing at the BOOST
SGND (Pins 2, 3, Exposed Pad Pin 21/Pins 4, 5, pin is from INTVCC to (VIN + INTVCC).
Exposed Pad Pin 21): Small-signal ground, must be routed BG (Pin 13/Pin 15): High Current Gate Drive for Bottom
separately from high current grounds to the common (Synchronous) N-channel MOSFET. Voltage swing at this
(–) terminals of the CIN capacitor. Pins 2, 3/4, 5, must pin is from ground to INTVCC.
both be electrically connected to small signal ground for
proper operation.The exposed pad must be soldered to INTVCC (Pin 14/Pin 16): Output of the Internal Linear
PCB ground for rated thermal performance. Low Dropout Regulator. The driver and control circuits
are powered from this voltage source. Must be decoupled
RUN (Pin 4/Pin 6): Digital Run Control Input. Forcing this to PGND with a minimum of 2.2µF ceramic or other low
pin below 1.16V shuts down the controller. Forcing this ESR capacitor. Do not use the INTVCC pin for any other
pin below 0.7V shuts down the entire LTC3891, reducing purpose.
quiescent current to approximately 14µA.
EXTVCC (Pin 15/Pin 17): External Power Input to an
SENSE– (Pin 5/Pin 7): The (–) Input to the Differential Internal LDO Connected to INTVCC. This LDO supplies
Current Comparator. When greater than INTVCC – 0.5V, the INTVCC power, bypassing the internal LDO powered from
SENSE– pin supplies power to the current comparator. VIN whenever EXTVCC is higher than 4.7V. See EXTVCC
SENSE+ (Pin 6/Pin 8): The (+) input to the differential Connection in the Applications Information section. Do
current comparator is normally connected to DCR sensing not float or exceed 14V on this pin.
network or current sensing resistor. The ITH pin voltage and PGND (Pin 16/Pin 18): Driver Power Ground. Connects to
controlled offsets between the SENSE– and SENSE+ pins in the source of bottom (synchronous) N-channel MOSFET
conjunction with RSENSE set the current trip threshold. and the (–) terminal of CIN.
VFB (Pin 7/Pin 9): Receives the remotely sensed feed- VIN (Pin 17/Pin 19): Main Supply Pin. A bypass capacitor
back voltage from an external resistive divider across should be tied between this pin and the SGND pins.
the output.
ILIM (Pin 18/Pin 20): Current Comparator Sense Voltage
ITH (Pin 8/Pin 10): Error Amplifier Outputs and Switching Range Inputs. Tying this pin to SGND, FLOAT or INTVCC
Regulator Compensation Point. The current comparator sets the maximum current sense threshold to one of three
trip point increases with this control voltage. different levels for the comparator.

3891fa

9
LTC3891
PIN FUNCTIONS
TRACK/SS (Pin 19/Pin 1): External Tracking and Soft- FREQ (Pin 20/Pin 2): The frequency control pin for the
Start Input. The LTC3891 regulates the VFB voltage to the internal VCO. Connecting the pin to GND forces the VCO
smaller of 0.8V or the voltage on the TRACK/SS pin. An to a fixed low frequency of 350kHz. Connecting the pin
internal 10μA pull-up current source is connected to this to INTVCC forces the VCO to a fixed high frequency of
pin. A capacitor to ground at this pin sets the ramp time 535kHz. Other frequencies between 50kHz and 900kHz
to final regulated output voltage. Alternatively, a resistor can be programmed by using a resistor between FREQ
divider on another voltage supply connected to this pin and GND. An internal 20µA pull-up current develops the
allows the LTC3891 output to track another supply during voltage to be used by the VCO to control the frequency.
start-up.

FUNCTIONAL DIAGRAM
INTVCC VIN

DB
PGOOD +
0.88V BOOST
–
VFB CB
+ DROP TG
TOP
OUT CIN
0.72V D
–
DET BOT
TOP ON SW
S Q

R Q INTVCC
SWITCH
SHDN LOGIC BOT BG
20µA
FREQ COUT
VCO CLK2 PGND
VOUT
CLK1
+ RSENSE
0.425V SLEEP L
–

ICMP IR
PFD – +
–
+
–+ +–
2mV SENSE+
SYNC
2.7V
PLLIN/MODE DET
0.65V
SENSE–
100k
SLOPE COMP
ILIM VFB
CURRENT RB
+
LIMIT
EA 0.80V
VIN –
TRACK/SS RA

+
EXTVCC OV
–
0.88V CC
ITH

5.1V 5.1V
7µA SHDN CC2 RC
LDO LDO 10µA
RST FOLDBACK
EN EN TRACK/SS
2(VFB)
+
11V
– SHDN CSS
4.7V
3891 FD

SGND INTVCC RUN

3891fa

10
 LTC3891
OPERATION
Main Control Loop Shutdown and Start-Up (RUN, TRACK/SS Pins)
The LTC3891 uses a constant frequency, current mode The LTC3891 can be shut down using the RUN pin. Pulling
step-down architecture. During normal operation, the this pin below 1.16V shuts down the main control loop.
external top MOSFET is turned on when the clock for Pulling the RUN pin below 0.7V disables the controller
that channel sets the RS latch, and is turned off when the and most internal circuits, including the INTVCC LDOs.
main current comparator, ICMP, resets the RS latch. The In this state, the LTC3891 draws only 14μA of quiescent
peak inductor current at which ICMP trips and resets the current.
latch is controlled by the voltage on the ITH pin, which is Releasing the RUN pin allows a small internal current to
the output of the error amplifier, EA. The error amplifier pull up the pin to enable the controller. The RUN pin has
compares the output voltage feedback signal at the VFB a 7μA pull-up which is designed to be large enough so
pin (which is generated with an external resistor divider
that the RUN pin can be safely floated (to always enable
connected across the output voltage, VOUT, to ground) to
the controller) without worry of condensation or other
the internal 0.800V reference voltage. When the load cur-
small board leakage pulling the pin down. This is ideal
rent increases, it causes a slight decrease in VFB relative
for always-on applications where the controller is enabled
to the reference, which causes the EA to increase the ITH
continuously and never shut down.
voltage until the average inductor current matches the
new load current. The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
After the top MOSFET is turned off each cycle, the bottom
source, do not exceed the absolute maximum rating of
MOSFET is turned on until either the inductor current starts
8V. The RUN pin has an internal 11V voltage clamp that
to reverse, as indicated by the current comparator IR, or
allows the RUN pin to be connected through a resistor to a
the beginning of the next clock cycle.
higher voltage (for example, VIN), so long as the maximum
current into the RUN pin does not exceed 100μA.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most The RUN pin can also be implemented as a UVLO by
other internal circuitry is derived from the INTVCC pin. connecting it to the output of an external resistor divider
When the EXTVCC pin is tied to a voltage less than 4.7V, network off VIN (see Applications Information section).
the VIN LDO (low dropout linear regulator) supplies 5.1V The start-up of the controller’s output voltage VOUT is
from VIN to INTVCC. If EXTVCC is taken above 4.7V, the VIN controlled by the voltage on the TRACK/SS pin. When the
LDO is turned off and an EXTVCC LDO is turned on. Once voltage on the TRACK/SS pin is less than the 0.8V internal
enabled, the EXTVCC LDO supplies 5.1V from EXTVCC to reference, the LTC3891 regulates the VFB voltage to the
INTVCC. Using the EXTVCC pin allows the INTVCC power TRACK/SS pin voltage instead of the 0.8V reference. This
to be derived from a high efficiency external source such allows the TRACK/SS pin to be used to program a soft-start
as one of the LTC3891 switching regulator outputs. by connecting an external capacitor from the TRACK/SS
The top MOSFET driver is biased from the floating bootstrap pin to SGND. An internal 10μA pull-up current charges
capacitor, CB, which normally recharges during each cycle this capacitor creating a voltage ramp on the TRACK/SS
through an external diode when the top MOSFET turns pin. As the TRACK/SS voltage rises linearly from 0V to
off. If the input voltage, VIN, decreases to a voltage close 0.8V (and beyond up to 5V), the output voltage VOUT rises
smoothly from zero to its final value. Alternatively the
to VOUT, the loop may enter dropout and attempt to turn
on the top MOSFET continuously. The dropout detector TRACK/SS pin can be used to cause the start-up of VOUT
to track that of another supply. Typically, this requires
detects this and forces the top MOSFET off for about one
connecting to the TRACK/SS pin an external resistor
twelfth of the clock period every tenth cycle to allow CB
to recharge. divider from the other supply to ground (see Applications
Information section).
3891fa

11
LTC3891
OPERATION
Light Load Current Operation (Burst Mode Operation, mined by the voltage on the ITH pin, just as in normal
Pulse-Skipping or Forced Continuous Mode) operation. In this mode, the efficiency at light loads is
(PLLIN/MODE Pin) lower than in Burst Mode operation. However, continu-
ous operation has the advantage of lower output voltage
The LTC3891 can be enabled to enter high efficiency Burst
ripple and less interference to audio circuitry. In forced
Mode operation, constant frequency pulse-skipping mode,
continuous mode, the output ripple is independent of
or forced continuous conduction mode at low load cur-
load current.
rents. To select Burst Mode operation, tie the PLLIN/MODE
pin to SGND. To select forced continuous operation, tie When the PLLIN/MODE pin is connected for pulse-skip-
the PLLIN/MODE pin to INTVCC. To select pulse-skipping ping mode, the LTC3891 operates in PWM pulse-skipping
mode, tie the PLLIN/MODE pin to a DC voltage greater mode at light loads. In this mode, constant frequency
than 1.2V and less than INTVCC – 1.3V. operation is maintained down to approximately 1% of
When the controller is enabled for Burst Mode opera- designed maximum output current. At very light loads, the
tion, the minimum peak current in the inductor is set to current comparator, ICMP, may remain tripped for several
approximately 25% of the maximum sense voltage even cycles and force the external top MOSFET to stay off for
though the voltage on the ITH pin indicates a lower value. the same number of cycles (i.e., skipping pulses). The
If the average inductor current is higher than the load cur- inductor current is not allowed to reverse (discontinuous
rent, the error amplifier, EA, will decrease the voltage on operation). This mode, like forced continuous operation,
the ITH pin. When the ITH voltage drops below 0.425V, exhibits low output ripple as well as low audio noise and
the internal sleep signal goes high (enabling sleep mode) reduced RF interference as compared to Burst Mode
and both external MOSFETs are turned off. The ITH pin is operation. It provides higher low current efficiency than
then disconnected from the output of the EA and parked forced continuous mode, but not nearly as high as Burst
at 0.450V. Mode operation.

In sleep mode, much of the internal circuitry is turned off, Frequency Selection and Phase-Locked Loop (FREQ
reducing the quiescent current that the LTC3891 draws to and PLLIN/MODE Pins)
only 50μA. In sleep mode, the load current is supplied by
The selection of switching frequency is a trade-off between
the output capacitor. As the output voltage decreases, the
efficiency and component size. Low frequency opera-
EA’s output begins to rise. When the output voltage drops
tion increases efficiency by reducing MOSFET switching
enough, the ITH pin is reconnected to the output of the
losses, but requires larger inductance and/or capacitance
EA, the sleep signal goes low, and the controller resumes
to maintain low output ripple voltage.
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator. The switching frequency of the LTC3891 can be selected
using the FREQ pin.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse If the PLLIN/MODE pin is not being driven by an external
current comparator, IR, turns off the bottom external clock source, the FREQ pin can be tied to SGND, tied
MOSFET just before the inductor current reaches zero, to INTVCC or programmed through an external resistor.
preventing it from reversing and going negative. Thus, the Tying FREQ to SGND selects 350kHz while tying FREQ to
controller operates in discontinuous operation. INTVCC selects 535kHz. Placing a resistor between FREQ
and SGND allows the frequency to be programmed between
In forced continuous operation or clocked by an external 50kHz and 900kHz, as shown in Figure 9.
clock source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop section), the inductor A phase-locked loop (PLL) is available on the LTC3891
current is allowed to reverse at light loads or under large to synchronize the internal oscillator to an external clock
transient conditions. The peak inductor current is deter- source that is connected to the PLLIN/MODE pin. The
3891fa

12
 LTC3891
OPERATION
LTC3891’s phase detector adjusts the voltage (through an than 10% above its regulation point of 0.800V, the top
internal lowpass filter) of the VCO input to align the turn-on MOSFET is turned off and the bottom MOSFET is turned
of the controller’s external top MOSFET to the rising edge on until the overvoltage condition is cleared.
of the synchronizing signal.
Power Good Pin
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is The PGOOD pin is connected to an open drain of an internal
applied. If prebiased near the external clock frequency, N-channel MOSFET. The MOSFET turns on and pulls the
the PLL loop only needs to make slight changes to the PGOOD pin low when the VFB pin voltage is not within ±10%
VCO input in order to synchronize the rising edge of the of the 0.8V reference voltage. The PGOOD pin is also pulled
external clock’s to the rising edge of TG. The ability to low when the RUN pin is low (shut down). When the VFB
prebias the loop filter allows the PLL to lock-in rapidly pin voltage is within the ±10% requirement, the MOSFET
without deviating far from the desired frequency. is turned off and the pin is allowed to be pulled up by an
external resistor to a source no greater than 6V.
The typical capture range of the phase-locked loop is from
approximately 55kHz to 900kHz, with a guarantee to be Foldback Current
between 75kHz and 750kHz. In other words, the LTC3891’s
PLL is guaranteed to lock to an external clock source whose When the output voltage falls to less than 70% of its
frequency is between 75kHz and 750kHz. nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
The typical input clock thresholds on the PLLIN/MODE the severity of the overcurrent or short-circuit condition.
pin are 1.6V (rising) and 1.2V (falling). Foldback current limiting is disabled during the soft-start
interval (as long as the VFB voltage is keeping up with the
Output Overvoltage Protection TRACK/SS voltage).
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the VFB pin rises by more

3891fa

13
LTC3891
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC3891 Filter components mutual to the sense lines should be
application circuit. LTC3891 can be configured to use placed close to the LTC3891, and the sense lines should
either DCR (inductor resistance) sensing or low value run close together to a Kelvin connection underneath the
resistor sensing. The choice between the two current current sense element (shown in Figure 1). Sensing cur-
sensing schemes is largely a design trade-off between rent elsewhere can effectively add parasitic inductance
cost, power consumption and accuracy. DCR sensing and capacitance to the current sense element, degrading
is becoming popular because it saves expensive current the information at the sense terminals and making the
sensing resistors and is more power efficient, especially programmed current limit unpredictable. If inductor DCR
in high current applications. However, current sensing sensing is used (Figure 2b), sense resistor R1 should be
resistors provide the most accurate current limits for the placed close to the switching node, to prevent noise from
controller. Other external component selection is driven coupling into sensitive small-signal nodes.
by the load requirement, and begins with the selection of
TO SENSE FILTER,
RSENSE (if RSENSE is used) and inductor value. Next, the NEXT TO THE CONTROLLER
power MOSFETs and Schottky diodes are selected. Finally,
input and output capacitors are selected. COUT
3891 F01

INDUCTOR OR RSENSE
Current Limit Programming Figure 1. Sense Lines Placement with Inductor or Sense Resistor
The ILIM pin is a tri-level logic input which sets the maximum
current limit of the controller. When ILIM is grounded, the VIN
INTVCC
VIN

maximum current limit threshold voltage of the current

comparator is programmed to be 30mV. When ILIM is BOOST
TG
floated, the maximum current limit threshold is 75mV. SW
RSENSE
VOUT
When ILIM is tied to INTVCC, the maximum current limit LTC3891
BG
threshold is set to 50mV.
R1*
SENSE+
SENSE+ and SENSE– Pins C1* PLACE CAPACITOR NEAR
SENSE PINS
SENSE–
The SENSE+ and SENSE– pins are the inputs to the cur- SGND
rent comparators. The common mode voltage range on *R1 AND C1 ARE OPTIONAL
3891 F02a

these pins is 0V to 28V (abs max), enabling the LTC3891 (2a) Using a Resistor to Sense Current
to regulate output voltages up to a nominal 24V (allowing
margin for tolerances and transients). VIN VIN
INTVCC
The SENSE+ pin is high impedance over the full common
BOOST INDUCTOR
mode range, drawing at most ±1μA. This high impedance TG
allows the current comparators to be used in inductor SW
L DCR
VOUT
DCR sensing. LTC3891
BG

The impedance of the SENSE– pin changes depending on R1

the common mode voltage. When SENSE– is less than SENSE+
C1* R2
INTVCC – 0.5V, a small current of less than 1μA flows out SENSE–
of the pin. When SENSE– is above INTVCC + 0.5V, a higher SGND

current (~700μA) flows into the pin. Between INTVCC – 0.5V *PLACE C1 NEAR (R1||R2) • C1 =
L
RSENSE(EQ) = DCR
R2
DCR R1 + R2
and INTVCC + 0.5V, the current transitions from the smaller SENSE PINS 3891 F02b

current to the higher current. (2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
3891fa

14
 LTC3891
APPLICATIONS INFORMATION
Low Value Resistor Current Sensing If the external (R1||R2) • C1 time constant is chosen to be
A typical sensing circuit using a discrete resistor is shown exactly equal to the L/DCR time constant, the voltage drop
in Figure 2a. RSENSE is chosen based on the required across the external capacitor is equal to the drop across
output current. the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
The current comparator has a maximum threshold the DCR is greater than the target sense resistor value.
VSENSE(MAX) determined by the ILIM setting. The current To properly dimension the external filter components, the
comparator threshold voltage sets the peak of the induc- DCR of the inductor must be known. It can be measured
tor current, yielding a maximum average output current, using a good RLC meter, but the DCR tolerance is not
IMAX, equal to the peak value less half the peak-to-peak always the same and varies with temperature; consult the
ripple current, ΔIL. To calculate the sense resistor value, manufacturers’ data sheets for detailed information.
use the equation:
Using the inductor ripple current value from the Inductor
VSENSE(MAX) Value Calculation section, the target sense resistor
RSENSE = value is:
DIL
IMAX +
2 VSENSE(MAX)
RSENSE(EQUIV) =
To ensure that the application will deliver full load current DIL
IMAX +
over the full operating temperature range, choose the 2
minimum value for the Maximum Current Sense Threshold
To ensure that the application will deliver full load current
(VSENSE(MAX)) in the Electrical Characteristics table (30mV,
over the full operating temperature range, choose the
50mV or 75mV, depending on the state of the ILIM pin).
minimum value for the Maximum Current Sense Threshold
When using the controller in very low dropout conditions, (VSENSE(MAX)) in the Electrical Characteristics table (30mV,
the maximum output current level will be reduced due 50mV or 75mV, depending on the state of the ILIM pin).
to the internal compensation required to meet stability
Next, determine the DCR of the inductor. When provided,
criterion for buck regulators operating at greater than
use the manufacturer’s maximum value, usually given at
50% duty factor. A curve is provided in the Typical Perfor-
20°C. Increase this value to account for the temperature
mance Characteristics section to estimate this reduction
coefficient of copper resistance, which is approximately
in peak inductor current depending upon the operating
0.4%/°C. A conservative value for TL(MAX) is 100°C.
duty factor.
To scale the maximum inductor DCR to the desired sense
Inductor DCR Sensing resistor value (RD), use the divider ratio:
For applications requiring the highest possible efficiency RSENSE(EQUIV)
at high load currents, the LTC3891 is capable of sensing RD =
DCRMAX at TL(MAX)
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC resistance of the copper wire, which can be C1 is usually selected to be in the range of 0.1μF to 0.47μF.
less than 1mΩ for today’s low value, high current inductors. This forces R1 || R2 to around 2k, reducing error that might
In a high current application requiring such an inductor, have been caused by the SENSE+ pin’s ±1μA current.
power loss through a sense resistor would cost several
points of efficiency compared to inductor DCR sensing.

3891fa

15
LTC3891
APPLICATIONS INFORMATION
The equivalent resistance R1 || R2 is scaled to the tem- The inductor value has a direct effect on ripple current.
perature inductance and maximum DCR: The inductor ripple current, ΔIL, decreases with higher
inductance or higher frequency and increases with higher
L VIN:
R1|| R2 =
(DCR at 20°C) • C1
1  V 
ΔIL = VOUT 1– OUT 
The sense resistor values are:

( f) (L)  VIN 
R1|| R2 R1• RD Accepting larger values of ΔIL allows the use of low in-
R1= ; R2 =
RD 1– RD ductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
The maximum power loss in R1 is related to duty cycle, ripple current is ΔIL = 0.3(IMAX). The maximum ΔIL occurs
and will occur in continuous mode at the maximum input at the maximum input voltage.
voltage: The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
PLOSS R1=
( VIN(MAX) – VOUT ) • VOUT inductor current required results in a peak current below
R1 25% of the current limit determined by RSENSE. Lower
inductor values (higher ΔIL) will cause this to occur at
Ensure that R1 has a power rating higher than this value. lower load currents, which can cause a dip in efficiency in
If high efficiency is necessary at light loads, consider this the upper range of low current operation. In Burst Mode
power loss when deciding whether to use DCR sensing or operation, lower inductance values will cause the burst
sense resistors. Light load power loss can be modestly frequency to decrease.
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However, Inductor Core Selection
DCR sensing eliminates a sense resistor, reduces conduc- Once the value for L is known, the type of inductor must
tion losses and provides higher efficiency at heavy loads. be selected. High efficiency converters generally cannot
Peak efficiency is about the same with either method. afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
Inductor Value Calculation cores. Actual core loss is independent of core size for a
The operating frequency and inductor selection are inter- fixed inductor value, but it is very dependent on inductance
related n that higher operating frequencies allow the use value selected. As inductance increases, core losses go
of smaller inductor and capacitor values. So why would down. Unfortunately, increased inductance requires more
anyone ever choose to operate at lower frequencies with turns of wire and therefore copper losses will increase.
larger components? The answer is efficiency. A higher Ferrite designs have very low core loss and are preferred
frequency generally results in lower efficiency because for high switching frequencies, so design goals can
of MOSFET switching and gate charge losses. In addi- concentrate on copper loss and preventing saturation.
tion to this basic trade-off, the effect of inductor value Ferrite core material saturates hard, which means that
on ripple current and low current operation must also be inductance collapses abruptly when the peak design current
considered. is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!

3891fa

16
 LTC3891
APPLICATIONS INFORMATION
Power MOSFET and Schottky Diode (Optional) where δ is the temperature dependency of RDS(ON) and
Selection RDR (approximately 2Ω) is the effective driver resistance
Two external power MOSFETs must be selected for the at the MOSFET’s Miller threshold voltage. VTHMIN is the
LTC3891 controller: one N-channel MOSFET for the top typical MOSFET minimum threshold voltage.
(main) switch, and one N-channel MOSFET for the bottom Both MOSFETs have I2R losses while the topside N-channel
(synchronous) switch. equation includes an additional term for transition losses,
The peak-to-peak drive levels are set by the INTVCC which are highest at high input voltages. For VIN < 20V
voltage. This voltage is typically 5.1V during start-up the high current efficiency generally improves with larger
(see EXTVCC Pin Connection). Consequently, logic-level MOSFETs, while for VIN > 20V the transition losses rapidly
threshold MOSFETs must be used in most applications. increase to the point that the use of a higher RDS(ON) device
Pay close attention to the BVDSS specification for the with lower CMILLER actually provides higher efficiency. The
MOSFETs as well. synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
Selection criteria for the power MOSFETs include the on- a short-circuit when the synchronous switch is on close
resistance, RDS(ON), Miller capacitance, CMILLER, input to 100% of the period.
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge The term (1+ δ) is generally given for a MOSFET in the
curve usually provided on the MOSFET manufacturers’ form of a normalized RDS(ON) vs Temperature curve, but
datasheet. CMILLER is equal to the increase in gate charge δ = 0.005/°C can be used as an approximation for low
along the horizontal axis while the curve is approximately voltage MOSFETs.
flat divided by the specified change in VDS. This result is A Schottky diode can be inserted in parallel with the bot-
then multiplied by the ratio of the application applied VDS tom MOSFET to conduct during the dead-time between
to the gate charge curve specified VDS. When the IC is the conduction of the two power MOSFETs. This prevents
operating in continuous mode the duty cycles for the top the body diode of the bottom MOSFET from turning on,
and bottom MOSFETs are given by: storing charge during the dead-time and requiring a
VOUT reverse recovery period that could cost as much as 3%
Main Switch Duty Cycle = in efficiency at high VIN. A 1A to 3A Schottky is generally
VIN
a good compromise for both regions of operation due to
VIN − VOUT
Synchronous Switch Duty Cycle = the relatively small average current. Larger diodes result
VIN in additional transition losses due to their larger junction

capacitance.
The MOSFET power dissipations at maximum output
current are given by: CIN and COUT Selection
VOUT 2 The selection of CIN is usually based off the worst-case RMS
PMAIN = (IMAX ) (1+ δ) RDS(ON) +
VIN input current. The highest (VOUT)(IOUT) product needs to
be used in the formula shown in Equation 1 to determine
2 I 
( VIN)  MAX  (R ) (C
2  DR MILLER
)• the maximum RMS capacitor current requirement.
In continuous mode, the source current of the top MOSFET
 1 1  is a square wave of duty cycle (VOUT)/(VIN). To prevent
 + ( f)
 VINTVCC – VTHMIN VTHMIN  large voltage transients, a low ESR capacitor sized for the

VIN – VOUT 2
PSYNC = (IMAX ) (1+ δ) RDS(ON)
VIN
3891fa

17
LTC3891
APPLICATIONS INFORMATION
maximum RMS current of one channel must be used. The To improve the frequency response, a feedforward ca-
maximum RMS capacitor current is given by: pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
IMAX  1/2 inductor or the SW line.
CIN Required IRMS ≈
VIN ( VOUT ) ( VIN – VOUT ) (1)
VOUT
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly LTC3891 RB CFF

used for design because even significant deviations do not VFB

offer much relief. Note that capacitor manufacturers’ ripple RA

current ratings are often based on only 2000 hours of life. 3891 F03

This makes it advisable to further derate the capacitor, or Figure 3. Setting Output Voltage
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet RUN Pin
size or height requirements in the design. Due to the high
operating frequency of the LTC3891, ceramic capacitors The LTC3891 is enabled using the RUN pin. It has a rising
can also be used for CIN. Always consult the manufacturer threshold of 1.21V with 50mV of hysteresis. Pulling the
if there is any question. RUN pin below 1.16V shuts down the main control loop.
Pulling it below 0.7V disables the controller and most
A small (0.1μF to 1μF) bypass capacitor between the chip internal circuits, including the INTVCC LDOs. In this state,
VIN pin and ground, placed close to the LTC3891, is also the LTC3891 draws only 14μA of quiescent current.
suggested. A small (≤10Ω) resistor placed between CIN
(C1) and the VIN pin provides further isolation. Releasing the RUN pin allows a small 7μA internal current
to pull up the pin to enable the controller. The RUN pin may
The selection of COUT is driven by the effective series be externally pulled up or driven directly by logic. When
resistance (ESR). Typically, once the ESR requirement driving the RUN pin with a low impedance source, do not
is satisfied, the capacitance is adequate for filtering. The exceed the absolute maximum rating of 8V. The RUN pin
output ripple (ΔVOUT) is approximated by: has an internal 11V voltage clamp that allows the RUN pin
  to be connected through a resistor to a higher voltage (for
1 example, VIN), so long as the maximum current into the
ΔVOUT ≈ ΔIL ESR + 
 8 • f • COUT  RUN pin does not exceed 100μA.

where f is the operating frequency, COUT is the output The RUN pin can be implemented as a UVLO by connecting
capacitance and ΔIL is the ripple current in the inductor. it to the output of an external resistor divider network off
The output ripple is highest at maximum input voltage VIN, as shown in Figure 4.
since ΔIL increases with input voltage.
VIN

Setting Output Voltage LTC3891 RB

The LTC3891 output voltage is set by an external feed- RUN

back resistor divider carefully placed across the output, RA

as shown in Figure 3. The regulated output voltage is 3891 F04

determined by: Figure 4. Using the RUN Pin as a UVLO

 R 
VOUT = 0.8V 1+ B 
 RA 
3891fa

18
 LTC3891
APPLICATIONS INFORMATION
The rising and falling UVLO thresholds are calculated using pin of the slave supply (VOUT), as shown in Figure 7.
the RUN pin thresholds: During start-up VOUT will track VX according to the ratio
 R  set by the resistor divider:
VUVLO(RISING) = 1.21V 1+ B 
 RA  VX RA R + RTRACKB
= • TRACKA
VOUT RTRACKA RA + RB
 R 
VUVLO(FALLING) = 1.16V 1+ B 
 RA  For coincident tracking (VOUT = VX during start-up):

The resistor values should be carefully chosen such that RA = RTRACKA

the absolute maximum ratings of the RUN pin do not get RB = RTRACKB
violated over the entire VIN voltage range.
VX(MASTER)
Tracking and Soft-Start (TRACK/SS Pin)

OUTPUT VOLTAGE
The start-up of VOUT is controlled by the voltage on the
TRACK/SS pin. When the voltage on the TRACK/SS pin is
less than the internal 0.8V reference, the LTC3891 regulates VOUT(SLAVE)

the VFB pin voltage to the voltage on the TRACK/SS pin

instead of 0.8V. The TRACK/SS pin can be used to program
an external soft-start function or to allow VOUT to track
another supply during start-up. TIME
3891 F06a

Soft-start is enabled by simply connecting a capacitor (6a) Coincident Tracking

from the TRACK/SS pin to ground, as shown in Figure 5.
An internal 10μA current source charges the capacitor, VX(MASTER)

providing a linear ramping voltage at the TRACK/SS pin.

OUTPUT VOLTAGE

The LTC3891 will regulate the VFB pin (and hence VOUT)
according to the voltage on the TRACK/SS pin, allowing
VOUT to rise smoothly from 0V to its final regulated value. VOUT(SLAVE)

The total soft-start time will be approximately:

0.8V
t SS = CSS • 3891 F06b

10µA TIME

(6b) Ratiometric Tracking

Figure 6. Two Different Modes of Output Voltage Tracking
LTC3891
TRACK/SS
CSS Vx VOUT
SGND
RB LTC3891
3891 F05
VFB
RA
Figure 5. Using the TRACK/SS Pin to Program Soft-Start
RTRACKB
TRACK/SS
Alternatively, the TRACK/SS pin can be used to track RTRACKA 3891 F07

another supply during start-up, as shown qualitatively in

Figures 6a and 6b. To do this, a resistor divider should be
Figure 7. Using the TRACK/SS Pin for Tracking
connected from the master supply (VX) to the TRACK/SS
3891fa

19
LTC3891
APPLICATIONS INFORMATION
INTVCC Regulators is less than 5.1V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
The LTC3891 features two separate internal P-channel
is greater than 5.1V, up to an absolute maximum of 14V,
low dropout linear regulators (LDO) that supply power
INTVCC is regulated to 5.1V.
at the INTVCC pin from either the VIN supply pin or the
EXTVCC pin depending on the connection of the EXTVCC Using the EXTVCC LDO allows the MOSFET driver and control
pin. INTVCC powers the gate drivers and much of the power to be derived from one of the LTC3891’s switching
LTC3891’s internal circuitry. The VIN LDO and the EXTVCC regulator outputs (4.7V ≤ VOUT ≤ 14V) during normal
LDO regulate INTVCC to 5.1V. Each of these can supply a operation and from the VIN LDO when the output is out of
peak current of at least 50mA and must be bypassed to regulation (e.g., start-up, short-circuit). If more current
ground with a minimum of 2.2μF ceramic capacitor. No is required through the EXTVCC LDO than is specified, an
matter what type of bulk capacitor is used, an additional external Schottky diode can be added between the EXTVCC
1μF ceramic capacitor placed directly adjacent to the INTVCC and INTVCC pins. In this case, do not apply more than 6V
and PGND pins is highly recommended. Good bypassing to the EXTVCC pin and make sure that EXTVCC ≤ VIN.
is needed to supply the high transient currents required Significant efficiency and thermal gains can be realized by
by the MOSFET gate drivers and to prevent interaction powering INTVCC from the output, since the VIN current
between the channels. resulting from the driver and control currents will be scaled
High input voltage applications in which large MOSFETs are by a factor of (Duty Cycle)/(Switcher Efficiency).
being driven at high frequencies may cause the maximum For 5V to 14V regulator outputs, this means connecting
junction temperature rating for the LTC3891 to be exceeded. the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
The INTVCC current, which is dominated by the gate charge an 8.5V supply reduces the junction temperature in the
current, may be supplied by either the VIN LDO or the
previous example from 125°C to:
EXTVCC LDO. When the voltage on the EXTVCC pin is less
than 4.7V, the VIN LDO is enabled. Power dissipation for the TJ = 70°C + (32mA)(8.5V)(43°C/W) = 82°C
IC in this case is highest and is equal to VIN • IINTVCC. The However, for 3.3V and other low voltage outputs, addi-
gate charge current is dependent on operating frequency tional circuitry is required to derive INTVCC power from
as discussed in the Efficiency Considerations section. the output.
The junction temperature can be estimated by using the
equations given in Note 3 of the Electrical Characteristics. The following list summarizes the four possible connec-
For example, the LTC3891 INTVCC current is limited to less tions for EXTVCC:
than 32mA from a 40V supply when not using the EXTVCC 1. EXTVCC Grounded. This will cause INTVCC to be powered
supply at a 70°C ambient temperature: from the internal 5.1V regulator resulting in an efficiency
TJ = 70°C + (32mA)(40V)(43°C/W for QFN) = 125°C penalty of up to 10% at high input voltages.
To prevent the maximum junction temperature from be- 2. EXTVCC Connected Directly to VOUT. This is the normal
ing exceeded, the input supply current must be checked connection for a 5V to 14V regulator and provides the
while operating in forced continuous mode (PLLIN/MODE highest efficiency.
= INTVCC) at maximum VIN. 3. EXTVCC Connected to an External Supply. If an external
When the voltage applied to EXTVCC rises above 4.7V, the supply is available in the 5V to 14V range, it may be
VIN LDO is turned off and the EXTVCC LDO is enabled. The used to power EXTVCC providing it is compatible with
EXTVCC LDO remains on as long as the voltage applied to the MOSFET gate drive requirements. Ensure that
EXTVCC remains above 4.5V. The EXTVCC LDO attempts EXTVCC < VIN.
to regulate the INTVCC voltage to 5.1V, so while EXTVCC

3891fa

20
 LTC3891
APPLICATIONS INFORMATION
4. EXTVCC Connected to an Output-Derived Boost Network. Fault Conditions: Current Limit and Current Foldback
For 3.3V and other low voltage regulators, efficiency The LTC3891 includes current foldback to help limit load
gains can still be realized by connecting EXTVCC to an current when the output is shorted to ground. If the output
output-derived voltage that has been boosted to greater voltage falls below 70% of its nominal output level, then
than 4.7V. This can be done with the capacitive charge the maximum sense voltage is progressively lowered from
pump shown in Figure 8. Ensure that EXTVCC < VIN. 100% to 45% of its maximum selected value. Under short-
circuit conditions with very low duty cycles, the LTC3891
will begin cycle skipping in order to limit the short-circuit
CIN current. In this situation the bottom MOSFET will be dis-
BAT85 BAT85 sipating most of the power but less than in normal opera-
VIN
tion. The short-circuit ripple current is determined by the
MTOP
NDS7002 BAT85 minimum on-time, tON(MIN), of the LTC3891 (≈95ns), the
TG
LTC3891
input voltage and inductor value:
L RSENSE
EXTVCC SW VOUT
V 
MBOT ΔIL(SC) = tON(MIN)  IN 
BG COUT
 L 

PGND 3891 F08

The resulting average short-circuit current is:

1
Figure 8. Capacitive Charge Pump for EXTVCC ISC = 45% • ILIM(MAX) – DIL(SC)
2

Topside MOSFET Driver Supply (CB, DB) Fault Conditions: Overvoltage Protection (Crowbar)
An external bootstrap capacitor, CB, connected to the The overvoltage crowbar is designed to blow a system
BOOST pin supplies the gate drive voltage for the topside input fuse when the output voltage of the regulator rises
MOSFET. Capacitor CB in the Functional Diagram is charged much higher than nominal levels. The crowbar causes huge
though external diode DB from INTVCC when the SW pin currents to flow, that blow the fuse to protect against a
is low. When the topside MOSFET is to be turned on, the shorted top MOSFET if the short occurs while the control-
driver places the CB voltage across the gate-source of ler is operating.
the MOSFET. This enhances the top MOSFET switch and
A comparator monitors the output for overvoltage condi-
turns it on. The switch node voltage, SW, rises to VIN and
tions. The comparator detects faults greater than 10%
the BOOST pin follows. With the topside MOSFET on, the
above the nominal output voltage. When this condition
boost voltage is above the input supply: VBOOST = VIN +
is sensed, the top MOSFET is turned off and the bottom
VINTVCC. The value of the boost capacitor, CB, needs to be
MOSFET is turned on until the overvoltage condition is
100 times that of the total input capacitance of the top-
cleared. The bottom MOSFET remains on continuously
side MOSFET(s). The reverse breakdown of the external
for as long as the overvoltage condition persists; if VOUT
Schottky diode must be greater than VIN(MAX).
returns to a safe level, normal operation automatically
When adjusting the gate drive level, the final arbiter is the resumes.
total input current for the regulator. If a change is made
A shorted top MOSFET will result in a high current condition
and the input current decreases, then the efficiency has
which will open the system fuse. The switching regulator
improved. If there is no change in input current, then there
will regulate properly with a leaky top MOSFET by altering
is no change in efficiency.
the duty cycle to accommodate the leakage.
3891fa

21
LTC3891
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
The LTC3891 has an internal phase-locked loop (PLL)
frequency be near external clock frequency, doing so will
comprised of a phase frequency detector, a lowpass filter,
prevent the operating frequency from passing through a
and a voltage-controlled oscillator (VCO). This allows the
large range of frequencies as the PLL locks.
turn-on of the top MOSFET to be locked to the rising edge
of an external clock signal applied to the PLLIN/MODE pin.
1000
The phase detector is an edge sensitive digital type that
900
provides zero degrees phase shift between the external 800
and internal oscillators. This type of phase detector does 700
not exhibit false lock to harmonics of the external clock.

FREQUENCY (kHz)
600

If the external clock frequency is greater than the inter- 500

nal oscillator’s frequency, fOSC, then current is sourced 400

continuously from the phase detector output, pulling up 300

200
the VCO input. When the external clock frequency is less
100
than fOSC, current is sunk continuously, pulling down the
0
VCO input. 15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
If the external and internal frequencies are the same but 3891 F09

exhibit a phase difference, the current sources turn on for Figure 9. Relationship Between Oscillator Frequency and
an amount of time corresponding to the phase difference. Resistor Value at the FREQ Pin
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are Table 2 summarizes the different states in which the FREQ
identical. At the stable operating point, the phase detector pin can be used.
output is high impedance and the internal filter capacitor,
Table 2
CLP, holds the voltage at the VCO input.
FREQ PIN PLLIN/MODE PIN FREQUENCY
Note that the LTC3891 can only be synchronized to an 0V DC Voltage 350kHz
external clock whose frequency is within range of the INTVCC DC Voltage 535kHz
LTC3891’s internal VCO, which is nominally 55kHz to Resistor DC Voltage 50kHz to 900kHz
900kHz. Any of the Above External Clock Phase Locked to
External Clock
This is guaranteed to be between 75kHz and 750kHz. Typi-
cally, the external clock (on the PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.1V.
Minimum On-Time Considerations
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro- Minimum on-time, tON(MIN), is the smallest time duration
nization frequency. The VCO’s input voltage is prebiased that the LTC3891 is capable of turning on the top MOSFET.
at a frequency corresponding to the frequency set by the It is determined by internal timing delays and the gate
FREQ pin. Once prebiased, the PLL only needs to adjust

3891fa

22
 LTC3891
APPLICATIONS INFORMATION
charge required to turn on the top MOSFET. Low duty MOSFETs. Each time a MOSFET gate is switched from
cycle applications may approach this minimum on-time low to high to low again, a packet of charge, dQ, moves
limit and care should be taken to ensure that: from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
VOUT control circuit current. In continuous mode, IGATECHG
tON(MIN) <
VIN ( f ) = f(QT + QB), where QT and QB are the gate charges of

the topside and bottom side MOSFETs.
If the duty cycle falls below what can be accommodated Supplying INTVCC from an output-derived source power
by the minimum on-time, the controller will begin to skip through EXTVCC will scale the VIN current required
cycles. The output voltage will continue to be regulated, for the driver and control circuits by a factor of (Duty
but the ripple voltage and current will increase. Cycle)/(Efficiency). For example, in a 20V to 5V applica-
The minimum on-time for the LTC3891 is approximately tion, 10mA of INTVCC current results in approximately
95ns. However, as the peak sense voltage decreases the 2.5mA of VIN current. This reduces the midcurrent loss
minimum on-time gradually increases up to about 130ns. from 10% or more (if the driver was powered directly
This is of particular concern in forced continuous applica- from VIN) to only a few percent.
tions with low ripple current at light loads. If the duty cycle 3. I2R losses are predicted from the DC resistances of the
drops below the minimum on-time limit in this situation, fuse (if used), MOSFET, inductor, current sense resis-
a significant amount of cycle skipping can occur with cor- tor and input and output capacitor ESR. In continuous
respondingly larger current and voltage ripple. mode the average output current flows through L and
RSENSE, but is chopped between the topside MOSFET
Efficiency Considerations
and the synchronous MOSFET. If the two MOSFETs have
The percent efficiency of a switching regulator is equal to approximately the same RDS(ON), then the resistance
the output power divided by the input power times 100%. of one MOSFET can simply be summed with the resis-
It is often useful to analyze individual losses to determine tances of L, RSENSE and ESR to obtain I2R losses. For
what is limiting the efficiency and which change would example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE
produce the most improvement. Percent efficiency can = 10mΩ and RESR = 40mΩ (sum of both input and
be expressed as: output capacitance losses), then the total resistance
%Efficiency = 100% – (L1 + L2 + L3 + ...) is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
where L1, L2, etc. are the individual losses as a percent- a 5V output, or a 4% to 20% loss for a 3.3V output.
age of input power. Efficiency varies as the inverse square of VOUT for the
Although all dissipative elements in the circuit produce same external components and output power level. The
losses, four main sources usually account for most of the combined effects of increasingly lower output voltages
losses in LTC3891 circuits: 1) IC VIN current, 2) INTVCC and higher currents required by high performance digital
regulator current, 3) I2R losses, 4) topside MOSFET systems is not doubling but quadrupling the importance
transition losses. of loss terms in the switching regulator system!
1. The VIN current is the DC supply current given in the 4. Transition losses apply only to the topside MOSFET(s),
Electrical Characteristics table, which excludes MOSFET and become significant only when operating at high
driver and control currents. VIN current typically results input voltages (typically 15V or greater). Transition
in a small (<0.1%) loss. losses can be estimated from:
2. INTVCC current is the sum of the MOSFET driver and Transition Loss = (1.7) • VIN • 2 • IO(MAX) • CRSS • f
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
3891fa

23
LTC3891
APPLICATIONS INFORMATION
Other hidden losses such as copper trace and internal have been determined. The output capacitors need to be
battery resistances can account for an additional 5% selected because the various types and values determine
to 10% efficiency degradation in portable systems. It the loop gain and phase. An output current pulse of 20%
is very important to include these system level losses to 80% of full-load current having a rise time of 1μs to
during the design phase. The internal battery and fuse 10μs will produce output voltage and ITH pin waveforms
resistance losses can be minimized by making sure that that will give a sense of the overall loop stability without
CIN has adequate charge storage and very low ESR at breaking the feedback loop.
the switching frequency. A 25W supply will typically
Placing a power MOSFET directly across the output
require a minimum of 20μF to 40μF of capacitance
capacitor and driving the gate with an appropriate signal
having a maximum of 20mΩ to 50mΩ of ESR. Other
generator is a practical way to produce a realistic load step
losses including body diode conduction losses during
condition. The initial output voltage step resulting from
dead-time and inductor core losses generally account
the step change in output current may not be within the
for less than 2% total additional loss.
bandwidth of the feedback loop, so this signal cannot be
Checking Transient Response used to determine phase margin. This is why it is better to
look at the ITH pin signal which is in the feedback loop and
The regulator loop response can be checked by looking at is the filtered and compensated control loop response.
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive) The gain of the loop will be increased by increasing RC
load current. When a load step occurs, VOUT shifts by an and the bandwidth of the loop will be increased by de-
amount equal to ΔILOAD (ESR), where ESR is the effective creasing CC. If RC is increased by the same factor that
series resistance of COUT. ΔILOAD also begins to charge or CC is decreased, the zero frequency will be kept the same,
discharge COUT generating the feedback error signal that thereby keeping the phase shift the same in the most
forces the regulator to adapt to the current change and critical frequency range of the feedback loop. The output
return VOUT to its steady-state value. During this recov- voltage settling behavior is related to the stability of the
ery time VOUT can be monitored for excessive overshoot closed-loop system and will demonstrate the actual overall
or ringing, which would indicate a stability problem. supply performance.
OPTI-LOOP compensation allows the transient response A second, more severe transient is caused by switching
to be optimized over a wide range of output capacitance in loads with large (>1μF) supply bypass capacitors. The
and ESR values. The availability of the ITH pin not only discharged bypass capacitors are effectively put in parallel
allows optimization of control loop behavior, but it also with COUT, causing a rapid drop in VOUT. No regulator can
provides a DC coupled and AC filtered closed-loop response alter its delivery of current quickly enough to prevent this
test point. The DC step, rise time and settling at this test sudden step change in output voltage if the load switch
point truly reflects the closed-loop response. Assuming a resistance is low and it is driven quickly. If the ratio of
predominantly second order system, phase margin and/or CLOAD to COUT is greater than 1:50, the switch rise time
damping factor can be estimated using the percentage of should be controlled so that the load rise time is limited
overshoot seen at this pin. The bandwidth can also be to approximately 25 • CLOAD. Thus a 10μF capacitor would
estimated by examining the rise time at the pin. The ITH require a 250μs rise time, limiting the charging current
external components shown in Figure 10 circuit will provide to about 200mA.
an adequate starting point for most applications. Design Example
The ITH series RC-CC filter sets the dominant pole-zero As a design example, assume VIN = 12V (nominal),
loop compensation. The values can be modified slightly VIN = 22V (max), VOUT = 3.3V, IMAX = 5A, VSENSE(MAX)
to optimize transient response once the final PC layout is = 75mV and f = 350kHz. The inductance value
done and the particular output capacitor type and value is chosen first based on a 30% ripple current
3891fa

24
 LTC3891
APPLICATIONS INFORMATION
assumption. The highest value of ripple current occurs A short-circuit to ground will result in a folded back cur-
at the maximum input voltage. Tie the FREQ pin to GND, rent of:
generating 350kHz operation. The minimum inductance
for 30% ripple current is: 34mV 1  95ns (22V ) 
ISC = – = 3.18A
0.01Ω 2  4.7µH 
VOUT  V 
ΔIL = 1– OUT 

( f) (L)  VIN(NOM)  with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
A 4.7μH inductor will produce 29% ripple current. The MOSFET is:
peak inductor current will be the maximum DC value plus
PSYNC = (3.28A ) (1.125) (0.022Ω)
2
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time = 250mW

of 95ns is not violated. The minimum on-time occurs at
maximum VIN: which is less than under full-load conditions. CIN is chosen
for an RMS current rating of at least 3A at temperature
VOUT 3.3V assuming only this channel is on. COUT is chosen with an
tON(MIN) = = = 429ns
VIN(MAX) ( f) 22V (350kHz ) ESR of 0.02Ω for low output ripple. The output ripple in

continuous mode will be highest at the maximum input
The equivalent RSENSE resistor value can be calculated by voltage. The output voltage ripple due to ESR is approxi-
using the minimum value for the maximum current sense mately:
threshold (64mV): VORIPPLE = RESR(DIL) = 0.02Ω(1.45A) = 29mVP-P

64mV PC Board Layout Checklist

RSENSE ≤ ≈ 0.01Ω
5.73A When laying out the printed circuit board, the following
Choosing 1% resistors: RA = 25k and RB = 78.7k yields checklist should be used to ensure proper operation of
an output voltage of 3.32V. the IC.

The power dissipation on the topside MOSFET can be easily Check the following in your layout:
estimated. Choosing a Fairchild FDS6982S dual MOSFET 1. Are the signal and power grounds kept separate? The
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At combined IC signal ground pin and the ground return
maximum input voltage with T(estimated) = 50°C: of CINTVCC must return to the combined COUT (–) ter-
minals. The path formed by the top N-channel MOSFET,
3.3V
( 5A ) 1+ (0.005) (50°C – 25°C)
2
PMAIN = Schottky diode and the CIN capacitor should have short
22V leads and PC trace lengths. The output capacitor (–)
(0.035Ω) + (22V) 5A2 (2.5Ω) (215pF ) • terminals should be connected as close as possible
2
to the (–) terminals of the input capacitor by placing
 1 1  the capacitors next to each other and away from the
 +  (350kHz ) = 331mW Schottky loop described above.
 5V – 2.3V 2.3V 
2. Does the LTC3891 VFB pin’s resistive divider connect to
the (+) terminal of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
3891fa

25
LTC3891
APPLICATIONS INFORMATION
3. Are the SENSE– and SENSE+ leads routed together with gest noise pickup at the current or voltage sensing inputs
minimum PC trace spacing? The filter capacitor between or inadequate loop compensation. Overcompensation of
SENSE+ and SENSE– should be as close as possible the loop can be used to tame a poor PC layout if regulator
to the IC. Ensure accurate current sensing with Kelvin bandwidth optimization is not required.
connections at the SENSE resistor.
Reduce VIN from its nominal level to verify operation
4. Is the INTVCC decoupling capacitor connected close of the regulator in dropout. Check the operation of the
to the IC, between the INTVCC and the power ground undervoltage lockout circuit by further lowering VIN while
pins? This capacitor carries the MOSFET drivers’ cur- monitoring the outputs to verify operation.
rent peaks. An additional 1μF ceramic capacitor placed Investigate whether any problems exist only at higher out-
immediately next to the INTVCC and PGND pins can help put currents or only at higher input voltages. If problems
improve noise performance substantially.
coincide with high input voltages and low output currents,
5. Keep the SW, TG, and BOOST nodes away from sensitive look for capacitive coupling between the BOOST, SW, TG,
small-signal nodes. All of these nodes have very large and possibly BG connections and the sensitive voltage
and fast moving signals and therefore should be kept and current pins. The capacitor placed across the current
on the output side of the LTC3891 and occupy minimum sensing pins needs to be placed immediately adjacent to
PC trace area. the pins of the IC. This capacitor helps to minimize the
6. Use a modified star ground technique: a low impedance, effects of differential noise injection due to high frequency
large copper area central grounding point on the same capacitive coupling. If problems are encountered with
side of the PC board as the input and output capacitors high current output loading at lower input voltages, look
with tie-ins for the bottom of the INTVCC decoupling for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
capacitor, the bottom of the voltage feedback resistive
sensing traces. In addition, investigate common ground
divider and the SGND pin of the IC.
path voltage pickup between these components and the
PC Board Layout Debugging SGND pin of the IC.

It is helpful to use a DC-50MHz current probe to monitor An embarrassing problem, which can be missed in an
the current in the inductor while testing the circuit. Monitor otherwise properly working switching regulator, results
the output switching node (SW pin) to synchronize the when the current sensing leads are hooked up backwards.
oscilloscope to the internal oscillator and probe the actual The output voltage under this improper hookup will still
output voltage as well. Check for proper performance over be maintained but the advantages of current mode control
the operating voltage and current range expected in the will not be realized. Compensation of the voltage loop will
application. The frequency of operation should be main- be much more sensitive to component selection. This
tained over the input voltage range down to dropout and behavior can be investigated by temporarily shorting out
until the output load drops below the low current opera- the current sensing resistor—don’t worry, the regulator
tion threshold—typically 25% of the maximum designed will still maintain control of the output voltage.
current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-

3891fa

26
 LTC3891
APPLICATIONS INFORMATION

ILIM
LTC3891
VIN VIN
TRACK/SS
PGND
FREQ CIN
GND

+
PLLIN/MODE

SGND EXTVCC CINTVCC 1µF

CERAMIC COUT
SGND INTVCC

+
RUN BG

SENSE– M1 M2
C1* BOOST D1*
SENSE+
SW
R1* L1 RSENSE
VOUT
VFB TG ROUT
VPULL-UP
ITH PGOOD PGOOD

3891 F10
*R1, C1 AND D1 ARE OPTIONAL

Figure 10. Recommended Printed Circuit Layout Diagram

L1 RSENSE
VIN SW VOUT

RIN
CIN
D1 COUT RL1

3891 F11

BOLD LINES INDICATE HIGH SWITCHING

CURRENT. KEEP LINES TO A MINIMUM LENGTH.

Figure 11. Branch Current Waveforms

3891fa

27
LTC3891
APPLICATIONS INFORMATION

VIN
4V TO 60V
CIN
22µF VIN INTVCC
100k LTC3891 2.2µF
INTVCC PGOOD
PGND
RUN

ILIM D1
EXTVCC TG MTOP
0.1µF
PLLIN/MODE BOOST L1 RSENSE
41.2k 4.7µH 8mΩ VOUT
FREQ SW 3.3V
2200pF COUT
10k BG MBOT 5A
150µF
ITH
100pF

SENSE+
0.1µF
1nF
TRACK/SS SENSE– 100k
SGND
VFB
SGND
31.6k

MTOP, MBOT: Si7850DP 3891 F12

L1 COILCRAFT SER1360-472KL
COUT: SANYO 6TPE470M
D1: DFLS1100

Figure 12. High Efficiency 3.3V Step-Down Converter

VIN
12.5V TO 60V
CIN
22µF VIN INTVCC
100k LTC3891 2.2µF
INTVCC PGOOD
PGND
RUN

ILIM D1
VOUT EXTVCC TG MTOP
0.1µF
PLLIN/MODE BOOST L1 RSENSE
8µH 9mΩ VOUT
FREQ SW 12V
470pF COUT
34.8k BG MBOT 3A
180µF
ITH
100pF

SENSE+
0.1µF
1nF
TRACK/SS SENSE– 100k
SGND
VFB
SGND
6.98k

3891 F13
MTOP, MBOT: BSC100N06LS3
L1 COILCRAFT SER1360-802KL
COUT: SANYO 16SVP180MX
D1: DFLS1100

Figure 13. High Efficiency 12V Step-Down Converter

3891fa

28
 LTC3891
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)

0.70 ±0.05

3.50 ±0.05
2.10 ±0.05 2.65 ±0.05
1.50 REF
1.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ±0.05
4.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.25
0.75 ±0.05
1.50 REF × 45° CHAMFER
3.00 ±0.10 R = 0.05 TYP
19 20
0.40 ±0.10

PIN 1 1
TOP MARK 2
(NOTE 6)
2.65 ±0.10
4.00 ±0.10 2.50 REF
1.65 ±0.10

(UDC20) QFN 1106 REV Ø

0.200 REF 0.25 ±0.05

R = 0.115
0.00 – 0.05 TYP 0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

3891fa

29
LTC3891
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CB

6.40 – 6.60*
3.86 (.252 – .260)
(.152) 3.86
(.152)
20 1918 17 16 15 14 13 12 11

6.60 ±0.10
2.74
4.50 ±0.10 (.108)
6.40
SEE NOTE 4 2.74 (.252)
(.108) BSC
0.45 ±0.05

1.05 ±0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV I 0211
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3891fa

30
 LTC3891
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/12 Added INTVCC to Absolute Maximum Ratings 2
Updated FE package 30

3891fa

31
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3891
TYPICAL APPLICATION

VIN
9V TO 60V
CIN
22µF VIN INTVCC
100k LTC3891 2.2µF
INTVCC PGOOD
PGND
RUN

ILIM D1
VOUT EXTVCC TG MTOP
0.1µF
PLLIN/MODE BOOST L1 RSENSE
8µH 10mΩ VOUT
FREQ SW 8.5V
470pF COUT
34.8k BG MBOT 3A
330µF
ITH

SENSE+
0.1µF
1nF
TRACK/SS SENSE– 100k
SGND
VFB
SGND
10.5k

3891 F14
MTOP, MBOT: Si7850DP
L1 COILCRAFT SER1360-802KL
COUT: SANYO 10TPE330M
D1: DFLS1100

Figure 14. High Efficiency 8.5V Step-Down Converter

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC3890/LTC3890-1 60V, Low IQ, Dual Output 2-Phase Synchronous Step- Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
Down DC/DC Controller 0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LTC3857/LTC3857-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V,
DC/DC Controllers with 99% Duty Cycle 0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LTC3858/LTC3858-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V,
DC/DC Controllers with 99% Duty Cycle 0.8V ≤ VOUT ≤ 24V, IQ = 170µA
LTC3868/LTC3868-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 24V,
DC/DC Controller with 99% Duty Cycle 0.8V ≤ VOUT ≤ 14V, IQ = 170µA
LTC3834/LTC3834-1 Low IQ, Single Output Synchronous Step-Down DC/DC Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ VIN ≤ 36V,
Controller with 99% Duty Cycle 0.8V ≤ VOUT ≤ 10V, IQ = 30µA
LTC3835/LTC3835-1 Low IQ, Single Output Synchronous Step-Down DC/DC Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ VIN ≤ 36V,
Controller with 99% Duty Cycle 0.8V ≤ VOUT ≤ 10V, IQ = 80µA
LT3845A 60V, Low IQ, Single Output Synchronous Step-Down Adjustable Fixed Frequency 100kHz to 500kHz, 4V ≤ VIN ≤ 60V,
DC/DC Controller 1.23V ≤ VOUT ≤ 36V, IQ = 120µA
LTC3859 Low IQ, Triple Output Buck/Buck/Boost Synchronous Outputs ≥ 4V Remain in Regulation Through Cold Crank, 2.5V ≤ VIN
DC/DC Controller ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 55µA
LTC3824 Low IQ, Single Output Step-Down Controller, 100% Fixed 200kHz to 600kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ VIN, IQ = 40µA,
Duty Cycle MSOP-10E

3891fa

32 Linear Technology Corporation

LT 1012 REV A • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2010