Scribd
Upload
118 views2 pages

Switching Theory and Logic Design (CSE-203) (Makeup)

This document appears to be an exam for a course on switching theory and logic design. It contains 6 questions with multiple parts each. Question 1 deals with combinational logic circuits including a truth table, K-maps, and logic expressions. Question 2 covers Boolean algebra theorems and uses K-maps to simplify logic expressions. Question 3 involves binary subtraction, VHDL code for a full adder and multiplier, and diagram of a carry lookahead adder. Question 4 covers priority encoders, decoders, and multiplexers. Question 5 discusses shift registers, JK flip-flops, and ripple counters. Question 6 briefly explains up-down counters and Schottky TTL and asks to design a mod-5 synchronous

Uploaded by

Random Shit
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
118 views2 pages

Switching Theory and Logic Design (CSE-203) (Makeup)

This document appears to be an exam for a course on switching theory and logic design. It contains 6 questions with multiple parts each. Question 1 deals with combinational logic circuits including a truth table, K-maps, and logic expressions. Question 2 covers Boolean algebra theorems and uses K-maps to simplify logic expressions. Question 3 involves binary subtraction, VHDL code for a full adder and multiplier, and diagram of a carry lookahead adder. Question 4 covers priority encoders, decoders, and multiplexers. Question 5 discusses shift registers, JK flip-flops, and ripple counters. Question 6 briefly explains up-down counters and Schottky TTL and asks to design a mod-5 synchronous

Uploaded by

Random Shit
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

REG.

NO

MANIPAL INSTITUTE OF TECHNOLOGY


(Constituent Institute of Manipal University)
MANIPAL-576104

III SEMESTER B.TECH.(COMPUTER SCIENCE AND ENGINEERING) DEGREE


END-SEMESTER EXAMINATION-JANUARY 2015
SUBJECT: SWITCHING THEORY AND LOGIC DESIGN (CSE 203)
DATE: 01-01-2015
TIME: 3 HOURS MAX.MARKS: 50

Instructions to Candidates
 Note: Answer any FIVE full questions.
 All inputs are available in un complimented form.

1A. If N1 and N2 are two bit binary number(N1=AB & N2=CD where A,B,C,D are
bits),which are the input of a combinational circuit. Then three outputs of the circuits are
LT= (AB<CD),EQ=(AB=CD) & GT=(AB>CD).
(i) Write the truth table for the above.
(ii) Derive the simplest expression for LT, EQ and GT using K-MAP. 2 marks
1B. Design the simplest POS circuit that implements the function G=A’BC+EF+DEF’
using algebraic manipulation. Show the construction of the circuit using
(i) Basic gates (ii) Only NAND gate with a fan in constrain of 2. 3 marks
1C. (i)Define (a) implicant (b) cover (c) minterm (d) essential prime implicant.
(ii)Simplify using K map. Write the prime implicants & essential prime implicants for the
following function. f(a, b, c, d) = ∑m(1,3, 4,5, 9, 11, 12, 13,14, 15). 5 marks

2 A. Prove the following equations using the Boolean algebraic theorems:


(i) A + A’B + A B’ = A + B (ii) A’BC + A B’ C + ABC’ + ABC = AB + BC + AC
(1+2) marks
2 B. Simplify the given expression to its minimal POS form and SOP form using K-maps
and realize using NAND and NOR gates. Which among this is the least cost
implementation. (Assume that there is no fan-in constraint & inputs are available in
uncomplimentary form only).
F(A,B,C,D) =∑m(1,3,5,8,9,11,15) +d(2,13) 5 marks
2 C. Design a minimum cost combined circuit that implement the following functions as a
multiple output circuit. Draw the resultant circuit diagram.
F1 =(X1+X2)X3X4+X1’X2’(X3+X4) F2’=X1’X2’+X3’X4’ 2 marks

3 A. Perform the following subtractions using 2’s complement method. Write the result in
both binary and decimal.
(i) 01000 – 01001 (ii) 01100 – 00011 2 marks
3 B. Write VHDL code for full adder. Using this as a component write the VHDL code for
3- bit multiplier 3 marks

CSE 203 Page 1 of 2


3 C. (i) Draw the circuit diagram of a 4 bit hierarchical carry look adder built using 2 bit
carry look ahead adder blocks.Write down all the expression of the circuit.
(ii) Explain the working of n-bit adder/subtractor unit with a diagram. 2+3 marks
4 A.(i) Design a logic circuit to implement an 8-to-3 priority encoder. 2 marks
(ii)Write the hierarchical code for 4-to-16 binary decoder using FOR GENERATE
and IF GENERATE statements. 3 marks
4 B. Implement the following function using 8 to 1 multiplexer.
Y(A,B,C,D) =∑(0,1,2,5,9,11,13,15). 3 marks
4 C. Decompose the given expression f=w1w2+w1’w3’+w1w3 using Shannon’s
expansion with respect to w1 & w3 so that it can be implemented using 4:1 multiplexer.
2marks

5 A.Using D-Flip flops explain the working of a 4-bit serial-in-serial-out shift register.
For a given input ‘1010’,show the output of each flip-flop for given continuous four
clock period of the Fig.5A.

Fig.5A 3marks

5 B. With relevant diagram explain the working of clocked master-slave JK flip flop
constructed using NAND gates. 5marks

5 C.(i)Write the excitation table of RS & JK flip-flops.


(ii) Draw the circuit diagram for 3-bit binary ripple counter using T-flipflop.Draw
the output waveform of all the three T flipflops(Q0,Q1 & Q3),which is triggered during
negative –going transition of 10 continuous clock pulses. 2 marks

6 A. Briefly explain the following.


(i) Synchronous 4 bit binary up down counter.
(ii)SchottkyTTL. 3+2 marks
6 B. What are synchronous counters? Design a Mod-5 synchronous counter using J-K
Flip-Flops. 5 marks

CSE 203 Page 2 of 2

You might also like