BCA: 3
BCA-S203: Computer Architecture & Assembly Language
Dr. Aditya Kumar Gupta
Associate Professor
Unit – II
General Register Organization
In programming the memory location is needed for storing pointers, counters, return address,
temporary address and partial products during multiplication etc., Having to refer to memory
locations for such applications is time consuming. It is more convenient and more efficient to store
these intermediate values in process register, that are connected through a common bus system. The
register communicates with each other for transferring data as well as foe executing microoperations.
Register organization show how registers are selected and how data flow between register and
ALU. A decoder is used to select a particular register. The output of each register is connected to
two multiplexers to form the two buses A and B. The selection lines in each multiplexer select the
input data for the particular bus. The A and B buses form the two inputs of an ALU. The operation
select lines decide the micro operation to be performed by ALU. The result of the micro operation is
available at the output bus. The output bus connected to the inputs of all registers, thus by selecting a
destination register it is possible to store the result in it. When we are using multiple general purpose
registers, instead of single accumulator register, in the CPU Organization then this type of
organization is known as General register based CPU Organization. In this type of organization,
computer uses two or three address fields in their instruction format. Each address field may specify
a general register or a memory word. If many CPU registers are available for heavily used variables
and intermediate results, we can avoid memory references much of the time, thus vastly increasing
program execution speed, and reducing program size.
The control unit that operates the CPU bus system directs the information flow through the registers
and ALU by selecting the various components in the system. For example, to perform the operation
R1 R2+ R3
The control must provide selection variables to the following selector inputs.
1. MUX A Select (SEL A): to place the content of R2 into bus A.
2. MUX B select (SEL B): to place the content of R3 into bus B.
3. ALU operation select (OPR): to provide the arithmetic addition A + B
4. Decoder destination select (SEL D): to transfer the content of the output bus into R1.
BCA-S203: Computer Architecture & Assembly Language
Figure: A bus organization for seven CPU register
EXAMPLE:
Let us repeat the above example once more, with assembly code instruction. The operation
R3 <= R1+R2
We have to provide following binary selection variable to the select inputs.
1. SEL A: 001 -To place the contents of R1 into bus A.
2. SEL B: 010 - To place the contents of R2 into bus B
3. SEL OPR: 10010 – To perform the arithmetic addition A+B
4. SEL D: 011 – To place the result available on output bus in R3.
BCA-S203: Computer Architecture & Assembly Language
Binary code SELA SELB SEL D
000 Input Input ---
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
Table: Register and multiplexer input selection code
Control Word
There are 14 binary selection inputs in the unit, and their combine value specifies a control word.
The 14-bit word is consisting four fields. The combined value of a binary selection inputs specifies
the control word. It consists of four fields SELA, SELB, and SELD contains three bit each and
SELOPR field contains five bits thus the total bits in the control word are 14-bits.
Format of Control Word
SEL A SELB SELD SELOPR
1. The three bit of SELA select a source registers of the a input of the ALU.
2. The three bits of SELB select a source registers of the b input of the ALU.
3. The three bits of SELED select a destination register using the decoder.
4. The four bits of SELOPR select the operation to be performed by ALU
BCA-S203: Computer Architecture & Assembly Language
CONTROL WORD FOR OPERATION R2 = R1+R3
SEL- D
OR SEL -
SEL A SEL B SEL- REG OPR
001 011 010 0010
Figure: Control words for all micro operation are stored in the control memory
Advantages of General Register Based CPU Organization:
Efficiency of CPU increases as there are large number of registers are used in this
organization.
Less memory space is used to store the program since the instructions are written in compact
way.
Disadvantages of General Register Based CPU Organization:
Care should be taken to avoid unnecessary usage of registers. Thus, compilers need to be
more intelligent in this aspect.
Since large number of registers are used, thus extra cost is required in this organization.
General register CPU Organisation of Two Type:
1. Register-Memory Reference Architecture (CPU with less register)
In this organisation Source 1 is always required in register, source 2 can be present either in
register or in memory. Here two address instruction format is the compatible instruction
format.
2. Register-Register Reference Architecture (CPU with more register)
In this organisation ALU operations are performed only on a register data. So operands are
required in the register. After manipulation result is also placed in register. Here three address
instruction format is the compatible instruction format.
BCA-S203: Computer Architecture & Assembly Language
Various Operation Code with symbol
Operation selection
code Operation Symbol
0000 Transfer A TSFA
0001 Increment A INC A
0010 A+B ADD
0011 A-B SUB
0100 Decrement A DEC
0101 A AND B AND
0110 A OR B OR
0111 A XOR B XOR
1000 Complement A COMA
1001 Shift right A SHR
1010 Shift left A SHL
Table: Operation Code with symbol
References: Mano, M. Morris. 1984. Digital Design. Pearson
BCA-S203: Computer Architecture & Assembly Language
