COURSE: Design and Synthesis using Verilog HDL

ASSIGNMENT-1

TOPIC: SYNTHESIS OF COMBINATIONAL LOGIC

Submitted by
Name: Parasa Sivadurgarao
Scholar ID: 21304056

Page 1 of 74
 NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE: Design and Synthesis using Verilog HDL

All questions are compulsory. Draw RTL schematic and construct Truth table wherever
necessary.

ASSIGNMENT-1

TOPIC: SYNTHESIS OF COMBINATIONAL LOGIC

1. Design an 8:1 Multiplexer and 1:4 demultiplexer using both verilog and VHDL codes and
implement in Xilinx.
2. Design and implement verilog and VHDL codes for a 2:4 decoder.
3. Design and implement 8 to 3 encoder (without priority & with priority) using
verilog and VHDL codes.
4. Design and implement 4-bit binary to gray converter using verilog and VHDL codes.
5. Design a 3-bit priority encoder. The input I is 3-bit and the output P is 3-bit. I(0) when high,
has the highest priority, followed by I(1) and I(2).The output P for highest Priority to lowest
is 0, 1 and 2 (decimal), respectively. Construct the truth table, minimize and write verilog
and VHDL codes.
6. Write both verilog and VHDL codes to realize a 4-bit comparator and implement the design
in Xilinx ISE.
7. Design a 4-bit parity generator .The output is 0 for even parity and 1 for odd parity. Write
verilog and VHDL codes and implement it.
8. Write both verilog and VHDL codes to describe the functions of a full Adder using all the
three modeling styles and implement it.
9. Design a 4-bit Full adder with carry Lookahead using verilog and VHDL codes and
implement in Xilinx.
10. Write a model for 32-bit Arithmetic Logic Unit using the schematic diagram shown below.

A1(3:0) Zout(3:0)

B1(3:0)

Opcode (3:0)

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The truth table is shown below:

Operation Opcode A B Zout

A+B 000 1111 0000 00001111
A-B 001 1110 0010 00001100
A or B 010 1111 1000 00001111
A and B 011 1001 1000 00001000
Not A 100 1111 0000 11110000
A1*B1 101 1111 1111 11100001
A nand B 110 1111 0010 11111101
A xor B 111 0000 0100 00000100

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 Solutions
Design an 8:1 Multiplexer and 1:4 demultiplexer using both verilog and VHDL codes
and implement in Xilinx.
8:1 Multiplexer Truth Table :
Inputs Output
S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 Z
0 0 0 X X X X X X X 1 1
0 0 1 X X X X X X 0 X 0
0 1 0 X X X X X 1 X X 1
0 1 1 X X X X 0 X X X 0
1 0 0 X X X 1 X X X X 1
1 0 1 X X 0 X X X X X 0
1 1 0 0 1 X X X X X X 1
1 1 1 X X X X X X X X 0

VHDL Code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_8_1 is
Port ( S : in STD_LOGIC_VECTOR (2 downto 0);
D : in STD_LOGIC_VECTOR (7 downto 0);
Z : out STD_LOGIC);
end mux_8_1;
architecture Behavioral of mux_8_1 is
begin
process(S, D)
begin
case S is
when "000"=> Z <= D(0);
when "001"=> Z <= D(1);
when "010"=> Z <= D(2);
when "011"=> Z <= D(3);
when "100"=> Z <= D(4);
when "101"=> Z <= D(5);
when "110"=> Z <= D(6);

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 when "111"=> Z <= D(7);
when others=> Z <= '0';
end case;
end process;
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux_8_1_tb IS
END mux_8_1_tb;
ARCHITECTURE behavior OF mux_8_1_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux_8_1
PORT(
S : IN std_logic_vector(2 downto 0);
D : IN std_logic_vector(7 downto 0);
Z : OUT std_logic
);
END COMPONENT;
--Inputs
signal S : std_logic_vector(2 downto 0) := (others => '0');
signal D : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Z : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux_8_1 PORT MAP (
S => S,
D => D,
Z => Z
);
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;

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 d<= "10101010";
s<= "000";
wait for 100 ns;
s<= "001";
wait for 100 ns;
s<= "010";
wait for 100 ns;
s<= "011";
wait for 100 ns;
s<= "100";
wait for 100 ns;
s<= "101";
wait for 100 ns;
s<= "110";
wait for 100 ns;
s<= "111";
wait for 100 ns;
end process;
END;
Simulation Result:

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RTL Schematic:

Verilog Code for 8:1 Multiplexer:

module mux(s,d,y);
input [7:0] d;
input [2:0] s;
output reg y;
always @ (d,s)
begin
case(s)
3'b000 : y=d[0];
3'b001 : y=d[1];
3'b010 : y=d[2];
3'b011 : y=d[3];
3'b100 : y=d[4];
3'b101 : y=d[5];
3'b110 : y=d[6];
3'b111 : y=d[7];
default :y=1'b0;
endcase
end
endmodule

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Test Bench for 8:1 Multiplexer:
module mux_tb;
// Inputs
reg [2:0] s;
reg [7:0] d;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux uut (
.s(s),
.d(d),
.y(y)
);
initial begin
// Initialize Inputs
d=8'b10101010;
#100;
s=3'b000;
#100;
s=3'b001;
#100;
s=3'b010;
#100;
s=3'b011;
#100;
s=3'b100;
#100;
s=3'b101;
#100;
s=3'b110;
#100;
s=3'b111;
#100;
end
endmodule

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 Simulation result:

RTL Schematic

1:4 Demultiplexer Truth Table:

Input Selection Line Output
D S1 S0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

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 VHDL Code for 1:4 Demultiplexer:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux_1_4 is
port( D: in STD_LOGIC;
S: in STD_LOGIC_VECTOR (1 DOWNTO 0);
Y: out STD_LOGIC_VECTOR(3 DOWNTO 0));
end demux_1_4;
architecture Behavioral of demux_1_4 is
begin
process (D,S) is
begin
IF D = '1' THEN
if (S= "00") then Y <= "0001";
elsif (S= "01") then Y <= "0010";
elsif (S= "10") then Y <= "0100";
elsif (S= "11") then Y <= "1000";
end if;
else Y<= "0000";
end if;
end process;
end Behavioral;
VHDL Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY DEMUX_1_4_TB IS
END DEMUX_1_4_TB;
ARCHITECTURE behavior OF DEMUX_1_4_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT demux_1_4
PORT(
D : IN std_logic;
S : IN std_logic_vector(1 downto 0);
Y : OUT std_logic_vector(3 downto 0)
);

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 END COMPONENT;
--Inputs
signal D : std_logic := '0';
signal S : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal Y : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: demux_1_4 PORT MAP (
D => D,
S => S,
Y => Y
);
-- Stimulus process
stim_proc: process
begin
D<= '1';
S<="00";
wait for 100 ns;
S<="00";
wait for 100 ns;
S<="01";
wait for 100 ns;
S<="10";
wait for 100 ns;
S<="11";
wait for 100 ns;
end process;
END;

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Simulation Result:

RTL Schematic:

Verilog Code for 1:4 Demultiplexer:

module demux(s,d,y);
input d;
input [1:0] s;
output reg [3:0] y;
always @ (d,s)
begin
case(s)
2'b00 : y[0]=d;
2'b01 : y[1]=d;
2'b10 : y[2]=d;
2'b11 : y[3]=d;
default :y=3'b000;
endcase
end
endmodule

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Test Bench:
module demux_tb;
// Inputs
reg [1:0] s;
reg d;
// Outputs
wire [3:0] y;
// Instantiate the Unit Under Test (UUT)
demux uut (
.s(s),
.d(d),
.y(y)
);
initial begin
// Initialize Inputs
d = 1'b1;
#100;
s = 2'b00;
#100;
s=2'b01;
#100;
s=2'b10;
#100;
s=2'b11;
#100;
end
endmodule
Simulation Result:

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 RTL Schematic:

Design and implement verilog and VHDL codes for a 2:4 decoder.
Truth Table:
Input Output
A1 A0 B3 B2 B1 B0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder_2_4 is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_2_4;
architecture Behavioral of decoder_2_4 is
begin
process(a)
begin
if (a = "00") then b <= "0001";
elsif (a = "01") then b <= "0010";

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elsif (a = "10") then b <= "0100";
else b<= "1000";
end if;
end process;
end Behavioral;
VHDL Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decoder_2_4_tb IS
END decoder_2_4_tb;
ARCHITECTURE behavior OF decoder_2_4_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder_2_4
PORT(
a : IN std_logic_vector(1 downto 0);
b : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal b : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: decoder_2_4 PORT MAP (
a => a,
b => b
);
-- Stimulus process
stim_proc: process
begin
a<="00";
wait for 100 ns;
a<="01";
wait for 100 ns;

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 a<="10";
wait for 100 ns;
a<="11";
wait for 100 ns;
end process;
END;
Simulation Result:

RTL Schematic:

Verilog Code:
module decoder2_to_4( in,out, en);
input [1:0] in;
input en;
output [3:0] out;
reg [3:0] out;
always @( in or en)
begin
if (en)
begin

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 out=4'd0;
case (in)
2'b00: out[0]=1'b1;
2'b01: out[1]=1'b1;
2'b10: out[2]=1'b1;
2'b11: out[3]=1'b1;
default: out=4'd0;
endcase
end
else
out=4'd0;
end
endmodule
Test Bench:
module decoder_tb;
// Inputs
reg [1:0] in;
reg en;
// Outputs
wire [3:0] out;
// Instantiate the Unit Under Test (UUT)
decoder2_to_4 uut (
.in(in),
.out(out),
.en(en)
);
initial begin
// Initialize Inputs
in = 2'b00;
en = 1'b1;
#100;
in = 2'b01;
en = 1'b1;
#100;in = 2'b10;
en = 1'b1;

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 #100;in = 2'b11;
en = 1'b1;
#100;
end
endmodule
Simulation Result:

RTL Schematic:

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Design and implement 8 to 3 encoder (without priority & with priority) using
verilog and VHDL codes.
8 to 3 encoder without Priority Truth Table:
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 E2 E1 E0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ENCODERWITHOUT is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
E : out STD_LOGIC_VECTOR (2 downto 0));
end ENCODERWITHOUT;
architecture Behavioral of ENCODERWITHOUT is
begin
process (D)

begin
if (D = "00000001") then E <= "000";
elsif (D = "00000010") then E <= "001";
elsif (D = "00000100") then E <= "001";
elsif (D = "00001000") then E <= "010";
elsif (D = "00010000") then E <= "100";
elsif (D = "00100000") then E <= "101";
elsif (D = "01000000") then E <= "110";
else E<= "111";
end if;
end process;

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VHDL Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ENCODERWITHOUT_TB IS
END ENCODERWITHOUT_TB;
ARCHITECTURE behavior OF ENCODERWITHOUT_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ENCODERWITHOUT
PORT(
D : IN std_logic_vector(7 downto 0);
E : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal E : std_logic_vector(2 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ENCODERWITHOUT PORT MAP (
D => D,
E => E
);
-- Stimulus process
stim_proc: process
begin
D<="00000001";
wait for 100 ns;
D<="00000010";
wait for 100 ns;
D<="00000100";
wait for 100 ns;
D<="00001000";
wait for 100 ns;
D<="00010000";

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 wait for 100 ns;
D<="00100000";
wait for 100 ns;
D<="01000000";
wait for 100 ns;
D<="10000000";
wait for 100 ns;
wait;
end process;
END;
Simulation Result:

RTL Schematic:

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Verilog Code:
module encoderwithout_v(
input [7:0] D,
output reg[2:0] E
);
always @ ( D)
begin

case (D)
8'b00000001: E = 3'b000;
8'b00000010: E = 3'b001;
8'b00000100: E = 3'b010;
8'b00001000: E = 3'b011;
8'b00010000: E = 3'b100;
8'b00100000: E = 3'b101;
8'b01000000: E = 3'b110;
8'b10000000: E = 3'b111;
endcase
end
Test Bench:
module encoderwithout_v_tb;
// Inputs
reg [7:0] D;
// Outputs
wire [2:0] E;
// Instantiate the Unit Under Test (UUT)
encoderwithout_v uut (
.D(D),
.E(E)
);
initial begin
// Initialize Inputs
D = 8'b00000001;
#100;
D = 8'b00000010;

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 #100;
D = 8'b00000100;
#100;
D = 8'b00001000;
#100;
D = 8'b00010000;
#100;
D = 8'b00100000;
#100;
D = 8'b01000000;
#100;
D = 8'b10000000;
#100;
end
endmodule
Simulation Result:

RTL Schematic:

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8 to 3 encoder Priority Truth Table :
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 E2 E1 E0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity priorityencoder is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
E : out STD_LOGIC_VECTOR (2 downto 0));
end priorityencoder;
architecture Behavioral of priorityencoder is
begin
process (D)
begin
If (D(7) = '1') then E <= "111";
elsif (D(6) = '1') then E <= "110";
elsif (D(5) = '1') then E <= "101";
elsif (D(4) = '1') then E <= "100";
elsif (D(3) = '1') then E <= "011";
elsif (D(2) = '1') then E <= "010";
elsif (D(1) = '1') then E <= "001";
elsif (D(0) = '1') then E <= "000";
end if ;
end process ;
end Behavioral;

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Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY priorityencoder_tb IS
END priorityencoder_tb;
ARCHITECTURE behavior OF priorityencoder_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT priorityencoder
PORT(
D : IN std_logic_vector(7 downto 0);
E : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal E : std_logic_vector(2 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: priorityencoder PORT MAP (
D => D,
E => E
);
-- Stimulus process
stim_proc: process
begin
D<="00000001";
wait for 100 ns;
D<="00000011";
wait for 100 ns;
D<="00000111";
wait for 100 ns;
D<="00001111";
wait for 100 ns;
D<="00011111";

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 wait for 100 ns;
D<="00111111";
wait for 100 ns;
D<="01111111";
wait for 100 ns;
D<="11111111";
wait for 100 ns;
D<="00000001";
wait for 100 ns;
wait;
end process;
END;
Simulation Result:

RTL Schematic:

Page 26 of 74
Verilog Code:
module priorityencoder_v(
input [7:0] D,
output [2:0] E
);
assign E = (D[7] ==1'b1 ) ? 3'b111:
(D[6] ==1'b1 ) ? 3'b110:
(D[5] ==1'b1 ) ? 3'b101:
(D[4] ==1'b1) ? 3'b100:
(D[3] ==1'b1) ? 3'b011:
(D[2] ==1'b1) ? 3'b010:
(D[1] ==1'b1) ? 3'b001:
(D[0] ==1'b1) ? 3'b000: 3'bxxx;
endmodule
Test Bench:
module encoderwithout_v_tb;
// Inputs
reg [7:0] D;
// Outputs
wire [2:0] E;
// Instantiate the Unit Under Test (UUT)
encoderwithout_v uut (
.D(D),
.E(E)
);
initial begin
// Initialize Inputs
D = 8'b00000001;
#100;
D = 8'b00000010;
#100;
D = 8'b00000100;
#100;
D = 8'b00001000;
#100;

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 D = 8'b00010000;
#100;
D = 8'b00100000;
#100;
D = 8'b01000000;
#100;
D = 8'b10000000;
#100;
D = 8'b00000001;
#100;
end
endmodule
Simulation Result:

RTL Schematic:

Page 28 of 74
Design and implement 4-bit binary to gray converter using verilog and VHDL codes.
Truth Table:
Binary Input Gray Output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BinarytoGray is
Port ( B : in STD_LOGIC_VECTOR (3 downto 0);
G : out STD_LOGIC_VECTOR (3 downto 0));
end BinarytoGray;
architecture Behavioral of BinarytoGray is
begin
process(B)

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begin
CASE B IS
WHEN "0000" => G<= "0000";
WHEN "0001" => G<= "0001";
WHEN "0010" => G<= "0011";
WHEN "0011" => G<= "0010";
WHEN "0100" => G<= "0110";
WHEN "0101" => G<= "0111";
WHEN "0110" => G<= "0101";
WHEN "0111" => G<= "0100";
WHEN "1000" => G<= "1100";
WHEN "1001" => G<= "1101";
WHEN "1010" => G<= "1111";
WHEN "1011" => G<= "1110";
WHEN "1100" => G<= "1010";
WHEN "1101" => G<= "1011";
WHEN "1110" => G<= "1001";
WHEN OTHERS => G<= "1000";
END CASE;
end process;
end Behavioral;
VHDL Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY BinarytoGray_TB IS
END BinarytoGray_TB;
ARCHITECTURE behavior OF BinarytoGray_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BinarytoGray
PORT(
B : IN std_logic_vector(3 downto 0);
G : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs

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 signal B : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal G : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BinarytoGray PORT MAP (
B => B,
G => G
);
-- Stimulus process
stim_proc: process
begin
B<="0000";
wait for 100 ns;
B<="0001";
wait for 100 ns;
B<="0010";
wait for 100 ns;
B<="0011";
wait for 100 ns;
B<="0100";
wait for 100 ns;
B<="0101";
wait for 100 ns;
B<="0110";
wait for 100 ns;
B<="0101";
wait for 100 ns;
B<="0110";
wait for 100 ns;
B<="0111";
wait for 100 ns;
B<="1000";
wait for 100 ns;
B<="1001";

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 wait for 100 ns;
B<="1010";
wait for 100 ns;
B<="1011";
wait for 100 ns;
B<="1100";
wait for 100 ns;
B<="1101";
wait for 100 ns;
B<="1101";
wait for 100 ns;
B<="1110";
wait for 100 ns;
B<="1111";
wait for 100 ns;
wait;
end process;
END;
Simulation Result:

RTL Schematic:

Page 32 of 74
Verilog Code:
module BinarytoGray_v(
input [3:0] B,
output reg [3:0] G
);
always @( B)
begin
case (B)
4'b0000: G=4'b0000;
4'b0001: G=4'b0001;
4'b0010: G=4'b0011;
4'b0011: G=4'b0010;
4'b0100: G=4'b0110;
4'b0101: G=4'b0111;
4'b0110: G=4'b0101;
4'b0111: G=4'b0100;
4'b1000: G=4'b1100;
4'b1001: G=4'b1101;
4'b1010: G=4'b1111;
4'b1011: G=4'b1110;
4'b1100: G=4'b1010;
4'b1101: G=4'b1011;
4'b1110: G=4'b1001;
4'b1111: G=4'b1000;
endcase
end
endmodule
Test Bench:
module BinarytoGray_v_tb;
// Inputs
reg [3:0] B;
// Outputs
wire [3:0] G;
// Instantiate the Unit Under Test (UUT)
BinarytoGray_v uut (

Page 33 of 74
 .B(B),
.G(G)
);
initial begin
// Initialize Inputs
B = 4'b0000;
#100;
B = 4'b0001;
#100;
B = 4'b0010;
#100;
B = 4'b0011;
#100;
B = 4'b0100;
#100;
B = 4'b0101;
#100;
B = 4'b0110;
#100;
B = 4'b0111;
#100;
B = 4'b1000;
#100;
B = 4'b1001;
#100;
B = 4'b1010;
#100;
B = 4'b1011;
#100;
B = 4'b1100;
#100;
B = 4'b1101;
#100;
B = 4'b1110;
#100;

Page 34 of 74
 B = 4'b1111;
#100;
end
endmodule
Simulation Result:

RTL Schematic:

Design a 3-bit priority encoder. The input I is 3-bit and the output P is 3-bit. I(0) when
high, has the highest priority, followed by I(1) and I(2).The output P for highest
Priority to lowest is 0, 1 and 2 (decimal), respectively. Construct the truth table,
minimize and write verilog and VHDL codes.

Page 35 of 74
Truth Table:
Inputs Outputs
I2 I1 I0 P2 P1 P0
0 0 0 0 1 0
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 0 0 0
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 0 0 1
1 1 1 0 0 0

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encoder_3 is
Port ( I : in STD_LOGIC_VECTOR (2 downto 0);
P : out STD_LOGIC_VECTOR (2 downto 0));
end encoder_3;
architecture Behavioral of encoder_3 is
begin
process(I)
begin
if (I = "000") then P <= "010";
elsif (I = "001") then P <= "000";
elsif (I = "010") then P <= "001";
elsif (I = "011") then P <= "000";
elsif (I = "100") then P <= "010";
elsif (I = "101") then P <= "000";
elsif (I = "110") then P <= "001";
else P<= "000";
end if;
end process;
end Behavioral;
VHDL Test Bench:

Page 36 of 74
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ENCODER_3_TB IS
END ENCODER_3_TB;
ARCHITECTURE behavior OF ENCODER_3_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT encoder_3
PORT(
I : IN std_logic_vector(2 downto 0);
P : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal I : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal P : std_logic_vector(2 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: encoder_3 PORT MAP (
I => I,
P => P
);
-- Stimulus process
stim_proc: process
begin
I<="000";
wait for 100 ns;
I<="001";
wait for 100 ns;
I<="010";
wait for 100 ns;
I<="011";
wait for 100 ns;
I<="100";
wait for 100 ns;

Page 37 of 74
 I<="101";
wait for 100 ns;
I<="110";
wait for 100 ns;
I<="111";
wait for 100 ns;
end process;
END;
Simulation Result:

RTL Schematic:

Verilog Code:
module encoder__3v(
input [2:0] I,
output reg [2:0] P
);
always @( I)
begin

Page 38 of 74
 case (I)
3'b000: P=3'b010;
3'b001: P=3'b000;
3'b010: P=3'b001;
3'b011: P=3'b001;
3'b100: P=3'b010;
3'b101: P=3'b000;
3'b110: P=3'b001;
3'b111: P=3'b000;
endcase
end
endmodule
Test Bench:
module encoder_3v_tb;
// Inputs
reg [2:0] I;
// Outputs
wire [2:0] P;
// Instantiate the Unit Under Test (UUT)
encoder__3v uut (
.I(I),
.P(P)
);
initial begin
// Initialize Inputs
I = 3'b000;
#100;
I = 3'b001;
#100;
I = 3'b010;
#100;
I = 3'b011;
#100;
I = 3'b100;
#100;

Page 39 of 74
 I = 3'b101;
#100;
I = 3'b110;
#100;
I = 3'b111;
#100;
end
endmodule
Simulation Result:

RTL Schematic:

Page 40 of 74
Write both verilog and VHDL codes to realize a 4-bit comparator and implement the
design in Xilinx ISE.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comparator is
Port ( A,B : in STD_LOGIC_VECTOR (3 downto 0);
GREATER,EQUAL,SMALLER : out STD_LOGIC);
end comparator;
architecture Behavioral of comparator is
begin
GREATER<= '1' WHEN (A > B) ELSE '0';
SMALLER<= '1' WHEN (A < B) ELSE '0';
EQUAL<= '1' WHEN (A = B) ELSE '0';
end Behavioral;
VHDL Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY comparator_tb IS
END comparator_tb;
ARCHITECTURE behavior OF comparator_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comparator
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
GREATER : OUT std_logic;
EQUAL : OUT std_logic;
SMALLER : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');

Page 41 of 74
 signal B : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal GREATER : std_logic;
signal EQUAL : std_logic;
signal SMALLER : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comparator PORT MAP (
A => A,
B => B,
GREATER => GREATER,
EQUAL => EQUAL,
SMALLER => SMALLER
);
-- Stimulus process
stim_proc: process
begin
A<= "1000";
B<="0100";
wait for 100 ns;
A<= "1000";
B<="1100";
wait for 100 ns;
A<= "1000";
B<="1000";
wait for 100 ns;
wait;
end process;
END;

Page 42 of 74
Simulation Result:

RTL Schematic:

Verilog Code:
module COMPARATOR_V(
input [3:0] A,
input [3:0] B,
output reg GREATER,
output reg SMALLER,

Page 43 of 74
 output reg EQUAL
);
always @( A,B)
begin
if (A==B)
begin
EQUAL = 1'b1;
SMALLER = 1'b0;
GREATER = 1'b0;
end
else if (A>B)
begin
EQUAL = 1'b0;
SMALLER = 1'b0;
GREATER = 1'b1;
end
else
begin
EQUAL = 1'b0;
SMALLER = 1'b1;
GREATER = 1'b0;
end
end
endmodule
Test Bench:
module COMPARATOR_V_TB;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
wire GREATER;
wire SMALLER;
wire EQUAL;
// Instantiate the Unit Under Test (UUT)
COMPARATOR_V uut (

Page 44 of 74
 .A(A),
.B(B),
.GREATER(GREATER),
.SMALLER(SMALLER),
.EQUAL(EQUAL)
);
initial begin
// Initialize Inputs
A = 4'b1000;
B = 4'b1000;
#100;
A = 4'b0000;
B = 4'b1100;
#100;
A = 4'b1000;
B = 4'b0000;
#100;
A = 4'b1000;
B = 4'b0001;
#100;
end
endmodule
Simulation Result:

Page 45 of 74
RTL Schematic:

Design a 4-bit parity generator .The output is 0 for even parity and 1 for odd parity.
Write verilog and VHDL codes and implement it.
Truth Table:
Inputs Outputs
A B C D PEVEN PODD
0 0 0 0 0 1
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1

Page 46 of 74
 1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 1

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PARITYGENERATOR is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
PEVEN,PODD : out STD_LOGIC);
end PARITYGENERATOR;
architecture Behavioral of PARITYGENERATOR is
begin
process(A)
begin
CASE A IS
WHEN "0000" => PEVEN<= '0';PODD<='1';
WHEN "0011" => PEVEN<= '0';PODD<='1';
WHEN "0101" => PEVEN<= '0';PODD<='1';
WHEN "0110" => PEVEN<= '0';PODD<='1';
WHEN "1001" => PEVEN<= '0';PODD<='1';
WHEN "1010" => PEVEN<= '0';PODD<='1';
WHEN "1100" => PEVEN<= '0';PODD<='1';
WHEN "1111" => PEVEN<= '0';PODD<='1';
WHEN OTHERS => PEVEN<= '1';PODD<='0';
END CASE;
end process;
end Behavioral;

VHDL Test Bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PARITYGENERATOR_TB IS

Page 47 of 74
END PARITYGENERATOR_TB;
ARCHITECTURE behavior OF PARITYGENERATOR_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PARITYGENERATOR
PORT(
A : IN std_logic_vector(3 downto 0);
PEVEN : OUT std_logic;
PODD : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal PEVEN : std_logic;
signal PODD : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PARITYGENERATOR PORT MAP (
A => A,
PEVEN => PEVEN,
PODD => PODD
);
-- Stimulus process
stim_proc: process
begin
A<="0000";
wait for 100 ns;
A<="0001";
wait for 100 ns;
A<="0010";
wait for 100 ns;
A<="0011";
wait for 100 ns;
A<="0100";
wait for 100 ns;

Page 48 of 74
 A<="0101";
wait for 100 ns;
A<="0110";
wait for 100 ns;
A<="0111";
wait for 100 ns;
A<="1000";
wait for 100 ns;
A<="1001";
wait for 100 ns;
A<="1010";
wait for 100 ns;
A<="1011";
wait for 100 ns;
A<="1100";
wait for 100 ns;
A<="1101";
wait for 100 ns;
A<="1110";
wait for 100 ns;
A<="1111";
wait for 100 ns;
wait;
end process;
END;
Simulation Result:

Page 49 of 74
RTL Schematic:

Verilog Code:
module paritygenerator_v(
input [3:0] A,
output reg[1:0]PEVENODD
);
always @( A )
begin
case (A)
4'b0000: PEVENODD=2'b01;
4'b0001: PEVENODD=2'b10;
4'b0010: PEVENODD=2'b10;
4'b0011: PEVENODD=2'b01;
4'b0100: PEVENODD=2'b10;
4'b0101: PEVENODD=2'b01;
4'b0110: PEVENODD=2'b01;
4'b0111: PEVENODD=2'b10;
4'b1000: PEVENODD=2'b10;
4'b1001: PEVENODD=2'b01;
4'b1010: PEVENODD=2'b01;
4'b1011: PEVENODD=2'b10;
4'b1100: PEVENODD=2'b01;
4'b1101: PEVENODD=2'b10;
4'b1110: PEVENODD=2'b10;

Page 50 of 74
 4'b1111: PEVENODD=2'b10;
endcase
end
endmodule
Test Bench:
module paritygenerator_v_tb;
// Inputs
reg [3:0] A;
// Outputs
wire [1:0] PEVENODD;
// Instantiate the Unit Under Test (UUT)
paritygenerator_v uut (
.A(A),
.PEVENODD(PEVENODD)
);
initial begin
A = 4'b0000;
#100;
A = 4'b0001;
#100;
A = 4'b0010;
#100;
A = 4'b0011;
#100;
A = 4'b0100;
#100;
A = 4'b0101;
#100;
A = 4'b0110;
#100;
A = 4'b0111;
#100;
A = 4'b1000;
#100;
A = 4'b1001;

Page 51 of 74
 #100;
A = 4'b1010;
#100;
A = 4'b1011;
#100;
A = 4'b1100;
#100;
A = 4'b1101;
#100;
A = 4'b1110;
#100;
A = 4'b1111;
#100;
end
endmodule
Simulation Result:

RTL Schematic:

Page 52 of 74
Write both verilog and VHDL codes to describe the functions of a full Adder using all
the three modeling styles and implement it.
Truth Table:
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S = A xor B xor C
Cout = AB + BCin + ACin
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( A,B,Cin : in STD_LOGIC;
S,Cout : out STD_LOGIC);
end fulladder;
architecture Dataflow of fulladder is
begin
S <= A xor B xor Cin;
Cout <= (A and B) or (B and Cin) or (Cin and A);
end Dataflow;
VHDL Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fulladder_tb IS
END fulladder_tb;
ARCHITECTURE behavior OF fulladder_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fulladder
PORT(
A : IN std_logic;

Page 53 of 74
 B : IN std_logic;
Cin : IN std_logic;
S : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Cin : std_logic := '0';
--Outputs
signal S : std_logic;
signal Cout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fulladder PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
-- Stimulus process
stim_proc: process
begin
A <='0';
B <= '0';
Cin <='0';
wait for 100 ns;
A <='0';
B <='0';
Cin <='0';
wait for 100 ns;
A <='0';
B <='0';

Page 54 of 74
 Cin <='1';
wait for 100 ns;
A <='0';
B <='1';
Cin <='0';
wait for 100 ns;
A <='0';
B <='1';
Cin <='1';
wait for 100 ns;
A <='1';
B <='0';
Cin <='0';
wait for 100 ns;
A <='1';
B <='0';
Cin <='1';
wait for 100 ns;
A <='1';
B <='1';
Cin <='0';
wait for 100 ns;
A <='1';
B <='1';
Cin <='1';
wait for 100 ns;
end process;
END;
Simulation Result:

Page 55 of 74
RTL Schematic:

Verilog Code:
Design a 4-bit Full adder with carry Lookahead using verilog and VHDL codes and
implement in Xilinx.

Page 56 of 74
CARRY LOOK A HEAD LOGIC:
Gi=Ai Bi
Pi=Ai + Bi
Ci+1 = Gi + Pi Ci
G0=A0 B0
G1=A1 B1
G2=A2 B2
G3=A3 B3
P0=A0 + B0
P1=A1 + B1
P2=A2 + B2
P3=A3 + B3
C1 = G0 + P0 C0
C2 = G1 + P1 C1
C3 = G2 + P2 C2
C4 = G3 + P3 C3

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CARRYLOOKAHEADLOGIC is
Port ( A0,A1,A2,A3 : in STD_LOGIC;
B0,B1,B2,B3 : in STD_LOGIC;
C0 : in STD_LOGIC;
C1,C2,C3,C4 : inout STD_LOGIC);
end CARRYLOOKAHEADLOGIC;
architecture Behavioral of CARRYLOOKAHEADLOGIC is
SIGNAL G0,G1,G2,G3:STD_LOGIC;
SIGNAL P0,P1,P2,P3:STD_LOGIC;
SIGNAL S1,S2,S3,S4:STD_LOGIC;
COMPONENT AND21 IS
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
END COMPONENT;

Page 57 of 74
COMPONENT OR21 IS
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
END COMPONENT;
begin
U1: AND21 PORT MAP(A0,B0,G0);
U2: AND21 PORT MAP(A1,B1,G1);
U3: AND21 PORT MAP(A2,B2,G2);
U4: AND21 PORT MAP(A3,B3,G3);
U5: OR21 PORT MAP(A0,B0,P0);
U6: OR21 PORT MAP(A1,B1,P1);
U7: OR21 PORT MAP(A2,B2,P2);
U8: OR21 PORT MAP(A3,B3,P3);
U9: AND21 PORT MAP(P0,C0,S1);
U10: OR21 PORT MAP(G0,S1,C1);
U11: AND21 PORT MAP(P1,C1,S2);
U12: OR21 PORT MAP(G1,S2,C2);
U13: AND21 PORT MAP(P2,C2,S3);
U14: OR21 PORT MAP(G2,S3,C3);
U15: AND21 PORT MAP(P3,C3,S4);
U16: OR21 PORT MAP(G3,S4,C4);
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CARRYLOOKAHEADLOGIC_TB IS
END CARRYLOOKAHEADLOGIC_TB;
ARCHITECTURE behavior OF CARRYLOOKAHEADLOGIC_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CARRYLOOKAHEADLOGIC
PORT(
A0 : IN std_logic;
A1 : IN std_logic;

Page 58 of 74
 A2 : IN std_logic;
A3 : IN std_logic;
B0 : IN std_logic;
B1 : IN std_logic;
B2 : IN std_logic;
B3 : IN std_logic;
C0 : IN std_logic;
C1 : INOUT std_logic;
C2 : INOUT std_logic;
C3 : INOUT std_logic;
C4 : INOUT std_logic
);
END COMPONENT;
--Inputs
signal A0 : std_logic := '0';
signal A1 : std_logic := '0';
signal A2 : std_logic := '0';
signal A3 : std_logic := '0';
signal B0 : std_logic := '0';
signal B1 : std_logic := '0';
signal B2 : std_logic := '0';
signal B3 : std_logic := '0';
signal C0 : std_logic := '0';
--BiDirs
signal C1 : std_logic;
signal C2 : std_logic;
signal C3 : std_logic;
signal C4 : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CARRYLOOKAHEADLOGIC PORT MAP (
A0 => A0,
A1 => A1,
A2 => A2,
A3 => A3,

Page 59 of 74
 B0 => B0,
B1 => B1,
B2 => B2,
B3 => B3,
C0 => C0,
C1 => C1,
C2 => C2,
C3 => C3,
C4 => C4
);
-- Stimulus process
stim_proc: process
begin
C0<='0';
A0<='0';
A1<='1';
A2<='0';
A3<='1';
B0<='1';
B1<='1';
B2<='1';
B3<='0';
wait;
end process;
END;
Simulation Result:

Page 60 of 74
RTL Schematic:

VHDL Code for adder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FULLADDER_CARRLOOKAHEAD is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C0 : in STD_LOGIC;
C4 : INOUT STD_LOGIC;
S0,S1,S2,S3 : out STD_LOGIC);
end FULLADDER_CARRLOOKAHEAD;
architecture Behavioral of FULLADDER_CARRLOOKAHEAD is
SIGNAL C1,C2,C3:STD_LOGIC;
COMPONENT CARRYLOOKAHEADLOGIC IS
Port ( A0,A1,A2,A3 : in STD_LOGIC;
B0,B1,B2,B3 : in STD_LOGIC;
C0 : in STD_LOGIC;

Page 61 of 74
 C1,C2,C3,C4 : inout STD_LOGIC);
END COMPONENT;
COMPONENT fulladder2 IS
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
S : out STD_LOGIC);
END COMPONENT;
begin
U1: CARRYLOOKAHEADLOGIC PORT
MAP(A(0),A(1),A(2),A(3),B(0),B(1),B(2),B(3),C0,C1,C2,C3,C4);
U2: fulladder2 PORT MAP (A(0),B(0),C0,S0);
U3: fulladder2 PORT MAP (A(1),B(1),C1,S1);
U4: fulladder2 PORT MAP (A(2),B(2),C2,S2);
U5: fulladder2 PORT MAP (A(3),B(3),C3,S3);
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FULLADDER_CARRYLOOKAHEAD_TB IS
END FULLADDER_CARRYLOOKAHEAD_TB;
ARCHITECTURE behavior OF FULLADDER_CARRYLOOKAHEAD_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FULLADDER_CARRLOOKAHEAD
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
C0 : IN std_logic;
C4 : INOUT std_logic;
S0 : OUT std_logic;
S1 : OUT std_logic;
S2 : OUT std_logic;
S3 : OUT std_logic
);
END COMPONENT;

Page 62 of 74
 --Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal C0 : std_logic := '0';
--BiDirs
signal C4 : std_logic;
--Outputs
signal S0 : std_logic;
signal S1 : std_logic;
signal S2 : std_logic;
signal S3 : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FULLADDER_CARRLOOKAHEAD PORT MAP (
A => A,
B => B,
C0 => C0,
C4 => C4,
S0 => S0,
S1 => S1,
S2 => S2,
S3 => S3
);
-- Stimulus process
stim_proc: process
begin
A<="1010";
B<="0111";
C0<='0';
wait for 100 ns;
wait;
end process;
END;

Page 63 of 74
Simulation Result:

RTL Schematic:

Verilog Code:
module adder_carrylookahead_v(
input A3,A2,A1,A0,B3,B2,B1,B0,CIN,
output COUT,SUM0,SUM1,SUM2,SUM3
);
wire G0,G1,G2,G3,P0,P1,P2,P3,S1,S2,S3,S4,C1,C2,C3,C4;

Page 64 of 74
and u1(G0,A0,B0);
and u2(G1,A1,B1);
and u3(G2,A2,B2);
and u4(G3,A3,B3);
or u5(P0,A0,B0);
or u6(P1,A1,B1);
or u7(P2,A2,B2);
or u8(P3,A3,B3);
and u9(S1,P0,CIN);
or u10(C1,G0,S1);
and u11(S2,P1,C1);
or u12(C2,G1,S2);
and u13(S3,P2,C2);
or u14(C3,G2,S3);
and u15(S4,P3,C3);
or u16(C4,G3,S4);
xor u17(SUM0,A0,B0,CIN);
xor u18(SUM1,A1,B1,C1);
xor u19(SUM2,A2,B2,C2);
xor u20(SUM3,A3,B3,C3);
and u21(COUT,C4,C4);
endmodule
Test Bench:
module adder_carrylookahead_v_tb;
// Inputs
reg A3;
reg A2;
reg A1;
reg A0;
reg B3;
reg B2;
reg B1;
reg B0;
reg CIN;
// Outputs

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wire COUT;
wire SUM0;
wire SUM1;
wire SUM2;
wire SUM3;
// Instantiate the Unit Under Test (UUT)
adder_carrylookahead_v uut (
.A3(A3),
.A2(A2),
.A1(A1),
.A0(A0),
.B3(B3),
.B2(B2),
.B1(B1),
.B0(B0),
.CIN(CIN),
.COUT(COUT),
.SUM0(SUM0),
.SUM1(SUM1),
.SUM2(SUM2),
.SUM3(SUM3)
);
initial begin
// Initialize Inputs
A3 =1'b1;
A2 =1'b0;
A1 =1'b1;
A0 =1'b0;
B3 =1'b0;
B2 =1'b1;
B1 =1'b1;
B0 =1'b1;
CIN = 0;
#100;
end

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 endmodule
Simulation Result:

RTL Schematic:

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 Write a model for 32-bit Arithmetic Logic Unit using the schematic diagram shown
below.

A1(3:0) Zout(3:0)

B1(3:0)

Opcode (3:0)

The truth table is shown below:

Operation Opcode A B Zout

A+B 000 1111 0000 00001111
A-B 001 1110 0010 00001100
A or B 010 1111 1000 00001111
A and B 011 1001 1000 00001000
Not A 100 1111 0000 11110000
A1*B1 101 1111 1111 11100001
A nand B 110 1111 0010 11111101
A xor B 111 0000 0100 00000100

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VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.NUMERIC_STD.all;
entity ALU32 is
Port ( A,B : in STD_LOGIC_VECTOR (31 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (31 downto 0));
end ALU32;
architecture Behavioral of ALU32 is
begin
process(S)
begin
CASE S IS
WHEN "000" => Y<= A + B;
WHEN "001" => Y<= A - B;
WHEN "010" => Y<= A OR B;
WHEN "011" => Y<= A AND B;
WHEN "100" => Y<= NOT A;
WHEN "101" => Y<= A * B;
WHEN "110" => Y<= A NAND B;
WHEN OTHERS => Y <=A XOR B;
END CASE;
end process;
end Behavioral;
VHDL Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU32_TB IS
END ALU32_TB;
ARCHITECTURE behavior OF ALU32_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU32

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 PORT(
A : IN std_logic_vector(31 downto 0);
B : IN std_logic_vector(31 downto 0);
S : IN std_logic_vector(2 downto 0);
Y : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(31 downto 0) := (others => '0');
signal B : std_logic_vector(31 downto 0) := (others => '0');
signal S : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal Y : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU32 PORT MAP (
A => A,
B => B,
S => S,
Y => Y
);
-- Stimulus process
stim_proc: process
begin
A<="00000000000000000000000000000000";
B<="11111111111111111111111111111111";
wait for 100 ns;
S<="000";
wait for 100 ns;
S<="001";
wait for 100 ns;
S<="010";
wait for 100 ns;
S<="011";
wait for 100 ns;

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 S<="100";
wait for 100 ns;
S<="000";
wait for 100 ns;
S<="101";
wait for 100 ns;
S<="110";
wait for 100 ns;
S<="111";
wait for 100 ns;
end process;
END;
Simulation Result:

RTL Schematic:

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Verilog Code:
module alu(
input [31:0] A,
input [31:0] B,
input [2:0] s,
output reg[64:0] Y
);
always @(A,B,s)
begin
case(s)
3'b000: Y = A + B ;
3'b001: Y = A - B ;
3'b010: Y= A | B;
3'b011: Y= A & B;
3'b100: Y = ~A;
3'b101: Y= A*B;
3'b110: Y =~(A & B);
3'b111: Y = A^B;
default: Y = 64'b0 ;
endcase
end
endmodule
Test Bench:
module alu_tb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [2:0] s;
// Outputs
wire [64:0] Y;
// Instantiate the Unit Under Test (UUT)
alu uut (
.A(A),
.B(B),
.s(s),

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 .Y(Y)
);
initial begin
// Initialize Inputs
A =32'b11111111111111111111111111111111;
B =32'b00000000000000000000000000000000;
s =3'b000;
#100;
s =3'b001;
#100;
s =3'b010;
#100;
s =3'b011;
#100;
s =3'b100;
#100;
s =3'b101;
#100;
s =3'b110;
#100;
s =3'b111;
#100;
end
endmodule

Simulation Result:

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RTL Schematic:

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