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LTC4162 L

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0% found this document useful (0 votes)

558 views52 pages

LTC4162 L

Uploaded by

mar_barudj

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Available Formats

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LTC4162-L

35V/3.2A Multicell
Lithium-Ion Step-Down Battery Charger
with PowerPath and I2C Telemetry
FEATURES DESCRIPTION
nn Li-Ion/Polymer Battery Charger with Termination The LTC®4162-L is an advanced monolithic synchronous
nn Wide Charging Input Voltage Range: 4.5V to 35V step-down switching battery charger and PowerPath™
nn High Efficiency Synchronous Operation manager that seamlessly manages power distribution
nn 16-Bit Digital Telemetry System Monitors V
BAT, between input sources such as wall adapters, backplanes,
IBAT, RBAT, TBAT, TDIE, VIN, IIN, VOUT solar panels, etc., and a rechargeable Lithium-Ion/Polymer
nn Charges 1-8 Lithium-Ion/Polymer Cells battery.
nn Input Undervoltage Charge Current Limit Loop
nn Input MPPT for Solar Panel Inputs
A high resolution measurement system provides exten-
sive telemetry information for circuit voltages, currents,
nn Input Current Limit Prioritizes System Load Output
nn Low Loss PowerPath™
battery resistance and temperature which can all be read
nn Instant-On Operation with Discharged or Missing
back over the I2C port. The I2C port can also be used to
configure many charging parameters including charging
Battery
nn JEITA Temperature Controlled Charging
voltages and currents, termination algorithms and numer-
ous system status alerts.
nn Pin Compatible with LiFePO and SLA Versions
4
The LTC4162-L can charge Lithium-Ion cell stacks from
1 cell to 8 cells with as much as 3.2A of charge current.
APPLICATIONS The power path topology decouples the output voltage
nn Medical Instruments from the battery allowing a portable product to start up
nn USB-C Power Delivery instantly under very low battery voltage conditions.
nn Industrial Handhelds
The LTC4162-L is available in a thermally enhanced 28-pin
nn Ruggedized Notebooks
4mm × 5mm × 0.75mm QFN surface mount package.
nn Tablet Computers All registered trademarks and trademarks are the property of their respective owners.

TYPICAL APPLICATION
1-8 Cell, 3.2A Step-Down Switching Battery Charger with PowerPath Charging Efficiency vs Input Voltage by Cell Count
VIN VOUT
100
7 CELLS
5 CELLS 6 CELLS 8 CELLS
VIN INFET CLP CLN VOUT 4 CELLS
95 3 CELLS
BATFET
2C 2 CELLS
I
EFFICIENCY (%)

SW 90
CSP 1 CELL

LTC4162-L 85
CSN
CELL BATSENS+
COUNT 80
NTCBIAS
NTC ICHARGE = 2.5A
75
GND T 5 10 15 20 25 30 35
INPUT VOLTAGE (V)
4162L TA01a 4162L TA01b

Rev A

Document Feedback For more information [Link] 1

LTC4162-L
TABLE OF CONTENTS
Features............................................................................................................................. 1
Applications........................................................................................................................ 1
Typical Application ................................................................................................................ 1
Description......................................................................................................................... 1
Absolute Maximum Ratings...................................................................................................... 3
Order Information.................................................................................................................. 3
Pin Configuration.................................................................................................................. 3
Electrical Characteristics......................................................................................................... 4
Typical Performance Characteristics........................................................................................... 7
Pin Functions......................................................................................................................10
Block Diagram.....................................................................................................................12
ESD Diagram......................................................................................................................13
Timing Diagram...................................................................................................................14
Operation..........................................................................................................................15
Applications Information........................................................................................................29
Register Descriptions............................................................................................................36
Typical Applications..............................................................................................................48
Package Description.............................................................................................................50
Revision History..................................................................................................................51
Typical Application...............................................................................................................52
Related Parts......................................................................................................................52

Rev A

2 For more information [Link]

LTC4162-L
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
TOP VIEW
BATSENS+, VIN, CSP, CSN, CLP,
CLN, VOUT, VOUTA................................... −0.3V to 36V

PGND
PGND
VOUT
VOUT
SW
SW
CSP to CSN, CLP to CLN.........................................±0.3V 28 27 26 25 24 23
CELLSO, CELLS1, SYNC ...................... −0.3V to INTVCC BOOST 1 22 BATFET
DVCC.......................................................... −0.3V to 5.5V INTVCC 2 21 CSP
SDA, SCL, SMBALERT.............................. −0.3V to DVCC VOUTA 3 20 CSN

ISW ........................................................................ ±3.5A CLN 4 AGND 19 BATSENS+

CLP 5 29 18 CELLS1
Operating Junction Temperature Range
INFET 6 17 CELLS0
(Notes 2, 4)............................................. −40 to 125°C VIN 7 16 SYNC
Storage Temperature Range....................... −65 to 150°C VCC2P5 8 15 DVCC
9 10 11 12 13 14

NTCBIAS
NTC
RT
SMBALERT
SCL
SDA
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION
PART TAPE AND TEMP
PART NUMBER DESCRIPTION TEMPERATURE RANGE
MARKING* REEL GRADE
LTC4162EUFD-LAD#PBF 4162A E I2C Adjustable Voltage –40°C to 125°C
LTC4162EUFD-L40#PBF 4162B E 4.0V Fixed Voltage –40°C to 125°C
LTC4162EUFD-L41#PBF 4162C E 4.1V Fixed Voltage –40°C to 125°C
LTC4162EUFD-L42#PBF 4162D E 4.2V Fixed Voltage –40°C to 125°C
LTC4162EUFD-LADM#PBF 4162K E I2C Adjustable Voltage MPPT ON –40°C to 125°C
LTC4162EUFD-L40M#PBF 4162L E 4.0V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162EUFD-L41M#PBF 4162M E 4.1V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162EUFD-L42M#PBF 4162N E 4.2V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162EUFD-LAD#TRPBF 4162A ✓ E I2C Adjustable Voltage –40°C to 125°C
LTC4162EUFD-L40#TRPBF 4162B ✓ E 4.0V Fixed Voltage –40°C to 125°C
LTC4162EUFD-L41#TRPBF 4162C ✓ E 4.1V Fixed Voltage –40°C to 125°C
LTC4162EUFD-L42#TRPBF 4162D ✓ E 4.2V Fixed Voltage –40°C to 125°C
LTC4162EUFD-LADM#TRPBF 4162K ✓ E I2C Adjustable Voltage MPPT ON –40°C to 125°C
LTC4162EUFD-L40M#TRPBF 4162L ✓ E 4.0V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162EUFD-L41M#TRPBF 4162M ✓ E 4.1V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162EUFD-L42M#TRPBF 4162N ✓ E 4.2V Fixed Voltage MPPT ON –40°C to 125°C

Rev A

For more information [Link] 3

LTC4162-L
ORDER INFORMATION
PART TAPE AND TEMP
PART NUMBER DESCRIPTION TEMPERATURE RANGE
MARKING* REEL GRADE
LTC4162IUFD-LAD#PBF 4162A I I2C Adjustable Voltage –40°C to 125°C
LTC4162IUFD-L40#PBF 4162B I 4.0V Fixed Voltage –40°C to 125°C
LTC4162IUFD-L41#PBF 4162C I 4.1V Fixed Voltage –40°C to 125°C
LTC4162IUFD-L42#PBF 4162D I 4.2V Fixed Voltage –40°C to 125°C
LTC4162IUFD-LADM#PBF 4162K I I2C Adjustable Voltage MPPT ON –40°C to 125°C
LTC4162IUFD-L40M#PBF 4162L I 4.0V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162IUFD-L41M#PBF 4162M I 4.1V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162IUFD-L42M#PBF 4162N I 4.2V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162IUFD-LAD#TRPBF 4162A ✓ I I2C Adjustable Voltage –40°C to 125°C
LTC4162IUFD-L40#TRPBF 4162B ✓ I 4.0V Fixed Voltage –40°C to 125°C
LTC4162IUFD-L41#TRPBF 4162C ✓ I 4.1V Fixed Voltage –40°C to 125°C
LTC4162IUFD-L42#TRPBF 4162D ✓ I 4.2V Fixed Voltage –40°C to 125°C
LTC4162IUFD-LADM#TRPBF 4162K ✓ I I2C Adjustable Voltage MPPT ON –40°C to 125°C
LTC4162IUFD-L40M#TRPBF 4162L ✓ I 4.0V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162IUFD-L41M#TRPBF 4162M ✓ I 4.1V Fixed Voltage MPPT ON –40°C to 125°C
LTC4162IUFD-L42M#TRPBF 4162N ✓ I 4.2V Fixed Voltage MPPT ON –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
operating junction temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 18V, DVCC = 3.3V, RSNSI = 10mΩ,
RSNSB = 10mΩ unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
System Voltages and Currents
VIN Input Supply Voltage l 4.5 35 V
VBAT Battery Voltage l 2.7 35 V
IBATSENS+ Battery Drain Current VIN – VBATSENS+ > VIN_DUVLO, Terminated 0.5 1 µA
VIN – VBATSENS+ < VIN_DUVLO 54 100 µA
VIN = 0, SHIPMODE Activated 2.8 5 µA
IVIN VIN Drain Current VIN – VBATSENS+ > VIN_DUVLO, Terminated 115 200 µA
Switching Battery Charger
VCHARGE Range 3.8125–4.2 V
Resolution (5 Bits) 12.5 mV
Per cell_count
Accuracy –0.5 0.5 %
l –1.5 1.5 %

Rev A

4 For more information [Link]

Rev A

For more information [Link] 5

LTC4162-L
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full specified
operating junction temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 18V, DVCC = 3.3V, RSNSI = 10mΩ,
RSNSB = 10mΩ unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Serial Port, SDA, SCL, SMBALERT
DVCC Logic Reference Level l 1.8 5.5 V
IDVCCQ DVCC Current SCL/SDA = DVCC, 0kHz 0 µA
ADDRESS I2C Address 0b1101000[R/W]
VIHI2C Input High Threshold 70 % DVCC
VILI2C Input Low Threshold 30 % DVCC
VOLI2C Digital Output Low (SDA/SMBALERT) ISDA/SMBALERT = 3mA 400 mV
FSCL SCL Clock Frequency 400 kHz
tLOW LOW Period of SCL Clock 1.3 µs
tHIGH HIGH Period of SCL Clock 0.6 µs
tBUF Bus Free Time Between Start and Stop 1.3 µs
Conditions
tHD,STA Hold Time, After (Repeated) Start 0.6 µs
Condition
tSU,STA Setup Time after a Repeated Start 0.6 µs
Condition
tSU,STO Stop Condition Set-Up Time 0.6 µs
tHD,DAT(OUT) Output Data Hold Time 0 900 ns
tHD,DAT(IN) Input Data Hold Time 0 ns
tSU,DAT Data Set-Up Time 100 ns
tSP Input Spike Suppression Pulse Width 50 ns
SYNC Pin
VIHSYNC Input High Threshold l 1.5 V
VILSYNC Input Low Threshold l 0.2 V
Pin Leakages (NTC, CELLS0, CELLS1, SDA, SCL, SYNC, SMBALERT)
Pin Current –50 50 nA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings 0°C to 85°C junction temperature. Specifications over the –40°C to
may cause permanent damage to the device. Exposure to any Absolute 125°C operating junction temperature range are assured by design,
Maximum Rating condition for extended periods may affect device characterization, and correlation with statistical process controls. The
reliability and lifetime. I-grade is guaranteed over the full –40°C to 125°C operating junction
Note 2: The LTC4162 includes over-temperature protection that is temperature range. The junction temperature (TJ) is calculated from the
intended to protect the device during momentary overload conditions. ambient temperature (TA) and power dissipation (PD) according to the
The maximum rated junction temperature will be exceeded when this formula TJ = TA + (PD • θJA). Note that the maximum ambient temperature
protection is active. Continuous operation above the specified absolute consistent with these specifications is determined by specific operating
maximum operating junction temperature may impair device reliability or conditions in conjunction with board layout, the rated package thermal
permanently damage the device. resistance and other environmental factors.
Note 3: The safety current limit features of this part are intended to Note 5: Charge Current is given by the charger servo voltage, VCSP-CSN,
protect the IC from short term or intermittent fault conditions. Continuous divided by the charge current setting resistor RSNSB. Errors in the value of
operation above the maximum specified pin current may result in device the external resistor contribute directly to the total charge current error.
degradation or failure. Note 6: Input Current is given by the VCLP-CLN servo voltage divided by
Note 4: The E-grade is tested under pulsed load conditions such the input current setting resistor RSNSI. Errors in the value of the external
that TJ ≈ TA. The E-grade is guaranteed to meet specifications from resistor contribute directly to the total input current error.

Rev A

6 For more information [Link]

LTC4162-L
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Input Current and Charge Current Resistive Source Input Voltage and
Charge Current vs Battery Voltage vs Load Current Charge Current vs Load Current
3.6 3.6 3.6 20
CHARGE CHARGE
3.2 3.2 3.2 CURRENT 18
CURRENT
2.8 2.8 2.8 16
CHARGE CURRENT (A)

CHARGE CURRENT (A)

2.4 2.4 14

INPUT VOLTAGE (V)

2.4

CURRENT (A)
2.0 INPUT 2.0 12
2.0 CURRENT
1.6 1.6 10
1.6 INPUT
1.2 1.2 VOLTAGE 8
1.2
0.8 0.8 6
0.8 0.4 0.4 4
VIN = 18V SOURCE IMPEDANCE = 5Ω
0.4 VIN = 12V 0.0 VBAT = 3.7V 0.0 input_undervoltage_setting = 7V 2
cell_count = 1 iin_limit_target = 1.2A cell_count = 1
0.0 −0.4 −0.4 0
2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0
BATTERY VOLTAGE (V) LOAD CURRENT (A) LOAD CURRENT (A)
4162L G01 4162L G02 4162L G03

No Input Battery Drain Current vs Ship Mode Battery Drain Current

VOUT vs VIN Power Path Controller Battery Voltage vs Battery Voltage
12.3 100 4
125°C 125°C
VOUT
BATTERY DRAIN CURRENT (µA)

BATTERY DRAIN CURRENT (µA)

25°C
12.2 3
VOUT VOLTAGE (V)

60 25°C –50°C
12.1 –50°C 2
40

12.0 1
20
VBAT
VIN
VIN = 0V
11.9 0 0
−0.05 0.00 0.05 0.10 0.15 0.20 0 5 10 15 20 25 30 35 2.5 9.0 15.5 22.0 28.5 35.0
VIN − VBAT VOLTAGE (V) BATTERY VOLTAGE (V) BATTERY VOLTAGE (V)
4162L G04 4162L G05 4162L G06

Top and Bottom Switch RDS(ON) Efficiency vs Input Voltage Efficiency vs Switching Frequency
170 100 100
7 CELLS
8 CELLS VBAT = 7.4V
5 CELLS 6 CELLS
4 CELLS ICHARGE = 2.5A
150 cell_count = 2
95 3 CELLS
125°C
SWITCH RESISTANCE (mΩ)

95
2 CELLS
130
EFFICIENCY (%)

EFFICIENCY (%)

90
75°C 1 CELL
110 90

25°C 85
90
85 VIN = 12V
80 VIN = 18V
70 −50°C
VIN = 24V
ICHARGE = 2.5A VIN = 30V
50 75 80
0.2 0.7 1.2 1.7 2.2 2.7 3.2 5 10 15 20 25 30 35 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SWITCH PIN CURRENT (A) INPUT VOLTAGE (V) SWITCHING FREQUENCY (MHz)
4162L G07 4162L G08 4162L G09

Rev A

For more information [Link] 7

LTC4162-L
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

2.2Ah 3-Cell Battery Charge Charge Current During BSR

Current and Voltage vs Time Example Power Path Handover Measurement Cycle
2.5 16.8 25 5
VIN = 18V
2.0 15.4 BATFET INFET 4
20

INFET / BATFET VOLTAGE (V)

CHARGE CURRENT (A)

BATTERY VOLTAGE (V)

CHARGE CURRENT (A)

1.5 14.0 3 OPEN CIRCUIT BATTERY
BATTERY 15 VOLTAGE MEASUREMENT
VOLTAGE ca. THIS TIME POINT
1.0 12.6 2
10
0.5 CHARGE 11.2 1
CURRENT
0.0 9.8 5 VBATSENS+ = 15V
0
VIN = 15V TO 15.5V
4 HOUR CV TIMER QGS = 6nC
TERMINATION
−0.5 8.4 0 −1
0 1 2 3 4 5 0 20 40 60 80 100 0 10 20 30 40 50
TIME (H) TIME (µs) TIME (ms)
4162L G10 4162L G11 4162L G12

Light to Dark Solar Panel Tracking Solar Panel Global Sweep

35 1.4 24 1.20
1 Cell
30 PANEL 1.2 21 1.05
CURRENT PANEL
VOLTAGE
18 0.90
25 PANEL 1.0
PANEL CURRENT (A)

PANEL CURRENT (A)

PANEL VOLTAGE (V)

VOLTAGE
15 0.75
20 0.8
12 PANEL 0.60
15 0.6 CURRENT
9 0.45
10 0.4
6 0.30

5 0.2 3 0.15

0 0.0 0 0.00
0 100 200 300 400 500 0.0 0.6 1.2 1.8 2.4 3.0
TIME (s) TIME (s)
4162L G13 4162L G14

Multi-Peak Solar Panel Charge Current and Die Temperature

Acquisition Using Thermal Regulation
35 1.4 4.0 100
PANEL THERMAL START = 70°C
VOLTAGE THERMAL END = 80°C
30 1.2
3.2 90
DIE TEMPERATURE (°C)

25 1.0
CHARGE CURRENT (A)
PANEL CURRENT (A)
PANEL VOLTAGE (V)

2.4 80
20 0.8

15 0.6
1.6 70
DIE
10 0.4 TEMP
0.8 60
5 PANEL 0.2 CHARGE
CURRENT CURRENT
0 0.0 0.0 50
0 1 2 3 4 5 25 40 55 70 85 100
TIME (s) AMBIENT TEMPERATURE (°C)
4162L G15 4162L G16

Rev A

8 For more information [Link]

LTC4162-L
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Histogram of thermistor_voltage
Histogram of vbat Readings Histogram of vout Readings Readings
6000 10000 3000
σ = 512µV σ = 2.69mV σ = 27m°C
5000 2500
8000

4000 2000

FREQUENCY
6000
FREQUENCY

FREQUENCY
3000 1500

4000
2000 1000

2000
1000 500

0 0 0
3.699 3.700 3.701 3.702 3.703 3.704 3.705 11.93 11.94 11.95 11.96 11.97 11.98 24.75 24.80 24.85 24.90 24.95 25.00
BATTERY VOLTAGE (V) OUTPUT VOLTAGE (V) THERMISTOR TEMPERATURE (°C)
4162L G17 4162L G18 4162L G19

Histogram of bsr Readings Histogram of die_temp Readings Histogram of ibat Readings

2500 2000 10000
RSNSI=10mΩ σ = 250µΩ σ = 28m°C σ = 270µA

2000 8000
1500
FREQUENCY

1500 6000
FREQUENCY

FREQUENCY

1000

1000 4000

500
500 2000

0 0 0
198.5 199.0 199.5 200.0 200.5 201.0 201.5 24.8 24.9 25.0 25.1 25.2 3.2025 3.2035 3.2045 3.2055 3.2065
bsr (mΩ) die_temp (°C) BATTERY CURRENT (A)
4162L G20 4162L G21 4162L G22

Histogram of iin Readings Histogram of vin Readings

3000 10000
σ = 1.75mA σ = 2.73mV
2500
8000

2000
6000
FREQUENCY

FREQUENCY

1500
4000
1000

2000
500

0 0
1.150 1.155 1.160 1.165 1.170 1.175 11.94 11.95 11.96 11.97 11.98 11.99
INPUT CURRENT (A) INPUT VOLTAGE (V)
4162L G23 4162L G24

Rev A

For more information [Link] 9

LTC4162-L
PIN FUNCTIONS
BOOST (Pin 1): Gate-Drive bias for the high side switch in NTCBIAS (Pin 9): NTC thermistor bias output. Connect a
the switching regulator. This pin provides a pumped bias low temperature coefficient bias resistor between NTCBIAS
voltage relative to SW. The voltage on this pin is charged and NTC, and a thermistor between NTC and GND. The
up through an internal diode from INTVCC. A 22nF multi- bias resistor should be equal in value to the nominal value
layer ceramic capacitor is required from SW to BOOST. of the thermistor. The LTC4162 applies 1.2V to this pin
INTVCC (Pin 2): Bypass pin for the internal 5V regulator. during NTC measurement and expects a thermistor β
This regulator provides power to the internal analog cir- value of 3490K. Higher β value thermistors can be used
cuitry. A 4.7µF multilayer ceramic capacitor is required with simple circuit modifications.
from INTVCC to GND. NTC (Pin 10): Thermistor input. The NTC pin connects to
VOUTA (Pin 3): Analog system power pin. VOUTA powers a negative temperature coefficient thermistor to monitor
the majority of circuits on the LTC4162. A 0.1µF multilayer the temperature of the battery. The voltage on this pin
ceramic capacitor is required from VOUTA to GND. is digitized by the analog to digital converter to qualify
battery charging and is available for readout via the I2C
CLN (Pin 4): Connection point for the negative terminal port. A low drift bias resistor is required from NTCBIAS
of the sense resistor that measures and regulates input to NTC and a thermistor is required from NTC to ground.
current by limiting charge current.
RT (Pin 11): Switching regulator frequency control pin.
CLP (Pin 5): Connection point for the positive terminal The RT pin controls the switching regulator's internal
of the sense resistor that measures and regulates input oscillator frequency by placing a resistor from RT to GND.
current by limiting charge current.
SMBALERT (Pin 12): Interrupt output. This open drain
INFET (Pin 6): Gate control output pin for an input reverse output pulls low when one or more of the programmable
blocking external N-channel MOSFET between VIN and alerts is triggered.
VOUT.
SCL (Pin 13): Open drain clock input for the I2C port. The
VIN (Pin 7): Supply voltage detection and INFET charge I2C port input levels are scaled with respect to DVCC for
pump supply for the INFET/BATFET PowerPath. When I2C compliance.
voltage at VIN is detected as being high enough to charge a
SDA (Pin 14): Open drain data input/output for the I2C
battery, the INFET charge-pump is activated and the BATFET
port. The I2C port input levels are scaled with respect to
charge-pump is deactivated thereby powering VOUTA from
the input supply through an external NMOS transistor and DVCC for I2C compliance.
also starting a charge cycle. A 0.1µF multilayer ceramic DVCC (Pin 15): Logic supply for the I2C port. DVCC sets the
capacitor is required from VIN to GND. reference level of the SDA and SCL pins for I2C compli-
ance. It should be connected to the same power supply
VCC2P5 (Pin 8): Bypass pin for the internal 2.5V regula-
as the SDA and SCL pull up resistors.
tor. This regulator provides power to the internal logic
circuitry. A 1µF multilayer ceramic capacitor is required SYNC (Pin 16): Optional external clock input for the switch-
from VCC2P5 to GND. ing battery charger. The switching battery charger will
lock to a square wave or pulse on this pin that is close to
the frequency programmed by the RT pin. Ground SYNC
if this feature is not needed.

Rev A

10 For more information [Link]

LTC4162-L
PIN FUNCTIONS
CELLS0 (Pin 17): Cell count selection pin. Used in com- PGND (Pins 23,24): Power ground pins. These pins should
bination with CELLS1, this pin sets the total number of be connected to a copper pour that forms the return for
series cells to be charged. The pin should be strapped to the VOUT bypass capacitor on the top layer of the printed
either INTVCC, VCC2P5 or GND to represent one of three circuit board.
possible states. See Table 5.
SW (Pin 25, 26): Switching regulator power transmission
CELLS1 (Pin 18): Cell count selection pin. Used in com- pins. The SW pins deliver power from the VOUT pins to the
bination with CELLS0, this pin sets the total number of battery via the step-down switching regulator. An inductor
series cells to be charged. The pin should be strapped to should be connected from SW to a sense resistor at CSP.
either INTVCC, VCC2P5 or GND to represent one of three See the Applications Information section for a discussion
possible states. See Table 5. of inductor value and current rating.
BATSENS+ (Pin 19): Positive terminal battery sense pin. VOUT (Pin 27, 28): Switching regulator input pins. The
BATSENS+ should Kelvin sense the positive terminal of the VOUT pins deliver power to the switching charger. Having
battery for optimized charging. A 10µF multilayer ceramic extremely high frequency current pulses, bypassing of
capacitor is required from BATSENS+ to ground. the VOUT pins should take precedence over all other PCB
layout considerations. A bypass capacitor of 10µF is a
CSN (Pin 20): Connection point for the negative terminal
good starting point.
of the current sense resistor used to measure and limit
charge current. AGND (Exposed PAD, Pin 29): Analog ground pin. This
is the ground pin used to return all of the analog circuitry
CSP (Pin 21): Connection point for the positive terminal
inside the LTC4162 and should be connected to an analog
of the current sense resistor used to measure and limit
ground pour that is common with PGND (pins 23 and 24).
charge current.
It should also be connected to a ground plane on layer 2
BATFET (Pin 22): Gate control pin for a reverse blocking of the PCB to which all of the analog components return
external N-channel MOSFET between the battery and VOUT. such as the RT resistor and the INTVCC and VCC2P5 by-
pass capacitors.

Rev A

BATSENS+ VBATDIV –
19 RT
PRESCALER OSCILLATOR 11
+
DVCC D/A SYNC
15 16
SMBALERT
12
SCL I2C
13
SDA
14
CELLS0
17 VOUTA
LOGIC 3
CELLS1
18
29R INTVCC LDO
NTCBIAS INTVCC
9 1.2V VOUTDIV 2
R 2.5V LDO
NTC
10 VCC2P5
VREF 8
VBATDIV
VOUTDIV AGND
29
VINDIV A/D
I_BAT
I_IN
T_DIE

4162L BD

Rev A

12 For more information [Link]

LTC4162-L
ESD DIAGRAM
INFET DVCC
6 15

VIN SCL
7 13
SDA
14
VOUTA SMBALERT
3 12

CLN
4

CLP
5
VCC2P5
8
BATFET
22
NTCBIAS
9
BATSENS+ NTC
19 10
RT
11
CSP
21

CSN
20
VOUT
27
VOUT
28
SYNC
16
SW CELLS0
25 17
SW CELLS1
26 18

PGND INTVCC
23 2
PGND
24
BOOST
1
AGND
29
4162L ESD

Rev A

For more information [Link] 13

LTC4162-L
TIMING DIAGRAM

SDA

tSU(DAT) tBUF
tHD(DAT) tSU(STA)
tLOW tHD(STA) tSU(STO)

SCL

tHD(STA) tf tf tSP
START tHIGH REPEATED START STOP START
CONDITION CONDITION CONDITION CONDITION 4162 TD

I2C SMBus Legend

S START CONDITION
Sr REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
A ACKNOWLEDGE
N NACK
P STOP CONDITION
PEC* PACKET ERROR CODE
MASTER TO SLAVE

SLAVE TO MASTER

SMBus WRITE WORD PROTOCOL

S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A P

SMBus WRITE WORD WITH PEC PROTOCOL

S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A PEC* A P

SMBus READ WORD PROTOCOL

S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH N P

SMBus READ WORD WITH PEC PROTOCOL

S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH A PEC* N P

SMBus ALERT RESPONSE ADDRESS PROTOCOL

S ALERT RESPONSE ADDRESS Rd A DEVICE ADDRESS Rd N P

SMBus ALERT RESPONSE ADDRESS PROTOCOL WITH PEC

S ALERT RESPONSE ADDRESS Rd A DEVICE ADDRESS Rd A PEC* N P

*USE OF PACKET ERROR CHECKING IS OPTIONAL

Rev A

14 For more information [Link]

LTC4162-L
OPERATION
Introduction so that system parameters can be varied as needed. All
The LTC4162 is an advanced power manager and switch- of the status change events are maskable for maximum
ing battery charger utilizing a high efficiency synchronous flexibility. For example, features such as battery presence
step-down switching regulator. detection and battery impedance measurement are easily
enabled.
Using multiple feedback control signals, power is deliv-
ered from the input to the battery by a 1.5MHz constant- To eliminate battery drain between manufacture and sale,
frequency step-down switching regulator. The switching a ship-and-store feature reduces the already low battery
regulator reduces output power in response to one of its drain current even further.
four regulation loops including battery voltage, battery The input undervoltage control loop can be engaged to
charge current, input current and input voltage. keep the input voltage from decreasing beyond a minimum
The switching regulator is designed to efficiently transfer level when a resistive cable or power limited supply such
power from a variety of possible sources, such as USB as a solar panel is providing input power. A maximum
ports, wall adapters and solar panels, to a battery while power point tracking algorithm using this control loop
minimizing power dissipation and easing thermal budget- can be deployed to maximize power extraction from solar
ing constraints. Since a switching regulator conserves panels and other resistive sources.
power, the LTC4162 allows the charge current to exceed Finally, the LTC4162 has a digital subsystem that provides
the source's output current, making maximum use of the substantial adjustability so that power levels and status
allowable power for battery charging without exceeding information can be controlled and monitored via the
the source's delivery specifications. By incorporating input conventional I2C port.
voltage and system current measurement and control
systems, the switching charger ports seamlessly to these LTC4162 Digital System Overview
sources without requiring application software to monitor The LTC4162 contains an advanced digital system which
and adjust system loads. By decoupling the system load can be accessed using the I2C port. Use of the I2C port
from the battery and prioritizing power to the system, is optional, it can be used extensively in the application
the instant-on PowerPath architecture ensures that the or not at all, as dictated by the application requirements.
system is powered upon input power arrival, even with a Cell count, charge current, input current regulation and
completely dead battery. switching charger frequency are all externally configurable
Two low power charge pumps drive external MOSFETs to without using the I2C port. For applications requiring the
provide low loss power paths from the input supply and LTC4162's advanced digital features, the I2C port provides
battery to the system load while preventing the system a means to use status and A/D telemetry data from the
node from back-driving the input supply or overcharging measurement system, monitor charger operation, config-
the battery. The power path from the battery to the system ure charger settings (e.g. charge voltage, charge current,
load guarantees that power is available to the system even temperature response, termination algorithm, etc), enable,
if there is insufficient or absent power from VIN. A wide disable, read and clear alerts, activate the low power ship
range of input current settings as well as battery charge mode, and enable/disable the battery charger.
current settings are available by software control and by
choosing the values of input and charge current sense Power Path Controller
resistors RSNSI and RSNSB. The LTC4162 features input and output N-channel MOS-
A measurement subsystem periodically monitors and FET charge pump gate drivers. These drivers make up a
reports on a large collection of system parameters via the dual unidirectional power path system that allows power
I2C port. An interrupt subsystem can be enabled to alert to be delivered to the system load by either the input
the host microprocessor of various status change events supply or the battery, whichever is greater. Only one of
Rev A

For more information [Link] 15

LTC4162-L
OPERATION
the external MOSFETs will be enabled at a time. If VIN is where icharge_jeita_2 through icharge_jeita_6 each range
more than 150mV above BATSENS+, the MOSFET from from 0 to 31.
the input to the system load will be enabled and the one If en_jeita is not set:
from the system load to BATSENS+ will block conduction
preventing overcharging of the battery. If VIN falls more 1mV
ICHARGE = (ch arg e _ current _ setting + 1)
than 20mV below BATSENS+ the MOSFET from the input R SNSB

supply to the system load will be disabled preventing
reverse conduction and the MOSFET from BATSENS+ to where charge_current_setting ranges from 0 to 31.
the system load will be enabled powering downstream If en_jeita is set, the charge voltage is given by the ex-
circuitry from the battery. It is important not to back drive pression:
VOUT as one or the other of the power path MOSFETs will
always be enabled. VCHARGE = (3.8125V + 12.5mV • vcharge_jeita_x) •
cell_count
Step Down Switching Battery Charger where vcharge_jeita_2 through vcharge_jeita_6 each
The LTC4162’s battery charger is based on a very efficient range from 0 to 31.
synchronous step down switching regulator. As with any
If en_jeita is not set:
modern battery charger, the LTC4162 incorporates both
constant-current and constant-voltage feedback control VCHARGE = (3.8125V + 12.5mV • vcharge_setting) •
loops to prevent overcharging. The switching charger can cell_count
charge either a single cell or a battery of up to eight series where vcharge_setting ranges from 0 to 31.
Lithium-Ion/Polymer cells.
Beyond the conventional constant-current and constant-
Normal charging begins with a constant current until the voltage control loops, the LTC4162 also has the ability to
battery reaches its target voltage. The charge current is
monitor and control both input current and input voltage,
determined by the combination of the sense resistor,
regulating battery charge power based on any one of these
RSNSB, placed in series with the inductor and the servo
four control loops. Power limit is prioritized based on the
control voltage set by either icharge_jeita_2 through
lowest set-point of the group. For example, if the combined
icharge_jeita_6 with en_jeita set or just charge_cur-
system load plus battery charge current is large enough
rent_setting if en_jeita is cleared. An internal soft-start
to cause the switching charger to reach the programmed
algorithm ramps up the charge current setting from zero
to its present setting. Once the battery voltage reaches the input current limit, the input current limit will reduce charge
programmed voltage limit the constant-current control current to limit the voltage across the input sense resistor,
loop hands off to the constant-voltage control loop. The RSNSI, to the iin_limit_target. Even if the charge current
final battery voltage is set with the combination of either is programmed to exceed the allowable input current, the
vcharge_jeita_2 through vcharge_jeita_6 with en_jeita input current due to charge current will not be violated;
set or with just vcharge_setting if en_jeita is cleared. The the charger will reduce its current as needed. Similarly,
cell_count, controlled by the CELLS0 and CELLS1 pins, the input voltage limit loop, controlled by input_under-
is a charge voltage multiplier so that multiple series cells voltage_setting, can be used to prevent resistive power
can be charged. sources such as a solar panel from dragging the input
voltage down below its under-voltage lockout level.
If en_jeita is set, the charge current is given by the ex-
pression: Only target values can be programmed with the I2C port.
The LTC4162 uses the target values as a starting point from
1mV
ICHARGE = (ich arg e _ jeita _ x + 1) which the charging algorithms calculate the actual values
R SNSB to be applied to the DACs to support functions such as
Rev A

16 For more information [Link]

LTC4162-L
OPERATION
temperature compensated charge voltages and currents, Optionally, the LTC4162 includes a maximum power
maximum power point tracking, charger soft starting, point tracking (MPPT) algorithm to find and track the
etc. The target value registers are read/write whereas the input_undervoltage_dac value that delivers the maximum
actual DAC value registers, icharge_dac, vcharge_dac, charge current to the battery. If mppt_en is set, the MPPT
iin_limit_dac and input_undervoltage_dac are read only. algorithm performs a global sweep of input_undervolt-
Due to its all NMOS switch design, a small charge pump age_dac values, measuring battery charge current at each
capacitor is required from SW to BOOST to provide high setting. Once the sweep is complete, the LTC4162 applies
the input_undervoltage_dac value corresponding to the
side boosted drive for the top switch.
maximum battery charge current ibat (i.e. the maximum
Input Current Regulation power point). The LTC4162 then tracks small changes
in the maximum power point by slowly dithering the
Input current control limits loading on the input source input_undervoltage_dac. The LTC4162 performs a new
during periods of high system demand by sacrificing charge global sweep of input_undervoltage_dac values every
current. Note that the LTC4162 only has the authority to 15 minutes, applies the new maximum power point, and
reduce charge current to zero and cannot further reduce resumes dithering at that point. Alternatively, the global
input current below the system load current. The input sweep will run immediately, bypassing the 15 minute wait,
current limit is controlled by a combination of the sense if ibat changes by more that 25%. With mppt_en, a solar
resistor, RSNSI, from CLP to CLN and either the default panel can be used as a suitable power source for charg-
32mV servo voltage or a lower value set by iin_limit_target. ing a battery and powering a load. The MPPT algorithm
The servo voltage across the sense resistor divided by the may not work for all solar panel applications and does not
resistor's value determines the input current regulation have to be used. Alternatively a solar panel can be used
set point. A 10mΩ resistor, for example, would have an without the MPPT algorithm by setting the input_under-
upper input current limit of 3.2A using the default 32mV voltage_setting value to match the optimum loaded solar
servo voltage. iin_limit_target has 6 bit resolution giving panel voltage, but significant shadows or drops in light
adjustable values from 500µV to 32mV in 500µV steps and will likely result in suboptimum power delivery.
can be calculated in Amperes, by the following expression:
Note that, due to the Power Path topology, current can flow
500μV from the input to the system load without being controlled
IINLIM = (iin _ limit _ t arg et + 1)
R SNSI by the LTC4162's switching charger. Therefore, the MPPT
algorithm does not have full authority to track and find
where iin_limit_target ranges from integer values of 0 to 63. the maximum power point under all conditions. To obtain
Input Undervoltage Regulation and Solar Panel complete Maximum Power Point operation, it may be
Maximum Power Point Tracking (MPPT) necessary to forgo the Power Path feature of the LTC4162
and connect the system load directly to the battery pack. In
The LTC4162 also contains an undervoltage control loop this configuration, the LTC4162 has full authority to track
that allows it to tolerate a resistive connection to the input the maximum power point of the solar panel.
power source by automatically reducing charge current
as the VIN pin drops to input_undervoltage_setting. This The input under voltage value, in Volts, will be given by
circuit helps prevent UVLO oscillations by linearly regulat- the following expression:
ing the input voltage above the LTC4162's undervoltage VINLIM = (input_undervoltage_setting + 1) • 140.625mV
lockout level.
where input_undervoltage_setting ranges from integer
values of 0 to 255.

Rev A

For more information [Link] 17

LTC4162-L
OPERATION
System Controls its 16-bit signed two's complement results are stored in
The switching battery charger can be disabled by setting registers accessible via the I2C port. The seven channels
suspend_charger. This might be necessary, for instance, to measured by the ADC each take approximately 1.6ms to
pass USB Suspend compliance testing. suspend_charger convert. The maximum range of the 16 bit ΔΣ A/D con-
should be used with caution as a low battery situation verter is ±1.8V and it has an internal span term of 18191
could prevent the system processor from being able to counts per Volt. It measures each of the above parameters
through different paths giving different sensitivity terms
clear it and may require a factory service call to remove
for each measurement as summarized in Table 1.
and replace the battery.
Battery Voltage Measurement
Input Overvoltage Protection
Battery voltage is measured through a resistive voltage
The LTC4162 has over-voltage detection on its input. If
divider whose attenuation ratio is based on the cell_count.
VIN exceeds approximately 38.6V as indicated by vin_ovlo,
The result is reported in vbat. The divider ratio is BAT-
the switching charger will stop delivering power. The
SENS+/(3.5 • cell_count) making the A/D span term
charger will resume switching if VIN falls below roughly
3.5 • cell_count/18191 or 192.4µV • cell_count per LSB
37.2V. The overvoltage detection cutoff circuit provides
where cell_count varies from 1 to 8. An alert may be
only modest over voltage protection and is not intended set on battery voltage by setting the vbat based value
to prevent damage in all circumstances. vbat_lo_alert_limit or vbat_hi_alert_limit and setting
en_vbat_lo_alert or en_vbat_hi_alert. These alerts are
Measurement Subsystem
indicated by vbat_lo_alert or vbat_hi_alert and are cleared
The LTC4162 includes a 16-bit ΔΣ A/D converter and signal by writing them to 0.
multiplexer to monitor numerous analog parameters. It
can measure the voltages at vin, vbat and vout, the input Input Voltage Measurement
current (voltage between CLP and CLN), iin, the battery Input voltage is measured through a 30:1 resistive volt-
charge current (voltage between CSP and CSN), ibat, the age divider making the A/D span term for input voltage
battery pack thermistor_voltage, its own internal die_temp measurements 30/18191 or 1.649mV/LSB and is digitized
and, once a charge cycle begins, the series resistance of to vin. An alert may be set on input voltage by setting the
the battery, bsr. To save battery current, the measure- value vin_lo_alert_limit or vin_hi_alert_limit and setting
ment system is disabled if the battery is the only source en_vin_lo_alert or en_vin_hi_alert. These alerts are indi-
of power (vin_gt_vbat = 0). This can be overridden with cated by vin_lo_alert and vin_hi_alert and are cleared by
force_telemetry_on. The A/D converter is automatically writing them to 0.
multiplexed between all of the measured channels and
Table 1. Measurement Subsystem LSB Sizes
MEASUREMENT UNITS REGISTER SYMBOL LSB SIZE OFFSET
BATTERY VOLTAGE V vbat 192.4µV • cell_count
INPUT VOLTAGE V vin 1.649mV
OUTPUT VOLTAGE V vout 1.653mV
INPUT CURRENT A iin 1.466µV/RSNSI
BATTERY CURRENT A ibat 1.466µV/RSNSB
DIE TEMPERATURE °C die_temp 0.0215°C 264.4°C
BATTERY IMPEDANCE Ω bsr RSNSB • cell_count/500
THERMISTOR VOLTAGE V thermistor_voltage 45.833µV/V

Rev A

18 For more information [Link]

LTC4162-L
OPERATION
VOUT Voltage Measurement on input current by setting the value iin_hi_alert_limit
Output voltage is measured through a 30.07:1 resistive and setting the en_iin_hi_alert. This alert is indicated by
voltage divider making the A/D span term for output volt- iin_hi_alert and is cleared by writing it to 0.
age measurements 30.07/18191 or 1.653mV/LSB and is
digitized to vout. An alert may be set on output voltage by Battery Series Resistance (BSR) Measurement
setting the value vout_lo_alert_limit or vout_hi_alert_limit The LTC4162 can optionally measure the series resistance
and setting en_vout_lo_alert or en_vout_hi_alert. These of the battery stack or cell. If run_bsr is set, the LTC4162
alerts are indicated by vout_lo_alert and vout_hi_alert and momentarily suspends the battery charger and calculates
are cleared by writing them to 0. the battery series resistance by dividing the voltage change
(charging vs not charging) by the measured charge current
Battery Current Measurement (bsr_charge_current).
Battery current is measured with a current sense resistor The per-cell resistance value is reported in bsr and the
between the CSP and CSN pins. An amplifier with a gain of charge current observed during the measurement is re-
37.5 amplifies this signal and refers it to ground internally ported in bsr_charge_current. The LTC4162 automatically
so that the A/D converter can measure it. The sensed bat- resets run_bsr after the bsr measurement is complete.
tery current is therefore given by IBAT • RSNSB • 37.5. For The total battery series resistance value is proportional to
a 10mΩ RSNSB current sense resistor, the A/D sensitivity the charge current sense resistor, RSNSB, as well as the
is 1/(18191 • 10mΩ • 37.5) or 146.6µA/LSB. The battery cell_count, and can be computed in Ω from the expression:
current measurement system has a built in commutator.
While charging a battery, two's complement number ibat bsr • cell _ count • R SNSB
RBAT (Ω) =
will be positive representing current into the battery. When 500
the battery charger is disabled or terminated, as detected Higher bsr_charge_current during a bsr measurement
by charger_suspended, the commutator is activated and results in a more accurate bsr measurement. Very low
ibat will be negative, representing current out of the bat- values of bsr_charge_current may adversely impact the
tery. An alert may be set on the ibat measurement by accuracy of the bsr measurement. If charge current is
setting the desired value in ibat_lo_alert_limit and setting less than C/10 (bsr_charge_current < icharge_over_10),
en_ibat_lo_alert. While charging, ibat_lo_alert_limit can bsr_questionable will be set indicating that bsr_charge_
be used to detect when the charge current has dropped current during the bsr test was less than optimum for an
below a given threshold. When charger_suspended, if set accurate reading. Recall that full charge current typically
to a negative number, ibat_lo_alert_limit can be used to flows at the beginning of a charge cycle (presuming the
detect if the battery load has exceeded a given threshold. battery is more deeply depleted) and will diminish when
This alert is indicated by ibat_lo_alert and is cleared by the charger enters the constant voltage phase of charging.
writing it to 0.
If run_bsr is set to 1 and the battery charger is not currently
Input Current Measurement running, then the LTC4162 will be queued to perform the
bsr measurement only after the start of the next charge
Input current is measured with a current sense resistor
cycle. An alert can be set with en_bsr_done_alert to gener-
between the CLP and CLN pins. An amplifier with a gain of
ate a bsr_done_alert indicating that a bsr measurement
37.5 amplifies this signal and refers it to ground internally
is complete and that the result is available. A bsr_hi_alert
so that the A/D converter can measure it. The sensed
may also be set on battery series impedance by writing a
input current is therefore given by IIN • RSNSI • 37.5. For
bsr_hi_alert_limit and setting en_bsr_hi_alert. Again, the
a 10mΩ RSNSI current sense resistor, the A/D sensitivity
bsr reading is the per-cell battery resistance and should be
is 1/(18191 • 10mΩ • 37.5) or 146.6µA/LSB. The input
scaled by cell_count or, consequently, the target total re-
current is digitized to iin. An upper limit alert may be set
Rev A

For more information [Link] 19

LTC4162-L
OPERATION
sistance threshold for bsr_hi_alert_limit should be divided ing, charger_state will switch to bat_missing_fault and
by cell_count before being written to bsr_hi_alert_limit. charging will halt. Either a thermistor_voltage_lo_alert or
thermistor_voltage_hi_alert may be set with en_thermis-
bsr_done_alert and bsr_hi_alert are cleared by writing
tor_voltage_lo_alert or en_thermistor_voltage_hi_alert,
them to 0.
both of which are cleared by writing them to 0.
Die Temperature Measurement The temperature vs resistance curve of a thermistor can
The LTC4162 has an integrated die temperature sensor be obtained from thermistor manufacturers in either table
that is monitored by the A/D converter and is digitized to form or estimated by applying the modified Steinhart-Hart
die_temp. The die temperature is derived from an internal equation:
circuit and follows the equation: B C D
(A+ + + )
TC +273.15 (T +273.15)2 (T +273.15)3
TDIE(°C) = die_temp • 0.0215°C/LSB – 264.4°C C C
RNTC = R 25 • e
An alert may be set on die temperature by setting the value
Where R25 is the thermistor's resistance at 25°C and A,
die_temp_hi_alert_limit and setting en_die_temp_hi_alert.
B, C and D are provided by the thermistor manufacturer
This alert is indicated by die_temp_hi_alert and is cleared
and TC is the temperature in °C.
by writing it to 0.
The temperature of the thermistor is computed from its
To set the die_temp_hi_alert_limit, compute the threshold
resistance value by the complementary Steinhart-Hart
value from:
expression where A1, B1, C1 and D1 are also provided
T (°C ) +264.4°C by the thermistor manufacturer.
die _ temp _ hi _ alert _ limit = DIE
0.0215°C/LSB 1
TC = (1)
RNTC R R
Battery Temperature (NTC Thermistor) Measurement A 1 +B1 ln( ) + C1 ln2 ( NTC ) + D1 ln3 ( NTC )
R 25 R 25 R 25
To measure the battery temperature using a thermistor,
connect the thermistor, RNTC, normally being located in −273.15o C
the battery pack, between the NTC pin and ground, and a Alternatively, the more common but less accurate con-
low drift bias resistor, RNTCBIAS, between NTCBIAS and densed version of Steinhart-Hart using the ubiquitous β
NTC. RNTCBIAS should be a 1% or better resistor with a parameter may be employed:
value equal to the value of the chosen thermistor at 25°C
1 1
(R25). The LTC4162 applies an excitation voltage of 1.2V to −β25/85 ( − )
RNTCBIAS to measure the thermistor value. The thermistor 298.15 C TC +273.15 o C
o
RNTC = R 25 • e
measurement result is available at thermistor_voltage. To
minimize battery stress due to charging at temperature Where again, R25 is the thermistor's resistance at 25°C
extremes, the LTC4162 has both a simple and a more and several β values are provided by the thermistor manu-
advanced JEITA (Japan Electronics and Information facturer, one for each of a number of temperature ranges.
Technology Industries Association) temperature qualified The inverse β form is:
charging algorithm. If the application does not require tem-
perature controlled charging, then the thermistor should be β 25/85
TC = – 273.15o C (2)
replaced with a resistor of equal value to the bias resistor RNTC β 25/85
ln( )+
RNTCBIAS to continuously simulate 25°C. If the thermistor is R 25 298.15 o C
found to be open (thermistor_voltage > open_thermistor)
either during the battery detection test or during charg-

Rev A

20 For more information [Link]

LTC4162-L
OPERATION
The LTC4162 thermistor measurement system is designed and telemetry_speed to tel_high_speed. telemetry_valid
specifically for a thermistor with a β25/85 value of 3490K indicates when fresh telemetry readings are available. To
and returns thermistor_voltage where: avoid polling for telemetry_valid a telemetry_valid_alert
can be set with en_telemetry_valid_alert. Once the read-
RNTC
thermistor _ voltage = 18191• 1.2 • ing is obtained, force_telemetry_on can be cleared or
RNTC +RNTCBIAS telemetry_speed set to tel_low_speed for power savings.
where typically RNTCBIAS is set equal to R25, the 25°C value Low Power Telemetry
of the thermistor. To arrive at the thermistor's temperature
in °C from thermistor_voltage substitute RNTC from: If input power is available (vin_gt_vbat = 1), and the battery
is being charged, the telemetry system will be in its high
thermistor_ voltage speed mode returning results at a rate of roughly once
RNTC = RNTCBIAS •
18191• 1.2 − thermistor_ voltage per 11ms. If, on the other hand, charging has terminated
normally or paused due to battery temperature out of
into Equation 1 or Equation 2.
range, the telemetry system will drop back to a rate of
For thermistors with a β25/85 value higher than 3490K about once every 5 seconds to save power. When input
see Alternate Thermistors and Biasing in the Applications power is not available (vin_gt_vbat = 0) it is still possible
Information section. to collect telemetry data by setting force_telemetry_on. To
save power in this mode the telemetry system will default
Output Current Measurement to the lower speed 5 second mode. To force the higher
There is no sense resistor dedicated to measuring output telemetry rate, and suffer the higher quiescent current
current but its value can be obtained nonetheless. Output of roughly 2.5mA, the telemetry_speed can be set to the
current is delivered from the input supply if vin_gt_vbat higher ~11ms rate by setting it to tel_high_speed.
is true and from the battery if it is false.
Configurable Limit Alert Subsystem
If vin_gt_vbat is true and the battery charger is enabled
(en_chg is true) then the input current measurement will The I2C port also supports the SMBus SMBALERT pro-
be the sum of current to the switching charger and the tocol, including the Alert Response Address. An alert can
output load. In this instance the switching charger will optionally be generated if a monitored parameter exceeds
need to be disabled with suspend_charger to obtain an a programmed limit or if a selected battery charger_state
output current reading. It's also possible that the charger or any of a wide number of other charge_status change or
may already be terminated. If en_chg is false then set fault events occur. This off-loads much of the continuous
telemetry_speed to tel_high_speed, wait 20ms or more, monitoring from the system's microcontroller and onto the
and record iin as output current. If en_chg is true then set LTC4162; reducing bus traffic and microprocessor load.
both suspend_charger and force_telemetry_on to 1 and The SMBALERT pin is asserted (pulled low) whenever
telemetry_speed to tel_high_speed, wait 20ms or more an enabled alert occurs. After asserting an interrupt, the
for at least one telemetry cycle, and again record iin as LTC4162 responds to the host's Alert Response Address
output current. suspend_charger should then be cleared. (ARA = 0b0001100[1]) with its own read address. If an-
Note that suspending the charger resets the tchargetimer other part with a pending alert and a lower address also
and tcvtimer termination timers to 0. responds, that part wins the arbitration and the LTC4162
On the other hand if vin_gt_vbat is false then the output will stop responding to this ARA, keeping its SMBALERT
current will be delivered from the battery and its value can be pin asserted. Only a response of the LTC4162's complete
obtained from –ibat. Since vin_gt_vbat is low, the telemetry read address will clear the LTC4162's SMBALERT signal.
system will be disabled and the ibat reading will be stale. To This allows the system to have many parts share a common
enable the telemetry system, set force_telemetry_on to 1 interrupt line. If multiple parts are asserting the SMBALERT
Rev A

For more information [Link] 21

LTC4162-L
OPERATION
Table 2. Summary of Limit Alerts Registers
ALERT VALUE SETTING (0x01 – 0x0C) EN_LIMIT_ALERTS_REG LIMIT_ALERTS_REG
vin_hi_alert_limit en_vin_hi_alert vin_hi_alert
vin_lo_alert_limit en_vin_lo_alert vin_lo_alert
thermistor_voltage_hi_alert_limit en_thermistor_voltage_hi_alert thermistor_voltage_hi_alert
thermistor_voltage_lo_alert_limit en_thermistor_voltage_lo_alert thermistor_voltage_lo_alert
bsr_hi_alert_limit en_bsr_hi_alert bsr_hi_alert
die_temp_hi_alert_limit en_die_temp_hi_alert die_temp_hi_alert
ibat_lo_alert_limit en_ibat_lo_alert ibat_lo_alert
iin_hi_alert_limit en_iin_hi_alert iin_hi_alert
vout_hi_alert_limit en_vout_hi_alert vout_hi_alert
vout_lo_alert_limit en_vout_lo_alert vout_lo_alert
vbat_hi_alert_limit en_vbat_hi_alert vbat_hi_alert
vbat_lo_alert_limit en_vbat_lo_alert vbat_lo_alert
NA en_bsr_done_alert bsr_done_alert
NA en_telemetry_valid_alert telemetry_valid_alert

Table 3. Summary of Charger State Alerts

CHARGER_STATE_REG EN_CHARGER_STATE_ALERTS_REG CHARGER_STATE_ALERTS_REG
bat_detect_failed_fault en_bat_detect_failed_fault_alert bat_detect_failed_fault_alert
battery_detection en_battery_detection_alert battery_detection_alert
charger_suspended en_charger_suspended_alert charger_suspended_alert
precharge en_precharge_alert precharge_alert
cc_cv_charge en_cc_cv_charge_alert cc_cv_charge_alert
ntc_pause en_ntc_pause_alert ntc_pause_alert
timer_term en_timer_term_alert timer_term_alert
c_over_x_term en_c_over_x_term_alert c_over_x_term_alert
max_charge_time_fault en_max_charge_time_alert max_charge_time_fault_alert
bat_missing_fault en_bat_missing_fault_alert bat_missing_fault_alert
bat_short_fault en_bat_short_fault_alert bat_short_fault_alert

Table 4. Summary of Charger Status Alerts

CHARGE_STATUS_REG EN_CHARGE_STATUS_ALERTS_REG CHARGE_STATUS_ALERTS_REG
constant_voltage en_constant_voltage_alert constant_voltage_alert
constant_current en_constant_current_alert constant_current_alert
iin_limit_active en_iin_limit_active_alert iin_limit_active_alert
vin_uvcl_active en_vin_uvcl_active_alert vin_uvcl_active_alert
thermal_reg_active en_thermal_reg_active_alert thermal_reg_active_alert
ilim_reg_active en_ilim_reg_active_alert ilim_reg_active_alert

Rev A

22 For more information [Link]

LTC4162-L
OPERATION
signal then multiple reads from the ARA are needed. For proceeds with battery charger soft-start. If the battery
more information refer to the SMBus specification. voltage does not remain stable, the LTC4162 proceeds
After the ARA process is complete, alert bits can be cleared with a battery open/short test. The battery is charged at
by individually writing them to 0 and writing the remaining minimum charge current for one to two seconds. Abnor-
mal results from the battery detection test result in char-
bits in the register to 1. This preserves any other pending
ger_state becoming bat_missing_fault, bat_short_fault or
alert bits as writing 1s to the alert registers are ignored.
bat_detect_failed_fault and will prevent further charging.
Series Cell Count Selection A charger_state of bat_missing_fault will also occur if
the thermistor is open or has a very high value (thermis-
Cell count selection of up to eight series cells is made via tor_voltage > open_thermistor). Programmable interrupts
the CELLS1 and CELLS0 pins. CELLS1 and CELLS0 should en_bat_short_fault_alert, en_bat_missing_fault_alert and
be pin strapped to either GND, VCC2P5, or INTVCC to make en_bat_detect_failed_fault_alert can be set to generate an
the cell_count selection (see Table 5). For added safety, SMBALERT if one of these cases occurs. In the event of a
cell_count can be read back from the I2C port. The GND/ battery detection fault, the battery detection test will retry
GND combination will result in a cell_count_err and will every 30 seconds.
inhibit charging. Note that the number of cells multiplied
by their expected maximum cell voltage during charging Battery Charger Soft-Start
cannot exceed VIN – VIN_DUVLO.
The LTC4162 soft starts charge current by ramping ich-
Table 5. CELLS0 and CELLS1 Pin Mapping to Series Cell Count
arge_dac from 0 to its target charge current setting at a
CELLS1 CELLS0 cell_count nominal rate of 400µS per icharge_dac LSB. This results
INTVCC INTVCC 1 in a maximum charge current soft start time of 31 • 400µs
INTVCC VCC2P5 2 or 12.4ms. Any time the battery charger needs to change
INTVCC GND 3 its charge current setting up or down, the ramp routine is
VCC2P5 INTVCC 4 invoked. The charge current target is derived from either
VCC2P5 VCC2P5 5 charge_current_setting or the JEITA temperature qualified
VCC2P5 GND 6 charging system, icharge_jeita_2 through icharge_jeita_6
GND INTVCC 7 (See Advanced JEITA Temperature Controlled Charging).
GND VCC2P5 8
Low Battery
When charging stacks of two or more cells in series it is
When a charge cycle begins, The LTC4162 first determines
important to consult with the battery manufacturer to ascer-
if the battery is deeply discharged. If the BATSENS+ pin
tain requirements pertaining to cell balancing. Repeatedly
voltage is lower than about 2.5V, the battery charger
charging series stacks of cells without balancing is usually
delivers roughly 10mA directly from INTVCC. This operat-
degenerative and typically leads to increased mismatch
ing mode is mainly used to pull a pack protected battery
accompanied with shorter battery life. For high reliability
out of protection mode. When the BATSENS+ pin voltage
applications an auxiliary battery balancer is recommended.
reaches 2.5V, charging hands over to the switching battery
Battery Detection charger. Above 2.5V absolute level but below about 2.85V
per cell_count the LTC4162 applies a preconditioning
The LTC4162 begins a charging cycle by performing a 2-4 charge setting equal to approximately C/10 (icharge_dac
second battery detection test, during which a 1mA load is = 3), and reports precharge. When the battery voltage
drawn from the battery followed by a small charge current exceeds 2.85V per cell_count, the LTC4162 proceeds to
being sent to the battery. If the battery voltage remains the full constant-current/constant-voltage charging phase
stable during the battery detection test, the LTC4162 and reports cc_cv_charge.

Rev A

For more information [Link] 23

LTC4162-L
OPERATION
Constant-Current Charging programmed to any temperature within the LTC4162's
When the battery voltage is above 2.85V per cell_count, the operating range.
charger will attempt to deliver either (icharge_jeita_x + 1)
Constant-Voltage Charging
• 1mV/RSNSB with en_jeita or (charge_current_setting + 1)
• 1mV/RSNSB without en_jeita in constant-current mode Once the BATSENS+ voltage reaches the programmed
where icharge_jeita_x or charge_current_setting ranges charging voltage the switching regulator will reduce its
from 0 to 31. For example, A 10mΩ resistor between output power and hold the battery voltage steady at either
CPS and CSN would give an upper limit charge current (3.8125V + 12.5mV • vcharge_jeita_x) • cell_count with en_
of 3.2A. Depending on available input power and external jeita or (3.8125V + 12.5mV • vcharge_setting) • cell_count
load conditions, the battery charger may not be able to without en_jeita where vcharge_jeita_x and vcharge_set-
charge at the full programmed rate. An alternate control ting each range from 0 to 31. In constant voltage mode
loop such as the input current limit loop or input voltage the charge current will decrease naturally toward zero
limit loop may be in force and only partial power will be providing inherently safe operation by preventing the
available to charge the battery. If input current limit is battery from being over charged. Multiple charge voltage
reached, for instance, the system load will be prioritized settings are available for final top-off voltage selection via
over the battery charge current. When system loads are vcharge_jeita_x with en_jeita or vcharge_setting without
light, battery charge current will be maximized and could en_jeita. While charge voltage trade-offs can be made to
be as high as the value programmed by icharge_jeita_x preserve battery life or maximize capacity, it is not pos-
or charge_current_setting. sible for the LTC4162 to be set to a charge voltage that
is dangerously high or inconsistent with a Lithium-Ion/
The charge current programming resistor, RSNSB, should Polymer Battery.
always be set to match the capacity of the battery with-
out regard to source or load limitations from any other Note that charge_current_setting and vcharge_setting do
control loop. The multiple control-loop architecture of not directly control the icharge_dac and vcharge_dac. They
the LTC4162 will correct for any discrepancies, always are only target values. For example, if the JEITA Tempera-
optimizing transfer of power to the battery and the load. ture Controlled Charging system is enabled (en_jeita = 1),
the DACs will be controlled by this user programmable
Thermal Regulation system (i.e. icharge_jeita_2 through icharge_jeita_6,
vcharge_jeita_2 through vcharge_jeita_6).
When the switching battery charger is enabled at an el-
evated ambient temperature, LTC4162 self heating may
Basic Temperature Controlled Charging
push its junction temperature to an unacceptable level.
To prevent overheating the LTC4162 monitors its own The LTC4162 provides temperature controlled charging if
die_temp and automatically reduces the icharge_dac to a grounded thermistor and a bias resistor are connected
limit power dissipation. The differential servo voltage at to the NTCBIAS and NTC pins and en_jeita is set to 0.
CSP to CSN can drop to as low as 1mV giving about 3% Charging is paused if thermistor_voltage rises above
(1/32) of the maximum charge current. The thermal regu- jeita_t1 (0°C) or falls below jeita_t6 (60°C). Recall that
lation algorithm achieves this by enforcing a maximum thermistors have a negative temperature coefficient so
icharge_dac setting which drops linearly from 31 to 0 as higher temperatures will read lower thermistor_voltage
die_temp increases from thermal_reg_start_temp (default and vice versa. If charging is not suspended, the charg-
120°C) to thermal_reg_end_temp (default 125°C). When ing voltage and current will follow vcharge_setting and
the thermal regulation algorithm is active, charge_status charge_current_setting respectively.
becomes thermal_reg_active. A thermal_reg_active_alert The default upper and lower limits are based on a thermis-
can be set with en_thermal_reg_active_alert and cleared tor with a β25/85 value of 3490K, such as provided by a
by writing either back to 0. Thermal regulation can be Vishay NTCS0402E3103FLT. This thermistor was chosen
Rev A

24 For more information [Link]

LTC4162-L
OPERATION
specifically because of its weak temperature characteristic thermistor_voltage based temperature set points jeita_t1
relative to other thermistors. Stronger thermistors can through jeita_t6. For each of the temperature regions, the
be diluted to match it by placing a low drift resistor in charge current and charge voltage can be programmed
series with the thermistor and increasing the bias resis- within the limits set by (VCSP – VCSN)/RSNSB (charge_cur-
tor accordingly. (see Alternate Thermistors and Biasing rent_setting) and battery charge voltage (vcharge_set-
in Applications Information for details). If the application ting). When en_jeita is true, The JEITA system writes its
does not require temperature controlled charging then the registers, icharge_jeita_2 through icharge_jeita_6 and
thermistor should be replaced with a resistor of equal value vcharge_jeita_2 through vcharge_jeita_6 to charge_cur-
to bias resistor RNTCBIAS, for example, 100kΩ. rent_setting and vcharge_setting which are then passed
on to the icharge_dac and vcharge_dac.
Advanced JEITA Temperature Controlled Charging
Writing values to charge_current_setting and vcharge_set-
A control system is included to provide compliance ting with en_jeita set is futile as the JEITA system will
with the Japan Electronics and Information Technology overwrite these values every 11ms.
Industries Association guidelines on battery charging by
The values for the JEITA registers are shown below. The
leaving en_jeita set to its default value of 1. Specifically,
bold values in the tables are programmable. The jeita_t1
a very flexible multi-point temperature-voltage-current
through jeita_t6 registers determine the thermistor_volt-
profile can be programmed into the LTC4162 to ensure
age values for the breakpoints between regions. Table 6
that charging parameters as a function of temperature
lists the default values of the JEITA charging parameters
are used. Figure 1 and Table 6 illustrate default values
along with example values of a 10kΩ thermistor with a β
of the JEITA system available in the LTC4162. There are
value of 3490K. All of the temperature, voltage and current
seven distinct temperature regions programmed by the six
settings can be modified for maximum flexibility.
Table 6. Tabular Representation of the JEITA system, Default JEITA Values and β = 3490K Equivalent Temperatures
Charge Charge JEITA
jeita_region vcharge_jeita Voltage icharge_jeita Current Temperature thermistor_voltage RNTC Temp

R1 Charger Off
jeita_t1 16117 28215Ω 0°C

R2 31 4.20V 15 16mV/RSNSB

jeita_t2 14113 18290Ω 10°C

R3 31 4.20V 31 32mV/RSNSB

jeita_t3 7970 5751Ω 40°C

R4 23 4.10V 31 32mV/RSNSB

jeita_t4 7112 4832Ω 45°C

R5 23 4.10V 15 16mV/RSNSB

jeita_t5 6325 4080Ω 50°C

R6 19 4.05V 15 16mV/RSNSB

jeita_t6 4970 2948Ω 60°C

R7 Charger Off

Rev A

For more information [Link] 25

LTC4162-L
OPERATION
Default JEITA Charge Voltage Profile when tchargetimer reaches max_charge_time and the
4.25
constant-voltage timer expires in constant_voltage when
tcvtimer reaches max_cv_time. Default max_cv_time is
4.20
14400 seconds (4 hours). To set different timer expira-
PER-CELL VOLTAGE (V)

tion values, max_charge_time and max_cv_time are both

4.15
adjustable. The resolution of max_cv_time is 1 second/
4.10
LSB and for max_charge_time it is 1 minute/LSB.
tcvtimer can be read back to determine the cummulative
4.05 time in constant_voltage regulation. max_cv_time is a 16
bit unsigned value ranging from 0 to 65535 seconds (~18
4.00
−10 0 10 20 30 40 50 60 70 hours). tchargetimer, the total charge time safety timer,
TEMPERATURE(°C) can be read back at any time to determine the elapsed time
4162L F01a
since the beginning of this charge cycle. max_charge_time
Default JEITA Charge Current Profile is a 16 bit unsigned value at 1 minute per LSB ranging
Servo Voltage (VCSP-VCSN) from 0 to 65535 minutes (~45 days). The tchargetimer
40 is disabled when max_charge_time is left at its default
value of 0. To enable the tchargetimer write a non 0 value
32
to max_charge_time.
SERVO VOLTAGE (mV)

24 max_charge_time_fault indicates that charging has termi-

nated due to tchargetimer reaching max_charge_time and
16 timer_term indicates that charging has terminated due to
tcvtimer reaching max_cv_time. The max_charge_time_
8 fault will persist until either the battery voltage drops to
less than 35% of its target voltage setting, whereupon a
0
−10 0 10 20 30 40 50 60 70
new charge cycle begins and the tchargetimer resets, or
TEMPERATURE(°C) a power cycle occurs resetting the entire charger state
4162L F01b
machine. A normal termination such as timer_term
or c_over_x_term also resets tchargetimer. Finally, the
Figure 1. Default JEITA Temperature Profile Gives A Graphical max_charge_time_fault is cleared upon abnormal condi-
Representation of the Seven JEITA Regions, the Six Breakpoint
and the Default Values tions such as the input voltage falling below the BATSENS+
pin voltage, suspend_charger or if any another system
fault occurs: not intvcc_gt_2p8v, not vin_gt_4p2v, not
Battery Charger Termination and Full Charge
vin_gt_vbat, thermal_shutdown, no_rt or cell_count_err.
Indication (C/x)
Alternately, if en_c_over_x_term is set, the LTC4162 will
The LTC4162 supports several battery charge termination
also terminate charging once constant_voltage is reached
methods.
and ibat has naturally dropped to the c_over_x_threshold.
If enabled, a maximum elapsed charge time timer is started The default c_over_x_threshold value of c_over_10 is a
at the beginning of each charge cycle and, upon achieving good indication that the battery has reached a nearly full
constant_voltage regulation, a constant-voltage timer is state of charge. The c_over_x_threshold is adjustable via
also started. At the expiration of either of these timers, the I2C port. If en_c_over_x_term is set, charging will
charging of the battery will discontinue and no more terminate at the first of either c_over_x_term, timer_term
current will be delivered. The elapsed time timer expires or max_charge_time_fault. The constant_voltage timer

Rev A

26 For more information [Link]

LTC4162-L
OPERATION
termination features cannot be disabled. Both of the charge Automatic Recharge
timers will be paused in ntc_pause.
After a normal termination, the charger will remain off. If
The LTC4162 can optionally be configured to generate an the portable product remains in this state long enough,
interrupt at C/x termination by setting en_c_over_x_term_ the battery will eventually self discharge. To ensure that
alert. Timer termination alerts can also be set with either the battery is always topped off, a new charge cycle will
en_timer_term_alert for the constant_voltage timer or automatically begin when the battery voltage falls below
en_max_charge_time_alert for max_charge_time_fault. approximately 97.5% of the programmed charge voltage.
c_over_x_term, timer_term and max_charge_time_fault The termination safety timers, tcvtimer and tchargetimer,
determine what caused the SMBALERT. The LTC4162 will reset back to zero. A new charge cycle will also be initi-
ated if input power is cycled or if the charger is momentarily
terminates charging by disabling the switching charger
disabled (e.g. suspend_charger set to 1, then back to 0).
which makes the SW node high impedance.

CHARGER
SUSPENDED
vin_gt_vbat = 0
+vin_gt_4p2v = 0
+thermal_shutdown = 1
+suspend_charger = 1
+cell_count_err = 1
+no_rt = 1

30-SECOND DELAY

BATTERY DETECTION FAILED FAULT

BATTERY
DETECTION BATTERY SHORTED FAULT

BATTERY MISSING FAULT

thermistor_voltage > open_thermistor
vbat ≥ 2.85V vbat < 2.85V

PRE-CHARGE

vbat < 2.85V

vbat > 2.9V
jeita_t1 > thermistor_voltage > jeita_t6
CONSTANT CURRENT/CONSTANT VOLTAGE NTC
jeita_t1 < thermistor_voltage < jeita_t6
CHARGING PAUSE

chargetimer tcvtimer > max_cv_time charge_status = constant_voltage

> max_charge_time AND max_cv_time ≠ 0 AND ibat < c_over_x_threshold

MAXIMUM CHARGE CONSTANT VOLTAGE CONSTANT VOLTAGE

TIME FAULT TIMER TERMINATION C/x TERMINATION

vbat < 35%VCHARGE vbat < 97.5%VCHARGE vbat < 97.5%VCHARGE

4162L F02

Figure 2. Battery Charging State Diagram

Rev A

For more information [Link] 27

LTC4162-L
OPERATION
Low Power Ship Mode Under Voltage Lockout Circuits/suspend_charger/
The LTC4162 can reduce its already low battery-only System Faults
standby current to about 2.8µA in a special mode designed Various supply monitor circuits, as well as suspend_char-
for shipment and storage. Ship mode is armed by setting ger, can disable charging. If the voltage at VIN falls below
arm_ship_mode to arm. It does not take effect, however, BATSENS+ (i.e. not vin_gt_vbat), or thermal_shutdown
until the input voltage VIN drops below approximately 1V. (die temperature above ~150°C), no_rt resistor, not
Upon return of the input voltage above approximately 1V the intvcc_gt_2p8v, not vin_gt_4p2v, or a CELLS0/1 pins
LTC4162 wakes from ship mode. The decision to remain out cell_count_err, the LTC4162 suspends charging and
of ship mode is latched once the internal voltage reference reports charger_suspended. In the absence of any of the
is re-biased and VIN is detected as having reached about above fault conditions, charging is re-enabled when VIN
4.2V (vin_gt_4p2v). In ship mode, the VCC2P5 2.5V logic rises VIN_DUVLO above the BATSENS+ voltage.
LDO and the INTVCC 5V system LDO are deactivated and,
along with them, all logic and communications with the LTC4162 Lithium-Ion/Polymer Variants
I2C port. Consequently, no settings or state information The LTC4162-LAD is fully programmable and follows the
will persist through a ship mode cycle. descriptions given thus far but there are three other non-
programmable voltage variants available as well. Each of
Oscillator Synchronization
these four versions is available with and without solar panel
The SYNC pin is available to synchronize the switching Maximum Power Tracking enabled by default.
battery charger to an external clock for optimum noise
The LTC4162 Lithium-Ion/Polymer variants are:
immunity. To use the SYNC pin, use the RT pin to set
the frequency of the internal oscillator to the frequency LTC4162-L40
expected by the SYNC signal. If no signal is present at LTC4162-L41
SYNC, the internal oscillator will run normally. If a signal
within the required tolerance range appears at SYNC, the LTC4162-L42
internal oscillator will detect it and synchronize with it. To LTC4162-LAD
avoid a long or short cycle, synchronization won't occur
until the internal oscillator and external signals coincide. The LTC4162-L40, LTC4162-L41 and LTC4162-L42
Therefore, synchronization may take several thousand JEITA values are not writable and follow the values
cycles (milliseconds) to occur. If SYNC is not used, it outlined below.
should just be grounded.

jeita_t1 jeita_t2 jeita_t3 jeita_t4 jeita_t5 jeita_t6

0x3EF5 0x3721 0x1F22 0x1BC8 0x18B5 0x136A
(0°C) (10°C) (40°C) (45°C) (50°C) (60°C)
VARIANT REGION1 REGION2 REGION3 REGION4 REGION5 REGION6 REGION7
CHARGE CURRENT 16mV/RSNSB 32mV/RSNSB 32mV/RSNSB 16mV/RSNSB 16mV/RSNSB
LTC4162-L40 4.0V 4.0V 3.9V 3.9V 3.95V
CHARGER CHARGER
LTC4162-L41 4.1V 4.1V 4.0V 4.0V 4.05V
OFF OFF
LTC4162-L42 4.2V 4.2V 4.1V 4.1V 4.05V
LTC4162-LAD 4.2V 4.2V 4.1V 4.1V 4.05V

Rev A

28 For more information [Link]

LTC4162-L
APPLICATIONS INFORMATION
SMBus and I2C Protocol Compatibility Alternate Thermistors and Biasing
The LTC4162 uses an SMBus/I2C style 2-wire serial port Thermistors with a β value higher than 3490K may be used
for some programming and all monitoring functions. Over with the LTC4162 by either diluting the thermistor with
the serial port the user may program alert values which an inexpensive low drift series resistor, RSERIES, or over-
are compared against measured parameters, set control writing jeita_t1 through jeita_t6 with appropriate values.
parameters and read status data. The Timing Diagram If a single dilution resistor is added, RNTCBIAS should be
shows the relationship of the signals on the bus. The two increased by an amount equal to the dilution resistor to
bus lines, SDA and SCL, must be high when the bus is not pad the bias resistor, thereby returning the resistor ratio
in use. External pull-up resistors are required on these lines. to 50% and, therefore, yielding no error at 25°C. Slightly
The LTC4162 is both a slave receiver and slave transmitter. more padding of RNTCBIAS may be desired to lift and center
It is never a master. The control signals, SDA and SCL, the error curve over a given temperature range. With the
are scaled internally to the DVCC supply for compliance addition of one more resistor, RPARALLEL, to the thermistor
with the I2C specification. DVCC should be connected to bias network, it's possible to further refine the temperature
the same power supply as the bus pull-up resistors. profile of a higher β thermistor to match the expected β
Aside from electrical levels and bus speed, the SMBus spec- value of 3490K. The values of RNTCBIAS, RPARALLEL and
ification is generally compatible with the I2C specification, RSERIES can be selected to nearly match the thermistor
profile expected by the LTC4162. An example is included
but extends beyond I2C to define and standardize specific
formats for various types of transactions. The LTC4162 here as a demonstration.
serial port is compatible with the 0Hz-400kHz speed and
ratiometric input thresholds of the I2C specification, but NTCBIAS
RNTCBIAS
supports both the Read-Word and Write-Word protocols NTC
of the SMBus specification, either with or without packet RSERIES
error checking (PEC). The SMBALERT and ARA protocols RPARALLEL
of the SMBus specification are also supported. Finally, it THERMISTOR T RNTC

has built-in timing delays and glitch suppression filters to

ensure correct operation with both protocols. 4162L F03

The input logic levels of I2C and SMBus are specified dif- Figure 3. Diluting the Thermistor with Low Drift Series and
Parallel Resistors
ferently. I2C specifies logic levels that are ratiometric to
supply and SMBus specifies absolute levels. By comparing
For a 10k Vishay NTCS0402E3103FHT thermistor which
the specifications, it can be shown that the logic levels
has a β25/75 value of 3950K, using RNTCBIAS = 10k, RSER-
are compatible for supply voltages ranging from 2.667V
IES = 549 and RPARALLEL = 187k will closely mimic the
to 3.000V, however, with a well designed system, I2C
profile of a thermistor β value of 3490K over the 0°C to
compatible and SMBus compatible parts are often found
60°C range resulting in a nominal error of under ±0.5°C
to be interchangeable. Appendix B of System Manage-
for the default JEITA temperature thresholds defined by
ment Bus (SMBus) Specification Version 2.0 highlights
jeita_t1 through jeita_t6. This error is significantly less
differences between SMBus and I2C, as does section 4 of
than the error tolerance of most thermistors.
I2C-bus Specification and User Manual.

Rev A

For more information [Link] 29

LTC4162-L
APPLICATIONS INFORMATION
1.0 based on the battery capacity only, without concern for
Thermistor: NTCS0402E3103FHT
RNTCBIAS = 10k the input source.
RSERIES = 549
0.5
RPARALLEL = 187k The maximum average input current is determined by
the sense resistor, RSNSI, connected between the CLP
ERROR (°C)

0.0 and CLN pins. Its value should be chosen based only on
the maximum available current limit of the expected input
source. The input and charge current loops servo the volt-
−0.5
ages across their respective sense resistors to a maximum
of 32mV, giving maximum input and charge currents of:
−1.0
0 10 20 30 40 50 60 IIN(MAX) = 32mV/RSNSI
TEMPERATURE (°C)
4162L F04 ICHG(MAX) = 32mV/RSNSB
Figure 4. Residual Error from 0°C to 60°C for The charge current and input current sense resistors con-
a β25/75 = 3950K Thermistor vert the charge and input currents into a voltage measurable
by the LTC4162. The accuracy and temperature coefficient
For tools that can assist with alternate thermistors, please of the current sense resistors contribute directly to the cur-
visit the LTC4162 web page. rent regulation accuracy of the LTC4162. While 4-terminal
resistors are available for current sensing applications,
Programming the Input and Battery Charge Current simpler 2-terminal resistors provide a more economical
Limits solution. Power dissipation of the sense resistors should
The LTC4162 features independent resistor programmabil- be carefully considered. For example, with a 3.2A charge
ity of the input current and battery charge current upper current the sense resistor would be 10mΩ and power
limits to facilitate optimal charging from a wide variety of dissipation would be 3.2²A² • 10mΩ = 102.4mW. While
input power sources. The battery charge current should be a 1/8W 0603 resistor is theoretically feasible in this ap-
programmed solely on the basis of the size of the battery plication, its temperature rise could be quite high. A 1/4W
and its associated safe charging rate. Typically, this rate is to 1/2W 0805 resistor might be a better choice for lower
about "1C", or equal to the current which would discharge thermal rise and subsequently better accuracy. Using
the battery in one hour. For example, a 2000mAh battery larger copper pours and having more copper coverage
would be charged with no more than 2A. With the full will reduce the thermal resistance of the sense resistors.
scale (default) charge current programmed via the resis- Figure 5 shows an example of a proper Kelvin connection
tor, RSNSB, between CSP and CSN, all other selectable to the current sense resistors.
charge current settings are lower and may be appropriate
for custom charge algorithms at extreme temperatures.
If the battery charge current limit requires more power
than is available from the selected input current limit, the 4162L F05

input current limit will be enforced and the battery will be Figure 5. Kelvin Current Sensing with an 0805 Resistor.
charged with less than the programmed current. Thus,
the battery charger sense resistor should be programmed

Rev A

30 For more information [Link]

LTC4162-L
APPLICATIONS INFORMATION
Power Path Isolation in Ship Mode Once the value for L is known, the type of inductor core
must be selected. Ferrite cores are recommended for their
In ship mode, the LTC4162 shuts down nearly all internal
very low core loss at frequencies above 100kHz, such as
circuits and reduces its quiescent current to only a few
is the operating frequency of the LTC4162. Ferrite core
micro-Amperes. The body diodes of the power path tran-
sistors still provide a conduction path from the battery to material saturates hard, however, which means that in-
ductance collapses abruptly when the peak design current
the system load however. If circuits down stream of the
LTC4162 power path must be completely cut off in ship is exceeded. This causes an abrupt increase in inductor
ripple current and consequent output voltage ripple. The
mode, an external PMOS transistor and one small signal
saturation current for the inductor should be about 30%
NMOS transistor can provide this isolation. The circuit of
higher than the maximum regulated current, ICHG(MAX).
Figure 6 exploits the fact that the VCC2P5 pin drops to
ground in ship mode. MP1 should be chosen to have a Setting the Switching Frequency (RT Resistor)
fairly low threshold voltage if full conductance is needed
for single cell applications because in the single cell case The operating frequency and inductor selection are inter-
MN1 drops out and RA and RB form a voltage divider related. Higher operating frequencies allow the use of
preventing full gate drive to MP1. smaller inductors and capacitors but generally also results
MP1
in lower efficiency because of switching and charge trans-
VOUT
Si5411EDU VLOAD
TO DOWN STREAM
fer losses. The feedback loops of LTC4162 are internally
RA CIRCUITRY compensated and cannot be adjusted. The LTC4162 is
1M
designed to operate properly with frequencies ranging from
VCC2P5
MN1 1MHz to 2.5MHz. Operation at lower or higher frequen-
RYM002N05
cies jeopardizes control loop stability. A resistor on the
RB
390k RT pin sets the LTC4162's step-down switching charger
4162L F06 operating frequency. To keep the inductor size down and
ensure peak efficiency and stability, the LTC4162 has been
Figure 6. Isolating Downstream Circuits in Ship Mode.
optimized to run at 1.5MHz with an RT value of 63.4kΩ.
Small changes in oscillator frequency can be achieved
Choosing the BOOST Capacitor by altering RT from this value. The oscillator frequency is
The BOOST capacitor should be a low ESR surface mount inversely proportional to RT as given by the expression:
ceramic type rated to at least 6.3V and should have a 94
value of 22nF. fOSC (MHz ) =
R T ( kΩ )
Choosing the Inductor
Choosing the VOUT, BATSENS+, INTVCC and VCC2P5
To ensure proper ripple current and control loop stability Bypass Capacitors
the inductor value as a function of switching frequency
and maximum input voltage should be computed from The style and value of the capacitors used with the LTC4162
the following expression: determine important parameters, such as regulator control
loop stability and input voltage ripple. Because the LTC4162
0.3 • VIN(MAX) uses a step-down switching power supply from VOUT to
L(µH) =
fOSC(MHz) BATSENS+, its input current waveform contains very high
frequency components. It is imperative that low equivalent

Rev A

For more information [Link] 31

LTC4162-L
APPLICATIONS INFORMATION
series resistance (ESR) multilayer ceramic capacitors be INFET and BATFET MOSFET Selection
used to bypass VOUT. Tantalum and aluminum capacitors
An external N-channel MOSFET is required for both the
will not work because of their high ESR and ESL. The
input and battery paths. Important parameters for the se-
value of the total capacitance on VOUT directly controls the lection of these MOSFETs are the maximum drain-source
amount of input ripple for a given load current. Increas-
voltage, VDSS, gate threshold voltage and on-resistance
ing the size of this capacitor will reduce the input ripple. (RDS(ON)). When the input is grounded, the battery stack
The LTC4162 has been designed with VOUT and PGND as voltage is applied across the input MOSFET. When VBAT
two corner pin groups so there is ample room to fit an is at 0V, the input voltage is applied across the battery
appropriate bypass capacitor. The need for low impedance MOSFET. Therefore, the VDSS of the input MOSFET must
capacitance directly adjacent to the VOUT and PGND pins withstand the maximum voltage on VBAT while the VDSS
cannot be overemphasized. PCB distance of only a few of the output MOSFET must withstand the highest voltage
millimeters will introduce nano-Henrys of inductance and on VIN. The gate drive for both is 5V. This requires the use
compromise the high frequency "hot-loop" (See Printed of logic-level threshold N-channel MOSFETs. As a general
Circuit Board Layout Considerations). rule, select MOSFETs with a low enough RDS(ON) to obtain
It is also recommended that a ceramic capacitor be used the desired VDS and power dissipation while operating at
to bypass BATSENS+. At least 10µF with low ESR is re- full load current.
quired. Multilayer ceramic chip capacitors typically have
exceptional ESR performance. MLCCs combined with a Operation Without a Battery
tight board layout and an unbroken ground plane will yield The LTC4162 has built in battery detection. Its switching
very good performance and low EMI emissions. regulator will generally not start if the battery is missing.
The INTVCC and VCC2P5 pins are the outputs of onboard However, if a battery is present at the beginning of a charge
low dropout regulators and also require ceramic capacitors. cycle and is removed, the LTC4162 will operate without
The INTVCC and VCC2P5 capacitors should be as close a battery. Typically the BATSENS+ pin will rise quickly
to the LTC4162 as possible and returned immediately to to the programmed constant-voltage level and remain
an analog ground plane. The INTVCC pin requires at least there. However, it is important that the impedance on the
4.7µF of capacitance rated to at least 6.3V and the VCC2P5 BATSENS+ node be kept relatively low at the switching
pin requires at least 1µF rated to 4V. frequency. Therefore a ceramic capacitor of 10µF or more
near the LTC4162 is necessary. Note that without a load on
The actual capacitance of any ceramic capacitor should
the BATSENS+ pin, the switching regulator will eventually
be measured with a small AC signal and DC bias, as is
terminate due to tcvtimer reaching max_cv_time.
expected in-circuit. Many vendors specify the capacitance
versus voltage with a 1VRMS AC test signal with no bias Operation With Long Battery Leads
and, as a result, grossly overstate the capacitance that
the capacitor will present in the application. Using similar The LTC4162 is generally resilient to operation with long
operating conditions as the application, the user must battery leads, however a ceramic capacitor of 10µF or
measure, or request from the vendor, the actual capacitance more of appropriate voltage tolerance near the LTC4162
to determine if the selected capacitor meets the minimum is necessary. Note that any parasitic battery resistance,
capacitance that the application requires. such as long cabling, will push the LTC4162 into constant
voltage charging sooner, dramatically extending charging

Rev A

32 For more information [Link]

LTC4162-L
APPLICATIONS INFORMATION
time. If possible, the BATSENS+ pin should be connected 2.0

to the battery terminals with a separate Kelvin connection

from that of the current carrying inductor path. The bulk 1.6

load capacitor should be on the inductor side of this

PANEL CURRENT (A)

CONSTANT CURRENT
1.2
connection, not the BATSENS+ side. A smaller ceramic
capacitor may additionally be added to the BATSENS+
0.8
pin near the LTC4162. A heavy copper run from the low CONSTANT VOLTAGE

side of battery to the GND (paddle) of the LTC4162 is also 0.4

necessary to reduce resistance optimizing charging time.
0.0
Resistive Inputs and Test Equipment 0 4 8 12 16 20 24
PANEL VOLTAGE (V)
Care must be exercised in the laboratory while evaluat- 4162L F07

ing the LTC4162 with inline ammeters. The combined Figure 7. High Quality 40W Solar Panel
resistance of the internal current sense resistor and fuse
of many meters can be 0.5Ω or more. At currents of 3A+ When the driving impedance is at or below a few Ohms
it is possible to drop several volts across the meter and the LTC4162's input voltage regulation loop is very stable.
wiring, possibly resulting in unusual voltage readings or However, in its attempt to find the maximum power point,
artificially high switch duty cycles. A resistive connection the LTC4162 drags the panel voltage down to its constant-
to the source of input power can be particularly trouble- current high impedance region. In this region the LTC4162
some. With the undervoltage limit feature enabled, the input voltage control loop will become unstable. To avoid
switching regulator output power will be automatically instability and UVLO restarts the real input impedance of
reduced to prevent VIN from falling below its programmed the LTC4162 should be maintained at about 2.5Ω in the
level. This feature greatly improves tolerance to resistive 1kHz to 10kHz band. To achieve this characteristic an R-C
input power sources (from either undersized wiring and network should be added to the solar panel. For example,
connectors or test equipment) and facilitates stable be- a lower quality 100μF to 1000μF capacitor plus a 2.5Ω
havior, but if engaged, could result in much less power series resistor would make a good impedance correction
delivery to the battery. network as shown in Figure 8.
Solar Panel Input Impedance Correction
The maximum power point tracking algorithm uses the
LTC4162's input voltage regulation control loop to find
– +
and operate at the maximum power point of the solar
panel. In general solar panels have two distinct regions of 2.5Ω 0.1µF

operation roughly corresponding to constant voltage and + VIN INFET CLP CLN
150µF
constant current. In its constant voltage region the panel LTC4162
4162L F08

presents a somewhat low impedance and in its constant

Figure 8. Input Impedance Compensation Network
current region a very high impedance. Figure 7 shows an
I-V characteristic collected from a brightly lit high quality Figure 9 shows the driving impedance presented by the
40W solar panel. Notice the very high impedance below combined solar panel plus 10μF bypass capacitor on VOUT
16V and fairly low impedance above 16V. in both low impedance and high impedance solar panel
regions. In the low impedance region the aggregate imped-
ance characteristic is about one to three Ohms in parallel

Rev A

For more information [Link] 33

LTC4162-L
APPLICATIONS INFORMATION
with a 10μF capacitor. Also shown is the troublesome Battery and Input Voltage Hot Plugging
constant-current region where the impedance is essentially Aluminum-polymer, aluminum-electrolytic or tantalum
that of just the 10μF bypass capacitor. Two other networks capacitors can minimize overshoot when hot plugging
are shown comprising a larger 100μF and 1000μF capacitor a battery or power connector. Ceramic capacitors are
both in series with a 2.5Ω resistor for impedance flattening required close to the LTC4162 VOUT pins to supply very
and phase shift mitigation. The compensation capacitor high frequency switching current but their extreme non-
should be a solid or "polymer" electrolytic type such as the linearity produces excessively high overshoot during hot
Panasonic ZA hybrid series to preserve stable ESR over plug. Their capacitance typically plunges by more than
temperature. Conventional, or "wet", electrolytic capacitors 80% as the voltage increases from 0V to rated voltage.
should be avoided as their ESR increases dramatically at This nonlinearity encourages high current at low voltage
low temperature. The larger compensation capacitor will while rapidly shedding capacitance as the voltage rises; a
create a wider impedance flattening frequency range and dangerous combination resulting in high voltage overshoot.
therefore more stable operation. Empirically, the combination of a ceramic capacitor near
the LTC4162 and a lower Q, voltage-stable, aluminum
10000
10µF type capacitor provides the most robust combination.
(High Impedance)
(HIGH IMPEDANCE)
1000
TVS diodes may also be used to limit voltage overshoot
10µF||(1000µF + 2.5Ω) on either the input connector or the battery connector
DRIVING IMPEDANCE (Ω)

100 of a portable product. A single protection device (lossy

10µF||(100µF + 2.5Ω)
capacitor or TVS) on the VOUT terminal may be sufficient
10 to handle hot plug events from either the battery or the
input connector as the power path MOSFETs diode-OR
1 to the VOUT node. For solar panel applications the solar
10µF||2.5Ω
(Low Impedance)
(LOW IMPEDANCE) panel compensation network may provide adequate hot
0.1
0.01 0.1 1 10 100
plug protection on the input terminal. See Application Note
FREQUENCY (kHZ) AN88 for examples.
4162L F10

Figure 9. Aggregate Input Impedance vs Frequency Printed Circuit Board Layout Considerations
The Exposed Pad on the backside of the LTC4162 must
USB Power Delivery be securely soldered to the PC board ground. It serves
as the analog ground pin and thermal sink. There should
For 1 to 4 cell Lithium-Ion products, the LTC4162 can sup-
be a group of vias under the grounded backside leading
port the USB Power Delivery specification. Table 7 shows
directly down to an internal unbroken ground plane.
the relevant compatibility of cell_count vs USB profile.
High frequency currents tend to find their way on the
Table 7. Cell Count Support vs USB Power Delivery Profile ground plane along a mirror path directly beneath the
USB PD 1 Cell 2 Cell 3 Cell 4 Cell incident path on the top of the board. If there are slits or
Voltage Product Product Product Product
cuts in the ground plane due to other traces on that layer,
5V ✔ ✘ ✘ ✘ the current will be forced to go around the slits. If high
9V ✔ ✔ ✘ ✘ frequency currents are not allowed to flow back through
15V ✔ ✔ ✔ ✘ their natural, least-area, path, excessive voltage will build
20V ✔ ✔ ✔ ✔ up and radiated emissions will occur (see Figure 10). To

Rev A

34 For more information [Link]

LTC4162-L
APPLICATIONS INFORMATION
minimize parasitic inductance, the ground plane should
be as close as possible to the top plane of the PC board
(i.e. layer 2).

4162L F12

Figure 12. Recommended Placement of the VOUT Bypass

Capacitor and Inductor

4162L F10

Figure 10. Currents Tend to Follow Their Natural Least

Area Path. Breaks in the Ground Plane Lead to Increased
Impedance and EMI

The capacitor from VOUT to PGND is the most critical high

frequency component. It's proximity to the LTC4162 should Figure 13. Recommended Placement of the VOUT Bypass
be prioritized above all else. The LTC4162 is designed to Capacitor and Inductor
have this capacitor placed directly adjacent to the short
side of the package where the connections to pins (27,28) Due to its high frequency switching circuitry, it is also
and (23,24) can be made on the top copper layer of the imperative that the INTVCC and VCC2P5 LDO capacitors
PC board (see Figures 12 and 13). The inductor connec- as well as the BOOST-SW capacitor be as close to the
tion to SW should feed out between the input capacitor LTC4162 as possible. Additionally, minimizing the SW
terminals or down to a lower layer with a group of vias pin trace area will help minimize high frequency radiated
very close to the LTC4162. energy.
The ceramic capacitor on BATSENS+ carries the inductor
VIN
ripple current. While not as critical as the VOUT bypass
+ S1
– capacitor, an unbroken copper pour from this capacitor's
COUT HOT LOOP
VBAT
low side to the LTC4162 PGND pins (23, 24) and the analog
S2 CBAT ground pin (paddle) will reduce output voltage ripple and
ensure proper regulation.
4162L F11

The LTC4162 demonstration board DC2038A provides an

excellent example of a suitable PC board layout.
Figure 11. Hot Loop

Rev A

For more information [Link] 35

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
vbat_lo_alert_limit 0x01 R/W [15:0] 0 Signed number that sets a lower limit that can be used to trigger an interrupt based
on the per-cell battery voltage out of range. The value is based on the A/D value, vbat,
which has a scaling factor of cell_count × 192.4µV/LSB. To compute the per-cell bit
count, divide the desired trigger voltage by both cell_count and 192.4µV. The alert is
enabled by setting en_vbat_lo_alert and can be read back and cleared at vbat_lo_alert.
vbat_hi_alert_limit 0x02 R/W [15:0] 0 Signed number that sets an upper limit that can be used to trigger an interrupt based
on the per-cell battery voltage out of range. The value is based on the A/D value, vbat,
which has a scaling factor of cell_count × 192.4µV/LSB. To compute the per-cell bit
count, divide the desired trigger voltage by both cell_count and 192.4µV. The alert is
enabled by setting en_vbat_hi_alert and can be read back and cleared at vbat_hi_alert.
vin_lo_alert_limit 0x03 R/W [15:0] 0 Signed number that sets a lower limit that can be used to trigger an interrupt based on
input voltage out of range. The value is based on the A/D value, vin, which has a scaling
factor of 1.649mV/LSB. The alert is enabled by setting en_vin_lo_alert and can be read
back and cleared at vin_lo_alert.
vin_hi_alert_limit 0x04 R/W [15:0] 0 Signed number that sets an upper limit that can be used to trigger an interrupt based on
input voltage out of range. The value is based on the A/D value, vin, which has a scaling
factor of 1.649mV/LSB. The alert is enabled by setting en_vin_hi_alert and can be read
back and cleared at vin_hi_alert.
vout_lo_alert_limit 0x05 R/W [15:0] 0 Signed number that sets a lower limit that can be used to trigger an interrupt based on
vout voltage out of range. The value is based on the A/D value, vout, which has a scaling
factor of 1.653mV/LSB. The alert is enabled by setting en_vout_lo_alert and can be read
back and cleared at vout_lo_alert.
vout_hi_alert_limit 0x06 R/W [15:0] 0 Signed number that sets an upper limit that can be used to trigger an interrupt based on
vout voltage out of range. The value is based on the A/D value, vout, which has a scaling
factor of 1.653mV/LSB. The alert is enabled by setting en_vout_hi_alert and can be read
back and cleared at vout_hi_alert.
iin_hi_alert_limit 0x07 R/W [15:0] 0 Signed number that sets an upper limit that can be used to trigger an interrupt based on
input current out of range. The value is based on the A/D value, iin, which has a scaling
factor of 1.466µV / RSNSI amperes/LSB. The alert is enabled by setting en_iin_hi_alert
and can be read back and cleared at iin_hi_alert.
ibat_lo_alert_limit 0x08 R/W [15:0] 0 Signed number that sets a lower limit that can be used to trigger an interrupt based on
charge current dropping below a particular value, such as during the constant-voltage
phase of charging, or, load current exceeding a particular limit when not charging.
When the charger is not running, and telemetry is enabled with force_telemetry_on,
this limit indicates that the battery draw has exceeded a particular value. Telemetry will
be enabled automatically if the input voltage exceeds the battery voltage, in which case
discharge current will be nearly zero. ibat values are positive for charging and negative
for discharging so the polarity of this register should be set according to the mode
in which the limit alert is of interest. The value is based on the A/D value, ibat, which
has a scaling factor of 1.466µV / RSNSB amperes/LSB. The alert is enabled by setting
en_ibat_lo_alert and can be read back and cleared at ibat_lo_alert.
die_temp_hi_alert_ 0x09 R/W [15:0] 0 Signed number that sets an upper limit that can be used to trigger an interrupt based on
limit high die temperature. The value in °C can be calculated from the A/D reading, die_temp,
as TDIE(°C) = die_temp × 0.0215°C/LSB - 264.4°C. The alert is enabled by setting
en_die_temp_hi_alert and can be read back and cleared at die_temp_hi_alert.
bsr_hi_alert_limit 0x0A R/W [15:0] 0 Sets an upper limit that can be used to trigger an interrupt based on high battery resistance.
The per-cell battery resistance is relative to the battery charge current setting resistor,
RSNSB, and can be computed in Ω from: BSR = cell_count × bsr × RSNSB / 500. The alert
is enabled by setting en_bsr_hi_alert and can be read back and cleared at bsr_hi_alert.

Rev A

36 For more information [Link]

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
thermistor_voltage_ 0x0B R/W [15:0] 0 Signed number that sets an upper limit that can be used to trigger an interrupt based on
hi_alert_limit thermistor value out of range. The value is based on the A/D value for thermistor_voltage.
The thermistor value can be determined by the expression RNTC = RNTCBIAS × (21829
- thermistor_voltage) / thermistor_voltage. Recall that the thermistor has a negative
temperature coefficient so higher temperatures correspond to lower thermistor_voltage
readings and vice-versa. The alert is enabled by setting en_thermistor_voltage_hi_alert
can be read back and cleared at thermistor_voltage_hi_alert.
thermistor_voltage_ 0x0C R/W [15:0] 0 Signed number that sets a lower limit that can be used to trigger an interrupt based on
lo_alert_limit thermistor value out of range. The value is based on the A/D value for thermistor_voltage.
The thermistor value can be determined by the expression RNTC = RNTCBIAS × (21829
- thermistor_voltage) / thermistor_voltage. Recall that the thermistor has a negative
temperature coefficient so higher temperatures correspond to lower thermistor_voltage
readings and vice-versa. The alert is enabled by setting en_thermistor_voltage_lo_alert
and can be read back and cleared at thermistor_voltage_lo_alert.
EN_LIMIT_ALERTS_ 0x0D R/W [15:0] 0 Enable limit monitoring and alert notification via SMBALERT
REG
en_telemetry_valid_ [15] 0 To ensure high measurement accuracy, the telemetry system in the LTC4162 has a
alert nominal start-up time of approximately 12ms. Setting this interrupt request causes
an SMBALERT telemetry_valid_alert when telemetry_valid indicates that the telemetry
system's readings are valid. Note that the switching battery charger will not operate until
this telemetry system warmup period has passed, regardless of the state of this setting.
en_bsr_done_alert [14] 0 Interrupt request that causes an SMBALERT upon bsr_done_alert when the bsr (battery-
series-resistance) measurement is finished.
en_vbat_lo_alert [11] 0 Interrupt request that causes an SMBALERT upon vbat_lo_alert when vbat is below
vbat_lo_alert_limit.
en_vbat_hi_alert [10] 0 Interrupt request that causes an SMBALERT upon vbat_hi_alert when vbat is above
vbat_hi_alert_limit.
en_vin_lo_alert [9] 0 Interrupt request that causes an SMBALERT upon vin_lo_alert when vin is below
vin_lo_alert_limit.
en_vin_hi_alert [8] 0 Interrupt request that causes an SMBALERT upon vin_hi_alert when vin is above
vin_hi_alert_limit.
en_vout_lo_alert [7] 0 Interrupt request that causes an SMBALERT upon vout_lo_alert when vout is below
vout_lo_alert_limit.
en_vout_hi_alert [6] 0 Interrupt request that causes an SMBALERT upon vout_hi_alert when vout is above
vout_hi_alert_limit.
en_iin_hi_alert [5] 0 Interrupt request that causes an SMBALERT upon iin_hi_alert when iin is above
iin_hi_alert_limit.
en_ibat_lo_alert [4] 0 Interrupt request that causes an SMBALERT upon ibat_lo_alert when ibat is below
ibat_lo_alert_limit.
en_die_temp_hi_ [3] 0 Interrupt request that causes an SMBALERT upon die_temp_hi_alert when die_temp is
alert above die_temp_hi_alert_limit.
en_bsr_hi_alert [2] 0 Interrupt request that causes an SMBALERT upon bsr_hi_alert when bsr is above
bsr_hi_alert_limit.
en_thermistor_ [1] 0 Interrupt request that causes an SMBALERT upon thermistor_voltage_hi_alert when
voltage_hi_alert thermistor_voltage is above thermistor_voltage_hi_alert_limit. Recall that the thermistor
has a negative temperature coefficient so higher thermistor_voltage readings correspond
to lower temperatures.
en_thermistor_ [0] 0 Interrupt request that causes an SMBALERT upon thermistor_voltage_lo_alert when
voltage_lo_alert thermistor_voltage is below thermistor_voltage_lo_alert_limit. Recall that the thermistor
has a negative temperature coefficient so lower thermistor_voltage readings correspond
to higher temperatures.

Rev A

For more information [Link] 37

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
EN_CHARGER_ 0x0E R/W [12:0] 0 Enable charger state notification via SMBALERT
STATE_ALERTS_REG
en_bat_detect_ [12] 0 Interrupt request that causes an SMBALERT upon bat_detect_failed_fault_alert as
failed_fault_alert indicated by bat_detect_failed_fault due to an inability to source power to the battery
during battery detection testing (usually due to either iin_limit_active or vin_uvcl_active).
en_battery_ [11] 0 Interrupt request that causes an SMBALERT upon battery_detection_alert as indicated
detection_alert by battery_detection due to the LTC4162 entering battery detection testing.
en_charger_ [8] 0 Interrupt request that causes an SMBALERT upon charger_suspended_alert as indicated
suspended_alert by charger_suspended whereby battery charging is terminated due to suspend_charger
or thermistor_voltage out of jeita_t1 - jeita_t6 range.
en_precharge_alert [7] 0 Interrupt request that causes an SMBALERT upon precharge_alert as indicated by
precharge denoting the onset of the precharge phase of a battery charging cycle.
en_cc_cv_charge_ [6] 0 Interrupt request that causes an SMBALERT upon cc_cv_charge_alert as indicated by
alert cc_cv_charge denoting the onset of the constant current / constant voltage phase of a
battery charging cycle.
en_ntc_pause_alert [5] 0 Interrupt request that causes an SMBALERT upon ntc_pause_alert as indicated by
ntc_pause whereby a battery charge cycle is interrupted due to thermistor_voltage out
of range as set by the jeita_t1 through jeita_t6 values.
en_timer_term_alert [4] 0 Interrupt request that causes an SMBALERT upon timer_term_alert as indicated
by timer_term whereby a battery charge cycle terminates due to tcvtimer reaching
max_cv_time, the maximum time allowed in constant_voltage mode.
en_c_over_x_term_ [3] 0 Interrupt request that causes an SMBALERT upon c_over_x_term_alert as indicated by
alert c_over_x_term whereby a battery charge cycle terminates due to ibat dropping below
the c_over_x_threshold.
en_max_charge_ [2] 0 Interrupt request that causes an SMBALERT upon max_charge_time_fault_alert as
time_alert indicated by max_charge_time_fault whereby charging has terminated due to tchargetimer
reaching max_charge_time.
en_bat_missing_ [1] 0 Interrupt request that causes an SMBALERT upon bat_missing_fault_alert as indicated
fault_alert by bat_missing_fault whereby charging is prohibited if no battery is detected during the
battery presence detection phase at the beginning of a charge cycle.
en_bat_short_fault_ [0] 0 Interrupt request that causes an SMBALERT upon bat_short_fault_alert as indicated by
alert bat_short_fault whereby charging is prohibited if a shorted battery is detected during
the battery presence detection phase at the beginning of a charge cycle.
EN_CHARGE_ 0x0F R/W [5:0] 0 Enable charge status notification via SMBALERT
STATUS_ALERTS_
REG
en_ilim_reg_active_ [5] 0 Interrupt request that causes an ilim_reg_active_alert SMBALERT upon ilim_reg_active
alert (VCSP-VCSN greater than 45mV). May indicates that the switching regulator is currently
controlling power delivery based on a safety current limit. This should not occur under
normal conditions and is likely the result of a circuit board fault. Alternately indicates
that the switching regulator is in dropout (near 100% duty cycle) and is not regulating
on any feedback control loop.
en_thermal_reg_ [4] 0 Interrupt request that causes a thermal_reg_active_alert SMBALERT upon thermal_reg_
active_alert active indicating that the icharge_dac is being dialed back to reduce internal die heating.
en_vin_uvcl_active_ [3] 0 Interrupt request that causes a vin_uvcl_active_alert SMBALERT upon vin_uvcl_active
alert indicating that the undervoltage regulation loop has taken control of the switching regulator.
en_iin_limit_active_ [2] 0 Interrupt request that causes a iin_limit_active_alert SMBALERT upon iin_limit_active
alert indicating that the input current regulation loop has taken control of the switching regulator.

Rev A

38 For more information [Link]

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
en_constant_ [1] 0 Interrupt request that causes a constant_current_alert SMBALERT upon constant_current
current_alert indicating that the battery charger constant current regulation loop has taken control
of the switching regulator.
en_constant_ [0] 0 Interrupt request that causes a constant_voltage_alert SMBALERT upon constant_voltage
voltage_alert indicating that the battery charger constant voltage regulation loop has taken control
of the switching regulator.
thermal_reg_start_ 0x10 R/W [15:0] 17897 Signed number that sets the start of the temperature region for thermal regulation. To
temp prevent overheating, a thermal regulation feedback loop utilizing die_temp sets an upper
limit on icharge_dac following a linear gradient from full scale (31) to minimum scale
(0) between thermal_reg_start_temp and thermal_reg_end_temp. The default value of
17897 corresponds to 120°C.
thermal_reg_end_ 0x11 R/W [15:0] 18130 Signed number that sets the end of the temperature region for thermal regulation. To
temp prevent overheating, a thermal regulation feedback loop utilizing die_temp sets an upper
limit on icharge_dac following a linear gradient from full scale (31) to minimum scale
(0) between thermal_reg_start_temp and thermal_reg_end_temp. The default value of
18130 corresponds to 125°C.
CONFIG_BITS_REG 0x14 R/W [5:1] 0 System configuration settings
suspend_charger [5] 0 Causes battery charging to be suspended. This setting should be used cautiously.
For embedded battery systems where two wire interface communication relies on a
minimum battery voltage, setting this bit could result in a deadlock that may require
factory service to correct.
run_bsr [4] 0 Causes the battery equivalent-series-resistance (bsr) measurement to be made as soon
as a charge cycle starts or immediately if a charge cycle is already running.
telemetry_speed [3] 0 Forces the telemetry system to take measurements at the higher rate of approximately
once every 11ms whenever the telemetry system is on. When this bit is disabled, the
telemetry system will slow down to about once every 5s to reduce power when not charging.
Setting telemetry_speed to tel_high_speed in conjunction with force_telemetry_on with
no input power available will increase battery drain.
Enums: tel_high_speed = 1,
tel_low_speed = 0
force_telemetry_on [2] 0 Causes the telemetry system to operate at all times, including times when only battery
power is available.
mppt_en [1] 0 Causes the Maximum Power-Point Tracking algorithm to run. The maximum power
point algorithm takes control of the input undervoltage regulation control loop via the
input_undervoltage_dac to seek the optimum power-point for resistive sources such
as a long cable or solar panel.
iin_limit_target 0x15 R/W [5:0] 63 Controls the target input current limit setting. The input current is limited by regulating
charge current in response to the voltage across an external current sense resistor,
RSNSI, between the CLP and CLN pins and is given by (iin_limit_target + 1) × 500µV /
RSNSI. Note that the LTC4162 can only limit charge current based on this setting. It does
not have the authority to block current from passing directly through to the system load.
Connecting the system load to the battery, however, can allow total input current control.
input_undervoltage_ 0x16 R/W [7:0] 31 Controls the input undervoltage regulation setting. The regulation voltage, given by
setting (input_undervoltage_setting + 1) × 140.625mV, is the voltage at which the charge
current will be reduced to prevent further droop in supply voltage due to a resistive
source. If mppt_en is set, the MPPT algorithm will override this setting. The actual input
undervoltage value can be read back from the input_undervoltage_dac.
arm_ship_mode 0x19 R/W [15:0] 0 Setting this register to arm arms the ultra low-power ship and store mode. Ship mode
does not take effect until the VIN pin drops below approximately 1V or immediately if
VIN is already below 1V.
Enum: arm = 21325

Rev A

For more information [Link] 39

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
charge_current_ 0x1A R/W [4:0] 31 Controls the target charge current regulation servo level. The charge current is regulated
setting by servoing the voltage across an external current sense resistor, RSNSB, between the
CSP and CSN pins. The servo voltage is given by (charge_current_setting + 1) × 1mV. The
effective charge current, determined by the external resistor, RSNSB, is given by (charge_
current_setting + 1) × 1mV / RSNSB. icharge_dac will follow charge_current_setting
unless thermal_reg_active is true or the JEITA algorithm, with en_jeita, has altered it.
vcharge_setting 0x1B R/W [4:0] 31 Controls the final charge voltage regulation servo level. To maintain inherent over-charge
protection, only Lithium Ion appropriate charge voltage values can be selected. The
charge voltage setting can be computed from cell_count × (vcharge_setting × 12.5mV
+ 3.8125V) where vcharge_setting ranges from 0 to 31 (4.2V max). vcharge_dac will
follow vcharge_setting unless the advanced JEITA temperature control system (en_jeita)
has altered it.
Enum: vcharge_lion_default = 31
c_over_x_threshold 0x1C R/W [15:0] 2184 Signed number that sets the ibat A/D value used to qualify C/x detection and termination.
The C/x level is based on the value for ibat which has a scaling factor of 1.466µV /
RSNSB amperes/LSB. For example, to make the C/x level C/10 (a very common choice)
then c_over_x_threshold should be set to c_over_10 which is 10% of the maximum
possible ibat reading (32mV × 37.5 × 18,191 / 10). 32mV is the full scale charge current
signal from CSP to CSN, 37.5 is the internal charge amplifier's gain and 18,191 is the
A/D's span term in counts per Volt.
Enum: c_over_10 = 2184
max_cv_time 0x1D R/W [15:0] 14400 Sets the constant-voltage termination setting against which the tcvtimer is compared.
The timer begins at the onset of the constant_voltage phase of charging and increments
at one count per second. The default setting is 14,400 (4 hours).
Enums: 30mins = 1800,
1hour = 3600,
2hours = 7200,
4hours_default = 14400
max_charge_time 0x1E R/W [15:0] 0 Sets the total charge time termination setting against which the tchargetimer is compared.
The default value of 0 disables the total charge time feature and prevents the tchargetimer
from running. If enabled with a non zero value, the tchargetimer begins counting at the
onset of a charge cycle and increments at one count per minute.
Enum: maxchargetime_disable = 0
jeita_t1 0x1F R/W [15:0] 16117 Signed number that sets the JEITA temperature region transition temperature T1 between
JEITA regions R1 and R2. The temperature is based on the thermistor reading from the
telemetry system; RNTC = RNTCBIAS × (21829 - thermistor_voltage) / thermistor_voltage.
Recall that the thermistor has a negative temperature coefficient so jeita_t1, representing
colder temperatures, will have the highest value and jeita_t6, representing warmer
temperatures, will have the lowest value. The default value of 16117 maps to about 0°C
for the expected thermistor β value of 3490K.
jeita_t2 0x20 R/W [15:0] 14113 Signed number that sets the JEITA temperature region transition temperature T2 between
JEITA regions R2 and R3. The temperature is based on the thermistor reading from the
telemetry system; RNTC = RNTCBIAS × (21829 - thermistor_voltage) / thermistor_voltage.
Recall that the thermistor has a negative temperature coefficient so jeita_t1, representing
colder temperatures, will have the highest value and jeita_t6, representing warmer
temperatures, will have the lowest value. The default value of 14113 maps to about 10°C
for the expected thermistor β value of 3490K.
jeita_t3 0x21 R/W [15:0] 7970 Signed number that sets the JEITA temperature region transition temperature T3 between
JEITA regions R3 and R4. The temperature is based on the thermistor reading from the
telemetry system; RNTC = RNTCBIAS × (21829 - thermistor_voltage) / thermistor_voltage.
Recall that the thermistor has a negative temperature coefficient so jeita_t1, representing
colder temperatures, will have the highest value and jeita_t6, representing warmer
temperatures, will have the lowest value. The default value of 7970 maps to about 40°C
for the expected thermistor β value of 3490K.

Rev A

40 For more information [Link]

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
jeita_t4 0x22 R/W [15:0] 7112 Signed number that sets the JEITA temperature region transition temperature T4 between
JEITA regions R3 and R4. The temperature is based on the thermistor reading from the
telemetry system; RNTC = RNTCBIAS × (21829 - thermistor_voltage) / thermistor_voltage.
Recall that the thermistor has a negative temperature coefficient so jeita_t1, representing
colder temperatures, will have the highest value and jeita_t6, representing warmer
temperatures, will have the lowest value. The default value of 7112 maps to about 45°C
for the expected thermistor β value of 3490K.
jeita_t5 0x23 R/W [15:0] 6325 Signed number that sets the JEITA temperature region transition temperature T5 between
JEITA regions R5 and R6. The temperature is based on the thermistor reading from the
telemetry system; RNTC = RNTCBIAS × (21829 - thermistor_voltage) / thermistor_voltage.
Recall that the thermistor has a negative temperature coefficient so jeita_t1, representing
colder temperatures, will have the highest value and jeita_t6, representing warmer
temperatures, will have the lowest value. The default value of 6325 maps to about 50°C
for the expected thermistor β value of 3490K.
jeita_t6 0x24 R/W [15:0] 4970 Signed number that sets the JEITA temperature region transition temperature T6 between
JEITA regions R6 and R7. The temperature is based on the thermistor reading from the
telemetry system; RNTC = RNTCBIAS × (21829 - thermistor_voltage) / thermistor_voltage.
Recall that the thermistor has a negative temperature coefficient so jeita_t1, representing
colder temperatures, will have the highest value and jeita_t6, representing warmer
temperatures, will have the lowest value. The default value of 4970 maps to about 60°C
for the expected thermistor β value of 3490K.
VCHARGE_ 0x25 R/W [9:0] 631 vcharge_setting values for JEITA temperature regions jeita_t6 and jeita_t5
JEITA_6_5_REG
vcharge_jeita_6 [9:5] 19 Sets the charge voltage to be used in JEITA region 6 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to vcharge_setting and can be calculated
using vcharge_jeita_6 × 12.5mV + 3.8125V. The default value of 19 corresponds to 4.05V.
vcharge_jeita_5 [4:0] 23 Sets the charge voltage to be used in JEITA region 5 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to vcharge_setting and can be calculated
using vcharge_jeita_5 × 12.5mV + 3.8125V. The default value of 23 corresponds to 4.1V.
VCHARGE_ 0x26 R/W [14:0] 24575 vcharge_setting values for JEITA temperature regions jeita_t4, jeita_t3, and jeita_t2
JEITA_4_3_2_REG
vcharge_jeita_4 [14:10] 23 Sets the charge voltage to be used in JEITA region 4 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to vcharge_setting and can be calculated
using vcharge_jeita_4 × 12.5mV + 3.8125V. The default value of 23 corresponds to 4.1V
vcharge_jeita_3 [9:5] 31 Sets the charge voltage to be used in JEITA region 3 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to vcharge_setting and can be calculated
using vcharge_jeita_3 × 12.5mV + 3.8125V. The default value of 31 corresponds to 4.2V.
vcharge_jeita_2 [4:0] 31 Sets the charge voltage to be used in JEITA region 2 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to vcharge_setting and can be calculated
using vcharge_jeita_2 × 12.5mV + 3.8125V. The default value of 31 corresponds to 4.2V.
ICHARGE_ 0x27 R/W [9:0] 495 charge_current_setting values for JEITA temperature regions jeita_t6 and jeita_t5
JEITA_6_5_REG
icharge_jeita_6 [9:5] 15 Sets the charge current to be used in JEITA region 6 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to charge_current_setting where the
charge current can be calculated using (icharge_jeita_6 + 1) × 1mV / RSNSB. The default
value of 15 corresponds to a VCSP-VCSN servo voltage of 16mV which is half scale or C/2.
icharge_jeita_5 [4:0] 15 Sets the charge current to be used in JEITA region 5 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to charge_current_setting where the
charge current can be calculated using (icharge_jeita_5 + 1) × 1mV / RSNSB. The default
value of 15 corresponds to a VCSP-VCSN servo voltage of 16mV which is half scale or C/2.
ICHARGE_ 0x28 R/W [14:0] 32751 charge_current_setting value for JEITA temperature regions jeita_t4, jeita_t3, and jeita_t2
JEITA_4_3_2_REG

Rev A

For more information [Link] 41

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
icharge_jeita_4 [14:10] 31 Sets the charge current to be used in JEITA region 4 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to charge_current_setting where the
charge current can be calculated using (icharge_jeita_4 + 1) × 1mV / RSNSB. The default
value of 31 corresponds to a VCSP-VCSN servo voltage of 32mV which is full scale.
icharge_jeita_3 [9:5] 31 Sets the charge current to be used in JEITA region 3 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to charge_current_setting where the
charge current can be calculated using (icharge_jeita_3 + 1) × 1mV / RSNSB. The default
value of 31 corresponds to a VCSP-VCSN servo voltage of 32mV which is full scale.
icharge_jeita_2 [4:0] 15 Sets the charge current to be used in JEITA region 2 as illustrated in the JEITA Temperature
Qualified Charging section. The value corresponds to charge_current_setting where the
charge current can be calculated using (icharge_jeita_2 + 1) × 1mV / RSNSB. The default
value of 15 corresponds to a VCSP-VCSN servo voltage of 16mV which is half scale or C/2.
CHARGER_CONFIG_ 0x29 R/W [2:0] 1 Battery charger configuration settings
BITS_REG
en_c_over_x_term [2] 0 Enables charge current based (C/x) battery charger termination as set by ibat dropping
to the c_over_x_threshold in constant_voltage.
en_jeita [0] 1 Enables the JEITA temperature qualified charging system.
tchargetimer 0x30 R [15:0] 0 If max_charge_time is written to a non zero value tchargetimer is the elapsed time in
minutes since the beginning of a charge cycle. The LTC4162 will terminate charging
when tchargetimer reaches the value in max_charge_time.
tcvtimer 0x31 R [15:0] 0 This is the elapsed time in seconds since the battery charger has been in the constant_
voltage phase of charging. If this value exceeds max_cv_time then charging is considered
complete and will terminate.
charger_state 0x34 R [12:0] 256 Real time battery charger state indicator. Individual bits are mutually exclusive.
Enums: bat_detect_failed_fault = 4096,
battery_detection = 2048,
charger_suspended = 256,
precharge = 128,
cc_cv_charge = 64,
ntc_pause = 32,
timer_term = 16,
c_over_x_term = 8,
max_charge_time_fault = 4,
bat_missing_fault = 2,
bat_short_fault = 1
charge_status 0x35 R [5:0] 0 Charge status indicator. Individual bits are mutually exclusive and are only active in
charging states.
Enums: ilim_reg_active = 32,
thermal_reg_active = 16,
vin_uvcl_active = 8,
iin_limit_active = 4,
constant_current = 2,
constant_voltage = 1,
charger_off = 0
LIMIT_ALERTS_REG 0x36 R [15:0] 0 Limit alert register. This input/output register indicates that an enabled alert has occurred.
Individual alerts are enabled in EN_LIMIT_ALERTS_REG. Writing 0 to any bit clears that
alert. Once set, alert bits remain high until cleared or disabled.
telemetry_valid_alert [15] 0 Alert that indicates that the telemetry system warm-up time has expired and valid
telemetry data is available from the serial port. This alert bit is cleared by writing it back
to 0 with the remaining bits in this register set to 1s. It can also be cleared by clearing
en_telemetry_valid_alert.

Rev A

42 For more information [Link]

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
bsr_done_alert [14] 0 Alert that indicates that the battery equivalent-series-resistance measurement is finished
and a result is available in bsr. This alert bit is cleared by writing it back to 0 with the
remaining bits in this register set to 1s. It can also be cleared by clearing en_bsr_done_alert.
vbat_lo_alert [11] 0 Alert that indicates that vbat is below the value set by vbat_lo_alert_limit. This alert bit
is cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_vbat_lo_alert.
vbat_hi_alert [10] 0 Alert that indicates that vbat is above the value set by vbat_hi_alert_limit. This alert bit
is cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_vbat_hi_alert.
vin_lo_alert [9] 0 Alert that indicates that vin is below the value set by vin_lo_alert_limit. This alert bit is
cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_vin_lo_alert.
vin_hi_alert [8] 0 Alert that indicates that vin is above the value set by vin_hi_alert_limit. This alert bit is
cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_vin_hi_alert.
vout_lo_alert [7] 0 Alert that indicates that vout is below the value set by vout_lo_alert_limit. This alert bit
is cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_vout_lo_alert.
vout_hi_alert [6] 0 Alert that indicates that vout is above the value set by vout_hi_alert_limit. This alert bit
is cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_vout_hi_alert.
iin_hi_alert [5] 0 Alert that indicates that iin is above the value set by iin_hi_alert_limit. This alert bit is
cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_iin_hi_alert.
ibat_lo_alert [4] 0 Alert that indicates that ibat is below the value set by ibat_lo_alert_limit. This alert bit
is cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_ibat_lo_alert.
die_temp_hi_alert [3] 0 Alert that indicates that die_temp is above the value set by die_temp_hi_alert_limit. This
alert bit is cleared by writing it back to 0 with the remaining bits in this register set to
1s. It can also be cleared by clearing en_die_temp_hi_alert.
bsr_hi_alert [2] 0 Alert that indicates that bsr is above the value set by bsr_hi_alert_limit. This alert bit is
cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_bsr_hi_alert.
thermistor_voltage_ [1] 0 Alert that indicates that thermistor_voltage is above the value set by thermistor_voltage_
hi_alert hi_alert_limit. This alert bit is cleared by writing it back to 0 with the remaining bits in
this register set to 1s. It can also be cleared by clearing en_thermistor_voltage_hi_alert.
thermistor_voltage_ [0] 0 Alert that indicates that thermistor_voltage is below the value set by thermistor_voltage_
lo_alert lo_alert_limit. This alert bit is cleared by writing it back to 0 with the remaining bits in
this register set to 1s. It can also be cleared by clearing en_thermistor_voltage_lo_alert.
CHARGER_STATE_ 0x37 R [12:0] 0 Alert that indicates that charger states have occurred. Individual bits are enabled by
ALERTS_REG EN_CHARGER_STATE_ALERTS_REG. Writing 0 to any bit while writing 1s to the
remaining bits clears that alert. Once set, alert bits remain high until cleared or disabled.
bat_detect_failed_ [12] 0 Alert that indicates a bat_detect_failed_fault. This alert bit is cleared by writing it back
fault_alert to 0 with the remaining bits in this register set to 1s. It can also be cleared by clearing
en_bat_detect_failed_fault_alert.
battery_detection_ [11] 0 Alert that indicates the battery charger is performing battery_detection. This alert bit is
alert cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_battery_detecttion_alert.
charger_suspended_ [8] 0 Alert that indicates the battery charger is in the charger_suspended state. This alert bit
alert is cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_charger_suspended_alert.

Rev A

For more information [Link] 43

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
precharge_alert [7] 0 Alert that indicates that the battery charger is in the precharge phase. This alert bit is
cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_precharge_alert.
cc_cv_charge_alert [6] 0 Alert that indicates that the battery charge is in the cc_cv_charge phase. This alert bit
is cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_cc_cv_charge_alert.
ntc_pause_alert [5] 0 Alert that indicates that the battery charger is in the ntc_pause state. This alert bit is
cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_ntc_pause_alert.
timer_term_alert [4] 0 Alert that indicates that the battery charge is in the timer_term state. This alert bit is
cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_timer_term_alert.
c_over_x_term_alert [3] 0 Alert that indicates that the battery charge is in the c_over_x_term state. This alert bit
is cleared by writing it back to 0 with the remaining bits in this register set to 1s. It can
also be cleared by clearing en_c_over_x_term_alert.
max_charge_time_ [2] 0 Alert that indicates that the battery charge is in the max_charge_time_fault state. This
fault_alert alert bit is cleared by writing it back to 0 with the remaining bits in this register set to
1s. It can also be cleared by clearing en_max_charge_time_alert.
bat_missing_fault_ [1] 0 Alert that indicates that a bat_missing_fault has been detected. This alert bit is cleared
alert by writing it back to 0 with the remaining bits in this register set to 1s. It can also be
cleared by clearing en_bat_missing_fault_alert.
bat_short_fault_alert [0] 0 Alert that indicates that a bat_short_fault has been detected. This alert bit is cleared by
writing it back to 0 with the remaining bits in this register set to 1s. It can also be cleared
by clearing en_bat_short_fault_alert.
CHARGE_STATUS_ 0x38 R [5:0] 0 Alerts that charge_status indicators have occurred. Individual bits are enabled by
ALERTS_REG EN_CHARGE_STATUS_ALERTS_REG. Writing 0 to any bit clears that alert. Once set,
alert bits remain high until cleared or disabled.
ilim_reg_active_alert [5] 0 Alert that indicates that charge_status is ilim_reg_active. This alert bit is cleared by writing
it back to 0 with the remaining bits in this register set to 1s. It can also be cleared by
clearing en_ilim_reg_active_alert.
thermal_reg_active_ [4] 0 Alert that indicates that charge_status is thermal_reg_active. This alert bit is cleared by
alert writing it back to 0 with the remaining bits in this register set to 1s. It can also be cleared
by clearing en_thermal_reg_active_alert.
vin_uvcl_active_alert [3] 0 Alert that indicates that charge_status is vin_uvcl_active. This alert bit is cleared by
writing it back to 0 with the remaining bits in this register set to 1s. It can also be cleared
by clearing en_vin_uvcl_active_alert.
iin_limit_active_alert [2] 0 Alert that indicates that charge_status is iin_limit_active. This alert bit is cleared by writing
it back to 0 with the remaining bits in this register set to 1s. It can also be cleared by
clearing en_iin_limit_active_alert.
constant_current_ [1] 0 Alert that indicates that charge_status is constant_current. This alert bit is cleared by
alert writing it back to 0 with the remaining bits in this register set to 1s. It can also be cleared
by clearing en_constant_current_alert.
constant_voltage_ [0] 0 Alert that indicates that charge_status is constant_voltage. This alert bit is cleared by
alert writing it back to 0 with the remaining bits in this register set to 1s. It can also be cleared
by clearing en_constant_voltage_alert.
SYSTEM_STATUS_ 0x39 R [8:0] N/A Real time system status indicator bits
REG
en_chg [8] N/A Indicates that the battery charger is active.
cell_count_err [7] N/A A cell count error will occur and charging will be inhibited if the CELLS0 and CELLS1
pins are programmed for more than 8 cells. cell_count_err always indicates true when
telemetry is not enabled such as when the charger is not enabled.

Rev A

44 For more information [Link]

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
no_rt [5] N/A Indicates that no frequency setting resistor is detected on the RT pin. The RT pin impedance
detection circuit will typically indicate a missing RT resistor for values above 1.4MΩ.
no_rt always indicates true when the battery charger is not enabled such as when there
is no input power available.
thermal_shutdown [4] N/A Indicates that the LTC4162 is in thermal shutdown protection due to an excessively high
die temperature (typically 150°C).
vin_ovlo [3] N/A Indicates that input voltage shutdown protection is active due to an input voltage above
its protection shut-down threshold of approximately 38.6V.
vin_gt_vbat [2] N/A Indicates that the VIN pin voltage is sufficiently above the battery voltage to begin a
charge cycle (typically +150mV).
vin_gt_4p2v [1] N/A Indicates that the VIN pin voltage is at least greater than the switching regulator under-
voltage lockout level (4.2V typical).
intvcc_gt_2p8v [0] N/A Indicates that the INTVCC pin voltage is greater than the telemetry system lockout level
(2.8V typical).
vbat 0x3A R [15:0] 0 Signed number that indicates the A/D measurement for the per-cell battery voltage. The
value is based on the A/D scaling factor for the battery voltage measurement which is
cell_count × 192.4µV/LSB at the BATSENS+ pin.
vin 0x3B R [15:0] 0 Signed number that indicates the A/D measurement for the input voltage. The value is
based on the A/D scaling factor for the input voltage measurement which is 1.649mV/LSB.
vout 0x3C R [15:0] 0 Signed number that indicates the A/D measurement for the vout voltage. The value is based
on the A/D scaling factor for the output voltage measurement which is 1.653mV/LSB.
ibat 0x3D R [15:0] 0 Signed number that indicates the A/D measurement for the battery current. The value
is based on the A/D scaling factor for the charge current measurement (VCSP - VCSN)
which is 1.466µV / RSNSB amperes/LSB. If the charger is not enabled the value represents
drain on the battery and will be negative.
iin 0x3E R [15:0] 0 Signed number that indicates the A/D measurement for the input current (VCLP - VCLN).
The value is based on the A/D scaling factor for the input current measurement which
is 1.466µV / RSNSI amperes/LSB.
die_temp 0x3F R [15:0] 0 Signed number that indicates the A/D measurement for the die temperature. The value
can be calculated from the A/D reading in °C as TDIE(°C) = die_temp × 0.0215°C/LSB
- 264.4°C.
thermistor_voltage 0x40 R [15:0] 0 Signed number that indicates the A/D measurement for the NTC pin voltage. The thermistor
value can be determined by the expression RNTC = RNTCBIAS × thermistor_voltage /
(21829 - thermistor_voltage). Recall that the thermistor has a negative temperature
coefficient so higher temperatures make lower thermistor_voltage readings and vice-versa.
Enum: open_thermistor = 21684
bsr 0x41 R [15:0] 0 Indicates the A/D measurement for the per-cell battery resistance. The battery resistance is
relative to the battery charge current setting resistor, RSNSB, and can be computed in Ω
from cell_count × bsr × RSNSB / 500. If the charge current, ibat, is below icharge_over_10,
bsr_questionable will be set.

Rev A

For more information [Link] 45

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
jeita_region 0x42 R [2:0] 0 Indicates the LTC4162 JEITA battery temperature region containing the thermistor_voltage.
The temperature region consists of the values bounded by the transition temperatures
jeita_t(R-1) and jeita_t(R). Recall that the thermistor has a negative temperature coefficient
so higher temperatures make lower thermistor_voltage readings and vice-versa. JEITA
temperature-controlled charging is active only when en_jeita is at its default value
of 1. JEITA regions R7 (jeita_region = 7) and R1 (jeita_region = 1) indicate that the
thermistor_voltage (battery temperature) is out of range for charging and therefore charging
is paused (ntc_pause). The transition temperatures are set by jeita_t1 through jeita_t6.
Enums: R7 = 7,
R6 = 6,
R5 = 5,
R4 = 4,
R3 = 3,
R2 = 2,
R1 = 1
CHEM_CELLS_REG 0x43 R [11:0] 0 Programmed battery chemistry
chem [11:8] 0 Indicates the chemistry of the battery being charged. For additional safety, application
software can test this value to ensure that the correct version of the LTC4162 (LTC4162-L,
LTC4162-F or LTC4162-S) is populated on the circuit board.
Enums: LTC4162_LAD = 0,
LTC4162_L42 = 1,
LTC4162_L41 = 2,
LTC4162_L40 = 3,
LTC4162_FAD = 4,
LTC4162_FFS = 5,
LTC4162_FST = 6,
LTC4162_SST = 8,
LTC4162_SAD = 9
cell_count [3:0] 0 Indicates the cell count value detected by the CELLS0 and CELLS1 pin strapping.
cell_count always indicates 0 when the battery charger is not enabled such as when
there is no input power available.
Enum: Unknown = 0
icharge_dac 0x44 R [4:0] 0 Indicates the actual charge current setting applied to the charge current digital to analog
converter. icharge_dac is ramped up/down to implement digital soft-start/stop. The
LTC4162 sets the value of icharge_dac based on charger_state, thermistor_voltage,
and charger settings including charge_current_setting, icharge_jeita_2 through
icharge_jeita_6, jeita_t1 through jeita_t6 and en_jeita. Recall that the charge current is
regulated by controlling the voltage across an external current sense resistor RSNSB.
The servo voltage is given by (icharge_dac + 1) × 1mV. The charge current servo level
is thus given by (icharge_dac + 1) × 1mV/RSNSB.
vcharge_dac 0x45 R [4:0] 0 This is the actual battery voltage setting applied to the charge voltage digital to analog
converter. The LTC4162 sets the value of vcharge_dac based on charger_state,
thermistor_voltage, and charger settings including vcharge_setting, vcharge_jeita_2
through vcharge_jeita_6, jeita_t1 through jeita_t6, thermistor_voltage and en_jeita. The
charge voltage setting can be computed from cell_count × (vcharge_setting × 12.5mV
+ 3.8125V) where vcharge_setting ranges from 0 to 31 (4.2V max).
iin_limit_dac 0x46 R [5:0] 0 Indicates the actual input current limit. The iin_limit_dac will follow the value programmed
in iin_limit_target. The input current will be regulated to a maximum value given by
(iin_limit_dac + 1) × 500µV / RSNSI.
vbat_filt 0x47 R [15:0] 0 Signed number that is a digitally filtered version of the A/D measurement of vbat. The
value is based on the A/D scaling factor for the battery voltage measurement which is
cell_count × 192.4µV/LSB at the BATSENS+ pin.

Rev A

46 For more information [Link]

LTC4162-L
REGISTER DESCRIPTIONS
Command Bit
Symbol Name Code Access Range Default Description
bsr_charge_current 0x48 R [15:0] 0 Signed number that is the battery charge current that existed during the battery series
resistance measurement. The value is based on the A/D value, ibat, which has a scaling
factor of 1.466µV / RSNSB amperes/LSB. If the battery series resistance (bsr) test runs
with ibat values less than icharge_over_10, the accuracy of the test is questionable due
to low signal level and bsr_questionable will set. Rerunning the battery series resistance
test earlier in the charge cycle with higher ibat, and therefore higher bsr_charge_current,
will give the most accurate result.
Enum: icharge_over_10 = 2184
TELEMETRY_ 0x4A R [1:0] 0 Telemetry system status register
STATUS_REG
bsr_questionable [1] 0 Indicates that the battery series resistance measurement is questionable due to low
signal, specifically that ibat was less than icharge_over_10, when the last battery series
resistance (bsr) measurement was taken. bsr_charge_current contains the ibat A/D value
present when the battery series resistance measurement was made.
telemetry_valid [0] 0 Indicates that the telemetry system autozero amplifiers have had sufficient time,
approximately 12ms, to null their offsets. Battery charging is disabled until the telemetry
system warm up time has passed.
input_undervoltage_ 0x4B R [7:0] 0 Input undervoltage regulation digital to analog converter value. The regulation voltage
dac is given by (input_undervoltage_dac + 1) × 140.625mV. If enabled, the MPPT algorithm
will directly manipulate this value. Otherwise it will follow input_undervoltage_setting.
Revision: 1773 Date: 2018-03-15 [Link] -0400 (Thu, 15 Mar 2018)

Rev A

For more information [Link] 47

LTC4162-L
TYPICAL APPLICATIONS
1-Cell USB Power Delivery Charger with PowerPath

MN1 11mΩ
VIN VOUT
0.1µF 10µF
7 6 5 4 3 27, 28
22
VIN INFET CLP CLN VOUTA VOUT BATFET MN2
1
BOOST
22nF
12
SMBALERT L1 4.7µH
15 25, 26
DVCC SW
µCONTROLLER 13 21
SCL CSP
14 LTC4162-L
SDA
16mΩ
20
16 CSN
SYNC + 19
17 BATSENS
CELLS0 10k
18 9
CELLS1 NTCBIAS
10
INTVCC VCC2P5 RT PGND AGND NTC
2 8 11 23, 24 29
R1
T 10µF
63.4k 10k
4.7µF 1µF

4162L TA02

MN1, MN2: FDMC8327L

R1: NTCS0402E3103FLT
L1: XAL5030-472MEC

9V to 35V 2-Cell 3.2A Charger with PowerPath and 2A Input Limit

MN1 16mΩ
VIN VOUT
0.1µF 10µF
7 6 5 4 3 27, 28
22
VIN INFET CLP CLN VOUTA VOUT BATFET MN2
1
BOOST
22nF
12
SMBALERT L1 6.8µH
15 25, 26
DVCC SW
µCONTROLLER 13 21
SCL CSP
14 LTC4162-L
SDA
10mΩ
20
16 CSN
SYNC 19
17 BATSENS+
CELLS0 10k
18 9
CELLS1 NTCBIAS
10
VCC2P5 INTVCC RT PGND AGND NTC
8 2 11 23, 24 29
R1
T 10µF
63.4k 10k
1µF 4.7µF

4162L TA03

MN1, MN2: FDMC8327L

R1: NTCS0402E3103FLT
L1: XAL6060-682MEC

Rev A

48 For more information [Link]

LTC4162-L
TYPICAL APPLICATIONS
Solar Powered 3-Cell 3.2A Charger with Maximum Power Point Tracking

36 CELL PANEL

– + MN1 16mΩ

2.5Ω 0.1µF 10µF

7 6 5 4 3 27, 28
+ C2 VIN INFET CLP CLN VOUTA VOUT BATFET
22
MN2
150µF 1
BOOST
22nF

12 L1
SMBALERT 4.7µH
15 25, 26
DVCC SW
13 21
SCL CSP
14 LTC4162-LADM
SDA
10mΩ
20
16 CSN
SYNC 19
17 BATSENS+
CELLS0 10k
18 9
CELLS1 NTCBIAS
10 SYSTEM
INTVCC VCC2P5 RT PGND AGND NTC
LOAD
MN1: FDMC8327L 2 8 11 23, 24 29 R1
T 10µF
MN2: 2N7002 10k
R1: NTCS0402E3103FLT 4.7µF 1µF 63.4k
L1: XAL5030-472MEC
4162L TA04

Rev A

For more information [Link] 49

LTC4162-L
PACKAGE DESCRIPTION

UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)

0.70 ±0.05

4.50 ±0.05
3.10 ±0.05

2.50 REF
2.65 ±0.05
3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH
2.50 REF R = 0.20 OR 0.35
R = 0.05 R = 0.115 × 45° CHAMFER
4.00 ±0.10 0.75 ±0.05
TYP TYP
(2 SIDES) 27 28

0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6) 1

5.00 ±0.10
3.50 REF
(2 SIDES)

3.65 ±0.10
2.65 ±0.10

(UFD28) QFN 0816 REV C

0.200 REF 0.25 ±0.05

0.00 – 0.05 0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

Rev A

50 For more information [Link]

LTC4162-L
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/18 Changed Parameter and Conditions for Symbol VOLI2C 6
Changed 3.5µA to 2.8µA in Low Power Ship Mode section 28

Rev A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For moreby
is granted information [Link]
implication or otherwise under any patent or patent rights of Analog Devices. 51
LTC4162-L
TYPICAL APPLICATION
USB PD (C Cable) Based Battery Charger with Power Path
MN1 MN2 16mΩ
VOUT
0.1µF 10µF
GND GND 200k
0.1µF
RX1+ TX1+
RX1– TX1– 32 31
VBUS VBUS VBUS_DISCHARGE VBUS
21 30
D+ D+ VBUS_C_CTRL0 7 6 5 4 3 27, 28
22 22
D– D– 10M VIN INFET CLP CLN VOUTA VOUT BATFET MN3
1
TX2– RX2– BOOST
TX2+ RX2+ 37 13 22nF
GPIO SCL
GND GND CYPD3125-40LQXIT L1 6.8µH
10k 25, 26
5 SW
CC2 CC1 CC1 36 14 21
GPIO SDA CSP
LTC4162-L
10k 10mΩ
390pF 15
DVCC 20
3 16 CSN
CC2 SYNC + 19
17 BATSENS
390pF GND VCCD VSYS XRES VDD VDDIO CELLS0
18 9 10k
33, 19 20 26 17 18 CELLS1 NTCBIAS
41 10
10k VCC2P5 INTVCC RT PGND AGND NTC
8 2 11 23, 24 29
R1
MN1, MN2, MN3: FDMC8327L 2.2µF T 10µF
2.2µF 63.4k 10k
R1: NTCS0402E3103FLT
1µF 4.7µF
L1: XAL6060-682MEC
2.2µF
4162L TA05

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Rev A

52
D16956-0-10/18(A)
[Link]
For more information [Link]  ANALOG DEVICES, INC. 2018

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LTC4162 L

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LTC4162 L

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LTC4162-L

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ISW ........................................................................ ±3.5A CLN 4 AGND 19 BATSENS+

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CHARGE CURRENT (A)

INPUT VOLTAGE (V)

No Input Battery Drain Current vs Ship Mode Battery Drain Current

BATTERY DRAIN CURRENT (µA)

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2.2Ah 3-Cell Battery Charge Charge Current During BSR

INFET / BATFET VOLTAGE (V)

BATTERY VOLTAGE (V)

CHARGE CURRENT (A)

Light to Dark Solar Panel Tracking Solar Panel Global Sweep

PANEL CURRENT (A)

PANEL VOLTAGE (V)

Multi-Peak Solar Panel Charge Current and Die Temperature

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Histogram of bsr Readings Histogram of die_temp Readings Histogram of ibat Readings

Histogram of iin Readings Histogram of vin Readings

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I2C SMBus Legend

SMBus WRITE WORD PROTOCOL

SMBus WRITE WORD WITH PEC PROTOCOL

SMBus READ WORD PROTOCOL

SMBus READ WORD WITH PEC PROTOCOL

SMBus ALERT RESPONSE ADDRESS PROTOCOL

SMBus ALERT RESPONSE ADDRESS PROTOCOL WITH PEC

*USE OF PACKET ERROR CHECKING IS OPTIONAL

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Table 3. Summary of Charger State Alerts

Table 4. Summary of Charger Status Alerts

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jeita_t2 14113 18290Ω 10°C

jeita_t3 7970 5751Ω 40°C

jeita_t4 7112 4832Ω 45°C

jeita_t5 6325 4080Ω 50°C

jeita_t6 4970 2948Ω 60°C

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tion values, max_charge_time and max_cv_time are both

24 max_charge_time_fault indicates that charging has termi-

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BATTERY DETECTION FAILED FAULT

BATTERY MISSING FAULT

vbat < 2.85V

chargetimer tcvtimer > max_cv_time charge_status = constant_voltage

MAXIMUM CHARGE CONSTANT VOLTAGE CONSTANT VOLTAGE

vbat < 35%VCHARGE vbat < 97.5%VCHARGE vbat < 97.5%VCHARGE

Figure 2. Battery Charging State Diagram

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jeita_t1 jeita_t2 jeita_t3 jeita_t4 jeita_t5 jeita_t6

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has built-in timing delays and glitch suppression filters to

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to the battery terminals with a separate Kelvin connection

load capacitor should be on the inductor side of this