DAYANANDA SAGAR COLLEGE OF ENGINEERING

(An Autonomous Institute Affiliated to VTU, Belagavi)

Shavige Malleshwara Hills, Kumaraswamy Layout, Bengaluru-560078

UG Semester End Examination, 2022

Course: Maximum marks: 100

Course Duration: 03 hours
Code:
Semester: IV

Note: i). Question ONE (a to t) must have four option and select four question from each module.
ii). Question 2 to 8 have a maximum of 16 marks and may have a maximum of four sub
question.
Q. No. Marks
c1 a) Another name for a unity gain amplifier is: 01
i) Difference amplifier ii) comparator iii) Single ended iv) Voltage follower
b) Slew rate of an ideal opamp is 01
i) Infinite ii) Very high iii)Low iv)Zero
c) A non-inverting amplifier has Ri =1 kΩ and Rf =100 kΩ. The voltage gain is  01
_____
i) 100 ii) 101 iii) 102 iv) 105
d) In the Op-Amp circuits capacitors are used to remove the_____content present at the input 01
and output.
i) DC ii) DC and AC iii) AC iv) DC or AC
e) In the capacitor coupled non inverting amplifier the input impedance is 01
i) very high ii) very low iii) 0 iv)Infinity
f) What is the output waveform? 01

i) Sine ii) Square iii) Triangular iv) Ramp

g) The capacitors have …………………………….impedance at low frequency. 01
i) high ii) low iii) zero iv)Infinity

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h) The voltage drop across each resistor in single polarity voltage follower is 01
i) Vcc/2 ii) Vcc iii) Vcc/4 iv) Infinity
i) An Astable multivibrator is also known as as 01
i) free-running multivibrator ii) bistable multivibrator iii) Tri-stable
multivibrator iv) All of these
j) A monostable multivibrator has R = 120kΩ and the time delay T = 1000ms, 01
calculate the value of C?
i) 7.57µF ii) 2.3µF iii) 7.07µF iv) 5.67µF
k) An op-amp clamper circuit is also referred as 01
i) DC cutter ii) DC inserter iii) DC lifter iv) DC leveller
l) The resistor in the peak detector are used to 01
i) To maintain proper operation
ii) Protect op-amp from damage
iii) To get shaped non-sinusoidal waveform
iv) None of the mentioned
m) A PLL locks the output ______ to the phase and frequency of input signal. 01
i) phase ii) phase and frequency iii) frequency iv) phase, amplitude and frequency
n) A 555 Timer consists of ____and a ____ . 01
i) Comparators, Voltage follower ii) Adders, Voltage follower iii) Comparators,
Flip flop iv) Comparators, multiplexer
o) A PLL locks the output ______ to the phase and frequency of input signal. 01
i) phase ii) phase and frequency iii) frequency iv) phase, amplitude and frequency
p) The gain of the first order low pass filter will 01
i)Increases at the rate 20dB/decade ii) Increases at the rate 40dB/decade
iii) Decreases at the rate 20dB/decade iv) Decreases at the rate 40dB/decade

q) A 7805 voltage regulator output is 01

i) 12V ii) 5V iii) 10V iv) 15V
r) ___________ is an example of fixed positive voltage regulator 01
i) IC7805 ii) IC7905 iii) IC7906 iv)None of the above
s) What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to 01
a binary-weighted digital-to-analog DAC converter?
i) It only uses two different resistor values.
ii) It has fewer parts for the same number of inputs
iii) Its operation is much easier to analyze
iv) The virtual ground is eliminated and the circuit is therefore easier to understand and
troubleshoot.
t) Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to: 01

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 i) sample and hold the output of the binary counter during the conversion process
ii). sample and hold the D/A converter staircase waveform during the conversion process.
iii) stabilize the comparator's threshold voltage during the conversion process
iv) stabilize the input analog signal during the conversion process
Question 2 is for 16 marks and can have maximum of four sub-question from Module I
2 a) Define the following and mention their typical values for a standard 741 Op-Amp. 06
i) CMRR ii) Slew rate iii)Input & output impedance
b) With a neat circuit diagram, explain the direct-coupled non-inverting amplifier with 06
necessary design steps.
c) If a non-inverting amplifier is designed for a gain of 100, using an op-amp with 95dB 04
CMRR, calculate the common mode output voltage for a common mode input voltage
of 2V.
Question 3 is for 16 marks and can have maximum of four sub-question from Module II
3 a) Design a capacitor-coupled voltage follower using a 741 operational amplifier. The lower 08
cutoff frequency for the circuit is to be 50 Hz and the load resistance is RL=3.9kΩ.
b) Explain high Zin capacitor coupled inverting amplifier with necessary design steps. 08
Question 4 is for 16 marks and can have maximum of four sub-question from Module III
4 a) Explain the operation of op-amp based monostable multivibrator. Use relevant 08
waveforms
b) With neat diagram, explain the operation of precision rectifier peak detector. Draw 08
the input and output waveforms.
Question 5 is for 16 marks and can have maximum of four sub-question from Module IV
5 a) Draw the block schematic of PLL and explain its operation. 06
b) Design a second order high pass active filter to have a cut-off frequency of 10KHz. 06
Use 741 op-amp
c) Design a second order low pass filter circuit to have a cutoff frequency of 2kHz. Draw 04
the circuit
OR
Question 6 is for 16 marks and can have maximum of four sub-question from Module IV
6 a) With neat block diagram, explain the operation of monostable multivibrator using 10
555 timer
b) Explain with a neat diagram explain voltage controlled oscillator 06
Question 7 is for 16 marks and can have maximum of four sub-question from Module V
7 a) Explain the working principle of successive approximation ADC with an example. 06
b) Explain the op-amp DAC with R and 2R resistors. 10
OR
Question 8 is for 16 marks and can have maximum of four sub-question from Module V
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8 a) With neat diagram explain the working of IC723 adjustable voltage regulator 05
b) What is a voltage regulator? With neat diagram explain the working of series op-amp 05
regulator
c) With neat figure explain the working of weighted resistor DAC. 06

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