ELE546T

Embedded Systems
Dr. Rohini. P
Department of ECE,
IIITDM Kancheepuram

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Embedded systems
Computers designed for specific purpose

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Internet of Things (IoT)
Internet connected embedded systems

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

 Embedded System
 Embedded Systems are everywhere

 Ubiquitous, invisible
Medical
Automotive
 Hidden (computer inside)

 Dedicated purpose
Communications
Military
 Around 5 Billion in today’s world

 Components inside a Embedded system

 Computer – x86 – standard in PC
Comsumer Industrial
 ARM

 A series – Cell phones

 M series – Microcontroller

 R series – Real time

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Considerations
Ability to test/verify

Ability to make profit

Lower power consumption

Small size

Time – Correct answer at correct time

The correctness of the system depends on not only on the logical result of the computation but also
on the time at which the results are produced

A correct value at a wrong time is a fault.

5
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])
Embedded System

 Microprocessor

Embedded system  Intel: 4004, ..8080,.. x86

Microcontroller LM3S or TM4C Electrical,
mechanical,  ARM, DEC, SPARC, MIPS, PowerPC,,…
Processor chemical,
I/O Ports or
RAM optical  Microcontroller
devices
ROM
ADC
DAC Analog
signals  Processor + Memory + I/O Ports
Bus
(Interfaces)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

 Microcontroller
 Memory
 Non-Volatile
ROM Memory Type Category Erasure Write Volatility
Mechanism
EPROM, EEPROM, Flash
Random-access Read-write Electrically,
 Volatile memory (RAM) memory byte-level
Electrically Volatile

RAM (DRAM, SRAM) Read-only

memory (ROM)
Masks
Read-only
Not possible
memory
 Interfaces Programmable
ROM (PROM)
 H/W: Ports Erasable PROM UV light, chip-
Nonvolatile
 S/W: Device Driver (EPROM) level
Electrically
Electrically
 Parallel, Serial, Analog, Time Erasable PROM
Read-mostly
memory
Electrically,
byte-level
(EEPROM)

 I/O Flash memory

Electrically,
block-level
 Memory-mapped vs. I/O-
instructions (I/O-mapped)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Von Neumann Architecture

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Harvard Architecture

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Microprocessor
Components include:

 Entire CPU fabricated on a chip

 Consists of
 Registers
 ALU
 Control unit
 System bus – for interfacing

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Micro computer
Computer system – built using microprocessor
Use external memory and I/O – not inbuilt
Complex and expensive for very small and low cost embedded system application

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Microcontroller
Microcomputer- onto a single chip
Inexpensive, small and low power – for use in embedded system design
Operates on data that are fed through input ports, controlled by the software stored in
on-chip memory

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Microcontroller

Fast and Effective

Low cost/ Low power
Compatibility

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Difference between microcontroller and PC
When PC executes a program- primarily loaded from disk/SSD to an allocated section
of memory
Program is loaded part by part to conserve memory space

There is an operating system that handles low level operations

Microcontroller – no disk to read from

On chip ROM stores the program

Size of the ROM limits the maximum size of program

No operating system – ROM must also include low level routines

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

History of ARM series Microcontrollers
Architectural ideas developed in 1983 by Acorn computers
The first commercial RISC implementation

The company founded in 1990

Advanced RISC Machine (ARM)

Initially owned by Acorn, Apple and VLSI

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

ARM Evolution

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Why ARM ?
Chips are high-speed processors that are known for their small die size and low power requirements

Probably the most widely used embedded processor architecture and indeed the most widely used
processor architecture of any kind in the world

Some Application examples:

ARM7: iPod
ARM9: Sony Ericsson
ARM11: Apple iPhone, Nokia N93, N100

Mainly used in battery operated devices

Due to low power consumption and reasonably good performance

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

ARM
Simple RISC based architecture with powerful design

A whole family of ARM exist

Share similar design principles and a common instruction set

Design Philosophy:
Small processor for lower power consumption (for embedded system application)
High code density for limited memory and physical size restrictions
Can interface with slow and low cost memory systems
Reduced die size for processor to accommodate more peripherals

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

ARM is based on RISC architecture
RISC – supports simple but powerful instructions – execute in a single cycle

Major design features of RISC Architecture:

Instruction: reduced set/ single cycle/ fixed length

Pipeline: decode in one stage

Registers: large number of general purpose registers

Load/ Store Architecture: data processing instructions work on registers only – Load / store
instructions to transfer data from/to memory

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

ARM features
ARM is different from pure RISC
Variable cycle execution for certain instructions ( multiple register load/store for
higher code density)

In-line barrel shifter results in more complex instruction

Thumb 16 bit instruction set (results in improvement in code density by about 30%)

Conditional execution

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Popular ARM architecture
ARM 7
3 Pipeline stages (fetch/decode/execute)
High code density and low power consumption
Most widely used for low end systems

ARM9
Compatible with ARM 7
5 stage pipeline (Fetch/decode/execute/memory/write)
Separate instruction and data cache

ARM10
6 stage pipeline (Fetch/issue/decode/execute/memory/write)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Pipelining
Mechanism for overlapped execution of input set - partitioning computation into k-sub computations.
Very nominal increase in the cost of implementation

Significant speedup ( ideally k-folds)

ARM 7

ARM 9

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Pipelining in ARM

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

With Complex instructions

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Processor Design
Instruction set Architecture
Instructions supported

Registers (GPRs, special)

Data Types (char, integer, float)

Addressing mode

Memory Access

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Registers

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Memory

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Memory map of TM4C123

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Assembly Language
Label field is optional and starts in the first column - used to identify the position in memory of
the current instruction

Opcode field specifies the processor command to execute

Operand field specifies where to find the data to execute the instruction

Comment field is also optional and is ignored by the assembler, but it allows you to describe the
software making it easier to understand

Label Opcode Operands Comment

Func MOV R0, #100 ; this sets R0 to 100
BX LR ; this is a function return

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

List of Symbols
Ra Rd Rm Rn Rt and Rt2 represent registers
{Rd,} represents an optional destination register
#imm16 represents a 16-bit constant, 0 to 65535
{cond} represents an optional logical condition as listed in Table 2.10
{type} encloses an optional data type
Rm {, shift} specifies an optional shift on Rm
Rn {, #offset} specifies an optional offset to Rn

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Conditions – {cond}
Suffix Flags Meaning
EQ Z=1 Equal
NE Z=0 Not equal
CS or HS C=1 Higher or same, unsigned ≥
CC or LO C=0 Lower, unsigned <
MI N=1 Negative
PL N=0 Positive or zero
VS V=1 Overflow
VC V=0 No overflow
HI C = 1 and Z = 0 Higher, unsigned >
LS C = 0 or Z = 1 Lower or same, unsigned ≤
GE N=V Greater than or equal, signed ≥
LT N≠V Less than, signed <
GT Z = 0 and N = V Greater than, signed >
LE Z = 1 and N ≠ V Less than or equal, signed ≤

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Addressing Modes and Operands
Immediate addressing

MOV R0,#100 ; R0=100, immediate addressing

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Addressing Modes and Operands
Indexed addressing
Data is in memory and a register will contain a pointer to the data

LDR R0,[R1] ; R0= value pointed to by R1

LDR R0,[R1,#4] ; R0= word pointed to by R1+4
LDR R0,[R1,#4]! ; first R1=R1+4, then R0= word pointed to by R1
LDR R0,[R1],#4 ; R0= word pointed to by R1, then R1=R1+4
LDR R0,[R1,R2] ; R0= word pointed to by R1+R2
LDR R0,[R1,R2, LSL #2] ; R0= word pointed to by R1+4*R2

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Addressing Modes and Operands
PC relative addressing

Indexed addressing mode using the PC as the pointer

B Location ; jump to Location, using PC-relative addressing

BL Subroutine ; call Subroutine, using PC-relative addressing

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Memory Access
An aligned access - word-aligned address is used for a word, a halfword-aligned
address is used for a halfword access

An unaligned word access - accessing a 32-bit object (4 bytes) but the address is not
evenly divisible by 4

Address of an aligned word access will have its bottom two LSB = 0

Address of an aligned halfword access will have its bottom bit equal to zero

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Instruction set
Logical Operations

Examples:
AND{S}{cond} {Rd,} Rn, ;Rd=Rn&op2
ORR{S}{cond} {Rd,} Rn, ;Rd=Rn|op2
EOR{S}{cond} {Rd,} Rn, ;Rd=Rn^op2
BIC{S}{cond} {Rd,} Rn, ;Rd=Rn&(~op2)
ORN{S}{cond} {Rd,} Rn, ;Rd=Rn|(~op2)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

 Instruction set
 Shift Operations

Examples:
LSR{S}{cond} Rd, Rm, Rs ; logical shift right Rd=Rm>>Rs (unsigned)
LSR{S}{cond} Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned)
ASR{S}{cond} Rd, Rm, Rs ; arithmetic shift right Rd=Rm>>Rs (signed)
ASR{S}{cond} Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed)
LSL{S}{cond} Rd, Rm, Rs ; shift left Rd=Rm< <Rs
LSL{S}{cond} Rd, Rm, #n ; shift left Rd=Rm<<n

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Instruction set
Arithmetic Operations

ADD{S}{cond} {Rd,} Rn, ;Rd = Rn + op2

ADD{S}{cond} {Rd,} Rn, #im12 ;Rd = Rn + im12
SUB{S}{cond} {Rd,} Rn, ;Rd = Rn - op2
SUB{S}{cond} {Rd,} Rn, #im12 ;Rd = Rn - im12
RSB{S}{cond} {Rd,} Rn, ;Rd = op2 - Rn
RSB{S}{cond} {Rd,} Rn, #im12 ;Rd = im12 - Rn
CMP{cond} Rn, ;Rn - op2
CMN{cond} Rn, ;Rn - (-op2)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Instruction set
Memory Access Instructions

mechanisms to read from and write to memory

LDR{type}{cond} Rd, [Rn] ; load memory at [Rn] to Rd
STR{type}{cond} Rt, [Rn] ; store Rt to memory at [Rn]
LDR{type}{cond} Rd, [Rn, #n] ; load memory at [Rn+n] to Rd
STR{type}{cond} Rt, [Rn, #n] ; store Rt to memory [Rn+n]
LDR{type}{cond} Rd, [Rn,Rm,LSL #n] ; load memory at [Rn+Rm<<n] to Rd
STR{type}{cond} Rt, [Rn,Rm,LSL #n] ; store Rt to memory [Rn+Rm<<n]

Example:
Input LDR R5,=0x400043FC ;R5=0x400043FC, R5 points to PortA
LDR R6,[R5] ;Input from PortA into R
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])
I/O ports

GPIO Ports Pins

PORTA PA0 – PA7
PORTB PB0- PB7
PORTC PC4 – PC7
PORTD PD0 – PD7
PORTE PE0 – PE5
PORTF PF0 - PF7

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

I/O ports
UART Universal asynchronous receiver/transmitter
SSI Synchronous serial interface
I2C Inter-integrated circuit
Timer Periodic interrupts, input capture, and output compare
PWM Pulse width modulation
ADC Analog to digital converter, measure analog signals
Analog Comparator Compare two analog signals
QEI Quadrature encoder interface
USB Universal serial bus
Ethernet High-speed network
CAN Controller area network

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

 Cortex M4 Systick
System Bus Interface NVIC

GPIO Port A GPIO Port B

PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
PA4/SSI0Rx UARTs I2Cs PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0
PC7 GPIO Port C GPIO Port D PD7
PC6 PD6
PC5 USB 2.0 Twelve PD5
PC4 Timers PD4
PC3/TDO/SWO PD3
PC2/TDI JTAG Six PD2
PC1/TMS/SWDIO 64-bit wide PD1
PC0/TCK/SWCLK PD0

GPIO Port E GPIO Port F

PE5
PE4 ADC Two Analog PF4
PE3 2 channels Comparators PF3
PE2 12 inputs PF2
PE1 12 bits Two PWM PF1
PE0 Modules PF0

Advanced High Performance Bus Advanced Peripheral Bus

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])
I/O Ports and Control Registers

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

I/O Ports and Control Registers
Read from port address
n n

Processor
n n
DQ Input/Output Port

Write to port address

Direction bits
n 1 means output
DQ 0 means input
Bus Write to port direction register

The input/output direction of a bidirectional port is specified by its direction register.

GPIO_PORTF_DIR_R , specify if corresponding pin is input or output:
0 means input
1 means output

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Switches and LED

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Switches and LED
Two switches and one 3-color LED

Switches are negative logic and will require activation of the internal pull-up resistors.

Set bits 0 and 4 in GPIO_PORTF_PUR_R register

LED interfaces on PF3 – PF1 are positive logic

To use the LED, make the PF3 – PF1 pins an output

To activate the red color, output a one to PF1, blue color is on PF2, green color is
controlled by PF3

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

Switches

Pull-down resistor - the digital signal will be low if the switch is not pressed and high if
the switch is pressed - positive logic because the asserted state is a logic high.

Pull-up resistor - the digital signal will be high if the switch is not pressed and low if the
switch is pressed - negative logic because the asserted state is a logic low.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

I/O programming
Direction register (e.g., GPIO_PORTF_DIR_R) - specify which pins are input and output

Individual port pins can be general purpose I/O (GPIO) or have an alternate function.

Set bits in the alternate function register (e.g., GPIO_PORTF_AFSEL_R) to activate the alternate functions

For each I/O pin whether GPIO or alternate function - the digital circuits must be enabled by setting the bit in the
enable register (e.g., GPIO_PORTF_DEN_R)

To enable analog input – enable analog mode select register (e.g., GPIO_PORTF_AMSEL_R)

Data register (e.g., GPIO_PORTF_DATA_R) - to perform input/output on the port - read and write the data
register multiple times

Each port has a clock – enabled by writing SYSCTL_RCGCGPIO_R

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

I/O programming
Initialization (executed once at beginning)

1. Turn on clock in SYSCTL_RCGCGPIO_R, Wait two bus cycles – check using PRGPIO register

2. Unlock PF0 (PD7 also needs unlocking)

3. Disable Analog function – AMSEL

4. Clear bits on PCTL – to select regular digital function

5. Set DIR to 1 for output or 0 for input

6. Clear AFSEL bits to 0 to select regular I/O

7. Set DEN bits to 1 to enable data pins

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

I/O Ports and Control Registers
Address 7 6 5 4 3 2 1 0 Name
400F.E608 - - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGCGPIO_R
4002.53FC - - - DATA DATA DATA DATA DATA GPIO_PORTF_DATA_R
4002.5400 - - - DIR DIR DIR DIR DIR GPIO_PORTF_DIR_R
4002.5420 - - - SEL SEL SEL SEL SEL GPIO_PORTF_AFSEL_R
4002.551C - - - DEN DEN DEN DEN DEN GPIO_PORTF_DEN_R

Initialization (executed once at beginning)

1. Turn on clock in SYSCTL_RCGCGPIO_R, Wait
two bus cycles
2. Unlock PF0
3. Disable Analog function – AMSEL
4. Clear bits on PCTL – to select regular digital
function
5. Set DIR to 1 for output or 0 for input
6. Clear AFSEL bits to 0 to select regular I/O
Set PUR bits to 1 to enable internal pull-up
7. Set DEN bits to 1 to enable data pins
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])
I/O programming
#include "inc/tm4c123gh6pm.h"
void PortF_Init(void)
{
SYSCTL_RCGCGPIO_R |= 0x00000020; // 1) activate clock for Port F
while((SYSCTL_PRGPIO_R&0x00000020) == 0){};// ready?
GPIO_PORTF_LOCK_R = 0x4C4F434B; // 2) unlock GPIO Port F
GPIO_PORTF_CR_R = 0x1F; // allow changes to PF4-0
GPIO_PORTF_DIR_R = 0x0E; // 5) PF4,PF0 in, PF3-1 out
GPIO_PORTF_PUR_R = 0x11; // enable pull-up on PF0 and PF4
GPIO_PORTF_DEN_R = 0x1F; // 7) enable digital I/O on PF4-0
}
uint32_t PortF_Input(void)
{
return (GPIO_PORTF_DATA_R&0x11); // read PF4,PF0 inputs
}
void PortF_Output(uint32_t data)
{ // write PF3-PF1 outputs
GPIO_PORTF_DATA_R = data;
}
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])
PortF_Init PortF_Input
LDR R1, =SYSCTL_RCGCGPIO_R ; 1) activate clock for Port F LDR R1, =GPIO_PORTF_DATA_R ; pointer to Port F data
LDR R0, [R1] LDR R0, [R1] ; read all of Port F
ORR R0, R0, #0x20 ; set bit 5 to turn on clock AND R0,R0,#0x11 ; just the input pins, bits 4,0
STR R0, [R1] BX LR ; return R0 with inputs
NOP
NOP ; allow time for clock to finish PortF_Output
LDR R1, =GPIO_PORTF_LOCK_R ; 2) unlock the lock register LDR R1, =GPIO_PORTF_DATA_R ; pointer to Port F data
LDR R0, =0x4C4F434B ; unlock GPIO Port F Commit Register STR R0, [R1] ; write to PF3-1
STR R0, [R1] BX LR
LDR R1, =GPIO_PORTF_CR_R ; enable commit for Port F
MOV R0, #0xFF ; 1 means allow access
STR R0, [R1]
LDR R1, =GPIO_PORTF_DIR_R ; 5) set direction register
MOV R0, #0x0E ; PF0 and PF7-4 input, PF3-1 output
STR R0, [R1]
LDR R1, =GPIO_PORTF_PUR_R ; pull-up resistors for PF4,PF0
MOV R0, #0x11 ; enable weak pull-up on PF0 and PF4
STR R0, [R1]
LDR R1, =GPIO_PORTF_DEN_R ; 7) enable Port F digital port
MOV R0, #0xFF ; 1 means enable digital I/O
STR R0, [R1]
BX LR

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])

I/O programming
If two or more software modules access the same port, a conflict will occur if one
module changes modes or output values set by another module.

Design to write friendly software - only affects the individual pins as needed.

Friendly software does not change the other bits in a shared register.

Unfriendly software modifies more bits of a register than it needs to.

The difficulty of unfriendly code is each module will run properly when tested by itself,
but weird bugs result when two or more modules are combined.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@[Link])