Q25) how many DRC’s you got in your recent design and how you fixed?

Ans: Errors like spacing between metals, width errors, corner to corner, via-enclosure,
colour-id violations, HV-DRC violations
Q26) Did you come across any timing issues in the placement of the design?
Ans:
1) Incomplete or Inaccurate Pin Constraints
To fix this problem, you may need to reevaluate area pin constraints. Not utilizing the
appropriate paths for signals to follow via pin constraints can lead to failure. Even though
some designs may not seem as though they need specific pin constraints, we always
recommend establishing some level of loose constraints to provide a satisfactory and
trackable timing margin.
2) Late-Stage Pin Placement Changes
While it would be ideal to alter pin placement at ANY stage of your design with no
repercussions, trying to do this in the later stages of your design can be costly. It is way more
effective to check how your pin placement might affect timing as early in the design process
as possible to achieve the most cost-effective design flow and successfully meet your design
goals. This is a simple fix that is very easy to implement.
3) Exceeding Maximum Fanout
Exceeding the signal fanout of a logic gate causes excessive loading problems which
in turn slow down signal timing. This problem should be easy to spot when observing the
connectivity details in the schematic, but without knowing the characteristics of the all the
receiving devices for the signal path, you won’t know the extent of the timing impact. One
possible solution here would be to add buffer drivers where needed to reduce the load on the
source logic or utilize stronger output driver source logic. If this is not an option, you may
have to duplicate the source logic to distribute the load required.
4) Too Many Logic Levels
Each level of logic a signal encounters adds delay so it’s important to keep your logic
levels to a minimum. This can be accomplished with early design-stage optimization
practices. With synchronous signal paths, if logic can’t be reduced enough to solve a specific
timing problem, you may be able to introduce a multi-cycle path which would effectively
broaden the available timing margin to achieve the proper timing. Introduction of a registered
buffer for a signal path may also help to achieve appropriate timing margins. This is typically
what’s done for pipelined data requirements when trying to synchronize two or more
asynchronous systems.
Q27) How will you fix the timing at placement stage?
Ans: At placement stage, one should only focus on fixing setup violations as the clock tree is
still not built at that phase in the design flow.
Setup violations at placement stage can be fixed using the following ways:
  Optimise data path with less depth as much as possible.
 Have better drive strength cells in the data path.
 Set the timing optimisation effort level to high (assuming congestion is under control
and the run time tradeoff is reasonable).
 Have regions defined to place specific timing critical logic in a specified area to
reduce the wire length.
Q28) what is mean by NDM?
Ans: New Data Module. It is a reference library format used by Synopsys IC compiler II tool.
Q29) which Vt cells used in the clock tree balancing?
Ans: Low VT cells usually used on clk tree path. Even though they may be more leaky than
High VT cells, they provide crisp edges. If we use High VT, then we may have to provide
more buffers to maintain crisp edge. This may eventually cause High VT to consume more
dynamic power than Low VT cells, even though they leak less.
Q30) do you have scripting knowledge? can you give me a command to list all the clock
nets in my design?
Ans: Yes.
First, time the design so that the nets are marked in the db as clock or not clock:
encounter> timeDesign -prePlace
Then, use dbGet as follows:
encounter> dbGet [dbGet -p top.nets.isClock 1].name
DTMF_INST/m_spi_clk DTMF_INST/m_clk DTMF_INST/m_rcc_clk
DTMF_INST/m_digit_clk DTMF_INST/TDSP_DS_CS_INST/n_28
DTMF_INST/TDSP_DS_CS_INST/n_30
Q31) which type of cells you used in the clock weather the inverters/ buffers why?
Ans: Inverters
Clock buffers and clock inverters are usually built to maintain uniform duty cycle. The main
difference is in the area where buffer uses a higher area to drive a signal to certain distance
before it has to be re-buffered. If inverters are used, you can drive the signal to the same
distance with almost half the number of cells.
Q32) clock spec file contains?
Ans: CTS spec file contains:
1. Inverters/Buffers to be defined to balance the clock tree
2. CTS Exceptions (end points of clock tree)
a. Non-stop pin
b. Exclude pin
c. Float pin
d. Stop pin
 e. Don’t touch sub-tree
f. Don’t buffer net
g. Don’t size net
3. Skew group information contains target skew, max target transition, and other timing
transitions as per clock tree
4. Top/Bottom layer routing information, Via’s information used during clock route
5. Clock related information like generated clock (eg. Clock divider/multiplier etc.)
6. NDR rule definition
Q*) Why clock inverters are preferred over normal inverters in clock tree?
Ans: A clocked inverter is a series combination of an normal inverter and a TG(Transmission
Gate).

FIG.: Clocked inverter. (a) An inverter plus transmission gate (TG). (b) The current flow in
the inverter and TG allows us to break the connection between the transistors in the inverter.
(c) Breaking the connection forms a clocked inverter. (d) A common symbol.

The arrows in Figure 2.19(b) represent the flow of current when the inverter is charging ( I R )
or discharging ( IF ) a load capacitance through the TG. We can break the connection between
the inverter cells and use the circuit of Fig.(c) without substantially affecting the operation of
the circuit. The symbol for the clocked inverter shown in Fig.(d) is common, but by no means
a standard.
We can use the clocked inverter to replace the inverter–TG pairs in latches and flip-flops. If
we wish to build a flip-flop with a fast clock-to-QN delay it may be better to build it using
clocked inverters and use inverters with TGs for a flip-flop with a fast clock-to-Q delay. It is
slightly easier to layout clocked inverters than an inverter plus a TG, so flip-flops in
commercial libraries include a mixture of clocked-inverter and TG implementations.
Q*) How to create NDM?
Ans:
Following is the basic flow (ICC2) to generate NDM views for library:
set workspace_lib ref_lib
set physical_lib phy_lib
create_workspace –technology input.tf –flow normal $workspace_libread_db{db files}
read_gds input.gds –library $physical_lib –trace_option none..
read_lef input.lef –library $physical_lib
current_lib $physical_lib
check_workspace
commit_workspace