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Project Report: Design of Binary To Gray and Gray To Binary Converter

This project report describes the design of a binary to gray code and gray to binary converter architecture. The architecture uses two parallel input and output registers, a counter to check iterations, and an XOR gate to perform the conversions. Testbenches are created to simulate and verify the design by displaying the output conversions and control signal waveforms. The project was completed by three students under the guidance of Dr. S Gurunarayan.

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SANCHIT KULKARNI
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329 views5 pages

Project Report: Design of Binary To Gray and Gray To Binary Converter

This project report describes the design of a binary to gray code and gray to binary converter architecture. The architecture uses two parallel input and output registers, a counter to check iterations, and an XOR gate to perform the conversions. Testbenches are created to simulate and verify the design by displaying the output conversions and control signal waveforms. The project was completed by three students under the guidance of Dr. S Gurunarayan.

Uploaded by

SANCHIT KULKARNI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PROJECT REPORT

VLSI Architecture
Design of Binary to Gray and Gray to binary converter

Under the guidance of:


Dr.S Gurunarayan

Submitted by:
C. Sahithi (2021H1400149H)
Sanchit Kulkarni (20211400153H)
Himanshi Sonava (2021H1400062H)
Abstract:-
This project motto is to design an architecture for converting an input from binary to
gray code and vice-versa. Both the processes are designed a single architecture. We have
designed the circuit using two Parallel input and Parallel Output registers. We have a
counter to check the number of iterations. An ex-OR gate has been used to convert from the
mutual conversion.
Architecture:-

Output:-

The above circuit shows the output displayed depicts conversion of binary to gray using
$display and $finish commands.
Waveforms:-
The below waveforms depicts the waveforms of the control signals processed throughout
the architecture.
Testbench:-
`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 27.02.2022 10:01:54
// Design Name:
// Module Name: tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module bi_g_tb(

);
reg [7:0] d_in;
reg clk,start;
reg type;
wire done;
bi_g
b1(d_in,clk,r1_in,r1_out,r2_in,r2_out,ld1,dec,r3_in,r3_out,r4_in,r4_out,r5_in,r5_out,shift,e
qz,sel);
bi_g_cp
c1(type,eqz,clk,start,r1_in,r1_out,shift,r3_in,r3_out,r4_in,r4_out,r5_in,r5_out,r2_in,r2_out,
dec,ld1,done,sel);
initial
begin
clk=1'b0;
#3 start =1'b1;
#500 $finish;
end
always #5 clk=~clk;
initial
begin
#7 type=1; //0--b2g//1--g2b
#7 d_in=8'b01011100;
end
initial
begin
// $monitor($time,"x=%b z=%b count=%b out_1=%b bus=%b exout=%b,done=%d r5_o=%d
r5_i=%d",b1.x,b1.z,b1.count,b1.out1,b1.bus,b1.exout,done,r5_out,r5_in);
// $monitor($time,"x=%b y=%d z=%b out2=%b out3=%b exout=%b
",b1.x,b1.y,b1.z,b1.out2,b1.out3,b1.exout);
// $monitor($time,"out2=%b out3=%d ex=%b",b1.out2,b1.out3,b1.exout);
$monitor("out2=%b out3=%b ex=%b bus=%b",b1.out2,b1.out3,b1.exout,b1.bus);
end

endmodule

The above written is the code used as the simulation source i.e as a testbench for the design
sources.

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