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Flujo 1

The document describes logic gates and their functionality using VHDL code. It includes a code example for an OR gate that outputs 1 if either or both inputs are 1, and outputs 0 only if both inputs are 0. It also includes a truth table for a 3-input logic gate.

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Wilmer Caicedo
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28 views2 pages

Flujo 1

The document describes logic gates and their functionality using VHDL code. It includes a code example for an OR gate that outputs 1 if either or both inputs are 1, and outputs 0 only if both inputs are 0. It also includes a truth table for a 3-input logic gate.

Uploaded by

Wilmer Caicedo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

library ieee; ó

use ieee.std_logic_1164.all;
entity tabla is
port (A,B,C: in std_logic ;
F : out std_logic) ;
end tabla ;
architecture flujo of tabla is
begin

F<=(NOT A AND NOT B AND NOT C)OR(NOT A AND B AND NOT C)OR(A AND NOT B
AND NOT C)OR(A AND NOT B AND C)OR(A AND B AND NOT C);

end flujo;

<= ‘0’
<= ‘1’

A B C F

0 0 0 1
0 0 1 0

0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

--declaracin funcional
library ieee;
use ieee.std_logic_1164.all;
entity com_or is
port (a,b: in std_logic;
f1: out std_logic) ;
end com_or;
architecture funcional of com_or is
begin
process (a,b) begin
if(a = ‘0’ and b = ‘0’) then
f1 <= ‘0’;
else
f1 <= ‘1’;
end if;
end process;
end funcional;

-- Declaración funcional
library ieee;
use ieee.std_logic_1164.all ;
entity com_or is
port (a,b: in std_logic;
f1: out std_logic) ;
end com_or ;
architecture funcional of com_or is
begin
process (a,b) begin
if (a = ‘0’ and b = ‘0’) then
f1 <= ‘0’;
else
f1 <= ‘1’;
end if;
end process;
end funcional;

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