A B C D E

1 1

Compal Confidential
2 YOGA Gloria 14" & 15" 2

DIS M/B Schematics Document

Intel KabyLake U Processor with DDR4
N16S-GTR-S(940) (23x23mm)

2016-6-6
3
LA-D471P 3

R E V !2 . 0

4 ZZZ BIUY2_PCB 4
Part Number Description
DAZ1JH00100 PCB BIUY2 LA-D471P LS-D471P/D472/D473 02
PCB@

Security Classification Compal Secret Data Compal Electronics, Inc.

2015/07/27 2016/07/27 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Thursday, October 20, 2016 Sheet 1 of 53
A B C D E
 1 2 3 4 5

BOM Structure Table

Voltage Rails Item BOM Structure
for 2+3E power 23E@
For Camera CMOS@
ZZZ1 @ ZZZ3 @
For DIS DIS@
+5VS
For UMA UMA@
+3VS
power For GPU GC6 GC6@
plane +1.0VS_VCCOPC
A No GPU GC6 NOGC6@ BARCODE_8X8 BARCODE_12X4 A
+VCCCORE
+5VALW For Keyboard backlight KBL@
+1.2V +VCCGT
+2.5V No Keyboard backlight NOKBL@ ZZZ2 @ ZZZ4 @
B+ +3VALW +1.0V_VCCST
For Thermal sensor EX_THM@
+1.0VS_VCCIO
+1.8VALW For RF RF@
+1.8VS
For EMI EMI@ BARCODE_20X4 BARCODE_10X10
State +1.0VALW +0.6VS
No EMI @EMI@
For ESD ESD@
No ESD @ESD@
Connector ME@
For Test Point TP@
For PCB PCB@
For Hynix Memory H2G@
S0 O O O O For Samsung Memory S2G@
For Micron Memory M2G@
For VARM X76 GM_X76@
S3 O O O X For Finger Print (only 15) FP@
for KBL platform KB_L@
S5 S4/AC
O O X X for SKL platform SKL@
B For 15" ESD_FP @ESD_FP@ B
S5 S4/ Battery only
O X X X For UHD UHD@
S5 S4/AC & Battery
don't exist X X X X

EC SM Bus1 address EC SM Bus2 address EC SM Bus4 address

Device Address Device Address Device Address
NCT7718W 1001 100x 98h BMA250E 0001 100X 18h
Smart Battery 0001 011x 16h AL3010 0001 110X 1Ch

PCH SM Bus address

Device Address
DDR_JDIMM1 1010 000x A0h
Touch Pad

C C

USB 2.0 Port Table

External Port USB 3.0 Port Table
Port USB Port
1 PCIE Port Table
1
2 USB2/3 MB(IO_Port2)
2 USB2/3 MB(IO_Port2)
3 USB2/3 MB(IO_Port1)
3 USB2/3 MB(IO_Port1) Port Lane
4
4
5 1 1
5 Camera
6 2 2 GPU
6
3 3
7 NGFF WLAN+BT SATA Port Table 4 4
5
Port
6 NGFF WLAN+BT
0 SSD 7
1 8
9 CardReader
SIGNAL 10
D STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock D

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

Security Classification Compal Secret Data Compal Electronics, Inc.
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Notes List
Size Document Number Rev
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-D471P
Monday, June 06, 2016 Sheet 3 of 53
1 2 3 4 5
 5 4 3 2 1

BIVS3/ VE3 -PowerMap_SKL-U22_DDR3L_Volume_NON CS]

B+

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power MAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date : Monday, June 06, 2016 Sheet 4 of 53
5 4 3 2 1
 5 4 3 2 1

[AAX05-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#

B+ B+
D D
+3VLP/+5VLP +3VLP/+5VLP

EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#

PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

+3V_PRIM +3V_PRIM

+1.8V_PRIM +1.8V_PRIM

EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

gate may choose to completely ignore it

+1.0V_MPHYPLL +1.0V_MPHYPLL

+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM

SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C C
AC_PRESENT AC_PRESENT

ON/OFF ON/OFF
tPCH43_Min : 95 ms
PBTN_OUT# PBTN_OUT#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#

PM_SLP_S4# PM_SLP_S4#

SYSON SYSON

+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3# PM_SLP_S3#

SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms
B
+1.0VS_VCCIO +1.0VS_VCCIO B

T <=10msec
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
T = 10msec
EC_VCCST_PG EC_VCCST_PG

VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA

+VCC_CORE +VCC_CORE

+VCC_GT +VCC_GT

VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK

H_CPUPWRGD H_CPUPWRGD

SYS_PWROK SYS_PWROK
A A

SUS_STAT# SUS_STAT#

SOC_PLTRST#
SOC_PLTRST#

Security Classification Compal Secret Data Compal Electronics, Inc.

2015/07/27 2016/07/27 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 5 of 53
5 4 3 2 1
 A B C D E

1 1

UC1A @ SKL-U
Rev_1.0
E55 C47
DDI1_TXN[0] EDP_TXN[0] EDP_TXN0 [27]
F55 C46
DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 [27]
E58 D46
DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 [27]
F58 C45
DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 [27]
F53 A45 <eDP>
DDI1_TXN[2] EDP_TXN[2] EDP_TXN2 [27]
G53 B45
DDI1_TXP[2] EDP_TXP[2] EDP_TXP2 [27]
F56 A47
DDI1_TXN[3] EDP_TXN[3] EDP_TXN3 [27]
G56 B47
DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 [27]
C50 E45 EDP_AUXN [27]
[28] HDMI_TX2-_CK DDI2_TXN[0] DDI EDP_AUXN
D50 EDP F45
[28] HDMI_TX2+_CK DDI2_TXP[0] EDP_AUXP EDP_AUXP [27]
C52
[28] HDMI_TX1-_CK DDI2_TXN[1]
D52 B52
[28] HDMI_TX1+_CK DDI2_TXP[1] EDP_DISP_UTIL
<HDMI> A50
[28] HDMI_TX0-_CK DDI2_TXN[2]
B50 G50
[28] HDMI_TX0+_CK DDI2_TXP[2] DDI1_AUXN
D51 F50
[28] HDMI_CLK-_CK DDI2_TXN[3] DDI1_AUXP
C51 E48
[28] HDMI_CLK+_CK DDI2_TXP[3] DDI2_AUXN F48
DDI2_AUXP G46
DISPLAY SIDEBANDS RSVD F46
L13 RSVD
L12 GPP_E18/DDPB_CTRLCLK L9
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7
GPP_E14/DDPC_HPD1 TMDS_B_HPD [28] From HDMI
N7 L6
[28] HDMICLK_NB GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2
N8 N9
HDMI DDC (Port C) [28] HDMIDAT_NB GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EC_SCI# [11,35]
GPP_E17/EDP_HPD EDP_HPD [27] From eDP
N11
N12 GPP_E22 R12
2 [27] TS_I2C_RST# GPP_E23 EDP_BKLTEN ENBKL [27,35] 2
R11
EDP_COMP EDP_BKLTCTL INVPWM [27]
E52 1 OF 20 U13
EDP_RCOMP EDP_VDDEN PCH_ENVDD [27]

< Compensat i on P UFor e DP > SKL-U_BGA1356

+1.0VS_VCCIO

RC3 1 2 EDP_COMP
24.9_0402_1%

Trace width=20 mils, Spacing=25mil, Max length=100mils

+1.0VS_VCCIO
1

If routed MS, PECI requires 18 mils spacing to other signals

+1.0V_VCCST RC4 UC1D @ SKL-U
1K_0402_5% Rev_1.0
D63 < PU/PD for CMC Debug >
H_PECI A54 CATERR# +1.0VS_VCCIO
[35] H_PECI
2

1 2 H_THERMTRIP# 1 2 H_PROCHOT#_R C65 PECI

[35,40] H_PROCHOT# H_THERMTRIP# C63 PROCHOT# JTAG
RC5 1K_0402_5% RC6 499_0402_1%
A65 THERMTRIP# SOC_XDP_TMS RC11 1 @ 2 51_0402_5%
SKTOCC# B61 CPU_XDP_TCK0
CPU MISC PROC_TCK
C55 D60 SOC_XDP_TDI SOC_XDP_TDI RC12 1 @ 2 51_0402_5%
D55 BPM#[0] PROC_TDI A61 SOC_XDP_TDO
B54 BPM#[1] PROC_TDO C60 SOC_XDP_TMS SOC_XDP_TDO RC13 1 @ 2 51_0402_5%
C56 BPM#[2] PROC_TMS B59 SOC_XDP_TRST#
BPM#[3] PROC_TRST#
A6 B56 PCH_JTAG_TCK1
A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI CPU_XDP_TCK0 RC14 1 @ 2 51_0402_5%
[27] TS_INT# GPP_E7/CPU_GP1 PCH_JTAG_TDI SOC_XDP_TDO
BA5 A56
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 SOC_XDP_TMS PCH_JTAG_TCK1 RC15 1 @ 2 51_0402_5%
GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 PCH_XDP_TRST#
PCH_TRST# T116 @
3 RC7 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 A59 CPU_XDP_TCK0 3
RC8 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
RC9 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC10 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP SOC_XDP_TRST# RC23 1 @ 2 51_0402_5%
4 OF 20
SKL-U_BGA1356

UC1
SA0000A3700
S IC FJ8067702739739 QLDM H0 2.5G C38
I5_7200U@

UC1
SA0000A3400
S IC FJ8067702739740 QLDN H0 2.7G BGA
I7_7500U@

UC1
SA0000A3800
S IC FJ8067702739738 QLDP H0 2.4G C38
I3_7100U@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(1/12)DDI,EDP,MISC,CMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev

LA-D471P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 6 of 53
A B C D E
 5 4 3 2 1

Interleaved Memory

D D

SKL-U
UC1C @
UC1B @ SKL-U Rev_1.0
Rev_1.0
[18] DDR_A_D[0..15] DDR_A_D0 DDR_A_CLK#0 Interleave / Non-Interleaved
AL71 AU53 DDR_A_CLK#0 [18]
AF65 AN45
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKN[0] AT53 DDR_A_CLK0 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46
DDR_A_D2 DDR0_DQ[1] DDR0_CKP[0] DDR_A_CLK#1 DDR_A_CLK0 [18] DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1]
AN68 AU55 DDR_A_CLK#1 [18]
AK65 AP45
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 DDR_A_CLK1 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46
DDR_A_D4 DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 [18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
AL70 AF66
DDR_A_D5 AL69 DDR0_DQ[4] BA56 DDR_A_CKE0 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[0] DDR_A_CKE1 DDR_A_CKE0 [18] DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0]
AN70 BB56 DDR_A_CKE1 [18]
AK67 AP55
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR_A_D8 DDR0_DQ[7] DDR0_CKE[2] TP@ T119 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2]
AR70 AY56 AF70 AP53
DDR_A_D9 DDR0_DQ[8] DDR0_CKE[3] TP@ T118 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
AR68 AF68
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 [18] DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0]
AU68 AU43 DDR_A_CS#1 [18]
AH68 AY42
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 [18] DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0]
AR69 AT43 AF69 AW42
DDR_A_D14 DDR0_DQ[13] DDR0_ODT[1] DDR_A_ODT1 [18] DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
AU70 AH70
DDR_A_D15 AU69 DDR0_DQ[14] AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 DDR_A_MA5 DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4
BA51 DDR_A_MA5 [18]
AT66 AY48
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50
[18] DDR_A_D[16..31] DDR_A_D16 Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR_A_MA9 [18] DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
BB65 BA52 AP65 BA48
DDR_A_D17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA8 DDR_A_MA6 [18] DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
AW65 AY52 AN65 BB48
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_MA8 [18] DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
AW63 AW52 DDR_A_MA7 [18]
AN66 AP48
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 [18] DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
BA65 AW54 DDR_A_MA12 [18]
AT65 AN50
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48
DDR_A_D22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_MA11 [18] DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
BA63 BA55 AT61 AN53
DDR_A_D23 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# M_A_ACT# [18] DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
BB63 AY54 DDR_A_BG1 [18]
AU61 AN52
C DDR_A_D24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU46 DDR_A_MA13 AP60 DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] BA43 C
DDR_A_D25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA15 DDR_A_MA13 [18] DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
AW61 AU48 DDR_A_MA15 [18]
AN60 AY43
DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44
DDR_A_D27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA16 DDR_A_MA14 [18] DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AW59 AU50 AP61 AW44
DDR_A_D28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_BA0 DDR_A_MA16 [18] DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
BB61 AU52 DDR_A_BA0 [18]
AT60 BB44
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_BA1 DDR_A_MA2 [18] DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
BA59 AT48 DDR_A_BA1 [18]
AU40 BA44
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46
[18] DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA1 DDR_A_MA10 [18] DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
AY39 BB50 AT37 AY46
DDR_A_D33 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA0 DDR_A_MA1 [18] DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
AW39 AY50 DDR_A_MA0 [18]
AU37 BA46
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46
DDR_A_D36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA4 DDR_A_MA3 [18] DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3]
BB39 BB52 AP37 BA47
DDR_A_D37 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_DQS#0 DDR_A_MA4 [18] DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4]
BA39 AM70 AR37
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS0 DDR_A_DQS#0 [18] DDR1_DQ[39]/DDR1_DQ[23]
BA37 AM69 DDR_A_DQS0 [18]
AT33
DDR_A_D39 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] DDR_A_DQS#1 DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved
BB37 AT69 DDR_A_DQS#1 [18]
AU33 AH66
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] AT70 DDR_A_DQS1 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65
DDR_A_D41 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_A_DQS1 [18] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2]
AW35 AT30 AG69
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] AG70
DDR_A_D43 DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR_A_DQS#2 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3]
AW33 BA64 DDR_A_DQS#2 [18]
AP33 AR66
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] AR65
DDR_A_D45 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#3 DDR_A_DQS2 [18] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6]
BA35 AY60 DDR_A_DQS#3 [18]
AP30 AR61
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] AR60
DDR_A_D47 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS3 [18] DDR1_DQSP[3]/DDR0_DQSP[7]
BB33 BA38 AU27 AT38
[18] DDR_A_D[48..63] DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] DDR_A_DQS4 DDR_A_DQS#4 [18] DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2]
AY31 AY38 DDR_A_DQS4 [18]
AT27 AR38
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 AT25 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] AT32
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS5 DDR_A_DQS#5 [18] DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3]
AY29 BA34 DDR_A_DQS5 [18]
AU25 AR32
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 AP27 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS6 DDR_A_DQS#6 [18] DDR1_DQ[52]
BB31 AY30 AN27 AR25
DDR_A_D53 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS#7 DDR_A_DQS6 [18] DDR1_DQ[53] DDR1_DQSN[6]
BA31 AY26 DDR_A_DQS#7 [18]
AN25 AR27
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 AP25 DDR1_DQ[54] DDR1_DQSP[6] AR22
DDR_A_D55 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 [18] DDR1_DQ[55] DDR1_DQSN[7]
BB29 AT22 AR21
DDR_A_D56 AY27 DDR0_DQ[55]/DDR1_DQ[39] AW50 AU22 DDR1_DQ[56] DDR1_DQSP[7] AN43
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# DDR_A_ALERT# [18] DDR1_DQ[57] DDR1_ALERT#
AW27 AT52 AU21 AP43
DDR_A_D58 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR DDR_A_PARITY [18] DDR1_DQ[58] DDR1_PAR DDR_DRAMRST# TP@ T123
AY25 AT21 AT13 DDR_DRAMRST# [18]
B DDR_A_D59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR CH - A AY67 +0.6V_VREFCA AN22 DDR1_DQ[59] DDR CH - B DRAM_RESET# AR18 B
DDR_A_D60 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA +0.6V_A_VREFDQ +0.6V_VREFCA [18] DDR1_DQ[60] DDR_RCOMP[0]
BB27 AY68 AP22 AT18
DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67
+0.6V_A_VREFDQ [18] Trace width/Spacing >= 20mils AP21 DDR1_DQ[61] DDR_RCOMP[1] AU18 SM_RCOMP0 RC16 1 2 121_0402_1%
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2] SM_RCOMP1 RC17 1 2 80.6_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 DDR_PG_CTRL DDR1_DQ[63] SM_RCOMP2 RC18 1 2 100_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL SKL-U_BGA1356
SKL-U_BGA1356

DDR_VTT_CNTL to DDR +1.2V

VTT supplied ramped +1.2V
<35uS

1
+3VS @
(tCPU18)
RC20
@ 470_0402_5%
0.1U_0201_10V K X5R 2 1 CC101
1

2
UC7
1 5 RC54 DDR_DRAMRST#
NC VCC 220K_0402_5%

2
DDR_PG_CTRL 2
2

A 4 ESD@ CC96
Y DDR_VTT_PG_CTRL [42]
3 100P_0402_50V8J

1
GND
2

74AUP1G07SE-7 SOT353
RC19
@ 2M_0402_5% Close to CPU
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(2/12)DDR3L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 7 of 53

5 4 3 2 1
 5 4 3 2 1

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

D UC1E @ SKL-U D
+3VALW Rev_1.0
SPI - FLASH
SMBUS, SMLINK
SOC_SPI_CLK AV2 R7 PCH_SMB_CLK
RC21 1 @ 2 1K_0402_5% SOC_SPI_IO2 SOC_SPI_SO AW3 SPI0_CLK GPP_C0/SMBCLK R8 PCH_SMB_DATA PCH_SMB_CLK [18,33] SMB
SOC_SPI_SI SPI0_MISO GPP_C1/SMBDATA SOC_SMBALERT# PCH_SMB_DATA [18,33]
AV3 R10 (Link to DDR,TP)
SOC_SPI_IO2 SPI0_MOSI GPP_C2/SMBALERT# TP@ T124
AW2
SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK
SOC_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SOC_SML0DATA
RC22 1 @ 2 1K_0402_5% SOC_SPI_IO3 AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SOC_SML0ALERT#
SPI0_CS1# GPP_C5/SML0ALERT# TP@ T125
AU1
RC24 1 @ 2 1K_0402_5% SPI0_CS2# W3 EC_SMB_CK2
GPP_C6/SML1CLK V3 EC_SMB_DA2 EC_SMB_CK2 [22,32,35] SML1
GPP_C7/SML1DATA EC_SMB_DA2 [22,32,35]
SPI - TOUCH AM7 SOC_SML1ALERT# (Link to EC,DGPU,Thermal Sensor)
M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
From WW36 MOW for SKL-U ES sample J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2 AY13 LPC_AD0
GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 [35]
+1.8VS_3VS_PGPPA M1 LPC BA13
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 [35]
BB13
GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 [35]
AY12
C LINK GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3 [35]
RC25 1 2 8.2K_0402_5% SERIRQ BA12
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# [35]
G3 BA11
G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
G1 CL_DATA
CL_RST# AW9 LPC_CLK0 RC26 1 EMI@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC [35]
AY9
KB_RST# AW13 GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN#
[35] KB_RST# GPP_A0/RCIN# GPP_A8/CLKRUN#
C C
+3VS SERIRQ AY11
[35] SERIRQ GPP_A6/SERIRQ 5 OF 20

SKL-U_BGA1356
RC112 1 2 10K_0402_5% KB_RST#
+3VS

RPC1, RPC3 and RC30 are close to UC3

RPC1
SOC_SPI_SO 1 8 SOC_SPI_SO_0_R SOC_SML0CLK 1 2
SOC_SPI_CLK 2 7 SOC_SPI_CLK_0_R RC28 499_0402_1%
SOC_SPI_SI 3 6 SOC_SPI_SI_0_R SOC_SML0DATA 1 2
SOC_SPI_IO3 4 5 SOC_SPI_IO3_0_R RC29 499_0402_1%
From SOC 33_0804_8P4R_5% SOC_SML1ALERT# 1 @ 2
EMI@ RC113 150K_0402_5%
SOC_SPI_IO2 1 2 SOC_SPI_IO2_0_R RPC2
RC30 EMI@ 33_0402_5% PCH_SMB_CLK 1 8
PCH_SMB_DATA 2 7
EC_SMB_CK2 3 6
EC_SMB_DA2 4 5
RPC3
EC_SPI_CLK 1 8 SOC_SPI_CLK_0_R 1K_0804_8P4R_5%
B [35] EC_SPI_CLK EC_SPI_MOSI SOC_SPI_SI_0_R B
2 7
[35] EC_SPI_MOSI EC_SPI_CS0# SOC_SPI_CS#0
From EC 3 6
[35] EC_SPI_CS0# EC_SPI_MISO SOC_SPI_SO_0_R
4 5 +1.8VS_3VS_PGPPA
[35] EC_SPI_MISO
33_0804_8P4R_5%
PM_CLKRUN# 1 @ 2
EMI@
RC31 8.2K_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

< SPI ROM - 8M >

+3VALW
@
UC3 SKL@ CC2 1 2 0.1U_0201_10V K X5R
SOC_SPI_CS#0 1 8
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R
4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R
GND DI(IO0)
1
W 25Q64FVSSIQ_SO8
CC3
10P_0402_50V8J
2 @EMI@

A
UC3 KB_L@ A

Compal Electronics, Inc.

SA000039A30
S IC FL 64M W 25Q64FVSSIQ SOIC 8P SPI ROM
Security Classification Compal Secret Data
Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(3/12)SPI,SMB,LPC,ESPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 8 of 53

5 4 3 2 1
 5 4 3 2 1

D D

UC1G @ SKL-U
Rev_1.0
< HD AUDIO >
AUDIO
RPC4
1 8 HDA_BIT_CLK HDA_SYNC BA22
[29] HDA_BITCLK_AUDIO HDA_SYNC HDA_BIT_CLK HDA_SYNC/I2S0_SFRM
[29] HDA_SYNC_AUDIO 2 7 AY22
3 6 HDA_SDOUT HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
[29] HDA_SDOUT_AUDIO SDIO / SDXC
4 5 BA21 HDA_SDO/I2S0_TXD
[29] HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
33_0804_8P4R_5% AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
EMI@ J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
< To Enable ME Override > AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 1 @ 2
RC116 2 1 0_0402_5% HDA_SDOUT D7 GPP_D19/DMIC_CLK0 SD_RCOMP RC76 200_0402_1%
[35] ME_EN GPP_D20/DMIC_DATA0
D8 AF13
C C8 GPP_D17/DMIC_CLK1 GPP_F23 C
GPP_D18/DMIC_DATA1
HDA_SPKR AW5
[29] HDA_SPKR GPP_B14/SPKR
7 OF 20

SKL-U_BGA1356

UC1I @ SKL-U
Rev_1.0
+3VS CSI-2

A36 C37
RC33 1 @ 2 2.2K_0402_5% HDA_SPKR B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 1 @ 2
D31 CSI2_DN4 CSI2_COMP B7 RC80 100_0402_1%
B C33 CSI2_DP4 GPP_D4/FLASHTRIG B
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
SPKR (Internal Pull Down): B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
TOP Swap Override B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
0 = Disable TOP Swap mode. ==> Default B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
1 = Enable TOP Swap Mode. A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 1 @ 2
EMMC_RCOMP RC129 200_0402_1%
SKL-U_BGA1356

A A

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 9 of 53

5 4 3 2 1
 5 4 3 2 1

@
+3VS SOC_XTAL24_IN
RPC5
8 1
7 2 CLKREQ_PCIE#5 SOC_XTAL24_OUT
6 3 CLKREQ_PCIE#1 1 2
5 4 UC1J @ SKL-U RC34 1M_0402_5%
Rev_1.0
10K_0804_8P4R_5% CLOCK SIGNALS
YC1
D42 24MHZ_12PF_5YEA24000122IF40Q3
RPC6 [19] CLK_PEG_VGA# CLKOUT_PCIE_N0
DGPU C42
CRCLK_REQ# [19] CLK_PEG_VGA VGA_CLKREQ# CLKOUT_PCIE_P0
8 1 [19] VGA_CLKREQ#
AR10 3 1
7 2 WLANCLK_REQ# GPP_B5/SRCCLKREQ0# 3 1
SENSOR_HUB_INT GND GND

15P_0402_50V8J

15P_0402_50V8J
6 3 B42
SENSOR_HUB_INT [11,36] CLKOUT_PCIE_N1

1
5 4 VGA_CLKREQ# A42 F43
D CLKREQ_PCIE#1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N 4 2 D

CC4

CC5
AT7 E43
10K_0804_8P4R_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P

2
D41 BA17 SUSCLK
[31] CLK_PCIE_WLAN# CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK [31]
NGFF WL+BT(KEY E) C41
SSDCLK_REQ# [31] CLK_PCIE_WLAN WLANCLK_REQ# CLKOUT_PCIE_P2 SOC_XTAL24_IN
1 PCIE@ 2 [31] WLANCLK_REQ#
AT8 E37
RC51 10K_0402_5% GPP_B7/SRCCLKREQ2# XTAL24_IN E35 SOC_XTAL24_OUT
D40 XTAL24_OUT
[34] CLK_PCIE_CR# CLKOUT_PCIE_N3 XCLK_BIASREF
CardReader C40 E42
[34] CLK_PCIE_CR CRCLK_REQ# CLKOUT_PCIE_P3 XCLK_BIASREF
AT10
[34] CRCLK_REQ# GPP_B8/SRCCLKREQ3# SOC_RTCX1
AM18
B40 RTCX1 AM20 SOC_RTCX2
[30] CLK_PCIE_SSD# CLKOUT_PCIE_N4 RTCX2
SSD A40
[30] CLK_PCIE_SSD SSDCLK_REQ# CLKOUT_PCIE_P4 SOC_SRTCRST#
AU8 AN18
[30] SSDCLK_REQ# GPP_B9/SRCCLKREQ4# SRTCRST# SOC_RTCRST#
AM16
E40 RTCRST#
E38 CLKOUT_PCIE_N5
+3VL_RTC CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5 +1.0V_CLK5_F24NS
GPP_B10/SRCCLKREQ5#
XCLK_BIASREF 1 2
RC36 1 2 20K_0402_5% SOC_SRTCRST# 10 OF 20 RC35 2.7K_0402_1%
1 @ 2
CC6 1 2 1U_0402_6.3V6K SKL-U_BGA1356 RC110 60.4_0402_1%

RC38
RC37 1 2 20K_0402_5% SOC_RTCRST# 2 1 EC_CLEAR_CMOS# [35] Follow 546765_2014WW48_Skylake_MOW_Rev_1_0
CC7 1 2 1U_0402_6.3V6K 0_0402_5%
Stuf f 2. 7k oh m( RC35) P Uf or SkyLake- U
CLRP2 1 2 SHORT PADS CLR CMOS < PCH PLTRST Buf f er >
RC42 1 @ 2 0_0402_5% Stuf f 60. 4 oh m( RC110) P Df or CannonLake- U
RC39 1 2 1M_0402_5% SM_INTRUDER#

C +3VS C

SOC_RTCX2

5
UC4
SOC_PLTRST# 1

P
B 4 SOC_RTCX1
Y PCI_RST# [19,30,31,35]
2
A

G
1 2

1
TC7SH08FUF_SSOP5 RC41 10M_0402_5%

1
RC44
100K_0402_5%
+3VALW CC8
100P_0402_50V8J

2
ESD@ YC2
RPC7

2
1 2
8 1 PCH_PWROK
7 2 EC_RSMRST# 32.768KHZ 9PF 20PPM 9H03280012
6 3 LAN_WAKE#
5 4 SYS_RESET#

10K_0804_8P4R_5% 1 1
CC9 CC10
6.8P_0402_50V8C 6.8P_0402_50V8C
2 2
UC1K @ SKL-U
ESD@ 1 2 SYS_RESET# Rev_1.0
CC97 100P_0402_50V8J SYSTEM POWER MANAGEMENT
ESD@ 1 2 EC_RSMRST# AT11
CC94 100P_0402_50V8J GPP_B12/SLP_S0# AP15 PM_SLP_S3#
SYS_PWROK SOC_PLTRST# GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# [35]
ESD@ 1 2 AN10 BA16
SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# [35,40,42]
CC95 100P_0402_50V8J B5 AY16 TP@T131
EC_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5#
[35] EC_RSMRST# RSMRST# AN15
A68 SLP_SUS# AW15
B EC_VCCST_PG B65 PROCPWRGD SLP_LAN# BB17 B
VCCST_PWRGD GPD9/SLP_WLAN# AN16
SYS_PWROK B6 GPD6/SLP_A#
[35] SYS_PWROK PCH_PWROK SYS_PWROK PBTN_OUT#
BA20 BA15
[35,45] PCH_PWROK EC_RSMRST# PCH_PWROK GPD3/PWRBTN# AC_PRESENT RC103 PBTN_OUT# [35]
BB20 AY15 1 @ 2 0_0402_5%
+3VALW DSW_PWROK GPD1/ACPRESENT PM_BATLOW# EC_VCIN1_AC_BYPASS [22,35]
AU13
AR13 GPD0/BATLOW#
1 2 WAKE# AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +3VALW
RC47 1K_0402_5% GPP_A15/SUSACK# AU11
WAKE# BB15 GPP_A11/PME# AP16 SM_INTRUDER#
LAN_WAKE# AM15 WAKE# INTRUDER# PM_BATLOW# 1 2
AW17 GPD2/LAN_WAKE# AM10 RC46 8.2K_0402_5%
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT# AC_PRESENT 1 @ 2
GPD7/RSVD 11 OF 20 GPP_B2/VRALERT# RC48 10K_0402_5%
SOC_VRALERT#1 @ 2
+1.0V_VCCST SKL-U_BGA1356 RC50 10K_0402_5%
From EC (Open-Drain)
1

RC52
1K_0402_5%
2

RC53 1 2 60.4_0402_1% EC_VCCST_PG

[35] VCCST_PWRGD
100P_0402_50V8J
CA47 ESD@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(5/12)CLK,PM,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 10 of 53

5 4 3 2 1
 5 4 3 2 1

GSPI0_MOSI (Internal Pull Down):

No Reboot

0 = Disable No Reboot mode. ==> Default

1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This funct i oni s us ef ul
when running ITP/XDP.

D D

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

0 = SPI Mode ==> Default

1 = LPC Mode
UC1F @ SKL-U
Rev_1.0
+3VS LPSS ISH

RC59 1 @ 2 4.7K_0402_5% GSPI0_MOSI AN8 P2

AP7 GPP_B15/GSPI0_CS# GPP_D9 P3
SOC_GPIOB17 AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 +3VS
RC60 1 @ 2 150K_0402_5% GSPI1_MOSI GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1
GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4
GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA ISH_I2C0_SDA [36] ISH_I2C0_SDA
AN7 N3 RC86 1 @ 2 1K_0402_1%
SENSOR_INT GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL ISH_I2C0_SCL [36]
AP5
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO N1 ISH_I2C0_SCL RC88 1 @ 2 1K_0402_1%
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
AB1 GPP_D8/ISH_I2C1_SCL
+3VS NGFF_SSD_PRESENT# AB2 GPP_C8/UART0_RXD AD11 RPC8
RPC10 SOC_GPIOC10 W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 DGPU_HOLD_RST# 1 8
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL DGPU_PWR_EN 2 7
UART0_RX [31] WLBT_OFF# GPP_C11/UART0_CTS# DGPU_PWROK
1 8 [19,23,24,49] DGPU_PWROK
3 6
2 7 UART0_TX AD1 U1 WLBT_OFF# 4 5
UART0_RTS [31] UART0_RX GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
3 6 AD2 U2
UART0_CTS [31] UART0_TX GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
4 5 [31] UART0_RTS
AD3 U3 10K_0804_8P4R_5%
C AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 C
[31] UART0_CTS GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
49.9K_0804_8P4R_1%
AC1 DGPU_PWR_EN
GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_PWR_EN [24]
RC82 1 @ 2 49.9K_0402_1% NGFF_SSD_PRESENT# I2C0_SDA_SEN U7 AC2 DGPU_HOLD_RST#
1K,3VS[35,36] I2C0_SDA_SEN I2C0_SCL_SEN U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 GPU_ALL_PGOOD DGPU_HOLD_RST# [19]
I2C0_SDA_SEN <Sensor> 1K,3VS [35,36] I2C0_SCL_SEN GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# DGPU_PRSNT# GPU_ALL_PGOOD [24]
RC72 1 2 1K_0402_1% AB4
U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
I2C0_SCL_SEN [27] I2C1_SDA_TS GPP_C18/I2C1_SDA
RC73 1 2 1K_0402_1% U9 AY8 ACC_INT1
[27] I2C1_SCL_TS GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 ACC_INT2
AH9 GPP_A19/ISH_GP1 BB7 ALS_INT3
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 DGPU_PRSNT#
R75 1 2 10K_0402_5% AY7
EC_SCI# [6,35]
AH11 GPP_A22/ISH_GP4 AW7
Funct i on (GPP_C15)
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6 DIS 0
AF11 UMA Only
RC27 1 @ 2 499_0402_1% I2C1_SDA_TS AF12 GPP_F8/I2C4_SDA 1 +3VS
GPP_F9/I2C4_SCL 6 OF 20
RC32 1 @ 2 499_0402_1% I2C1_SCL_TS DGPU_PRSNT# 10K_0402_5% 2 UMA@ 1 R73
SKL-U_BGA1356
10K_0402_5% 2 DIS@ 1 R74

SENSOR_HUB_INT RC196 1 2 0_0402_5% SENSOR_INT

[10,36] SENSOR_HUB_INT
SENSOR_EC_INT RC205 1 @ 2 0_0402_5%
[35] SENSOR_EC_INT +3VS

B SOC_GPIOC10 RC2041 2 0_0402_5% GPU_EVENT# ACC_INT1 RC146 1 @ 2 4.7K_0402_5% B

GPU_EVENT# [22]

SOC_GPIOB17 RC1951 2 0_0402_5% GC6_FB_EN TO DGPU ACC_INT2

GC6_FB_EN [22,23] RC147 1 @ 2 4.7K_0402_5%

ALS_INT3 RC148 1 @ 2 4.7K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(6/12)GPIO,I2C,GSPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 11 of 53

5 4 3 2 1
 5 4 3 2 1

UC1H @ SKL-U
Rev_1.0

PCIE / USB3 / SATA SSIC / USB3

D H8 D
USB3_1_RXN G8
H13 USB3_1_RXP C13
[19] PCIE_PRX_DTX_N1 PCIE1_RXN/USB3_5_RXN USB3_1_TXN
[19] PCIE_PRX_DTX_P1 G13 D13
CC11 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP
[19] PCIE_PTX_C_DRX_N1 PCIE1_TXN/USB3_5_TXN
[19] PCIE_PTX_C_DRX_P1 CC14 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P1 A17 J6 USB3_RX2_N [34]
PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6
USB3_2_RXP / SSIC_RXP USB3_RX2_P [34]
G11 B13 USB2/3 MB(IO_Port2)
[19] PCIE_PRX_DTX_N2 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN USB3_TX2_N [34]
F11 A13
[19] PCIE_PRX_DTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_TX2_P [34]
CC15 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N2 D16
[19] PCIE_PTX_C_DRX_N2 CC16 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
[19] PCIE_PTX_C_DRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN USB3_RX3_N [34]
H10 USB3_RX3_P [34]
H16 USB3_3_RXP B15
dGPU [19] PCIE_PRX_DTX_N3 PCIE3_RXN USB3_3_TXN USB3_TX3_N [34] USB2/3 MB(IO_Port1)
G16 A15
[19] PCIE_PRX_DTX_P3 PCIE3_RXP USB3_3_TXP USB3_TX3_P [34]
CC12 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N3 D17
[19] PCIE_PTX_C_DRX_N3 PCIE3_TXN
CC13 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P3 C17 E10
[19] PCIE_PTX_C_DRX_P3 PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
[19] PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15
[19] PCIE_PRX_DTX_P4 CC17 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_N4 B19 PCIE4_RXP USB3_4_TXP
[19] PCIE_PTX_C_DRX_N4 PCIE4_TXN
CC18 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PTX_DRX_P4 A19 AB9
[19] PCIE_PTX_C_DRX_P4 PCIE4_TXP USB2N_1 AB10
F16 USB2P_1
E16 PCIE5_RXN AD6 USB20_N2
PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 [34]
C19 AD7 USB2/3 MB(IO_Port2)
PCIE5_TXN USB2P_2 USB20_P2 [34]
D19
PCIE5_TXP AH3 USB20_N3
USB2N_3 USB20_P3 USB20_N3 [34]
[31] PCIE_PRX_DTX_N6 G18 AJ3 USB2/3 MB(IO_Port1)
PCIE6_RXN USB2P_3 USB20_P3 [34]
[31] PCIE_PRX_DTX_P6 F18
1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_N6 D20 PCIE6_RXP AD9
C NGFF WLAN+BT [31] PCIE_PTX_C_DRX_N6
CC102
PCIE_PTX_DRX_P6 C20 PCIE6_TXN USB2N_4
C
CC103 1 2 0.1U_0201_10V K X5R AD10
[31] PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4
F20 AJ1 USB20_N5
[30] SATA_PRX_DTX_N7 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 [27]
E20 AJ2 Camera
[30] SATA_PRX_DTX_P7 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 [27]
B21 USB2
[30] SATA_PTX_DRX_N7 A21 PCIE7_TXN/SATA0_TXN AF6
[30] SATA_PTX_DRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 AF7
G21 USB2P_6
SSD [30] PCIE_PRX_DTX_N8 PCIE8_RXN/SATA1A_RXN USB20_N7
F21 AH1
[30] PCIE_PRX_DTX_P8 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 [31]
D21 AH2 NGFF WLAN+BT
[30] PCIE_PTX_C_DRX_N8 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 [31]
C21
[30] PCIE_PTX_C_DRX_P8 PCIE8_TXP/SATA1A_TXP AF8
USB2N_8 USB20_N8 [34]
E22 AF9 Finger Print (For 15)
[34] PCIE_CRX_DTX_N9 PCIE9_RXN USB2P_8 USB20_P8 [34]
E23
[34] PCIE_CRX_DTX_P9 1 2 0.1U_0201_10V6K PCIE_CTX_DRX_N9 B23 PCIE9_RXP AG1
CardReader [34] PCIE_CTX_C_DRX_N9
CC19
PCIE_CTX_DRX_P9 PCIE9_TXN USB2N_9
CC20 1 2 0.1U_0201_10V6K A23 AG2
[34] PCIE_CTX_C_DRX_P9 PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC70 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 RC104 1 2 1K_0402_5%
RC71 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 RC105 1 2 1K_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
D56 GPP_E9/USB2_OC0# C9 USB_OC1#
D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2#
BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
E28 J1 DEVSLP0
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 DEVSLP0 [30]
E27 J2
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 W L_OFF#
D24 J3
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
When PCIE8/SATA1A is used as SATA Port 1 (ODD), then E30 PCIE11_TXP/SATA1B_TXP H2 NGFF_SSD_PEDET
PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1. F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
NGFF_SSD_PEDET [30]
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1
8 OF 20 GPP_E8/SATALED# +3VALW

SKL-U_BGA1356
RPC9
USB_OC2# 8 1
USB_OC0# 7 2
USB_OC3# 6 3
USB_OC1# 5 4

10K_0804_8P4R_5%

+3VS

PCIE@
NGFF_SSD_PEDET RC130 1 2 10K_0402_5%

@
W L_OFF# RC131 1 2 10K_0402_5%
A A

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 12 of 53

5 4 3 2 1
 5 4 3 2 1

+1.2V +1.0VS_VCCIO
UC1N @ SKL-U
Rev_1.0
+VL +1.0VALW CPU POWER 3 OF 4
AU23 AK28
+1.0V_VCCST AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
VDDQ_AU35 VCCIO

1U_0402_6.3V6K

1U_0402_6.3V6K
I(Max) : 0.16 A(+1.0V_VCCST) AU42 AL42
+1.0VALW TO +1.0V_VCCST 1 1 VDDQ_AU42 VCCIO

CC21

CC22
RON(Max) : 25 mohm RC77 1 2 0_0402_5% BB23 AM28
BB32 VDDQ_BB23 VCCIO AM30
D V drop : 0.004 V D
VDDQ_BB32 VCCIO +VCCSA

0.1U_0201_10V K X5R
@ 1 BB41 AM42
2 2 +1.0VS_VCCIO VDDQ_BB41 VCCIO

CC23
BB47
BB51 VDDQ_BB47 AK23
VDDQ_BB51 VCCSA AK25
UC5 2 VCCSA G23
1 14 +1.0V_VCCST AM40 VCCSA G25
2 VIN1 VOUT1 13 VDDQC VCCSA G27
VIN1 VOUT1 A18 VCCSA G28
RC74 2 1 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 VCCST VCCSA J22
ON1 CT1
Follow 543977_SKL_PDDG_Rev0_91 VCCSA
[35,42] SYSON CC24 A22 J23
CC24 10PF ->22us(Spec:<= 65us) VCCSTG_A22 VCCSA
4 11 10P_0402_50V8J J27
VBIAS GND AL23 VCCSA K23
RC75 2 1 0_0402_5% EN_1.8VS 5 10 1 2 VCCPLL_OC VCCSA K25
[35,37,42] SUSP# ON2 CT2 CC25 K20 VCCSA K27
6 9 1000P_0402_50V7K K21 VCCPLL_K20 VCCSA K28
+1.8VALW 7 VIN2 VOUT2 8 VCCPLL_K21 VCCSA K30
VIN2 VOUT2 +1.8VS VCCSA
15 AM23
GPAD RC78 1 2 0_0402_5% VCCIO_SENSE AM22
EM5209VF DFN 14P DUAL LOAD SW VSSIO_SENSE
+1.8VALW TO +1.8VS VSSSA_SENSE

0.1U_0201_10V K X5R
1U_0402_6.3V6K
1 1 H21
VSSSA_SENSE VCCSA_SENSE VSSSA_SENSE [46]

CC27
CC26
H20
VCCSA_SENSE VCCSA_SENSE [46]
14 OF 20
@
2 I(Max) : 0.2 A(+1.8VS) 2 SKL-U_BGA1356 Trace Length Match < 25 mils
RON(Max) : 25 mohm
V drop : 0.005 V
C C

+1.0VALW TO +1.0VS_VCCIO
+1.0V_VCCST +1.0VS_VCCIO
+VL +1.0VALW I(Max) : 3.04 A(+1.0VS_VCCIO)
RON(Max) : 6.2 mohm PSC Side BSC Side
V drop : 0.019 V
1U_0402_6.3V6K
0.1U_0201_10V K X5R

1 1
CC32
CC30

UC6
+1.0VS_VCCIO

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
@ 1 1 1 1
2 2 2 VIN1
VIN2

CC35
CC28

CC34
7 6 +1.0VS_VCCIO_STG RC79 1 2 0_0805_5% @
VIN thermal VOUT 2 2 2
1
3
VBIAS CC33
SUSP# RC81 2 1 0_0402_5% 4 5 @ 0.1U_0201_10V K X5R
ON GND 2
B B
TPS22961DNYR_W SON8 Close to A18 Close to K20 Close to A22

change pakage of 1U from 0201 to 0402 change pakage of 1U from 0201 to 0402
+1.0VS_VCCIO +1.2V

BSC Side PSC Side BSC Side PSC Side BSC Side
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

1U_0402_6.3V6K
1U_0402_6.3V6K

10U_0603_6.3V6M
1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1
CC36

CC37

CC39

CC41

CC29

CC44

CC49
CC38

CC48
CC40

CC46

CC50
CC42

CC43

CC45

CC47
@ @ @ @ @ @ @ @
2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2
change pakage of 10U
from 0402 to 0603
Underneath CPU Close to CPU Close to AL23 Close to AM40 Close to CPU Underneath CPU
A A

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(8/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 13 of 53

5 4 3 2 1
 5 4 3 2 1

Follow 543016_SKL_U_Y_PDG_1_0
D +1.0VALW D
+1.0V_APLL +1.0VALW +1.8VALW
RF@ UC1O SKL-U
LC1 Rev_1.0 +3VALW
MURATA BLM15EG221SN1D CPU POWER 4 OF 4
1 2 CC51 1 2 1U_0402_6.3V6K AB19
SM01000HC00 AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3V_1.8V_PGPPA

0.1U_0402_25V6
R_0402 2 @ P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16
VCCPGPPC

CC31
RF@
CC54 1 2 1U_0402_6.3V6K AF18 Y15
AF19 VCCPRIM_CORE VCCPGPPD T16
1 Imax : 2.57A V20 VCCPRIM_CORE VCCPGPPE AF16
@
VCCPRIM_CORE VCCPGPPF
VCCPGPPF support 1.8V only
V21 AD15
VCCPRIM_CORE VCCPGPPG
CC55 1 2 1U_0402_6.3V6K DCPDSW AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
CC56 1 2 1U_0402_6.3V6K K17 T1 +1.0VALW
L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1
Close to K17 VCCMPHYAON_1P0
+1.0V_AMPHYPLL AA1 CC57 1 2 1U_0402_6.3V6K
CC1001 2 22U_0603_6.3V6M N15 VCCATS_1P8
N16 VCCMPHYGT_1P0_N15 AK17
@
Imax : 1.54A N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
LC2 1 2 0_0603_5% CC66 1 2 1U_0402_6.3V6K P15 VCCMPHYGT_1P0_N17 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
22U_0603_6.3V6M

1U_0402_6.3V6K
Close to P15 P16 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
CC58

CC59

+1.0V_AMPHYPLL
K15 BB10 DCPRTC CC62 1 2 0.1U_0201_10V K X5R
L15 VCCAMPHYPLL_1P0 DCPRTC
@ @ VCCAMPHYPLL_1P0 A14
2 2 VCCCLK1 +1.0V_CLK6_24TBT
V15
+1.0V_APLL VCCAPLL_1P0 K19
AB17 VCCCLK2
Y18 VCCPRIM_1P0_AB17 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL
AD17 N20
+3VALW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4_F100OC
AD18
+1.0V_CLK5_F24NS AJ17 VCCDSW_3P3_AD18 L19
C VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS C
Follow 543016_SKL_U_Y_PDG_1_0
+3V_1.8V_HDA
AJ19 A10 +1.0V_CLK6_24TBT
RC85 1 2 0_0603_5% RF@ +3V_1.8V_HDA VCCHDA VCCCLK6
+3VALW RC115 AJ16 AN11
VCCSPI GPP_B0/CORE_VID0
22U_0603_6.3V6M
22U_0603_6.3V6M

MURATA BLM15EG221SN1D AN13

1 2 1 2 AF20 GPP_B1/CORE_VID1
1 1 VCCSRAM_1P0
CC64
CC63

SM01000HC00 CC65 1U_0402_6.3V6K AF21

VCCSRAM_1P0
0.1U_0402_25V6

R_0402 @ Close to AF20 T19

@ @ T20 VCCSRAM_1P0
2 2 1 VCCSRAM_1P0
CC52
RF@

1 2 AJ21
CC67 1U_0402_6.3V6K VCCPRIM_3P3_AJ21
2 @ AK20
Close to AJ21 VCCPRIM_1P0_AK20
1 2 N18
CC68 1U_0402_6.3V6K VCCAPLLEBB_1P0 15 OF 20
+1.0V_CLK4_F100OC Close to N18
Follow 543016_SKL_U_Y_PDG_1_0 SKL-U_BGA1356
@
RC87 1 2 0_0603_5%
22U_0603_6.3V6M

22U_0603_6.3V6M

1 1
CC69

CC70

+3VALW +3V_1.8V_PGPPA
@ @ LPC 3.3V
2 2
Follow 543016_SKL_U_Y_PDG_1_0
RTC Bat t er y
RC89 1 2 0_0402_5%
+1.0VALW +3VALW +1.8VALW +3VALW +3VL_RTC +RTCBATT

W=20mils
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
+1.0V_CLK6_24TBT 1 1 1 1 1 1 RC90 1 2 0_0402_5%

1U_0402_6.3V6K
CC71

CC72

CC73

CC74

CC75

CC76

1U_0402_6.3V6K

0.1U_0201_10V K X5R
1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1
B Follow 543016_SKL_U_Y_PDG_1_0 1 B

CC80

CC77

CC79
CC78

CC81
@ @ @ @ @ @ @ @ @ CC82
RC91 1 2 0_0603_5% 2 2 2 2 2 2 1U_0402_6.3V6K
2 2 2 2 2
2
22U_0603_6.3V6M

22U_0603_6.3V6M

+3VS
1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 +1.8VS_3VS_PGPPA
CC85

CC86

Close to AG15 Close to Y16 Close to T16 Close to AK17

CC83

CC84

LPC 3.3V
@ @ @ @ Saf t y s ugges t i on r emove EE s i de , Keep PW
R s i de
2 2 2 2 RC93 1 2 0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(9/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 14 of 53

5 4 3 2 1
 5 4 3 2 1

+VCCCORE +VCCCORE +VCCGT +VCCGT

UC1M SKL-U
UC1L SKL-U Rev_1.0
Rev_1.0 CPU POWER 2 OF 4
CPU POWER 1 OF 4
N70
A30 G32 A48 VCCGT N71
A34 VCC_A30 VCC_G32 G33 A53 VCCGT VCCGT R63
A39 VCC_A34 VCC_G33 G35 A58 VCCGT VCCGT R64
D D
A44 VCC_A39 VCC_G35 G37 A62 VCCGT VCCGT R65
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
AM37 VCC_AM35 VCC_K38 K40 AC67 VCCGT VCCGT W64
AM38 VCC_AM37 VCC_K40 K42 AC68 VCCGT VCCGT W65
G30 VCC_AM38 VCC_K42 K43 AC69 VCCGT VCCGT W66
VCC_G30 VCC_K43
Trace Length Match < 25 mils VCCGT VCCGT
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
RSVD VCC_SENSE VCCCORE_SENSE [46] VCCGT VCCGT
E33 J43 W69
+1.0VS_VCCOPC AK32 VSS_SENSE VSSCORE_SENSE [46] VCCGT VCCGT
J45 W70
RSVD B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
AB62 VIDALERT# A63 VR_SVID_CLK J48 VCCGT VCCGT Y62
VCCOPC_AB62 VIDSCK VR_SVID_DATA VR_SVID_CLK [46] VCCGT VCCGT
P62 D64 J50
+1.8VALW V62 VCCOPC_P62 VIDSOUT J52 VCCGT
VCCOPC_V62 G20 J53 VCCGT AK42
VCCSTG_G20
ALERT signal must be routed between CLK and DATA signals VCCGT VCCGTX_AK42
1 23E@ 2 +1.8V_VCCOPCH63 J55 AK43
RC111 0_0402_5% VCC_OPC_1P8_H63 +1.0VS_VCCIO J56 VCCGT VCCGTX_AK43 AK45
G61 J58 VCCGT VCCGTX_AK45 AK46
VCC_OPC_1P8_G61 J60 VCCGT VCCGTX_AK46 AK48
VCCOPC_SENSE AC63 K48 VCCGT VCCGTX_AK48 AK50
C For CPU 23e SKU T157 TP@ VCCOPC_SENSE VCCGT VCCGTX_AK50
C
VSSOPC_SENSE AE63 K50 AK52
T158 TP@ VSSOPC_SENSE VCCGT VCCGTX_AK52
K52 AK53
AE62 K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
AL63 K58 VCCGT VCCGTX_AK58 AK60
AJ62 VCCEOPIO_SENSE K60 VCCGT VCCGTX_AK60 AK70
VSSEOPIO_SENSE 12 OF 20 L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
VCCGT VCCGTX_AL46
For CPU GT3 SKU
SKL-U_BGA1356 L64 AL50
@ L65 VCCGT VCCGTX_AL50 AL53
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
SVID ALERT N66 VCCGT
VCCGT
VCCGTX_AU58
VCCGTX_AU63
AU63
+1.0V_VCCST N67 BB57
Place the PU VCCGT VCCGTX_BB57
N69 BB66
resistors close to CPU VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62 VCCGTX_SENSE
VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE T161 TP@
1

VSSGT_SENSE J69 AL61 VSSGTX_SENSE

VSSGT_SENSE VSSGT_SENSE T162 TP@
RC94 13 OF 20VSSGTX_SENSE
56_0402_5%
B B
Trace Length Match < 25 mils SKL-U_BGA1356
@
2

SOC_SVID_ALERT# 1 2 (To VR) For CPU GT3 SKU

VR_ALERT# [46]
RC95 220_0402_5%

+1.0VS_VCCOPC
BSC Side BSC Side
+1.0V_VCCST

SVID DATA Place the PU

resistors close to CPU

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M
1 1 1 1 1 1 1
1

CC87

CC89

CC93
CC90

CC91

CC92
CC88
RC96

23E@

23E@

23E@

23E@

23E@
23E@
23E@
100_0402_1%
2 2 2 2 2 2 2
2

VR_SVID_DATA
VR_SVID_DATA [46] (To VR)
Close to AE62,AG62 Close to AB62,P62,V62

A A

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(10/12)Power,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 15 of 53

5 4 3 2 1
 5 4 3 2 1

D D
UC1P SKL-U UC1Q SKL-U
Rev_1.0 Rev_1.0 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3 Rev_1.0
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
C AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 C
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46 @
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
B AK27 VSS VSS AR5 B58 VSS VSS F1 B
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @

A A

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(11/12)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 16 of 53

5 4 3 2 1
 5 4 3 2 1

D D

UC1S SKL-U UC1T SKL-U

Rev_1.0 Rev_1.0
RESERVED SIGNALS-1 +1.8VALW SPARE

E68 BB68 AW69 F6

B67 CFG[0] RSVD_TP_BB68 BB69 AW68 RSVD_AW69 RSVD_F6 E3
D65 CFG[1] RSVD_TP_BB69 AU56 RSVD_AW68 RSVD_E3 C11
D67 CFG[2] AK13 RC98 AW48 RSVD_AU56 RSVD_C11 B11
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 0_0402_5% C7 RSVD_AW48 RSVD_B11 A11
C68 CFG[4] RSVD_TP_AK12 1 @ 2 U12 RSVD_C7 RSVD_A11 D12
D68 CFG[5] BB2 U11 RSVD_U12 RSVD_D12 C12
CFG[6] RSVD_BB2 RSVD_U11 RSVD_C12

1U_0402_6.3V6K
C67 BA3 1 H11 F52
F71 CFG[7] RSVD_BA3 RSVD_H11 RSVD_F52
CFG[8]

CC98
G69 20 OF 20
F70 CFG[9] AU5 @
G68 CFG[10] TP5 AT5 2 SKL-U_BGA1356
H70 CFG[11] TP6 @
G71 CFG[12]
H69 CFG[13] D5
G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
E63 RSVD_B2 C2
F63 CFG[16] RSVD_C2
CFG[17] B3
E66 RSVD_B3 A3
F66 CFG[18] RSVD_A3
C CFG[19] AW1 C
CFG_RCOMP E60 RSVD_AW1
CFG_RCOMP E1
E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
RSVD_AY1 RSVD_BB4
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RC97 1 2 0_0402_5%
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3 +3VS
RSVD_TP_BA68 TP2
J71 AY71 LPM_ZVM# 1 23E@ 2
J68 RSVD_J71 VSS_AY71 AR56 LPM_ZVM# RC114 10K_0402_5%
B RSVD_J68 ZVM# LPM_ZVM# [45] B
F65 AW71
G65 VSS_F65 RSVD_TP AW70
VSS_G65 RSVD_TP For 2+3e Solut i on
F61 AP56 PM_MSM# LPM_ZVM#
RSVD_F61 MSM# T185 TP@
E61 C64 SKL_CNL# +1.0V_VCCST PM_MSM#
RSVD_E61 PROC_SELECT#
19 OF 20 1 @ 2
RC99 100K_0402_5%
1 2 CFG_RCOMP SKL-U_BGA1356
RC100 49.9_0402_1% @

1 2 CFG4
Follow 544669_SKL_U_DDR3L_RVP7_schemat i c_r ev1. 0
RC101 1K_0402_5%
Stuf f 100k( RC99) f or CannonLake- U
Un-stuf f 100k( RC99) f or SkyLake- U

Display Port Presence Strap

1 : Disabled;
No Physical Display Port at t ac hed t o E mbedded Dis pl ay Port
CFG4
0 : Enabled;
A An external Display Port device is connected to the Embedded Display Port A

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(12/12)CFG,RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 17 of 53

5 4 3 2 1
 A B C D E

[7] DDR_A_DQS#[0..7]

[7] DDR_A_D[0..63]

[7] DDR_A_DQS[0..7] +1.2V

[7] DDR_A_MA[0..16]
+1.2V JDIMM1
[7] DDR_A_BA0
[7] DDR_A_BA1
1 2
[7] DDR_A_BG0 DDR_A_D4 VSS1 VSS2 DDR_A_D1
3 4
[7] DDR_A_BG1 DQ5 DQ4
5 6
DDR_A_D5 7 VSS3 VSS4 8 DDR_A_D0
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
[7] DDR_A_CLK0 DQS0_t VSS7 DDR_A_D3
15 16
[7] DDR_A_CLK#0 DDR_A_D2 VSS8 DQ6 +1.2V
1 17 18 1
[7] DDR_A_CLK1 DQ7 VSS9 DDR_A_D7
19 20
[7] DDR_A_CLK#1 DDR_A_D6 VSS10 DQ2
21 22
23 DQ3 VSS11 24 DDR_A_D9
DDR_A_D8 25 VSS12 DQ12 26
[7] DDR_A_CKE0 DQ13 VSS13 DDR_A_D13 +DIMM_VREF_DQ
27 28
[7] DDR_A_CKE1 DDR_A_D12 VSS14 DQ8
29 30
DQ9 VSS15 DDR_A_DQS#1

2
31 32
[7] DDR_A_CS#0 VSS16 DQS1_c DDR_A_DQS1 +0.6V_VREFCA_R
33 34 RD200 1 2 0_0402_5% RD194
[7] DDR_A_CS#1 DM1_n/DBI_n DQS1_t [7] +0.6V_VREFCA
35 36 1K_0402_1%
DDR_A_D11 37 VSS17 VSS18 38 DDR_A_D15 RD10
39 DQ15 DQ14 40 20mil 2_0402_1%

1
DDR_A_D10 41 VSS19 VSS20 42 DDR_A_D14 RD201 1 @ 2 0_0402_5% 2 1
[8,33] PCH_SMB_DATA DQ10 DQ11 [7] +0.6V_A_VREFDQ
43 44
[8,33] PCH_SMB_CLK DDR_A_D21 VSS21 VSS22 DDR_A_D17
45 46
47 DQ21 DQ20 48
DDR_A_D20 VSS23 VSS24 DDR_A_D16 1
49 50
[7] DDR_A_ODT0 DQ17 DQ16
51 52 CD21
[7] DDR_A_ODT1 DDR_A_DQS#2 VSS25 VSS26
53 54 0.022U_0402_16V7K
DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56 2
57 DQS2_t VSS27 58 DDR_A_D23
VSS28 DQ22

1
DDR_A_D22

2
59 60
61 DQ23 VSS29 62 DDR_A_D19 RD12 RD199
DDR_A_D18 63 VSS30 DQ18 64 24.9_0402_1% 1K_0402_1%
65 DQ19 VSS31 66 DDR_A_D28
DDR_A_D25 67 VSS32 DQ28 68

1
69 DQ29 VSS33 70 DDR_A_D29
Note: DDR_A_D24 VSS34 DQ24
Layout Note: 71 72
Check voltage tolerance of 73 DQ25 VSS35 74 DDR_A_DQS#3
Place near JDIMM1 VREF_DQ at the DIMM socket 75 VSS36 DQS3_c 76 DDR_A_DQS3
77 DM3_n/DBI3_n DQS3_t 78
DDR_A_D30 79 VSS37 VSS38 80 DDR_A_D31
81 DQ30 DQ31 82
DDR_A_D26 83 VSS39 VSS40 84 DDR_A_D27
85 DQ26 DQ27 86
+1.2V 87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
@ 93 CB1/NC CB0/NC 94
VSS45 VSS46
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 2 95 96
6/16 INTEL suggest 1
RD165 2
240_0402_1% 97 DQS8_c DM8_n/DBI_n/NC 98
1 1 1 1 1 1 1 1 DQS8_t VSS47
RD166 240_0402_1% 99 100
VSS48 CB6/NC
CD5

CD6

CD17
CD4

CD7

CD8

CD9

CD18

@ 101 102
103 CB2/NC VSS49 104
2 2 2 2 2 2 2 2 105 VSS50 CB7/NC 106
2
107 CB3/NC VSS51 108 DDR_DRAMRST#_R 2
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1
111 CKE0 CKE1 112
DDR_A_BG1 VDD1 VDD2 1
113 114 ESD@
DDR_A_BG0 BG1 ACT_n M_A_ACT# [7]
4 as near side of the DIMM close to VDD pins 115 116 CD34
BG0 ALERT_n DDR_A_ALERT# [7] 100P_0201_25V8J
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11 2
+1.2V DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
DDR_A_MA6 A8 A5 DDR_A_MA4
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

127 128
129 A6 A4 130
DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
1 DDR_A_MA1 A3 A2
1 1 1 1 1 1 1 1 @ 133 134
A1 EVENT_n/NF
CD13

CD14

CD15
CD10

CD11

CD12

CD19

CD20

+ CD35 135 136

330U_D3_2.5VY_R6M DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1
DDR_A_CLK#0 139 CK0_t CK1_t/NF 140 DDR_A_CLK#1
2 2 2 2 2 2 2 2 2 141 CK0_c CK1_c/NF 142
143 VDD11 VDD12 144 DDR_A_MA0
[7] DDR_A_PARITY DDR_A_BA1 PARITY A0 DDR_A_MA10
145 146
147 BA1 A10/AP 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
DDR_A_MA14 151 CS0_n BA0 152 DDR_A_MA16
153 WE_n/A14 RAS_n/A16 154
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_MA15
DDR_A_CS#1 157 ODT0 CAS_n/A15 158 DDR_A_MA13 +DIMM_VREF_DQ
159 CS1_n A13 160
DDR_A_ODT1 161 VDD17 VDD18 162
163 ODT1 C0/CS2_n/NC 164
165 VDD19 VREFCA 166
+3VS 167 C1, CS3_n,NC SA2 168
DDR_A_D37 169 VSS53 VSS54 170 DDR_A_D34
Place these caps on the VTT plane close to DIMM DQ37 DQ36 +1.2V
171 172
DDR_A_D33 173 VSS55 VSS56 174 DDR_A_D32
+0.6VS 175 DQ33 DQ32 176
DDR_A_DQS#4 177 VSS57 VSS58 178
+3VS_DIMM DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180
181 DQS4_t VSS59 182 DDR_A_D39
DDR_A_D38 183 VSS60 DQ39 184
DQ38 VSS61

1
DDR_A_D36
10U_0603_6.3V6M
10U_0603_6.3V6M

1@ 1 1 1@ 1 1 1 1 DDR_A_D35
185
VSS62 DQ35
186
CD23
CD22

CD30 CD31 CD32 CD33 @ 187 188 RD43

@ C2142 CD28 189 DQ34 VSS63 190 DDR_A_D41
470_0402_1%
DDR_A_D44 VSS64 DQ45
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

2.2U_0402_6.3V6M 0.1U_0201_10V K X5R 191 192

2 2 2 2 2 2 2 2 193 DQ44 VSS65 194 DDR_A_D40

2
DDR_A_D45 195 VSS66 DQ41 196
3 3
197 DQ40 VSS67 198 DDR_A_DQS#5 DDR_DRAMRST#_R RD45 1 2 0_0402_5%
VSS68 DQS5_c DDR_A_DQS5 DDR_DRAMRST# [7]
199 200
201 DM5_n/DBI5_n DQS5_t 202
close to DIMM DDR_A_D43 VSS69 VSS70 DDR_A_D47
203 204
205 DQ46 DQ47 206
DDR_A_D42 207 VSS71 VSS72 208 DDR_A_D46
209 DQ42 DQ43 210
DDR_A_D49 211 VSS73 VSS74 212 DDR_A_D48
213 DQ52 DQ53 214
DDR_A_D52 215 VSS75 VSS76 216 DDR_A_D53
217 DQ49 DQ48 218
DDR_A_DQS#6 219 VSS77 VSS78 220
DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222
223 DQS6_t VSS79 224 DDR_A_D54
DDR_A_D55 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_A_D51
DDR_A_D50 229 VSS82 DQ50 230
+2.5V 231 DQ51 VSS83 232 DDR_A_D57
DDR_A_D59 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_A_D56
DDR_A_D58 237 VSS86 DQ57 238 +3VS +3VS
239 DQ56 VSS87 240 DDR_A_DQS#7
+2.5V 241 VSS88 DQS7_c 242 DDR_A_DQS7 +0.6VS
DM7_n/DBI7_n DQS7_t

2
243 244
DDR_A_D61 245 VSS89 VSS90 246 DDR_A_D63 RD109 RD108
247 DQ62 DQ63 248
VSS91 VSS92 10K_0402_5% 10K_0402_5%
DDR_A_D60 DDR_A_D62
10U_0603_6.3V6M

249 250
1
C2140
1
CD29
Reverse Type 251 DQ58 DQ59 252
@ @

1
PCH_SMB_CLK 253 VSS93 VSS94 254 PCH_SMB_DATA
+3VS_DIMM SCL SDA DDR_A_SA0
1U_0402_6.3V6K

255 256
2 2 257 VDDSPD SA0 258 DDR_A_SA1 DDR_A_SA0
2-3A to 1 DIMMs/channel 259 VPP1 VTT 260 DDR_A_SA1
261 VPP2 SA1 262
GND1 GND2

1
RD139 RD138
0_0402_5% 0_0402_5%

2
DEREN_40-42261-26001RHF
LTCX006OD00
ME@

4 4

Interleaved Memory
Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_DIMM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 18 of 53

A B C D E
 1 2 3 4 5

UV1A
COMMON
1/14 PCI_EXPRESS
Place near Place near BGA +1.0VS_DGPU
AB6
balls
PEX_WAKE# 1.0V

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
NOGC6@ AA22

4.7U_0603_6.3V6K
PEX_IOVDD
PLT_RST_VGA_MON# PLT_RST_VGA#

CV202

CV205

CV199

CV204
RV379 1 2 AC7 PEX_RST# PEX_IOVDD AB23 1 1 1 1 1 1 1

CV9

CV7
0_0402_5% AC24

CV2 DIS@
PEX_IOVDD
CLKREQ_PCIE#0_R AC6 PEX_IOVDD AD25
PEX_CLKREQ#
PEX_IOVDD AE26
2 2 2 2 2 2 2

DIS@

DIS@

@
AE8 PEX_REFCLK PEX_IOVDD AE27
[10] CLK_PEG_VGA
PCIE CLK AD8 PEX_REFCLK#
[10] CLK_PEG_VGA#
PCIE_PRX_DTX_P1 CV11 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_P1 AC9
[12] PCIE_PRX_DTX_P1 PEX_TX0
A (From PCH CLKOUT0) PCIE_PRX_DTX_N1 CV12 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_N1 AB9 A
[12] PCIE_PRX_DTX_N1 PEX_TX0#
PCIE_PTX_C_DRX_P1 AG6
[12] PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1
PEX_RX0 Place near Place near BGA +1.0VS_DGPU
AG7 PEX_IOVDDQ AA10
[12] PCIE_PTX_C_DRX_N1 PEX_RX0#
AA12
balls
PCIE_PRX_DTX_P2 PCIE_PRX_C_DTX_P2
PEX_IOVDDQ 1.0V
CV13 DIS@ 1 2 0.22U_0402_6.3V6K AB10 PEX_TX1 PEX_IOVDDQ AA13
[12] PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 PCIE_PRX_C_DTX_N2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
CV14 DIS@ 1 2 0.22U_0402_6.3V6K AC10 AA16

4.7U_0603_6.3V6K
PEX_TX1# PEX_IOVDDQ
[12] PCIE_PRX_DTX_N2

CV201

CV200

CV198

CV203
PEX_IOVDDQ AA18 1 1 1 1 1 1 1
PCIE_PTX_C_DRX_P2

CV10 @

CV8
AF7 AA19

CV3 @
PEX_RX1 PEX_IOVDDQ
[12] PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2 AE7 PEX_RX1# PEX_IOVDDQ AA20
[12] PCIE_PTX_C_DRX_N2
PEX_IOVDDQ AA21
PCIE_PRX_DTX_P3 PCIE_PRX_C_DTX_P3 2 2 2 2 2 2 2

DIS@

DIS@

DIS@
PCIE X4 Bus CV15 DIS@ 1 2 0.22U_0402_6.3V6K AD11 PEX_TX2 PEX_IOVDDQ AB22
[12] PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 PCIE_PRX_C_DTX_N3
CV16 DIS@ 1 2 0.22U_0402_6.3V6K AC11 PEX_TX2# PEX_IOVDDQ AC23
[12] PCIE_PRX_DTX_N3
(Link to CPU Port 1~4) PEX_IOVDDQ AD24
PCIE_PTX_C_DRX_P3 AE9 PEX_IOVDDQ AE25
[12] PCIE_PTX_C_DRX_P3 PEX_RX2
PCIE_PTX_C_DRX_N3 AF9 PEX_IOVDDQ AF26
[12] PCIE_PTX_C_DRX_N3 PEX_RX2#
PEX_IOVDDQ AF27
PCIE_PRX_DTX_P4 CV17 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_P4 AC12
[12] PCIE_PRX_DTX_P4 PEX_TX3
PCIE_PRX_DTX_N4 CV18 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_PRX_C_DTX_N4 AB12
[12] PCIE_PRX_DTX_N4 PEX_TX3#
PCIE_PTX_C_DRX_P4 AG9
[12] PCIE_PTX_C_DRX_P4 PEX_RX3
PCIE_PTX_C_DRX_N4 AG10
[12] PCIE_PTX_C_DRX_N4 PEX_RX3#

AB13 PEX_TX4
AC13 PEX_TX4#

AF10 PEX_RX4
AE10 PEX_RX4#

AD14 NC FOR GF119

PEX_TX5
AC14 PEX_TX5# PEX_PLL_HVDD AA8
PEX_PLL_HVDD AA9

NC FOR GM108
AE12 +3VS_DGPU_AON
PEX_RX5
AF12 PEX_RX5# Place near BGA
+3VS AB8
B Reset Control PEX_SVDD_3V3
B

0.1U_0201_10V6K
AC15

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
PEX_TX6
AB15 PEX_TX6# 1 1 1

CV207 DIS@

CV5 DIS@

CV4 DIS@
5

UV12 AG12 PEX_RX6

PCI_RST# 1 AG13 PEX_RX6#
P

[10,30,31,34] PCI_RST# B PLT_RST_VGA_MON# 2 2 2

4
DGPU_HOLD_RST# Y PLT_RST_VGA_MON# [22]
2 AB16 PEX_TX7
[11] DGPU_HOLD_RST# A
G

(From PCH) AC16 PEX_TX7#

TC7SH08FUF_SSOP5 +3VS_DGPU_AON
3

DIS@ AF13 PEX_RX7

AE13 PEX_RX7#
5

UV15
1 AD17
P

B PEX_TX8
4 PLT_RST_VGA# AC17
Y PEX_TX8#
PLT_RST_VGA_HOLD# 2
[22] PLT_RST_VGA_HOLD# A
G

(From GPU) AE15 PEX_RX8

TC7SH08FUF_SSOP5 RV378 AF15 PEX_RX8#
3

GC6@ 10K_0402_5%
DIS@ AC18 VDD_SENSE F2 VDD_SENSE_GPU
PEX_TX9 VDD_SENSE_GPU [49]
AB18 PEX_TX9# To POWER
2

AG15 GND_SENSE F1 GND_SENSE_GPU

PEX_RX9 GND_SENSE_GPU [49]
AG16 PEX_RX9# trace width: 16mils
differential voltage sensing.
AB19 PEX_TX10
AC19
differential signal routing.
PEX_TX10#

AF16
CLK_REQ AE16
PEX_RX10
PEX_RX10#

NC FOR GF117/GK208/GM108
+3VS_DGPU
AD20 PEX_TX11
AC20 PEX_TX11#
DIS@
1

AE18 PEX_RX11
RV17 AF18
C PEX_RX11# C
10K_0402_5%
RV16 @ AC21 PEX_TX12
1 2 AB21 PEX_TX12#
[11,23,24,49] DGPU_PWROK
2

0_0402_5%
PEX_PLL_CLK_OUT RV4 2
1U_0402_6.3V6K

1 AG18 PEX_RX12 PEX_TSTCLK_OUT AF22 @ 1200_0402_1%

+3VS_DGPU_AON PEX_PLL_CLK_OUT#
CV121

AG19 PEX_RX12# PEX_TSTCLK_OUT# AE22

@

AD23 PEX_TX13
1

2 AE23 +1.0VS_DGPU
RV68 PEX_TX13#
PEX_PLLVDD_GPU
1.0V
10K_0402_5% AF19 PEX_RX13 PEX_PLLVDD AA14 RV377 2 1 0_0402_5%
2

DIS@ AE19 PEX_RX13# PEX_PLLVDD AA15

G

0.1U_0201_10V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
2

CV206
AF24 PEX_TX14 Place near BALL 1 1 1
CLKREQ_PCIE#0_R VGA_CLKREQ#

CV208 DIS@
3 1 AE24

CV6 DIS@
VGA_CLKREQ# [10] PEX_TX14#
S

(To SOC) AE21 PEX_RX14

2 2 2

DIS@
DIS@ QV3 AF21 PEX_RX14#
2N7002K_SOT23-3 AD9 GPU_TESTMODE
TESTMODE
VGS(Max) : 2.5 V AG24 PEX_TX15 Place near BGA
AG25 PEX_TX15#
@
RV375 1 2 0_0402_5% AG21 PEX_RX15
AG22 PEX_RX15#

PEX_TERMP GPU_TESTMODE [22]

PEX_TERMP AF25

1
N16S-GT-S-A2_BGA595
DIS@ RV376
2.49K_0402_1%
DIS@

2
D D

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(1/5)-PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

LA-D471P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 19 of 53

1 2 3 4 5
 1 2 3 4 5

UV1G
IFPA/B
UV1J
COMMON IFPE/F UV1H
COMMON IFPC
COMMON 5/14 IFPC
4/14 IFPAB
7/14 IFPEF IFPC
GF119/GK208
T6 IFPC_RSET GF119/GK208
DVI-DL DVI-SL/HDMI DP
IFPA_TXC# AC4
IFPA_TXC AC3 I2CY_SDA I2CY_SDA IFPE_AUX# J3 DVI/HDMI DP
I2CY_SCL I2CY_SCL IFPE_AUX J2
AA6 J7 M7 N5

NC FOR GF117/GM108
IFPAB_RSET IFPEF_PLLVDD IFPC_PLLVDD I2CW_SDA IFPC_AUX#
IFPA_TXD0# Y3 N7 IFPC_PLLVDD I2CW_SCL IFPC_AUX N4
Y4 J1

NC FOR GF117/GM108
IFPA_TXD0 TXC TXC IFPE_L3#
A IFPE_L3 K1 A

NC FOR GF117/GM108
TXC TXC
V7 IFPAB_PLLVDD K7 IFPEF_PLLVDD TXC IFPC_L3# N3

NC FOR GF117/GK208/GM108
IFPA_TXD1# AA2 IFPE_L2# K3 TXC IFPC_L3 N2
W7 AA3 TXD0 TXD0 K2
IFPAB_PLLVDD IFPA_TXD1 IFPE_L2
TXD0 TXD0

NC FOR GF117/GM108
IFPC_L2# R3
TXD0
K6 IFPEF_RSET IFPE_L1# M3 TXD0 IFPC_L2 R2
TXD1 TXD1
IFPA_TXD2# AA1 IFPE_L1 M2
TXD1 TXD1
IFPA_TXD2 AB1 TXD1 IFPC_L1# R1
IFPE_L0# M1 TXD1 IFPC_L1 T1
TXD2 TXD2

NC FOR GF117/GM108
IFPE_L0 N1
AA5 TXD2 TXD2 T3
IFPA_TXD3# TXD2 IFPC_L0#
IFPA_TXD3 AA4 T2
IFPE NC FOR GK208 TXD2 IFPC_L0

IFPB_TXC# AB4 GF117

IFPB_TXC AB5 HPD_E GPIO18 C2 P6 IFPC_IOVDD GPIO15 C3
HPD_E NC

W6 AB2 NC FOR GF117

IFPA_IOVDD IFPB_TXD4#
IFPB_TXD4 AB3 N16S-GT-S-A2_BGA595
Y6 IFPB_IOVDD H6 IFPE_IOVDD DIS@
GF119/GK208
IFPB_TXD5#
IFPB_TXD5
AD2
AD3
J6 IFPF_IOVDD
DVI-DL DVI-SL/HDMI DP
H4
UV1I
COMMON
IFPD
I2CZ_SDA IFPF_AUX# 6/14 IFPD
I2CZ_SCL IFPF_AUX H3
IFPB_TXD6# AD1
AE1 U6 GF119/GK208
IFPB_TXD6 IFPD_RSET
TXC IFPF_L3# J5
J4 DVI/HDMI DP

NC FOR GF117/GM108
TXC IFPF_L3
IFPB_TXD7# AD5
IFPB_TXD7 AD4 TXD3 TXD0 IFPF_L2# K5 T7 IFPD_PLLVDD I2CX_SDA IFPD_AUX# P4
K4 P3

NC FOR GF117/GM108
TXD3 TXD0 IFPF_L2 I2CX_SCL IFPD_AUX
R7 IFPD_PLLVDD
L4

NC FOR GF117/GM108
TXD4 TXD1 IFPF_L1#
GF117 IFPF TXD4 TXD1 IFPF_L1 L3 TXC IFPD_L3# R5
TXC IFPD_L3 R4
NC GPIO14 B3 TXD5 TXD2 IFPF_L0# M5
B
IFPAB TXD5 TXD2 IFPF_L0 M4
TXD0
TXD0
IFPD_L2#
IFPD_L2
T5
T4
B

N16S-GT-S-A2_BGA595
NC FOR GK208
DIS@ TXD1 IFPD_L1# U4
IFPD TXD1 IFPD_L1 U3
GPIO19 F7
HPD_F
IFPD_L0# V4
TXD2
TXD2 IFPD_L0 V3
NC FOR GF117

UV1K DAC_A N16S-GT-S-A2_BGA595 R6 IFPD_IOVDD

GF117

NC GPIO17 D4
COMMON DIS@
3/14 DACA

GF117/GM108 GF117 GM108/GK208

W5 B7 I2CA_SCL
DACA_VDD NC NC I2CA_SCL I2CA_SCL [22]
A7 I2CA_SDA
NC I2CA_SDA I2CA_SDA [22]
AE2 DACA_VREF TSEN_VREF N16S-GT-S-A2_BGA595
DIS@
AF2 DACA_RSET DACA_HSYNC AE3 +1.0VS_DGPU
NC NC
NC DACA_VSYNC AE4 Place near balls
1V DIS@
1 2 GPU_PLLVDD +3VS_DGPU_AON
DACA_RED AG3 LV5 PBY160808T-300Y-N 0603

0.1U_0201_10V K X5R
NC

22U_0603_6.3V6M
@
AF4 XTAL_OUTBUFF 1 2
NC DACA_GREEN 1 1

CV32 DIS@

DIS@ CV31
RV23 10K_0402_1%
NC

GM108
DACA_BLUE AF3
2 2
UV1M
COMMON
9/14 XTAL_PLL
X'TAL
GK208 +1.0VS_DGPU Place near BGA Place near balls
GF117
L6 PLLVDD
N16S-GT-S-A2_BGA595 LV6 1 2 0_0603_5% VID_PLLVDD M6 SP_PLLVDD
DIS@

0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
22U_0603_6.3V6M

22U_0603_6.3V6M
1V N6 VID_PLLVDD

10U_0603_6.3V6M
NC

DIS@ CV30
1 1 1 1 1

CV61 DIS@

CV35 DIS@

DIS@ CV60
DIS@ CV34
GF119/GK208 GF117/GM108
C C

2 2 2 2 2 DIS@
2 RV21 1 A10 XTALSSIN XTALOUTBUFF C10 XTAL_OUTBUFF 1 RV20 2
10K_0402_1% 10K_0402_1%
DIS@
C11 XTALIN XTALOUT B10

N16S-GT-S-A2_BGA595
DIS@
90-OHM DIFF Impedance for XTALIN & XTALOUT.

YV1

XTALIN 1 3 XTAL_OUT
1 3
GND GND
2 2 4 27MHZ_10PF 2
CV210 DIS@ CV209
10P_0402_50V8J 10P_0402_50V8J
1 DIS@ 1 DIS@

D D

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(2/5)-IFP_ABCDEF_DAC_XTAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 20 of 53

1 2 3 4 5
 1 2 3 4 5

Place under GPU +VGA_CORE

UV1F
UV1E COMMON
UV1D COMMON 13/14 GND
+1.35VS_VRAM COMMON Voltage by GPU SKU A2 M13
11/14 NVVDD GND GND
12/14 FBVDDQ K10 VDD AB17 GND GND M15
K12 VDD AB20 GND GND M17
A B26 FBVDDQ K14 VDD AB24 GND GND N10 A
C25 FBVDDQ K16 VDD AC2 GND GND N12

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

E23 K18 AC22 N14

DIS@ CV38
DIS@ CV217

DIS@ CV218

DIS@ CV221
1 1 1 1 1 1 FBVDDQ VDD GND GND
E26 L11 AC26 N16

DIS@ CV222

DIS@ CV215
2 2 2 2 2 2
F14
F21
G13
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
GPU_Decoupling L13
L15
L17
VDD
VDD
VDD
VDD
AC5
AC8
AD12
GND
GND
GND
GND
GND
GND
GND
GND
N18
P11
P13
G14
G15
G16
FBVDDQ
FBVDDQ
FBVDDQ
CAPs @ Power M10
M12
M14
VDD
VDD
VDD
AD13
A26
AD15
GND
GND
GND
GND
GND
GND
P15
P17
P2
G18
G19
G20
FBVDDQ
FBVDDQ
FBVDDQ
Page M16
M18
N11
VDD
VDD
VDD
AD16
AD18
AD19
GND
GND
GND
GND
GND
GND
P23
P26
P5
G21 FBVDDQ N13 VDD AD21 GND GND R10
L22 FBVDDQ N15 VDD AD22 GND GND R12
L24 FBVDDQ N17 VDD AE11 GND GND R14
L26 FBVDDQ P10 VDD AE14 GND GND R16
M21 FBVDDQ P12 VDD AE17 GND GND R18
N21 FBVDDQ P14 VDD AE20 GND GND T11
R21 FBVDDQ P16 VDD AB11 GND GND T13
T21 FBVDDQ P18 VDD AF1 GND GND T15
V21 FBVDDQ R11 VDD AF11 GND GND T17
W21 FBVDDQ R13 VDD AF14 GND GND U10
R15 VDD AF17 GND GND U12
R17 VDD AF20 GND GND U14
GF117 T10 AF23 U16
GF119
VDD GND GND
T12 VDD AF5 GND GND U18
GK208 T14 AF8 U2
VDD GND GND
H24 FBVDDQ_AON T16 VDD AG2 GND GND U23
FBVDDQ
22U_0603_6.3V6M

H26 FBVDDQ_AON T18 VDD AG26 GND GND U26

10U_0603_6.3V6M

FBVDDQ
J21 U11 AB14 U5
DIS@ CV44

1 1 FBVDDQ_AON FBVDDQ VDD GND GND

CV45 DIS@

K21 FBVDDQ_AON U13 VDD B1 GND GND V11

FBVDDQ
U15 VDD B11 GND GND V13
U17 VDD B14 GND GND V15
2 2 V10 B17 V17
B VDD GND GND B
V12 VDD B20 GND GND Y2
V14 VDD B23 GND GND Y23
V16 VDD B27 GND GND Y26
V18 VDD B5 GND GND Y5
B8 GND
E11 GND
Place near GPU N16S-GT-S-A2_BGA595 E14 GND
DIS@ E17 GND
E2 GND
E20 GND
E22 GND
E25 GND
E5 GND
E8 GND
Near Ball +1.35VS_VRAM H2 GND
H23 GND
H25 GND
FB_CAL_PD_VDDQ D22 1 2 H5 GND
40.2_0402_1% RV41 K11 GND
DIS@ K13 GND
FB_CAL_PU_GND C24 2 1 K15 GND
42.2_0402_1% RV42 K17 GND
DIS@ L10 GND
FB_CALTERM_GND B25 2 1 L12 GND
51.1_0402_1% RV43 L14 GND
DIS@ L16 GND
N16S-GT-S-A2_BGA595 L18 GND
DIS@ L2 GND
L23 GND
L25 GND
L5 GND GND AA7
M11 GND GND AB7

C C
N16S-GT-S-A2_BGA595
DIS@

UV1C
COMMON
14/14 XVDD/VDD33
+3VS_DGPU
Under GPU Near GPU
AD10 NC VDD33 G8
AD7 NC VDD33 G9
0.1U_0201_10V6K
0.1U_0201_10V6K

GM108
4.7U_0603_6.3V6K

G10
DIS@ CV219

DIS@ CV216

VDD33 1 1 1 1
1U_0402_6.3V6K

3V3_AON
G12
DIS@ CV211
DIS@ CV220

3V3_AON VDD33

F11 3V3AUX_NC
2 2 2 2
V5 FERMI_RSVD1_NC
V6 FERMI_RSVD2_NC

+3VS_DGPU_AON
Under GPU Near GPU
CONFIGURABLE
POWER CHANNELS
1U_0402_6.3V6K

4.7U_0603_6.3V6K
DIS@ CV213
DIS@ CV212

* nc on substrate 1 1
0.1U_0201_10V6K

1
G1
DIS@ CV214

XPWR_G1
G2 XPWR_G2
G3 2 2
XPWR_G3
G4 2
XPWR_G4
G5 XPWR_G5
G6 XPWR_G6
G7 XPWR_G7

** XPWR pins are configurable.

V1 XPWR_V1
D D
V2 XPWR_V2 These pins are not connected on the substrate.

Therefore, XPWR pins can be assigned as needed,

to improve Top layer routing, power delivery.

W1 XPWR_W1

Compal Electronics, Inc.

W2 XPWR_W2
W3 XPWR_W3
Security Classification Compal Secret Data
W4 XPWR_W4 2014/05/19 2015/12/31 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(3/5)-POWER
N16S-GT-S-A2_BGA595 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DIS@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 21 of 53

1 2 3 4 5
 1 2 3 4 5

Internal Thermal Sensor

+3VS_DGPU_AON

Link to PCH SML1

5
G
DIS@ PU @ PCH SIDE

VGA_THERMDN and VGA_THERMDP:

UV1N
COMMON
8/14 MISC1
GPIO +3VS_DGPU_AON

I2CS_SCL 4 3
QV2B

S
1. 5mil track width and spacing I2CS_SCL EC_SMB_CK2 [8,32,35]

D
I2CS_SCL D9 RV203 1 DIS@ 2 2.2K_0402_5%
2. 5mil grounded gurad tracks width and spacing D8 I2CS_SDA RV204 1 DIS@ 2 2.2K_0402_5% 2N7002KDW_SOT363-6
3. ground referenced I2CS_SDA I2CS SMBUS: 0x96 and 0x9E(Default)
4. Connect guard tracks to pin5 A9 I2CC_SCL RV205 1 @ 2 2.2K_0402_5%
I2CC_SCL I2CC_SDA

2
B9 RV206 1 @ 2 2.2K_0402_5%

G
I2CC_SDA
A DIS@ A
QV2A
E12 GF117
THERMDN
C9 I2CB_SCL I2CS_SDA 1 6

S
NC I2CB_SCL I2CB_SDA EC_SMB_DA2 [8,32,35]

D
F12 THERMDP I2CB_SDA C8
NC
2N7002KDW_SOT363-6
GPU_JTAG_TCK AE5
T231
T232
TP@
TP@
GPU_JTAG_TMS
GPU_JTAG_TDI
AD6
JTAG_TCK
JTAG_TMS For GC6 2.0
T242 TP@ AE6 JTAG_TDI
GPU_JTAG_TDO AF6
T243 TP@ JTAG_TDO
GPU_JTAG_TRST# AG4 C6 GPIO0_GC6_FB_EN RV202 1 2 0_0402_5%
JTAG_TRST# GPIO0 GC6_FB_EN [11,23]
GPIO1 B2
GPIO2 D6
GPIO3 C7
GPIO4 F9 GC6@
A3 DGPU_MAIN_EN
GPIO5 GPU_EVENT#_D DGPU_MAIN_EN [24,49]
GPIO6 A4 2 1
GK208 GPU_EVENT# [11]
GM108 GPIO7 B6 DV1
A6 GPIO8_OVERT# RB751V-40_SOD323-2
OVERT GPIO8 GPIO9_ALERT#
GPIO9 F8
GPIO10 C5
E7 GPU_VID0
GPIO11 VGA_AC_DET GPU_VID0 [49] To DGPU VR
D7
GPIO12
B4 PSI
From EC
GPIO13 PSI [49] To DGPU VR
GM108 GK208 GF117 GF119

GPIO16 D5
GPIO16 GPIO16 NC
GPIO20 E6
GPIO20 GPIO20 NC
GPIO21 C4 PLT_RST_VGA_HOLD#
GPIO21 GPIO8 NC PLT_RST_VGA_HOLD# [19]

NC E9 PLT_RST_VGA_MON#
GPIO8 NC NC PLT_RST_VGA_MON# [19]

N16S-GT-S-A2_BGA595
DIS@

UV1L +3VS_DGPU_AON
COMMON
10/14 MISC2 RPV5 +3VS Reserve for
PLT_RST_VGA_HOLD# 1 8
B DGPU_MAIN_EN leakage issue B
2 7
PSI 3 6
E10 VGA_AC_DET 4 5 +3VS +3VS
VMON_IN0_NC
F10 VMON_IN1_NC ROM_CS# D12
10K_0804_8P4R_5%
ROM_SI

2
ROM_SI B12 DIS@
A12 ROM_SO RV15 RV26
ROM_SO
STRAP0 D1 C12 ROM_SCLK GPIO8_OVERT# 1 DIS@ 2 10K_0402_5%
STRAP0 ROM_SCLK 10K_0402_5%
STRAP1 D2 STRAP1 RV69 100K_0402_5% @ @
STRAP2 E4 NC FOR GPU_EVENT#_D 1 DIS@ 2 @
STRAP2 DV4

1
E3 GM10 8 RV72 10K_0402_5%
STRAP3 STRAP3
STRAP4 D3 VGA_AC_DET 2 1 EC_VCIN1_AC_BYPASS
STRAP4 EC_VCIN1_AC_BYPASS [10,35]
RPV6 RB751V-40_SOD323-2
GPIO9_ALERT# 1 8
+3VS_DGPU_AON C1 STRAP5_NC 2 7 1 @ 2
RV2751 D11 GPU_BUFRST PLT_RST_VGA_MON# 3 6 RV126 0_0402_5%
BUFRST#
0_0402_5% @ FB_CLAMP 4 5
FB_CLAMP
1 2 STRAPREF0 F6 MULTISTRAP_REF0_GND PGOOD D10
NC
GF117 10K_0804_8P4R_5%
GK208 GF117 GF119 DIS@
GM108 GK208
F4 MULTISTRAP_REF1_GND NC
GM108 RPV3
I2CA_SCL
1

DIS@ 1 8
[20] I2CA_SCL I2CA_SDA
RV380 F5 MULTISTRAP_REF2_GND 2 7
40.2K_0402_1% NC [20] I2CA_SDA I2CB_SCL
I2CB_SDA
3
4
6
5 STRAP +3VS_DGPU
2

N16S-GT-S-A2_BGA595 2.2K_0804_8P4R_5%
DIS@ @

1
1

4.99K_0402_1%
GPU_BUFRST 1 @ 2 X76@ @ @

10K_0402_1%
14.7K_0402_1%
RV67 10K_0402_5%
GPU_JTAG_TRST# 1 DIS@ 2

RV84
RV70 10K_0402_5%

RV81

RV80
2
2

2
GPU_TESTMODE 1 DIS@ 2
[19] GPU_TESTMODE ROM_SI
RV71 10K_0402_5%
ROM_SO
ROM_SCLK

1
4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
X76@ DIS@ DIS@

C C

RV65

RV64

RV381
2

2
From EC
RAM_CFG[3:0] BAX40
(ROM_SI)

0x9(PU 10K)
STRAP STRAP0 : PU 49.9K (50K)
0xA(PU 15K) STRAP[1:5] : Reserved
+3VS_DGPU_AON
0xB(PU 20K)
0x3(PD 20K)

0x4(PD 24.9K)

1
1

1
10K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

49.9K_0402_1%
@ @ @ @
DIS@

RV51
RV61

RV389

RV382

RV384
0x5(PD 30.1K)

2
2
2

2
STRAP0
0x1(PD 10K) S2G STRAP1
STRAP2
STRAP3
STRAP4
0x2(PD 15K) H2G
1

1
1
45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
4.99K_0402_1%
@ @ @ @ @
RV385

RV387

RV388

RV383
RV390
0x3(PD 20K)
2

2
0x4(PD 24.9K)
0x5(PD 30.1K)

D D
0xF(PU 45.3K)

0xE(PU 34.8K)

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(4/5)-GPIO/Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-D471P
Date: Monday, June 06, 2016 Sheet 22 of 53

1 2 3 4 5
 1 2 3 4 5

+3VS GC6_FB_EN

UV1B
For GC6

2
COMMON
2/14 FBA 1 RV88
[26] FBA_D[0..31] FBA_D0 FB_CLAMP
E18 FBA_D0 NC FB_CLAMP F3 @ 10K_0402_5%
FBA_D1 FB_CLAMP
F18 FBA_D1 0.1U_0201_10V K X5R GC6@
FBA_D2 E16 CV223
FBA_D2 GF119

1
A
FBA_D3 F17 2 A
FBA_D3
FBA_D4 D20 FBA_D4

5
FBA_D5 D21 UV23
FBA_D5
FBA_D6 F20 GC6_FB_EN 2
FBA_D6

G Vcc
FBA_D7 [11,22] GC6_FB_EN B
E21 FBA_D7 4
FBA_D8 E15 1 Y 1.35V_PWR_EN [24,50]
FBA_D8 [11,19,24] DGPU_PWROK
FBA_D9 D15 A
FBA_D9
FBA_D10 F15 GC6@ MC74VHC1G32DFT2G SC70-5
FBA_D10

3
FBA_D11 F13 FBA_D11
FBA_D12 C13 FBA_D12
FBA_D13 B13 FBA_D13
FBA_D14 E13 1 NOGC6@2
FBA_D14
FBA_D15 D13 RV201 0_0402_5%
FBA_D15
FBA_D16 B15 FBA_D16
FBA_D17 C16 Stuff RV201 if not support GC6
FBA_D17
FBA_D18 A13 FBA_D18
FBA_D19 A15 FBA_D19
FBA_D20 B18 FBA_D20
FBA_D21 A18 FBA_D21
FBA_D22 A19 FBA_D22
FBA_D23 C19 FBA_D23
FBA_D24 B24 FBA_D24
FBA_D25 C23
FBA_D26 A25
FBA_D25
FBA_D26
From DG-07158-001_v05_secured(NVDIA Spec)
FBA_D27 A24 FBA_D27
FBA_D28 A21 FBA_D28
FBA_D29 B21 FBA_D29 FBA_CMD[0..30] [25,26]
FBA_D30 C20 FBA_D30
FBA_D31 C21
[25] FBA_D[32..63] FBA_D31
FBA_D32 R22 FBA_D32
FBA_D33 R24 FBA_CMD0 C27 FBA_CMD0
FBA_D33
FBA_D34 T22 FBA_CMD1 C26 FBA_CMD1
FBA_D34
FBA_D35 R23 E24 FBA_CMD2
FBA_D35 FBA_CMD2
FBA_D36 N25 FBA_CMD3 F24 FBA_CMD3
FBA_D36
FBA_D37 N26 FBA_CMD4 D27 FBA_CMD4
FBA_D37
B FBA_D38 N23 FBA_CMD5 D26 FBA_CMD5 B
FBA_D38
FBA_D39 N24 F25 FBA_CMD6
FBA_D39 FBA_CMD6
FBA_D40 V23 FBA_CMD7 F26 FBA_CMD7 FBA_DOT_L FBA_CMD2
FBA_D40
FBA_D41 V22 FBA_CMD8 F23 FBA_CMD8
FBA_D41
FBA_D42 T23 FBA_CMD9 G22 FBA_CMD9 FBA_DOT_H FBA_CMD18
FBA_D42
FBA_D43 U22 FBA_CMD10 G23 FBA_CMD10
FBA_D43
FBA_D44 Y24 G24 FBA_CMD11 FBA_CKE_L FBA_CMD3
FBA_D44 FBA_CMD11
FBA_D45 AA24 F27 FBA_CMD12
FBA_D45 FBA_CMD12
FBA_D46 Y22 FBA_CMD13 G25 FBA_CMD13 FBA_CKE_H FBA_CMD19
FBA_D46
FBA_D47 AA23 FBA_CMD14 G27 FBA_CMD14
FBA_D47
FBA_D48 AD27 FBA_CMD15 G26 FBA_CMD15
FBA_D48

2
FBA_D49 AB25 M24 FBA_CMD16

10K_0402_5%

10K_0402_5%

10K_0402_5%
10K_0402_5%
FBA_D49 FBA_CMD16
FBA_D50 AD26 M23 FBA_CMD17
FBA_D50 FBA_CMD17
FBA_D51 AC25 K24 FBA_CMD18

1 DIS@

1 DIS@

1 DIS@
1 DIS@
RV2437

RV2438

RV2440
RV2439
FBA_D51 FBA_CMD18
FBA_D52 AA27 FBA_CMD19 K23 FBA_CMD19
FBA_D52
FBA_D53 AA26 M27 FBA_CMD20
FBA_D53 FBA_CMD20
FBA_D54 W26 M26 FBA_CMD21
FBA_D54 FBA_CMD21
FBA_D55 Y25 M25 FBA_CMD22
FBA_D55 FBA_CMD22
FBA_D56 R26 FBA_CMD23 K26 FBA_CMD23
FBA_D56
FBA_D57 T25 FBA_CMD24 K22 FBA_CMD24
FBA_D57
FBA_D58 N27 J23 FBA_CMD25
FBA_D58 FBA_CMD25
FBA_D59 R27 J25 FBA_CMD26
FBA_CMD26
FBA_D60
FBA_D61
FBA_D62
V26
V27
FBA_D59
FBA_D60
FBA_D61
FBA_CMD27
FBA_CMD28
J24
K27
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_RST
W27 FBA_D62 FBA_CMD29 K25
FBA_D63 W25 J27 FBA_CMD30
FBA_D63 FBA_CMD30
J26 FBA_CMD5
FBA_CMD31
[26] DQMA[3..0]
DQMA0 D19 FBA_DQM0

2
DQMA1 D14 FBA_DQM1 FBVDDQ_GPU
DQMA2 C17 FBA_DQM2 GF117/GF119 RV2447
DQMA3 C22 FBA_DQM3 GK208 +1.35VS_VRAM 10K_0402_5%
[25] DQMA[7..4]
DQMA4 P24 FBA_DQM4 DIS@
DQMA5 W24 FBA_DQM5 NC
FBA_CMD32 B19 1.35V

1
C DQMA6 AA25 FBA_DQM6 C
DQMA7 U25 FBA_DQM7 FBA_DEBUG0 FBA_CMD34 F22 RV82 1 @ 2 60.4_0402_1%
FBA_DEBUG1 FBA_CMD35 J22 RV83 1 @ 2 60.4_0402_1%
[26] FBA_DQSP[3..0] FBA_DQSP0 E19
FBA_DQS_WP0
FBA_DQSP1 C15
FBA_DQS_WP1
FBA_DQSP2 B16 FBA_CLK0 D24 CLKA0
FBA_DQS_WP2 CLKA0 [26]
FBA_DQSP3 B22 FBA_CLK0# D25 CLKA0#
[25] FBA_DQSP[7..4] FBA_DQS_WP3 CLKA0# [26]
FBA_DQSP4 R25 FBA_CLK1 N22 CLKA1
FBA_DQS_WP4 CLKA1 [25]
FBA_DQSP5 W23 FBA_CLK1# M22 CLKA1#
FBA_DQS_WP5 CLKA1# [25]
FBA_DQSP6 AB26
FBA_DQS_WP6
FBA_DQSP7 T26
FBA_DQS_WP7

[26] FBA_DQSN[3..0] FBA_DQSN0 F19

FBA_DQS_RN0 FBA_WCK01 D18
FBA_DQSN1 C14 FBA_WCK01# C18
FBA_DQS_RN1
FBA_DQSN2 A16 FBA_WCK23 D17
FBA_DQS_RN2
FBA_DQSN3 A22 FBA_WCK23# D16
[25] FBA_DQSN[7..4] FBA_DQS_RN3
FBA_DQSN4 P25 FBA_WCK45 T24
FBA_DQS_RN4
FBA_DQSN5 W22 FBA_WCK45# U24
FBA_DQS_RN5
FBA_DQSN6 AB27 FBA_WCK67 V24
FBA_DQS_RN6
FBA_DQSN7 T27 FBA_WCK67# V25
FBA_DQS_RN7
+1.0VS_PLLAVDD +1.0VS_DGPU
Close to P22 Close to F16
GF119 1.0V DIS@
F16 +1.0VS_PLLAVDD 1 2
FB_PLLAVDD
NC
LV7 PBY160808T-300Y-N 0603
CV55

0.1U_0201_10V K X5R

22U_0603_6.3V6M
CV53

0.1U_0201_10V K X5R
CV52

0.1U_0201_10V K X5R

FB_PLLAVDD P22
1 2 1 1

CV51 DIS@
FB_PLLAVDD FB_DLLAVDD H22
DIS@

DIS@
DIS@

GF117
2 1 2 2

D D

For VRAM DEBUG using Close to H22 Near GPU

FB_VREF D23
T2401 TP@ FB_VREF_PROBE

N16S-GT-S-A2_BGA595
DIS@

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(5/5)-MEMORY FBA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-D471P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2 3 4 Date: Monday, June 06, 2016 Sheet 5 23 of 53
 5 4 3 2 1

I_Continuous(Max) : 0.79 A(+1.0VS_DGPU)

RON(Max) : 22 mohm
+VGA_CORE +1.0V_PRIM to +1.0VS_DGPU
+3VS to +3VS_DGPU V drop : 0.0175 V
Rising : ~ 208us
+1.0VALW +1.0VS_DGPU
QV5 DIS@

2
ME2320D-G 1N SOT-23-3
+5VALW RV240
10_0603_5% 1 3

S
@

2
1 1

1
2
+3VS DIS@ +3VS_DGPU +5VALW CV133 CV314 RV239
1

G
2
@
RV2745 QV26 CV316 10_0603_5%

0.1U_0201_10V6K

DIS@
1U_0402_6.3V6K
47K_0402_5% ME2301DC-G_SOT23-3 @

1
D 2 2

0.1U_0201_10V K X5R
DIS@
DIS@

1
2
3 1 2 DGPU_MAIN_EN# 2

D
@

1
G RV2752

1U_0402_6.3V6K
4.7U_0603_6.3V6K

1
QV31

470_0603_5%
1 2 S 47K_0402_5%

3
D DIS@ D

G
2

1
D

CV319

CV318

RV2742
RV2746 @ 2N7002K_SOT23-3

1
DGPU_MAIN_EN# DGPU_MAIN_EN#_GATE DGPU_MAIN_EN_GATE

@
@ @ 2
2 1 G

2
10K_0402_5% DIS@ 1 CV320 QV29 S

3
6
+1.35VS_VRAM RV85

1
D DGPU_MAIN_EN_GATE DGPU_MAIN_EN_R_GATE

0.1U_0201_10V K X5R
DIS@
RV2747 2N7002K_SOT23-3
0_0402_5% @ 2
DGPU_MAIN_EN 1 2 2 QV30A 2 QV25 G +5VALW 10K_0402_5% DIS@
[22,49] DGPU_MAIN_EN

1
L2N7002DW1T1G 2N SC88-6 2N7002K_SOT23-3 D
@

0.1U_0402_25V6
S

3
DIS@ RV2006 DGPU_MAIN_EN# 2 DIS@ 1

1
1U_0402_6.3V6K
1 22_0603_1% G CV315

1
CV321 @
@ 2N7002K_SOT23-3 S QV146 DIS@

3
RV2007

2
DGPU_MAIN_EN# 2
100K_0402_1%
2

3
D
1.35V_PWR_EN# 5 @
G QV145B
2N7002KDW_SOT363-6
S

4
6
D
2 @
[23,50] 1.35V_PWR_EN G QV145A
+5VALW 2N7002KDW_SOT363-6
+3VS to +3VS_DGPU_AON S

1
2

+3VS DIS@ +3VS_DGPU_AON

RV2739 QV20
47K_0402_5% ME2301DC-G_SOT23-3
DIS@
3
S 1

D
1

1U_0402_6.3V6K
4.7U_0603_6.3V6K

1
470_0603_5%
1 2
G
2

CV312

CV311

RV2735
RV2741 @
DGPU_PWR_EN# DGPU_PWR_EN#_GATE

@
@
2 1

2
10K_0402_5% DIS@ 1 CV313
3

C C

1
D
0.1U_0201_10V K X5R
DIS@

RV2748 QV30B
0_0402_5% L2N7002DW1T1G 2N SC88-6 @ 2
DGPU_PWR_EN 1 2 5 DIS@ 2 QV19 G
[11,35] DGPU_PWR_EN
2N7002K_SOT23-3 S

3
4

DGPU_PWR_EN#
1U_0402_6.3V6K

1
CV317 @

+3VS_DGPU_AON

RG82
10K_0402_5%
DIS@ DIS@
DG4
1

DGPU_PWROK 1 2
[11,19,23,49] DGPU_PWROK
RB751V-40_SOD323-2

+1.35VGS_PGOOD RG83 1 2 0_0402_5% GPU_ALL_PGOOD

[50] +1.35VGS_PGOOD GPU_ALL_PGOOD [11]
Only For N16S-GT(GB2B-64)

B B

A A

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DGPU_DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 24 of 53
5 4 3 2 1
 1 2 3 4 5

Memory Partition A - Upper 32 bits [64..32]

A A
UV7 @ UV6 @
+VREFC_UV7 FBA_D52 [23] FBA_D[32..63] +VREFC_UV7 FBA_D35
M8 E3 M8 E3
+VREFD_UV7 H1 VREFCA DQ0 F7 FBA_D49 +VREFD_UV7 H1 VREFCA DQ0 F7 FBA_D37
VREFDQ DQ1 FBA_D53 [23] DQMA[7..4] VREFDQ DQ1 FBA_D34
F2 F2
FBA_CMD9 N3 DQ2 F8 FBA_D50 FBA_CMD9 N3 DQ2 F8 FBA_D39
FBA_CMD11 A0 DQ3 FBA_D54 [23] FBA_DQSP[7..4] FBA_CMD11 A0 DQ3 FBA_D33
P7 H3 P7 H3
FBA_CMD8 P3 A1 DQ4 H8 FBA_D48 FBA_CMD8 P3 A1 DQ4 H8 FBA_D38
FBA_CMD25 A2 DQ5 FBA_D55 [23] FBA_DQSN[7..4] FBA_CMD25 A2 DQ5 FBA_D32
N2 G2 N2 G2
FBA_CMD10 P8 A3 DQ6 H7 FBA_D51 FBA_CMD10 P8 A3 DQ6 H7 FBA_D36
FBA_CMD24 A4 DQ7 [23,26] FBA_CMD[0..30] FBA_CMD24 A4 DQ7
P2 P2
FBA_CMD22 R8 A5 FBA_CMD22 R8 A5
FBA_CMD7 R2 A6 D7 FBA_D44 FBA_CMD7 R2 A6 D7 FBA_D56
FBA_CMD21 T8 A7 DQ8 C3 FBA_D40 FBA_CMD21 T8 A7 DQ8 C3 FBA_D60
FBA_CMD6 R3 A8 DQ9 C8 FBA_D46 FBA_CMD6 R3 A8 DQ9 C8 FBA_D58
FBA_CMD29 L7 A9 DQ10 C2 FBA_D41 FBA_CMD29 L7 A9 DQ10 C2 FBA_D61
FBA_CMD23 R7 A10/AP DQ11 A7 FBA_D45 FBA_CMD23 R7 A10/AP DQ11 A7 FBA_D57
FBA_CMD28 N7 A11 DQ12 A2 FBA_D43 FBA_CMD28 N7 A11 DQ12 A2 FBA_D63
FBA_CMD20 T3 A12/BC# DQ13 B8 FBA_D47 FBA_CMD20 T3 A12/BC# DQ13 B8 FBA_D59
FBA_CMD4 T7 A13 DQ14 A3 FBA_D42 FBA_CMD4 T7 A13 DQ14 A3 FBA_D62
FBA_CMD14 M7 A14 DQ15 FBA_CMD14 M7 A14 DQ15
A15/NC +1.35VS_VRAM A15/NC +1.35VS_VRAM
FBA_CMD12
1.35V FBA_CMD12
1.35V
M2 B2 M2 B2
FBA_CMD27 N8 BA0 VDD D9 FBA_CMD27 N8 BA0 VDD D9
Place close to Vram

1U_0402_6.3V6K

1U_0402_6.3V6K
BA1 VDD BA1 VDD

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
FBA_CMD26 M3 G7 FBA_CMD26 M3 G7

DIS@ CV100

DIS@ CV101

DIS@ CV102

DIS@ CV112

DIS@ CV113

DIS@ CV114
BA2 VDD 1 1 1 BA2 VDD 1 1 1
K2 K2
CLKA1 VDD K8 VDD K8
VDD N1 VDD N1
VDD VDD
1

CLKA1 J7 N9 2 2 2 CLKA1 J7 N9 2 2 2
RV2723
[23] CLKA1
CLKA1# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST CLKA1# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST
162_0402_1%
[23] CLKA1# CK# VDD R9 TO THE MEMORY DEVICES CK# VDD R9 TO THE MEMORY DEVICES
DIS@ VDD VDD
FBA_CMD19 K9 FBA_CMD19 K9
PLACE LARGER CAPACITORS PLACE LARGER CAPACITORS
2

B
CLKA1# J9 CKE0 A1 J9 CKE0 A1 B
FBA_CMD18 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY FBA_CMD18 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY
J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
FBA_CMD16 L2 ODT1/NC VDDQ C9 FBA_CMD16 L2 ODT1/NC VDDQ C9
L1 CS0# VDDQ D2 L1 CS0# VDDQ D2
CS1#/NC VDDQ E9 +1.35VS_VRAM CS1#/NC VDDQ E9 +1.35VS_VRAM
VDDQ F1 VDDQ F1
FBA_CMD30 J3 VDDQ H2 FBA_CMD30 J3 VDDQ H2
FBA_CMD15 RAS# VDDQ 1.35V FBA_CMD15 RAS# VDDQ 1.35V
K3 H9 K3 H9
FBA_CMD13 L3 CAS# VDDQ FBA_CMD13 L3 CAS# VDDQ
WE# WE#

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
A9 A9

DIS@ CV96

DIS@ CV97
DIS@ CV95

DIS@ CV98

DIS@ CV99

DIS@ CV92

DIS@ CV93
DIS@ CV116

DIS@ CV111
DIS@ CV103

DIS@ CV115

DIS@ CV108
DIS@ CV104

DIS@ CV107

DIS@ CV109

DIS@ CV110
FBA_DQSP6 VSS 1 1 1 1 1 1 1 1 FBA_DQSP4 VSS 1 1 1 1 1 1 1 1
F3 B3 F3 B3
FBA_DQSP5 C7 LDQS VSS E1 FBA_DQSP7 C7 LDQS VSS E1
UDQS VSS G8 UDQS VSS G8
VSS J2 2 2 2 2 2 2 2 2 VSS J2 2 2 2 2 2 2 2 2
FBA_DQSN6 G3 VSS J8 FBA_DQSN4 G3 VSS J8
FBA_DQSN5 B7 LDQS# VSS M1 FBA_DQSN7 B7 LDQS# VSS M1
UDQS# VSS M9 UDQS# VSS M9
VSS P1 VSS P1
DQMA6 E7 VSS P9 DQMA4 E7 VSS P9
DQMA5 D3 LDM VSS T1 DQMA7 D3 LDM VSS T1
UDM VSS T9 UDM VSS T9
VSS VSS

FBA_CMD5 T2 B1 FBA_CMD5 T2 B1
RESET# VSSQ B9 RESET# VSSQ B9
VSSQ D1 VSSQ D1
VSSQ D8 VSSQ D8
RV27201 DIS@ 2 243_0402_1% L8 VSSQ E2 RV27211 DIS@ 2 243_0402_1% L8 VSSQ E2
ZQ0 VSSQ E8 ZQ0 VSSQ E8
L9 VSSQ F9 L9 VSSQ F9
ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
C C
96-BALL 96-BALL
SDRAM DDR3L SDRAM DDR3L
H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96

+1.35VS_VRAM +1.35VS_VRAM
1

RV2722 RV2718
1.33K_0402_1% 1.33K_0402_1%
DIS@ DIS@
2

+VREFC_UV7 +VREFD_UV7
1
1

1 1
RV2719 CV293 RV2724 CV292
1.33K_0402_1% 0.01U_0402_16V7K 1.33K_0402_1% 0.01U_0402_16V7K
DIS@ DIS@ DIS@ DIS@
2 2
2
2

D D

Security Classification
2011/07/15
Compal Secret Data
2012/07/15 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3_A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-D471P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 25 of 53

1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Lower 32 bits [31..0]

[23] FBA_D[0..31]
UV5 @
UV4 @
+VREFC_UV5 FBA_D12 [23] DQMA[3..0]
A M8 E3 A
+VREFD_UV5 H1 VREFCA DQ0 F7 FBA_D8 +VREFC_UV5 M8 E3 FBA_D4
VREFDQ DQ1 FBA_D13 [23] FBA_DQSP[3..0] +VREFD_UV5 VREFCA DQ0 FBA_D1
F2 H1 F7
FBA_CMD9 N3 DQ2 F8 FBA_D10 VREFDQ DQ1 F2 FBA_D5
FBA_CMD11 A0 DQ3 FBA_D14 [23] FBA_DQSN[3..0] FBA_CMD9 DQ2 FBA_D0
P7 H3 N3 F8
FBA_CMD8 P3 A1 DQ4 H8 FBA_D11 FBA_CMD11 P7 A0 DQ3 H3 FBA_D6
FBA_CMD25 A2 DQ5 FBA_D15 [23,25] FBA_CMD[0..30] FBA_CMD8 A1 DQ4 FBA_D2
N2 G2 P3 H8
FBA_CMD10 P8 A3 DQ6 H7 FBA_D9 FBA_CMD25 N2 A2 DQ5 G2 FBA_D7
FBA_CMD24 P2 A4 DQ7 FBA_CMD10 P8 A3 DQ6 H7 FBA_D3
FBA_CMD22 R8 A5 FBA_CMD24 P2 A4 DQ7
FBA_CMD7 R2 A6 D7 FBA_D16 FBA_CMD22 R8 A5
FBA_CMD21 T8 A7 DQ8 C3 FBA_D20 FBA_CMD7 R2 A6 D7 FBA_D31
FBA_CMD6 R3 A8 DQ9 C8 FBA_D23 FBA_CMD21 T8 A7 DQ8 C3 FBA_D27
FBA_CMD29 L7 A9 DQ10 C2 FBA_D19 FBA_CMD6 R3 A8 DQ9 C8 FBA_D30
FBA_CMD23 R7 A10/AP DQ11 A7 FBA_D17 FBA_CMD29 L7 A9 DQ10 C2 FBA_D25
FBA_CMD28 N7 A11 DQ12 A2 FBA_D18 FBA_CMD23 R7 A10/AP DQ11 A7 FBA_D28
FBA_CMD20 T3 A12/BC# DQ13 B8 FBA_D22 FBA_CMD28 N7 A11 DQ12 A2 FBA_D26
FBA_CMD4 T7 A13 DQ14 A3 FBA_D21 FBA_CMD20 T3 A12/BC# DQ13 B8 FBA_D29
FBA_CMD14 M7 A14 DQ15 FBA_CMD4 T7 A13 DQ14 A3 FBA_D24
A15/NC +1.35VS_VRAM FBA_CMD14 M7 A14 DQ15
A15/NC +1.35VS_VRAM
FBA_CMD12
1.35V
M2 B2 1.35V
FBA_CMD27 N8 BA0 VDD D9 FBA_CMD12 M2 B2

1U_0402_6.3V6K
BA1 VDD BA0 VDD

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
FBA_CMD26 M3 G7 FBA_CMD27 N8 D9

DIS@ CV296

DIS@ CV295

DIS@ CV308
1 1 1

1U_0402_6.3V6K
BA2 VDD BA1 VDD

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
K2 FBA_CMD26 M3 G7

DIS@ CV88

DIS@ CV89

DIS@ CV302
VDD BA2 VDD 1 1 1
K8 K2
VDD N1 VDD K8
CLKA0 J7 VDD N9 2 2 2 VDD N1
[23] CLKA0
K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST J7 VDD N9 2 2 2
CLKA0# CLKA0 PLACE 0.1uF CAPS CLOSEST
[23] CLKA0# CK# VDD R9 TO THE MEMORY DEVICES CLKA0# K7 CK VDD R1
VDD CK# VDD R9 TO THE MEMORY DEVICES
FBA_CMD3 K9 VDD
CKE0 PLACE LARGER CAPACITORS FBA_CMD3
J9 A1 K9 PLACE LARGER CAPACITORS
FBA_CMD2 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY J9 CKE0 A1
J1 ODT0 VDDQ C1 FBA_CMD2 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY
B FBA_CMD0 L2 ODT1/NC VDDQ C9 J1 ODT0 VDDQ C1 B
L1 CS0# VDDQ D2 FBA_CMD0 L2 ODT1/NC VDDQ C9
CS1#/NC VDDQ E9 +1.35VS_VRAM L1 CS0# VDDQ D2
VDDQ F1 CS1#/NC VDDQ E9 +1.35VS_VRAM
FBA_CMD30 J3 VDDQ H2 VDDQ F1
FBA_CMD15 RAS# VDDQ 1.35V FBA_CMD30 VDDQ
K3 H9 J3 H2 1.35V
FBA_CMD13 L3 CAS# VDDQ FBA_CMD15 K3 RAS# VDDQ H9
WE# FBA_CMD13 L3 CAS# VDDQ

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

10U_0603_6.3V6M
WE#

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
A9

DIS@ CV84

DIS@ CV85

DIS@ CV294

DIS@ CV300
DIS@ CV305

DIS@ CV307

DIS@ CV297

DIS@ CV301
1 1 1 1 1 1 1 1

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSS

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
FBA_DQSP1 F3 B3 A9

DIS@ CV90

DIS@ CV91

DIS@ CV68
DIS@ CV86

DIS@ CV87

DIS@ CV306

DIS@ CV304

DIS@ CV298
FBA_DQSP2 LDQS VSS FBA_DQSP0 VSS 1 1 1 1 1 1 1 1
C7 E1 F3 B3
UDQS VSS G8 FBA_DQSP3 C7 LDQS VSS E1
VSS J2 2 2 2 2 2 2 2 2 UDQS VSS G8
FBA_DQSN1 G3 VSS J8 VSS J2 2 2 2 2 2 2 2 2
FBA_DQSN2 B7 LDQS# VSS M1 FBA_DQSN0 G3 VSS J8
UDQS# VSS M9 FBA_DQSN3 B7 LDQS# VSS M1
VSS P1 UDQS# VSS M9
DQMA1 E7 VSS P9 VSS P1
DQMA2 D3 LDM VSS T1 DQMA0 E7 VSS P9
UDM VSS T9 DQMA3 D3 LDM VSS T1
VSS UDM VSS T9
VSS
FBA_CMD5 T2 B1
RESET# VSSQ B9 FBA_CMD5 T2 B1
VSSQ D1 RESET# VSSQ B9
VSSQ D8 VSSQ D1
RV27291 DIS@ 2 243_0402_1% L8 VSSQ E2 VSSQ D8 +1.35VS_VRAM
ZQ0 VSSQ E8 RV27311 DIS@ 2 243_0402_1% L8 VSSQ E2
L9 VSSQ F9 ZQ0 VSSQ E8
ZQ1/NC VSSQ G1 L9 VSSQ F9
VSSQ ZQ1/NC VSSQ

1
G9 G1
VSSQ VSSQ G9 RV2730
96-BALL VSSQ 1.33K_0402_1%
SDRAM DDR3L 96-BALL DIS@
C H5TC4G63AFR-11C_FBGA96 SDRAM DDR3L C

2
H5TC4G63AFR-11C_FBGA96 +VREFD_UV5

+1.35VS_VRAM

1
1
RV2728 CV299
1.33K_0402_1% 0.01U_0402_16V7K

1
DIS@ DIS@
RV2727 2
Place close to Vram

2
1.33K_0402_1%
CLKA0 DIS@

2
1

+VREFC_UV5
RV2725
162_0402_1%

1
DIS@ 1
RV2726 CV303
2

CLKA0# 1.33K_0402_1% 0.01U_0402_16V7K

DIS@ DIS@
2

2
D D

Security Classification
2011/07/15
Compal Secret Data
2012/07/15 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3_A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-D471P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 26 of 53

1 2 3 4 5
 5 4 3 2 1

+3VS Camera +3VS_CMOS

W=60mils
+3VS
LCD Power Circuit +LCDVDD_CONN
W=20mils R312 1 2 0_0603_5%
W=20mils
D D
W=60mils U5 1 1
5 1 +LCDVDD R311 1 2 0_0805_5%

4.7U_0603_6.3V6K
IN OUT Q4 @ C129 CMOS@ C130 CMOS@
2 ME2301DC-G_SOT23-3 0.1U_0201_10V K X5R 10U_0603_6.3V6M

C128
GND 1 2 2
1

D
C1220 4 3 3 1
1U_0402_6.3V6K EN OC
@ G5016KD1U SOT23 2
2

G
2
R119 @
[6] PCH_ENVDD
150K_0402_5%
CMOS_ON#_R
CMOS_ON#

1
1
R120
100K_0402_5% C132 @
0.1U_0201_10V K X5R

2
2

+3VS

@
eDP CONN.

5
U15
2 +LEDVDD
From PCH

P
[6] ENBKL B B+
4 DISPOFF#
1 Y W=100mils
From EC [35] BKOFF# A

G
C R121 2 1 0_0805_5% C

2
1

3
2

R124 @
R211 TC7SH08FUF_SSOP5 100K_0402_5% C133
100K_0402_5% 4.7U_0805_25V6-K
@ 2

1
1

JEDP1
R123 1 2 0_0402_5% 1
2 1
3 2
4 3
[6] INVPWM 4
DISPOFF# 5
EDP_HPD_R 6 5
W=60mils 7 6
+LCDVDD_CONN 7
8
9 8
R126 1 2 0_0402_5% EDP_HPD_R C134 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 10 9
[6] EDP_HPD [6] EDP_AUXN EDP_AUXP_C 10
C135 1 2 0.1U_0201_10V K X5R 11
eDP [6] EDP_AUXP
1

C136 1 2 0.1U_0201_10V K X5R EDP_TXP0_C 12 11

[6] EDP_TXP0 EDP_TXN0_C 12
C137 1 2 0.1U_0201_10V K X5R 13
[6] EDP_TXN0 14 13
R128
100K_0402_5% C138 1 2 0.1U_0201_10V K X5R EDP_TXP1_C 15 14
[6] EDP_TXP1 EDP_TXN1_C 15
C139 1 2 0.1U_0201_10V K X5R 16
[6] EDP_TXN1
2

17 16
C141 1UHD@2 0.1U_0201_10V K X5R EDP_TXP2_C 18 17
[6] EDP_TXP2 EDP_TXN2_C 18
C140 1UHD@2 0.1U_0201_10V K X5R 19
[6] EDP_TXN2 19
20
C142 1UHD@2 0.1U_0201_10V K X5R EDP_TXP3_C 21 20
[6] EDP_TXP3 EDP_TXN3_C 21
C143 1UHD@2 0.1U_0201_10V K X5R 22
[6] EDP_TXN3 22
23
EMI [36] SENSE_SDA_R
[36] SENSE_SCL_R
+3VALW
24
25
26
23
24
25
LID_SW# 27 26
Sensor BD TAB_SW#
28 27
USB20_N5_R +3VS USB20_P5_R 28
R125 1 2 0_0402_5% 29
[12] USB20_N5 USB20_N5_R 29
Camera W=20mils 30
B
31 30 B
Camera R127 1 2 0_0402_5% USB20_P5_R +3VS_CMOS
32 31
[12] USB20_P5 DMIC_CLK 32
DMIC 33
DMIC_DAT 34 33
+3VS 34
+3VS 35
R122 1 2 0_0402_5% TS_RST# 36 35 41
[35] TS_DISABLE# 37 36 G1 42
[6] TS_I2C_RST# 37 G2
Touch Screen 38 43
[11] I2C1_SCL_TS 39 38 G3 44
[11] I2C1_SDA_TS 39 G4
40 45
[6] TS_INT# 40 G5

EMI ACES_50398-04041-001
ME@
SP010013I00

10P_0402_50V8J
@EMI@
1

C1211
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP / Camera
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 27 of 53
5 4 3 2 1
 5 4 3 2 1

EMI
Near JHDMI1

EMI@
EMI
CH229 1 2 0.1U_0201_10V K X5R HDMI_CLK+_CK_C R326 1 2 8.2_0402_1%HDMI_CLK+_CONN HDMI_CLK+_CONN R327 1 EMI@ 2 HDMI_CLK-_CONN
[6] HDMI_CLK+_CK
300_0402_5%

CH230 1 2 0.1U_0201_10V K X5R HDMI_CLK-_CK_C R330 1 2 8.2_0402_1%HDMI_CLK-_CONN HDMI_TX0+_CONN R328 1 EMI@ 2 HDMI_TX0-_CONN
[6] HDMI_CLK-_CK
EMI@ 300_0402_5%
HDMI_TX1+_CONN R329 1 EMI@ 2 HDMI_TX1-_CONN
300_0402_5%
+5V_Display
HDMI_TX2+_CONN R331 1 EMI@ 2 HDMI_TX2-_CONN UH6
D D
300_0402_5%
+5VS 3
EMI@ OUT W=40mils
HDMI_TX0+_CK_C 1
CH231 1 2 0.1U_0201_10V K X5R R332 1 2 8.2_0402_1%HDMI_TX0+_CONN 1
[6] HDMI_TX0+_CK IN
1 CH140
@ 2 0.1U_0201_10V K X5R
CH232 1 2 0.1U_0201_10V K X5R HDMI_TX0-_CK_C R333 1 2 8.2_0402_1%HDMI_TX0-_CONN CH141 GND 2
[6] HDMI_TX0-_CK
EMI@ 0.1U_0201_10V K X5R
2 G5250Q1T73U_SC59-3

For HDMI

EMI@
CH233 1 2 0.1U_0201_10V K X5R HDMI_TX1+_CK_C R334 1 2 8.2_0402_1%HDMI_TX1+_CONN JHDMI1
[6] HDMI_TX1+_CK
+5V_Display 19
HDMI_DET 1 +5V Power
CH234 1 2 0.1U_0201_10V K X5R HDMI_TX1-_CK_C R335 1 HDMI_TX1-_CONN
2 8.2_0402_1% HDMI_TX2+_CONN 3 HPD
[6] HDMI_TX1-_CK TMDS D2+
EMI@ 4
HDMI_TX2-_CONN 5 TMDS D2 Shield
HDMI_TX1+_CONN 6 TMDS D2-
7 TMDS D1+
HDMI_TX1-_CONN 8 TMDS D1 Shield
HDMI_TX0+_CONN 9 TMDS D1-
+3VS 10 TMDS D0+
HDMI_TX0-_CONN 11 TMDS D0 Shield
EMI@ HDMI_CLK+_CONN 12 TMDS D0-
CH235 1 2 0.1U_0201_10V K X5R HDMI_TX2+_CK_C R336 1 2 8.2_0402_1%HDMI_TX2+_CONN 13 TMDS CLK+
[6] HDMI_TX2+_CK TMDS CLK Shield

2
HDMI_CLK-_CONN 14
RH133 15 TMDS CLK-
CH236 1 2 0.1U_0201_10V K X5R HDMI_TX2-_CK_C R337 1 2 8.2_0402_1%HDMI_TX2-_CONN 1M_0402_5% 16 CEC 20
[6] HDMI_TX2-_CK HDMICLK_R DDC/CEC GND GND
EMI@ QH5 17 21
SCL GND

2
HDMIDAT_R

G
2N7002K_SOT23-3 18 22

1
2 SDA GND 23
3 1 HDMI_DET Utility GND
[6] TMDS_B_HPD
SINGA_2HE2016-100211F

D
C C

2
ME@
RH137 SP011506241
20K_0402_5%
RPH29

1
5 4
6 3
7 2
8 1

470 +-5% 8P4R

RPH30
8 1
7 2
6 3
5 4

470 +-5% 8P4R +3VS

1

D
2
G
S QH7
3

2N7002K_SOT23-3

+3VS +3VS +5V_Display

ESD
@ESD@ DH1 @ESD@ DH2 @ESD@ DH3
HDMI_DET 9 10 HDMI_DET HDMI_TX1-_CONN HDMI_TX1-_CONN HDMI_TX2+_CONN HDMI_TX2+_CONN
1 1 9 10 1 1 9 10 1 1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
2

B B
2

+5V_Display +5V_Display HDMI_TX1+_CONN HDMI_TX1+_CONN HDMI_TX2-_CONN HDMI_TX2-_CONN

8 9 2 2 8 9 2 2 8 9 2 2
G
RH144

RH143

RH145

RH146

HDMIDAT_R HDMIDAT_R HDMI_CLK-_CONN HDMI_CLK-_CONN HDMI_TX0+_CONN HDMI_TX0+_CONN

QH6A 7 7 4 4 7 7 4 4 7 7 4 4
1

HDMICLK_R HDMICLK_R HDMICLK_R HDMI_CLK+_CONN HDMI_CLK+_CONN HDMI_TX0-_CONN HDMI_TX0-_CONN

1 6 6 6 5 5 6 6 5 5 6 6 5 5
S

[6] HDMICLK_NB
D

2N7002KDW_SOT363-6 3 3 3 3 3 3
5

8 8 8
G

QH6B
L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD
4 3 HDMIDAT_R
S

[6] HDMIDAT_NB
D

2N7002KDW_SOT363-6

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title
HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 28 of 53
5 4 3 2 1
 A B C D E

+5VS
ALC3240 +5VS_PVDD RA1 1 2 0_0805_5% Input

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
+3VDD_CODEC
2 1 2 1
+1.8VS

CA3
CA1

CA2
CA32
1 2 1 2
2 place close audio codec
CA17
4.7U_0603_6.3V6K +3VDD_CODEC
1
@
Combo Jack

2
29

34
39
1
UA1
RA38 (Normal Open)

PVDD1
PVDD2
CPVDD
DVDD
33_0402_5% 2 1 RA12 HDA_SDIN0_AUDIO 7 100K_0402_5%
1 [9] HDA_SDIN0 SDATA-IN HP_OUTL 1
4 25
[9] HDA_SDOUT_AUDIO Headphone

1
SDATA-OUT HPOUT-L(PORT-I-L) 26 HP_OUTR PLUG_IN_R RA13 1 2 200K_0402_1%~N
HPOUT-R(PORT-I-R) PLUG_IN [34]

EMI PC_BEEP 11
PCBEEP
VREF
22
CA27 1 2 1U_0402_6.3V6K
AGND
5 27 CPVEE 2 1 SM010016720
Place RA10 & CA12 on AGND moat[9]
22P_0402_50V8J @EMI@ CA12
HDA_BITCLK_AUDIO
33_0402_5% 2 @EMI@ 1 RA10
BCLK CPVEE
CA20 1U_0402_6.3V6K EXT_MIC_SLEEVE EMI@
SM010016720
RA19 2 1 FBMA-L11-160808-121LMT 0603
EMI HGNDB
W=40mils EXT_MIC_RING2 HGNDB [34]
W=40mils EMI@ RA20 2 1 FBMA-L11-160808-121LMT 0603 HGNDA HGNDA [34]
RA6 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R HP_OUTL EMI@ RA22 1 2 47_0402_5% HPOUT_L

wide 40MIL 1 2 2.2K_0402_5% EXT_MIC_SLEEVE 14 MIC2-L(PORT-F-L)/RING

MIC2-R(PORT-F-R)/SLEEVE
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
18 LINE1-L
EMI HP_OUTR EMI@ RA23 1 2 47_0402_5% HPOUT_R HPOUT_L
HPOUT_R
AGND

RA7 CA19 2 1 2.2U_0402_6.3V6M 15 24

+LINE1-VREFO-R SD028470A80
23 MIC2-CAP LINE1-VREFO-L 12 PLUG_IN_R SD028470A80
+MIC2-VREFO MIC2-VREFO HP/ LINE1-JD(JD1) SM01000BV00
SPK_L2+ 35 2 DMIC_DAT_R 0_0402_5% 2 1 RA14
External DMIC

CA33 @EMI@

CA34 @EMI@

CA35 @EMI@

CA36 @EMI@
For Universal Audio Jack

470P_0402_50V7K

470P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
SPK-OUT-LP GPIO0/DMIC-DATA12

2
SPK_L1- 36 3 DMIC_CLK_R 220_0402_5% 2 1 LA1 DMIC_DAT
SPK-OUT-LN GPIO1/DMIC-CLK 1 1

2
SPK_R1- 37 EMI@ DMIC_CLK LINE1-L CA21 2 1 1U_0402_6.3V6K

RA26

RA27
10K_0402_5%

10K_0402_5%
SPK_R2+ 38 SPK-OUT-RN 8 @ @
SPK-OUT-RP DVDD-IO +IOVDD_CODEC
AGND AGND

LINE1-R CA22 2 1 1U_0402_6.3V6K

1
2.2U_0402_6.3V6M 1 2 CA26 2 2
1

1
LDO1 21 28
2.2U_0402_6.3V6M 1 2 CA16 LDO2 32 LDO1-CAP CBN 30 CA15
LDO3 6 LDO2-CAP CBP RA29 1 2 4.7K_0402_5% AGND AGND AGND AGND
LDO3-CAP 1U_0402_6.3V6K
2.2U_0402_6.3V6M 1 2 CA13 2
40 1 2 EC_MUTE# [35] +LINE1-VREFO-R RA32 1 2 4.7K_0402_5%
10 PDB 0_0402_5% RA11 2 1 AGND AGND

VD33STB
9 DC DET 41

AVDD1
AVDD2
AVSS1
AVSS2
[9] HDA_SYNC_AUDIO SYNC THERMAL PAD RA8 10K_0402_5%
@

20
33
19
31

16
2
Output 2

+5VDDA_CODEC
AGND +3VALW
+1.8VS EMI
RA5 1 2
SPEAK 4 ohm 40 M
IL
0_0402_5% SPEAK 8 ohm 20 M
IL
Place RA5 on AGND moat JSPK1
SPK_R1- LA5 1 2 0_0603_5% SPK_R1-_CONN 1
CA8 1 2 1U_0402_6.3V6K SPK_R2+ LA6 1 2 0_0603_5% SPK_R2+_CONN 2 1
AGND SPK_L1- SPK_L1-_CONN 2
LA7 1 2 0_0603_5% 3
SPK_L2+ LA8 1 2 0_0603_5% SPK_L2+_CONN 4 3
Place near Pin33 5 4
6 G1

1000P_0402_50V7K

1000P_0402_50V7K
1000P_0402_50V7K

1000P_0402_50V7K
G2
1 1 1 1 ACES_50224-00401-001
ME@

EMI@ CA29

EMI@ CA30
EMI@ CA28

EMI@ CA31
SP02000GC10

+5VS +5VDDA_CODEC Each PlaK or m Po wer Net Support Li st

2 2 2 2

+5VS +5VDDA_CODEC
+1.5VS +1.8VS +3VS +5VS +3VALW
ESD protection needs to be placed near connector side
RA4 2 1 0_0603_5% 1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5)
Intel Broadwell V X V V V ESD
0.1U_0201_10V K X5R

1 1
1U_0402_6.3V6K

Intel Skylake X V V V V
CA7
CA11

Place RA4 on AGND moat +5VS

2 2 @ESD@ DA3
SPK_R1-_CONN 6 3 SPK_L2+_CONN
I/O4 I/O2

3 3
5 2
AGND VDD GND

Place near Pin20

SPK_R2+_CONN 4 1 SPK_L1-_CONN
I/O3 I/O1

Each PlaK or m HDA Li nk Volt age Support ( Pi n 8) AZC099-04S.R7G_SOT23-6

3.3V 1.5V
Intel Broadwell V (default) V
Intel Skylake V (default) V

+3VS +I OVDD_CODEC +3VS +3VDD_CODEC PC Beep EMI

place close audio codec
+3VS +IOVDD_CODEC +3VS +3VDD_CODEC
RA40 1 2 47K_0402_5% BEEP_N CA37 2 1 1U_0402_6.3V6K PC_BEEP
EC Beep [35] BEEP#
RA42 1 2 0_0402_5%
RA41 1 2 47K_0402_5%
RA3 2 1 0_0603_5% RA2 2 1 0_0603_5% APU Beep [9] HDA_SPKR
100P_0402_50V8J
CA40 @ESD@

1 RA43 1 2 0_0402_5%
1U_0402_6.3V6K
0.1U_0201_10V K X5R

1
0.1U_0201_10V K X5R

1
CA4

CA5

1 RA39
27K_0402_5% EMI@ CA41 1 2 0.1U_0402_25V6
CA6

4 4
2
2

2
Place near Pin8
2

2 update from 4K7 to 27K EMI@ CA42 1 2 0.1U_0402_25V6

Place near Pin1

AGND GND AGND

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC3240
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 29 of 53
A B C D E
 A B C D E F G H

SSD

+3VS_SSD

1 1

R134 1 @ 2 0_0402_5%
NGFF_SSD_PEDET [12]

2
PCIE@
R133
10K_0402_5%

1
D
NGFF_SSD_PEDET# 2
G PCIE@
S QV32

3
2N7002K_SOT23-3

+3VS_SSD

+3VS_SSD

0.01U_0402_16V7K

0.1U_0201_10V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1
+3VS
NGFF_SSD_PEDET#

C1176

C1177

C1178

C1179
@ 2 @ 2
R17 1 2 0_0805_5% H : PCIE Interface
2 2
L :SATA Interface
Fellow 543016_SKL_U_Y_PDG_0_9
JSSD1
1 2
3 GND 3P3VAUX 4
2 2
5 GND 3P3VAUX 6
7 PERn3 NC 8
9 PERp3 NC 10
11 GND DAS/DSS# 12
13 PETn3 3P3VAUX 14
15 PETp3 3P3VAUX 16
17 GND 3P3VAUX 18
19 PERn2 3P3VAUX 20
21 PERp2 NC 22
23 GND NC 24
25 PETn2 NC 26
27 PETp2 NC 28
PCIE_PRX_DTX_N8 29 GND NC 30
[12] PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 31 PERn1 NC 32
[12] PCIE_PRX_DTX_P8 PERp1 NC
33 34
PCIE_PTX_C_DRX_N8 PCIE@ C2168 1 2 0.22U_0402_6.3V6K PCIE4_L2_TXN_CONN 35 GND NC 36
[12] PCIE_PTX_C_DRX_N8 PCIE_PTX_C_DRX_P8 PCIE4_L2_TXP_CONN PETn1 NC
PCIE@ C2169 1 2 0.22U_0402_6.3V6K 37 38
[12] PCIE_PTX_C_DRX_P8 PETp1 DEVSLP DEVSLP0 [12]
39 40
SATA@ C1277 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P7_C 41 GND NC 42
[12] SATA_PRX_DTX_P7 SATA_PRX_DTX_N7_C PERn0/SATA-B+ NC
[12] SATA_PRX_DTX_N7 SATA@ C1280 1 2 0.01U_0402_16V7K 43 44
45 PERp0/SATA-B- NC 46
SATA@ C1275 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N7_C 47 GND NC 48
[12] SATA_PTX_DRX_N7 SATA_PTX_DRX_P7_C PETn0/SATA-A- NC SSD_RST#
SATA@ C1276 1 2 0.01U_0402_16V7K 49 50 R166 1 2 0_0402_5%
PCI_RST# [10,19,31,34,35]
[12] SATA_PTX_DRX_P7 51 PETp0/SATA-A+ PERST# 52
CLK_PCIE_SSD# GND CLKREQ# SSDCLK_REQ# [10]
53 54
[10] CLK_PCIE_SSD# CLK_PCIE_SSD 55 REFCLKN PEWake# 56
[10] CLK_PCIE_SSD REFCLKP NC
57 58
GND NC

C1277
PCIE@ 0_0402_5% 59 60
NGFF_SSD_PEDET# 61 NC SUSCLK(32kHz) 62
C1280 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
PCIE@ 0_0402_5% 65 GND 3P3VAUX 66
67 GND 3P3VAUX
C1275 GND 68
3
PCIE@ 0.22U_0402_6.3V6K GND1 69 3
GND2
C1276 BELLW_80159-3221
PCIE@ 0.22U_0402_6.3V6K ME@
SP070018L00

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/TPM/APS/NFC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 30 of 53
A B C D E F G H
 A B C D E

1 1

+3VS +3VS_WLAN

NGFF for WLAN / BT(Key E) RWL153 1 2 0_0805_5%

+3VS_WLAN

JWLAN1
1 2 1 1 @
3 GND 3.3VAUX 4 CWL155 CWL156
[12] USB20_P7 USB_D+ 3.3VAUX
BT 5 6
[12] USB20_N7 7 USB_D- LED1# 8 4.7U_0603_6.3V6K 0.1U_0201_10V K X5R
9 GND PCM_CLK 10 2 2
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
2 2
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22 WL_UART_RX @
23 SDIO_WAKE# UART_RX RPWL1 Devic e
SDIO_RESET# 0_0804_8P4R_5%
1 8
UART0_TX [11]
2 7
WL_UART_TX UART0_RX [11]
24 3 6
25 UART_TX 26 WL_UART_CTS 4 5 UART0_RTS [11]
GND UART_CTS WL_UART_RTS UART0_CTS [11]
27 28
[12] PCIE_PTX_C_DRX_P6 29 PETP0 UART_RTS 30 1 2 0_0402_5%
RWL155
[12] PCIE_PTX_C_DRX_N6 PETN0 RESERVED EC_TX [35]
31 32 RWL156 1 2 0_0402_5%
GND RESERVED EC_RX [35]
33 34
[12] PCIE_PRX_DTX_P6 35 PERP0 RESERVED 36
WLAN [12] PCIE_PRX_DTX_N6
37 PERN0 COEX3 38
39 GND COEX2 40
[10] CLK_PCIE_WLAN REFCLKP0 COEX1 SUSCLK_R
41 42 RWL157 1 2 0_0402_5%
[10] CLK_PCIE_WLAN# REFCLKN0 SUSCLK WL_RST# SUSCLK [10]
43 44
RWL158 1 2 0_0402_5% WLANCLK_REQ#_R 45 GND PERST0# 46 BT_DISABLE_R RWL159 1 2 0_0402_5%
[10] WLANCLK_REQ# WAKE#_R CLKEQ0# W_DISABLE2# WLBT_OFF# [11]
[35] PCIE_WAKE# RWL162 1 @ 2 0_0402_5% 47 48 RWL161 1 2 0_0402_5%
49 PEWAKE0# W_DISABLE1# 50 WL_OFF#
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
Note: The real behavior of BT_DISABLE are
57 GND RESERVED 58 BT_DISABLE=LOW, BT=OFF
59 RSRVD/PERP1 RESERVED 60 BT_DISABLE=HIGH, BT=ON
61 RSRVD/PERN1 RESERVED 62
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
67 RESERVED 3.3VAUX
GND

69 68
MTG77 MTG76

CONCR_213EAAA32FA
ME@
3 3
SP070011I00

2
@
RWL507 RWL508 WL_RST# RWL164 1 2 0_0402_5%
PCI_RST# [10,19,30,34,35]
100K_0402_5% 100K_0402_5%

4 4

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF WLAN / BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 31 of 53
A B C D E
 5 4 3 2 1

D D

+3VS_DGPU_AON +3VS

2
2
Thermal Sensor EX_THM@
R186
R176
0_0402_5%
@

0_0402_5%

1
DDR VRAM
1

+3V_Thermal

+EC_VCCA +EC_VCCA
Close to UTS17
UTS17 EX_THM@

16.5K_0402_1%

16.5K_0402_1%
1

1
1 8 EC_SMB_CK2
1 VDD SCL EC_SMB_CK2 [8,22,35]
EX_THM@

RTS336

RTS337
CTS587 REMOTE1+ 2 7 EC_SMB_DA2
D+ SDA EC_SMB_DA2 [8,22,35]
2200P_0402_50V7K
2 REMOTE1- 3 6

2
D- ALERT#
C +3V_Thermal RTS335 1 2 4.7K_0402_5% 4 5 C
EX_THM@ T_CRIT# GND
[35] DDR_TEMP [35] VRAM_TEMP
NCT7718W_MSOP8

1
RTS338 RTS339
SMB Address: 1001100x 100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K
REMOTE1+/-:
Trace width/space:10/10 mil

2
Trace length:<8"
ECAGND ECAGND

REMOTE1+
Close to VRAM
1
1

C
@ CTS588 2 QTS1 @
100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 E
3

REMOTE1-

CPU VGA NGFF Shielding Clip

H1 H2 H3 H14 H18 H5
Larger
B B
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA CLIP1 CLIP10 CLIP11 CLIP13
HOLEA HOLEA HOLEA HOLEA

1
1

1
@ @ @ @

1
1

1
+5VS H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P4

JFAN1
RF168 2 1 0_0603_5% +5VS_FAN1 1
2 1
Smaller
EC_FAN_SPEED1 2
[35] EC_FAN_PWM1 3 H8 H16 H20 H17 H21 H24 H6 H9 CLIP2 CLIP3 CLIP5 CLIP6 CLIP7 CLIP8 CLIP9 CLIP12
4 3 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
5 4
2 G1
6
CF162 G2 @ @ @ @ @ @ @ @

1
1

1
1

1
1

1
1
10U_0603_6.3V6M ACES_50224-00401-001
1 ME@
SP02000GC10
H_3P6 H_2P5 H_2P5 H_2P7 H_3P3 H_3P3 H_3P6X4P5 H_3P6X4P5

CLIP14 CLIP15 CLIP16

HOLEA HOLEA HOLEA
H23 H26
HOLEA HOLEA
FD1 FD2 FD3 FD4 @ @ @

1
1
1
1

1
1

1
+5VS H_2P5N H_2P8X2P5N

JFAN2
RF169 2 1 0_0603_5% +5VS_FAN2 1
2 1
EC_FAN_SPEED2 2
A [35] EC_FAN_PWM2 3 A
4 3
5 4
2 G1
6
CF163 G2
10U_0603_6.3V6M ACES_50224-00401-001
1 ME@
SP02000GC10

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title
FAN / Thermal Senser
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 32 of 53
5 4 3 2 1
Power But t on LE D Keyboard
KSI[0..7]
KSI[0..7] [35]
@ KSO[0..15]
KSO[0..15] [35]
R174
1 2 +VL
Power (White) 300_0402_5%

3
R173
PWR_LED# 1 2 1 2 +3VS JKB2
[35] PWR_LED# +3VLP
100_0402_5% JKB1
CAPS_LED#_R 1
LED2 R263 2 1 470_0402_5% CAPS_LED#_R 1 CAPS_LED# 2 1
LTW-110DC5-C_WHITE 2 1 KSO15 3 2
[35] CAPS_LED# 2 3
KSO15 3 KSO10 4
KSO10 4 3 KSO11 5 4
4 5

C1378
KSO11 5 KSO14 6
KSO14 6 5 KSO13 7 6
1 6 7
KSO13 7 KSO12 8
ESD@ KSO12 8 7 KSO3 9 8
8 9

0.1U_0201_10V K X5R
KSO3 9 KSO6 10
2 KSO6 10 9 KSO8 11 10
KSO8 11 10 KSO7 12 11
KSO7 12 11 KSO4 13 12
KSO4 13 12 KSO2 14 13
KSO2 14 13 KSI0 15 14
KSI0 15 14 KSO1 16 15
KSO1 16 15 KSO5 17 16
KSO5 17 16 KSI3 18 17
KSI3 18 17 KSI2 19 18
KSI2 19 18 KSO0 20 19
19 20

Touch Pad
KSO0 20 KSI5 21
KSI5 21 20 KSI4 22 21
KSI4 22 21 KSO9 23 22
KSO9 23 22 KSI6 24 23
KSI6 24 23 KSI7 25 24
KSI7 25 24 KSI1 26 25
KSI1 26 25 27 26
RTP258 1 2 0_0402_5% 27 26 28 27
+3VS 27 28
28 29
@ 29 28 30 29
CTP163 30 29 EC_GPIO72 31 30
0.1U_0201_10V K X5R EC_GPIO72 31 30 32 31
[35] EC_GPIO72 32 31 32
JTP1 32 33
8 33 GND 34
7 GND GND 34 GND
GND GND
TP_VCC 6
TP_CLK 5 6 ACES_51510-0320N-P01
[35] TP_CLK TP_DATA 5
4 ACES_51510-0320N-P01 SP011509010
[35] TP_DATA 3 4 SP011509010 ME@
RTP260 1 2 0_0402_5% TP_SMB_CLK 2 3 ME@
[8,18] PCH_SMB_CLK TP_SMB_DATA 2
RTP261 1 2 0_0402_5% 1
[8,18] PCH_SMB_DATA 1
ACES_88514-00601-071
ME@
SP010014M00
3

1 1
@ @ @ESD@
CTP164 CTP165 DTP5
100P_0402_50V8J 100P_0402_50V8J PSOT24C_SOT23-3
2 2

But t on
1

ESD

Keyboard Backlight
Power Bot t on +3VLP

2
+5VS +VCC_KB_LED
R170
+5VS +5VALW 100K_0402_5%
KBL@ SW6

1
QKBL121 JKBL1 TSS31-EG2-160-T18-S017_3P
1

1 1
1
S

KBL@ @ 3 1 2 2 ON/OFF#
3 2 3 ON/OFF#
RKBL1 RKBL2
10K_0402_5% 10K_0402_5% ME2301DC-G_SOT23-3 4 3
@ CKBL906

KBL@ CKBL908

G
G
G
G
10U_0603_6.3V6M

0.1U_0201_10V K X5R

4
G

1 2
2

7
6
5
4
2

5
1 RKBL3 2 GND 6
0_0402_5% GND
2 1
1
1 RKBL4 2 KBL@ CVILU_CF06041H0RB-NH
0_0402_5% CKBL907 ME@
0.01U_0402_16V7K SP01001FV00
2
1
OUT

2
2 +VCC_KB_LED
[35] KB_BL_PWM IN
ESD
GND

@ D24
QKBL122 L03ESDL5V0CC3-2_SOT23-3
DTC124EKAT146_SC59-3 JKBL2 ESD@
3

1
2 1
3 2
4 3
4
5
GND 6
GND

CVILU_CF06041H0RB-NH
ME@
SP01001FV00

Security Classification Compal Secret Data Compal Electronics, Inc.

2015/07/27 2016/07/27 Title
Issued Date Deciphered Date KBL/KBD/LED/TP/HS Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 33 of 53
 5 4 3 2 1

USB Charge ESD

ESD@ D6 ESD@ D7 ESD@ D8 ESD@ D9
+3VLP +5VALW_USBCH +5V_CHGUSB U3RXDN3 9 10 1 1U3RXDN3 U3RXDN2 9 10 1 1 U3RXDN2 U2DP3 3 6 U2DP2 3 6
I/O2 I/O4 I/O2 I/O4
U3RXDP3 8 9 2 2U3RXDP3 U3RXDP2 8 9 2 2 U3RXDP2

1
U3TXDN3 7 7 4 4U3TXDN3 U3TXDN2 7 7 4 4 U3TXDN2 2 5 +5V_CHGUSB 2 5 +USB3_VCCA
R118 GND VDD GND VDD

10K_0402_5%
R306 U3TXDP3 6 6 5 5U3TXDP3 U3TXDP2 6 6 5 5 U3TXDP2
10K_0402_5%
@ 3 3 3 3 1 4 U2DN3 1 4 U2DN2
80mil

2
U12 I/O1 I/O3 I/O1 I/O3
1 12 8 8
USB_CHG_STATUS# 9 IN OUT 10 USB20_CH_P3 AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
[35] USB_CHG_STATUS# STATUS# DP_IN 11 USB20_CH_N3
D
13 D
4 FAULT# DM_IN 2 USB20_N3 L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD
USB_CHG_EN ILIM_SEL DM_OUT 3 USB20_P3 USB20_N3 [12]
[35] USB_CHG_EN USB_CHG_CTL1
5
USB20_P3 [12]
USB3.0 With USB2.0 For Charge
6 EN DP_OUT 15 R183 1 @ 2 20K_0402_1%
USB_CHG_CTL1 USB_CHG_CTL2 CTL1 ILIM_LO 16
[35] USB_CHG_CTL2 7 R197 1 2 24.9_0402_1%

USB3.0_Port
USB_CHG_CTL3 8 CTL2 ILIM_HI 14
USB_CHG_CTL3
1
CTL3 GND 17
T-PAD EMI Add resistor

10K_0402_5%
2

470P_0402_50V7K
C194

100U_1206_6.3V6M

47U_0805_6.3V6M
PI5USB2546ZHEX TQFN 16P 1 1 1 Intel_PCH_USB2.0

R1659

C2174

C2175
0.1U_0201_10V K X5R
2

C198
@ L12 EMI@
1 4 U2DN2
2 2 2 [12] USB20_N2 1 4

1
2 3 U2DP2
[12] USB20_P2 2 3
+5VALW
MCM1012B900F06BP_4P

+VL

5
+5VALW_USBCH +5VALW L13 RF@
22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

47U_0805_6.3V6M

1 1 1 1 1 Intel_PCH_USB3.0 GND
C2172
C2177

C2173

C2171

C2178

4 6 U3RXDN2
2 2 2 2 2 [12] USB3_RX2_N 4 6
L59
1 R215 2 2 1 3 1

D
1
0_0603_5% BLM15PX331SN1D_2P Q28 3 1 U3RXDP2
1 [12] USB3_RX2_P 3 1
USB3.0 CONN

ME2301DC-G_SOT23-3
L60 C453 W=80mils
C454 2 1 4.7U_0603_6.3V6K Layout JUSB2 close HDMI

G
2
4.7U_0603_6.3V6K BLM15PX331SN1D_2P 2 +USB3_VCCA
2 GND
JUSB1

2
CMF-2012-2G45-32T_6P U3TXDP2 9
+VL 1 SSTX+
R130 U3TXDN2 8 VBUS
1 2 U2DP2 3 SSTX-
C D+ C
7
GND

5
100K_0402_5% L15 RF@ U2DN2 2 10
GND U3RXDP2 6 D- GND 11
@ C168 4 SSRX+ GND 12
1 GND GND 13

1
D
@ C90 0.1U_0201_10V K X5R U3RXDN2 5
1 R338 2 EC_ON_R 2 0.1U_0201_10V K X5R 1 2 U3TXDN2_L 4 6 U3TXDN2 SSRX- GND
[41] EC_ON [12] USB3_TX2_N 4 6
470K_0402_1% G Q29 C169 ACON_TARBA-9U1393
S 2N7002K_SOT23-3 2 0.1U_0201_10V K X5R ME@

3
1 2 U3TXDP2_L 3 1 U3TXDP2 DC231508280
[12] USB3_TX2_P 3 1
1 R339 2
[41] SPOK
0_0402_5%

2 GND
@

2
C457 CMF-2012-2G45-32T_6P
0.1U_0201_10V K X5R
1
Intel_PCH_USB2.0
W=80mils
USB20_CH_N3 1
L16 EMI@
4 U2DN3 +5V_CHGUSB
USB3.0 CONN (For Charge)
1 4 Layout JUSB2 close EDP
USB20_CH_P3 2 3 U2DP3 JUSB2
2 3 U3TXDP3 9
MCM1012B900F06BP_4P 1 SSTX+
U3TXDN3 8 VBUS
U2DP3 3 SSTX-
7 D+
GND

5
L17 RF@ U2DN3 2 10

IO Board FP GND U3RXDP3 6 D- GND 11

Intel_PCH_USB3.0 4 SSRX+ GND 12
U3RXDN3 5 GND GND 13
4 6 U3RXDN3 SSRX- GND

B
+3VLP
(For 15) [12]

[12]
USB3_RX3_N

USB3_RX3_P
3
4

3
6

1
1 U3RXDP3
ACON_TARBA-9U1393
ME@
DC231508280 B
2

GND
R172

2
100K_0402_5% CMF-2012-2G45-32T_6P
1

JIO1
28
27 GND JFP1
GND

5
26 1 L18 RF@
25 26 2 1 GND
[29] HGNDA 25 2
24 3 C172
23 24 4 3 0.1U_0201_10V K X5R
[29] HGNDB 23 4
MIC/HP 22 +3VS 5 1 2 U3TXDN3_L 4 6 U3TXDN3
22 5 [12] USB3_TX3_N 4 6
HPOUT_L 21 6 9 C173
21 [12] USB20_P8 6 G1 10
HPOUT_R 20 RC102 7 0.1U_0201_10V K X5R
20 [12] USB20_N8 7 G2
19 1 2 8 1 2 U3TXDP3_L 3 1 U3TXDP3
[29] PLUG_IN 19 8 [12] USB3_TX3_P 3 1
18
R237 2 1 0_0402_5%BATT_CHG_LED#_R 17 18 0_0603_5% ACES_51522-00801-001
[35] BATT_CHG_LED# 17
+3VLP
16 ME@
R236 2 1 0_0402_5%BATT_LOW_LED#_R 15 16 SP01001AE00 GND
BATT LED [35] BATT_LOW_LED#
14 15 2
Place TX AC coupling Cap (C168,169~171& 173). Close to connector

2
PCIE_CTX_C_DRX_P9 13 14 C2 CMF-2012-2G45-32T_6P
[12] PCIE_CTX_C_DRX_P9 PCIE_CTX_C_DRX_N9 13
[12] PCIE_CTX_C_DRX_N9 12 2.2U_0402_6.3V6M
11 12 1 FP@
PCIE_CRX_DTX_P9 10 11
[12] PCIE_CRX_DTX_P9 PCIE_CRX_DTX_N9 10
9 2A/Active Low+USB3_VCCA
[12] PCIE_CRX_DTX_N9 9 +5VALW
8
CardReader [10] CLK_PCIE_CR
CLK_PCIE_CR
CLK_PCIE_CR#
7
6
8
7 W=80mils U10
1
W=80mils
[10] CLK_PCIE_CR# 6 OUT
+3VS 5 5
4 5 IN 2
CRCLK_REQ# 3 4 D25 @ESD_FP@ USB_EN# 4 GND
[10] CRCLK_REQ# PCI_RST# 3 USB20_P8 [35] USB_EN# EN
[19,30,31,35] PCI_RST# 2 6 3 3
1 2 I/O4 I/O2 OCB
NOVO# 1 1
A
C196 SY6288D20AAC_SOT23-5 A
E-T_6712K-F26N-02L 0.1U_0201_10V K X5R 1
ME@ +5VALW
5 2 1
SP01001AN00 VDD GND 2 C178 + @
150U_D2_6.3VY_R17M C177
SGA00009100 470P_0402_50V7K
USB20_N8 4 1 2 2
I/O3 I/O1 FP module side
AZC099-04S.R7G_SOT23-6

Security Classification Compal Secret Data Compal Electronics, Inc.

AGND 2015/07/27 2016/07/27 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB2 / USB3 / FP / IO Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 34 of 53
5 4 3 2 1
 +3VLP +3VLP +5VALW

USB_EN# R194 1 2 10K_0402_5%

R189 1 2 0_0603_5% 1@
C179
+3VALW_EC 100P_0402_50V8J
1 1 1 1 2

0.1U_0201_10V K X5R
C180

0.1U_0201_10V K X5R
C181

1000P_0402_50V7K
C182

1000P_0402_50V7K
C183
L20
FBM-11-160808-601-T_0603
1 2 2 2 @ 2 @ 2 +EC_VCCA
+3VALW_EC +EC_VCCA
SM010016810 1 1
C185 @
C184

111
125
0.1U_0201_10V K X5R 1000P_0402_50V7K

22
33
96

67
9
1 2 2 ECAGND 2 U11
L21

VCC2
VCC3
VCC4
VCC1/LPC

VCC5/SPI

AVCC
VSBY
FBM-11-160808-601-T_0603
SM010016810
ECAGND
NOVO# 1 21
NOVO# GPIO85/GA20 GPIO15/A_PWM VCCST_PWRGD [10]
2 23 BEEP#
[8] KB_RST# GPIO86/KBRST# GPIO21/B_PWM BEEP# [29]

100P_0402_50V8J
CA48 @ESD@
3 PWM Output 26 1
[8] SERIRQ 4 SERIRQ/GPIOF0 GPIO32/D_PWM 27 EC_VCIN1_AC_BYPASS EC_FAN_PWM1 [32] +3VS
[8] LPC_FRAME# LFRAME#/GPIOF6 GPIO45/E_PWM
5
EMI
@EMI@ @EMI@
[8] LPC_AD3
[8] LPC_AD2
[8] LPC_AD1
7
8
10
LAD3/GPIOF4
LAD2/GPIOF3
LAD1/GPIOF2 GPIO90/AD0
63
64
VCIN1_BATT_TEMP [39,40]
2

2 1 R190 2 1 10_0402_1% [8] LPC_AD0 LAD0/GPIOF1 LPC & MISC GPIO91/AD1 65 VCIN1_BATT_DROP [41] TP_CLK R260 1 2 4.7K_0402_5%
GPIO92/AD2 ADP_I
C186 22P_0402_50V8J 12 AD Input 66
[8] CLK_LPC_EC 13 LCLK/GPIOF5 GPIO93/AD3 75 DCHG_I
[10,30,31,34] PCI_RST# EC_RST# LRESET#/GPIOF7 GPIO05/AD4 TS_detect [36]
1 2 37 76
+3VALW_EC R192 47K_0402_5% EC_SCI# 20 ECRST# GPIO04/AD5 VRAM_TEMP [32] TP_DATA R261 1 2 4.7K_0402_5%
[6,11] EC_SCI# SENSOR_EC_INT 38 GPIO54/ECSCI#
2 [11] SENSOR_EC_INT GPIO11/CLKRUN# TAB_SW#
68
GPIO94/DA0 70 TAB_SW#
C187
GPIO95/DA1 TS_DISABLE# [27] VCIN1_BATT_TEMP
0.1U_0402_25V6

ESD@

0.1U_0201_10V K X5R DA Output 71 1 2

DGPU_PWR_EN [24]
1

1 KSI0 55 GPIO96/DA2 72 C189 100P_0402_50V8J

56 KBSIN0/GPIOA0 GPIO97/DA3 USB_EN# [34] EC_VCIN1_AC_BYPASS 1 2
KSI1
KSI2 57 KBSIN1/GPIOA1 C190 100P_0402_50V8J
2

KBSIN2/GPIOA2 EC_SMB_CK3
C188

KSI3 58 83 R2017 1 @ 2 0_0402_5% 1 2

KBSIN3/GPIOA3 GPIO31/SCL3/PSCLK1 EC_SMB_DA3 I2C0_SCL_SEN [11,36]
KSI4 59 84 R2016 1 @ 2 0_0402_5% HID over I2C R203 @ 4.7K_0402_5%
KBSIN4/GPIOA4/N2TCK GPIO23/SDA3/PSDAT1 I2C0_SDA_SEN [11,36]
KSI5 60 85
61 KBSIN5/GPIOA5/N2TMS GPIO47/SCL4/PSCLK2 86 EC_SMB_CK4 [36]
KSI6 PS2 InterfaceGPIO53/SDA4/PSDAT2 SM bus to sensors
KBSIN6/GPIOA6 TP_CLK EC_SMB_DA4 [36] +3VS
KSI7 62 87
ESD KSO0
KSO1
KSO2
39
40
41
KBSIN7/GPIOA7
KBSOUT0/GPIOB0/SOUT_CR/JENK#
KBSOUT1/GPIOB1/TEST#
GPIO50/PSCLK3
GPIO52/PSDAT3
88 TP_DATA TP_CLK [33]
TP_DATA [33]
EC_SMB_CK3 1
RP1

8
KSO3 42 KBSOUT2/GP(I)OB2/TRIST# 97 EC_SMB_DA3 2 7
KBSOUT3/GP(I)OB3/XORTR# GPIO02 ENBKL [6] EC_SMB_CK4
KSO4 43 98 3 6
44 KBSOUT4/GPIOB4/SDP_VIS# GPIO75 99 SYS_PWROK [10] EC_SMB_DA4 4 5
KSO5 GPIO
KSO6
KSO7
KSO8
45
46
47
KBSOUT5/GPIOB5/TDO
KBSOUT6/GPIOB6/RDY#
KBSOUT7/GPIOB7 Int. K/B
GPIO76
VCIN1/GPIO16
109
ME_EN [9]
VCIN0_PH1 [39]
2.2K_0804_8P4R_5%
@
KBL_SELECT
KSO9 48 KBSOUT8/GPIOC0 Matrix 119
Funct i on KBL_ID
KSO[0..15] 49 KBSOUT9/GPIOC1 F_SDI&F_SDIO1/GPO80 120 EC_SPI_MISO [8]
KSO10 KBL 1
KSO[0..15] [33] KBSOUT10&P80_CLK/GPIOC2 F_SDIO&F_SDIO0/GPIOC6 EC_SPI_MOSI [8]
KSO11 50 126
KSI[0..7] KBSOUT11&P80_DAT/GPIOC3 F_CLK/GPIOC4 EC_SPI_CLK [8]
KSO12 51 SPI Flash ROM F_CS0#/GPIOC5 128
KSI[0..7] [33]
KSO13 52 KBSOUT12/GPIO64/TCK EC_SPI_CS0# [8] NO KBL 0
KSO14 53 KBSOUT13/GPIO63/TMS
KBSOUT14/GPIO62/TDI +3VALW
+3VALW_EC KSO15 54 73 +3VALW
KBSOUT15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM DDR_TEMP [32] EC_MUTE# +3VS
81 74 R198 1 @ 2 10K_0402_5%
GPIO60/KBSOUT16 GPIO07/AD7/CIRTX1 CMOS_ON#
R201 82 89
1 2 EC_SMB_CK1 GPIO57/KBSOUT17 GPIO67/N2TMS 90 EC_MUTE# [29]
GPIO51/N2TCK BATT_CHG_LED# [34]

1
2.2K_0402_5% 91
EC_SMB_CK1 77 GPIO36 92 CAPS_LED# [33]
R202 GPIO +3VALW R340 R324
EC_SMB_DA1 [39,40] EC_SMB_CK1 EC_SMB_DA1 GPIO17/SCL1/N2TCK GPIO40/F_PWM PWR_LED# [33]
1 2 78 93 10K_0402_5% 10K_0402_5%
[39,40] EC_SMB_DA1 EC_SMB_CK2 GPIO22/SDA1/N2TMS GPIO35 BATT_LOW_LED# [34]
2.2K_0402_5% 79 95 SYSON
[8,22,32] EC_SMB_CK2 EC_SMB_DA2 GPIO73/SCL2 GPIO06/IOX_DOUT +2.5V_EN SYSON [13,42] @ @
80 SM Bus 121
[8,22,32] EC_SMB_DA2 +2.5V_EN [42]

2
GPIO74/SDA2 GPIO81/F_WP#

2
127 EC_FAN_REVERSE KB_BL_PWM
GPIO84/IOX_SCLK

1
R1657
6 100 10K_0402_5% R325
[34] USB_CHG_STATUS# 14 GPIO24 GPIO26/RSMRST# 101 EC_RSMRST# [10]
USB_CHG_CTL1 EC_FAN_SPEED2 10K_0402_5%

1
15 GPIO10/LPCPD# GPIO20/TA2/IOX_DIO 102 EC_GPIO72
[10] EC_CLEAR_CMOS# GPIO65/SMI# VC_IN2/GPIO72 VCOUT1_PROCHOT# EC_GPIO72 [33] NOKBL@
16 103
USB_CHG_CTL3

2
17 GPIO34/1_WIRE/CIRRXL VC_OUT2/GPIO37 104
[34] USB_CHG_EN GPIO01/TB2 VC_OUT1/GPIO25 VCOUT0_MAIN_PWR_ON [41]
R179 18 GPIO 105 BKOFF#
1 2 [34] USB_CHG_CTL2 EC_PCIE_WAKE# 19 GPIO43 GPIO77 106 BKOFF# [27]
[31] PCIE_WAKE# GPIO42/CIRTX2 GPIO GPIO44 PM_SLP_S3# [10]
0_0402_5% 25 107
[33] KB_BL_PWM 28 GPIO13/C_PWM GPIO12 108 VR_PWRGD [46]
EC_FAN_SPEED1 VCIN1_AC_IN GPIO56/TA1 GPIO30/F_WP# VR_ON [46]

100P_0402_50V8J
CA46 ESD@
29 1
[40] VCIN1_AC_IN EC_TX GPIO14/TB1
30
[31] EC_TX EC_RX 31 GPIO83/SOUT_CR/P80_DATA 110 EC_VCIN1_AC_BYPASS @
[31] EC_RX PCH_PWROK GPIO87/SIN_CR/P80_CLK AC_IN/GPIO41/F_WP# EC_ON EC_VCIN1_AC_BYPASS [10,22]
32 112 R1664
[10,45] PCH_PWROK EC_FAN_PWM2 34 GPIO27/RSMRST# EC_ON/GPIO71 114 EC_ON [41] 2 1 2
GPIO ON/OFF# SUSP#
[32] EC_FAN_PWM2 GPIO66/G_PWM ON_OFFBTN#/GPIO70 LID_SW#
100P_0402_50V8J
CA49 ESD@

1 36 115
GPIO33/H_PWM GPO82/IOX_LDSH/LIDIN LID_SW#
1 R207 2 116 SUSP# 100K_0402_5%
GPIO46/CIRRXM/PLCIN 117 NUVOTON_VTT SUSP# [13,37,42]
10K_0402_5%
@ VTT 118 PECI 1 2
2 PBTN_OUT#
PECI PECI H_PECI [6]
122 R208 43_0402_1%
[10] PBTN_OUT# PM_SLP_S4# GPIO00/EXTCLK
Share ROM 123 124 +V18R R209 1 @ 2 0_0402_5% +3VALW_EC
[10,40,42] PM_SLP_S4# GPIO55/CLKOUT/IOX_DIO VCORF
C192
1
4.7U_0603_6.3V6K
AGND
GND4
GND5
GND3
GND1
GND2

VCOUT1_PROCHOT# R204 1 2 0_0402_5%

2
+3VALW
94
113
35

69
11
24

NPCE388NA1DX LQFP 128P KBC

R205 1 2 0_0402_5% H_PROCHOT# [6,40]
[46] VR_HOT#
ECAGND

R212 1
1 2 PCIE_WAKE# @
1K_0402_5%

R195
ESD 2
C191
47P_0402_50V8J

1 2 PBTN_OUT# SYSON
ESD 10K_0402_5%

C193
0.1U_0201_10V K X5R
1 @ESD@
@ESD@ 1
C197
0.1U_0201_10V K X5R
2 +1.0V_VCCST
2

NUVOTON_VTT R210 1 2 0_0402_5%

+3VS

1 2 EC_FAN_SPEED1
R214 10K_0402_5%
1 2 EC_FAN_SPEED2
R217 10K_0402_5%

1
R218
2 EC_FAN_REVERSE
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC NPCE388
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 35 of 53
 5 4 3 2 1

Sensor Hub +3VS_SEN

+3VS R16 1 2 0_0402_5%

+3VS_SEN
[11] ISH_I2C0_SCL
[11] ISH_I2C0_SDA SENSE_SCL
SENSE_SDA
R5216
R5215
R2109
R2110
1
1
1
1
@
@
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
SENSE_SCL_R
SENSE_SDA_R
[27]
[27]

1
+3VS_PLL R2015 1 @ 2 0_0402_5%
[35] EC_SMB_CK4
R5 R2014 1 @ 2 0_0402_5%
[35] EC_SMB_DA4
100K_0402_5% R15 1 2 0_0402_5%

+AVCC

2
WRST# R4 1 2 0_0402_5%
D I2C0_SCL_SEN_R R2107 2 1 0_0402_5% D
I2C0_SDA_SEN_R I2C0_SCL_SEN [11,35]
1 R2108 2 1 0_0402_5%
I2C0_SDA_SEN [11,35]
C9
1U_0402_6.3V6K
2
SENSOR_DEBUG_CLK
SENSOR_DEBUG_DAT TP@ T120
TP@ T121
Reserved for debugging
& updat i ng F W Intel
Sensor Hub EC Sensor Hub
U2102 +3VS_SEN +3VS_SEN
33
+AVCC AVCC
1 R2107 R2016
C16
R2108 R2017

0.1U_0201_10V6K
To CPU I2C NC

1
RC72(PH) RP1(PH)

2.2K_0402_5%

2.2K_0402_5%
2
I2C0_SCL_SEN_R
RC73(PH)
47 R8 R7
7 SMCLK0/GPB3 48 I2C0_SDA_SEN_R
+3VS_PLL VSTBY(PLL) SMDAT0/GPB4 SENSOR_DEBUG_CLK
2 R2109 R2014 R5215

2
SMCLK2/GPF6

SM BUS
3 SENSOR_DEBUG_DAT
SMDAT2/GPF7 13 SENSE_SCL R2110 R2015 R5216
1 SMCLK4/GPE0 SENSE_SDA To Sensor IC R7(PH) RP1(PH) RC86(PH)
C15 +3VS_SEN 1 12

0.1U_0201_10V6K
VSTBY SMDAT4/GPE7
36
VSTBY R8(PH) RC88(PH)
1 1 23
2 C11 C12 16 VSTBY

0.1U_0201_10V6K

0.1U_0201_10V6K
4 VSTBY
VSTBY
2 2
To CPU Int RC196 RC205 Test Point
WRST# 11
WRST#

40 15
FSCE#/GPG3 PWM0/GPA0 TS_detect [35]
41 14
42 FMOSI/GPG4 PWM1/GPA1 17
FMISO/GPG5 FSPI PWM4/SMCLK5/GPA4
C 44 PWM 19 C
FSCK/GPG7 PWM5/SMDAT5/GPA5 18
PWM6/SSCK/GPA6

IT8350E
LQFP-48 UART
RXD/SIN0/GPB0
45
46
RXD
TXD
T25
T28
TXD/SOUT0/GPB1

Reserved TX/RX for debugging

37
[10,11] SENSOR_HUB_INT GPH5/ID5/DM
+3VS_SEN 1 @ 2 38 USB
GPH6/ID6/DP 27
R46 ADC0/GPI0 28
1.5K_0402_5% ADC1/SMINT0/GPI1 29
6 ADC2/SMINT1/GPI2 30
PWRSW/GPE4 A/D ADC3/SMINT2/GPI3
@ 21 31
R5213 1 2 100K_0402_5% 20 KSI0 ADC4/SMINT3/GPI4 32
R5214 1 2 100K_0402_5% 26 KSI6 ADC5/GPI5
KSI7 GPIO
@
For Sensor Debug 43
GPG6 R14
39 1 2
SSCE0#/GPG2 25
KSO17/SMISO/GPC5 100K_0402_5%
SSPI 22
5 KSO16/SMOSI/GPC3
24 VSS
35 VSS
VSS oscillator required for use of USB or UART

10 9 CK32KE
VCORE CK32KE/GPJ7 8 CK32K
CK32K/GPJ6
CLOCK
1 Y3 @
B B
C10 34 2 1
0.1U_0201_10V6K

AVSS
32.768KHZ 12.5PF 9H03200031

1
2
IT8350E-128-CX_LQFP48 R2111
SA000076330 0_0402_5% 1 1
C13 @ C1 @

2
22P_0402_50V8J 22P_0402_50V8J
2 2

G-Sensor x1
+3VS +3VS
UGS2
7 3
10 VDD VDDIO 11
A 1 1 A
CSB PS
CGS3 T128 TP@ 5 4 CGS5
0.1U_0201_10V6K 6 INT1 NC 0.1U_0201_10V6K
2 T129 TP@ INT2 2
1
SENSE_SDA_R 2 SDO 9
SENSE_SCL_R 12 SDx GND 8
SCx GNDIO
BMA250E_LGA12

Security Classification Compal Secret Data Compal Electronics, Inc.

SMB Address: 0001 1000(0X18) Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title
when SDO is pulled to GND.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_RTL8111H / RTL8107E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 36 of 53
5 4 3 2 1
 A B C D E

+3VS
+3VALW J4
2 1
2 1
+VL

10U_0603_6.3V6M
JUMP_43X79

10U_0603_6.3V6M

0.1U_0201_10V K X5R
1 0.1U_0201_10V K X5R 1 1 1

C211

C212
1 1

C205

C206
@
@ +3VALW to +3VS 2 2
2 2
U13
1 14
2 VIN1 VOUT1 13 +3VALW_3VS
VIN1 VOUT1
3 12 C207 1 2
ON1 CT1 470P_0402_50V7K
4 11
[13,35] SUSP# VBIAS GND
5 10 1 2 220P_0402_50V7K +5VS
+5VALW ON2 CT2 C213 J5
6 9 +5VALW_5VS 2 1
7 VIN2 VOUT2 8 2 1
VIN2 VOUT2
10U_0603_6.3V6M

10U_0603_6.3V6M
JUMP_43X79
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
1 1 15 1 1
GPAD
C214

C215

C217

C218
@ EM5209VF_DFN14_2X3 @
2 2 2 2

+5VALW to +5VS

2 2

For +1.8VALW Discharge For +0.6VS Discharge

+1.8VALW

+0.6VS
+5VALW
1

+5VALW
1

R2005
22_0603_1% R228
1

3 3
@
1

R2004 470_0402_5%
2

100K_0402_1% R230
2

@
100K_0402_5%
2

D D
2

1.8VALW_PWR_EN# 5 SUSP 5 @
G Q143B G Q144B
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S
4

4
6

D D
2 SUSP# 2 @
[41,43] 3V/5VALW_PG G G
Q143A Q144A
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC to DC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 37 of 53
A B C D E
 5 4 3 2 1

ACES_50278-00401-001 EMI@ PL101 ADP_ID

6
G2 5 PF101
FBMA-L11-201209-221LMA30_2P
1 2
VIN AC Adapter 65W 45W
G1 4 APDIN 7A_32VDC_0437007.WRML
4 3 1 2 APDIN1 R(ohm) 287 118
3 2
2 1 ADP_ID(V) 0.913 0.448
1

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
1 2
@ JDCIN1 EMI@ PL102 Detection voltage 0.693~1.134 0.234~0.663
FBMA-L11-201209-221LMA30_2P

1
D D

EMI@ PC101

EMI@ PC102

EMI@ PC103

EMI@ PC104
2

2
C C
2

PR107
+CHGRTC
45.3K_0603_1%

PR108
1.5K_0603_5%
1

1 2
+3VLP
PD101
B
+RTCBATT 1 2 +CHGRTC_R B

PR109
RB751V-40_SOD323-2 1K_0603_5%
1 2

A A

Security Classification Compal Secret Data

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 38 of 53
5 4 3 2 1
 5 4 3 2 1

EMI@ PL201
CONN@ VMB2 VMB S SUPPRE_ 5A Z120 25M 0805
PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
SUYIN_125022HB008M200ZL

1 1 2
1 2 BATT+
EMI@ PL202
2 3 EC_SMCA S SUPPRE_ 5A Z120 25M 0805
3 4 EC_SMDA 1 2
4 5 TH
5 6
6

1
7
7

1
100_0402_1%

100_0402_1%
8
8 9 PC201 EMI@ PC202 EMI@
D GND 10 1000P_0402_50V7K 0.01U_0402_25V7K D

2
GND

PR201

PR202
11

2
GND 12
GND
+CHGRTC_R

EC_SMB_CK1 <35,40>

EC_SMB_DA1 <35,40>
1 2
+3VLP
PR203
1200K_0402_1%
2
+3VALW
PR204
@ 200K_0402_1%
1 2
PR205
VCIN1_BATT_TEMP <35,40> PH201 under CPU botten side :
10K_0402_5%
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

+EC_VCCA

16.5K_0402_1%
1
PR206
C C

2
<35> VCIN0_PH1

1
PH201
100K +-1% 0402 B25/50 4250K

2
ECAGND

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SKL
Date: Monday, June 06, 2016 Sheet 39 of 53
5 4 3 2 1
 5 4 3 2 1

ISL95520_NVDC

Protection for reverse input

Vgs = 20V
Vds = 60V
D D
Id = 250mA

1
D
Inverse_GATE 2 PQ302
G L2N7002WT1G_SC70-3
S max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W

3
Rds(on) = 15.8mohm max CSR rating: 1W
1 2 1 2
Vgs = 20V VCSIP-VCSIN spec < 81mV
PR302 PR303 Vds = 30V
1M_0402_1% 3M_0402_5% ID = 10.5A (Ta=70C) P3
PQ301 P1 PQ303
Need check the SOA for inrush MDU1512RH_POWERDFN56-8-5 AON7506_DFN33-8-5 P2 PR301
1 1 0.01_1206_1% P4
2 2
5 3 3 5 1 4
VIN

EMI@

EMI@
2 3 Isat: 10A

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V7K
DCR: 14mohm

1
CSIN_CHG_R

PC302

PC303
CSIP_CHG_R

PC304

PC305
@ PJP301

2
1 2
1 2
JUMP_43X118

1
Co-lay jump and ISN choke.

1
0_0402_5%
@ PR304
PR305

1
2_0402_5%
PR306

2
287K_0402_1% ASGATE_CHG_R
BATT+

2
PC301
2

1 2 PQ304

4.02K_0402_1%

4.02K_0402_1%
AON7506_DFN33-8-5
C
1 C
0.1U_0402_25V6

1
1
2
5 3

PR309
ACDET rise 2~2.15 V(17.7~19.03V) 100_0402_1%

PC307 0.22U_0603_25V7K
2
2

4
PR307

PR308
1 2 Rds(on) = 32mohm max

BGATE_CHG
BATT+ Vgs = 20V
Vds = 30V
1

CMSRC_CHG ID = 8A (Ta=70C) @ PC308

49.9K_0402_1%

1
PR310

1
PC306 ASGATE_CHG 1 2
0.1U_0402_25V6
2

BGATE_CHG
2

OPCN_CHG 2
0.1U_0402_25V7K

CSIN_CHG
CSIP_CHG

OPCP_CHG

VBAT_CHG
0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 10m Ω a nd R s2 = 10Ω
m Rds(on) = 32mohm max B+
1 VDD_CHG

BIT0 = 1.14uA/W Vgs = 20V

BIT1 = 0.285uA/W PC309
Vds = 30V

5
10U_0805_25V6K
=========================================================
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20 Ω
m PU301
ID = 8A (Ta=70C) PQ305 1 2
100K_0402_1%

support Turbo boost : 2200P 7X7X3 Support max charge 3.5A

32

31

30

29

28

27

26

25
BIT0 = 2.28uA/W no support Turbo boost : 0.1u ISL95520HRZ-T_QFN32_4X4 PC310
BIT1 = 0.57uA/W AON7408L_DFN8-5 Isat: 7.8A Power loss: 0.245W
PR311

10U_0805_25V6K

CSIN

CMSRC

OPCN

VBAT
CSIP

ASGATE

QPCP

BGATE
PR312 PC311 4 DCR: 18mohm 1 2 CSR rating: 1W
2.2_0603_5% 0.22U_0603_25V7K VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2
2

Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBA T ) ACIN BOOT PR315

2 23 UG_CHG PL302 0.01_1206_1%
R_Psys = 1.2V / Ipsys

3
2
1
KPSYS = 1.14uA/W <10,34,35> VCIN1_AC_IN @ ACOK UGATE 2.2UH_7.8A_20%_7X7X3_M BATT_CHG+
1

1 2 0_0402_5% EC_SMB_DA1_CHG
3 22 LX_CHG 1 2 1 4
158K_0402_1%

adapter wattage = 45W PR313

<35,39> EC_SMB_DA1 SDA PHASE
PR314

Battery wattage = 40Wh 1 @ 2 0_0402_5% EC_SMB_CK1_CHG

4 21 LG_CHG 2 3
PR316

680P_0603_50V7K 4.7_1206_5%
Ipsys = 1.14 x (45+40) = 96.9uA <35,39> EC_SMB_CK1 SCL LGATE

EMI@ PR318

10U_0603_25V6M

10U_0805_25V6K
R_Psys = 1.2V / 96.9uA = 12.3K-ohm.

5
PR317 1 @ 2 0_0402_5% H_PROCHOT#_CHG
5 20 VDDP_CHG PQ306

10U_0603_25V6M
2

===================================== <6,35> H_PROCHOT# PROCHOT# VDDP

AON7752_DFN3X3EP8-5
B 1 1 B

1
adapter wattage = 65W 2 0_0402_5% AMON_ISL95520 6 VDD_CHG

PC312

PC313

PC314
PR319 1 @ 19 1 2
Battery wattage = 40Wh <35> ADP_I AMON VDD

2
Ipsys = 1.14 x (65+40) = 119.7uA PR321 1 @ 2 0_0402_5% BMON_ISL95520 7 18 DCIN_CHG PR320 4.7_0402_5%

2
<35> DCHG_I BMON DCIN

1
R_Psys = 1.2V / 96.9uA = 10K-ohm. 4 2 2
8 17

BATGONE
Close to EC. PC315 PC316
<46> PMON_SKYLAKE PSYS NTC

1
NTC_CHG

EMI@ PC317
1U_0402_16V6K 1U_0402_16V6K

2
CCLIM

ACLIM
COMP
PROG
AGND

CSON

CSOP
FSET

1
10K_0402_1%

PC319 PR322

3
2
1

2
1
1

PR323

PC318 1000P_0402_25V8J 19.6K_0402_1%

DCIN_R
PD301
33

13

14
9

10

11

12

15

16

3
**Design Notes** 1000P_0402_25V8J Follow adapter and PR324 10_1206_5% 3 PQ307
VIN
2

battery wattage in @ 1 2 1 @

470K_0402_5%_B25/50 4700K
For 45W/65W /90W system, 2S/3S/4S battery

2
NTC_R
VCIN1_BATT_TEMP_CHG

Close to Vsys current source. 2 PR335 1 2 0_0402_5% LMUN5113T1G_SOT323-3

Maximum Charging current 3.5A BATT+
2

2
EC.
FSET_CHG

PC320
VF = 0.38V 2

1U_0603_25V6
Base on CPU Core VR design.
Maximum Battery discharge power 55W The resistor is pop on CPU VR schematic. LRB715FT1G_SOT323-3

1
#Register Setting PR336 1 @ 2 0_0402_5%
BA

1
PH301
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function 10uA current source output.
2. Disable turbo when AC only VDD=5V VDD_CHG
If the NTC pin voltage is below 180mV.

1
#Circuit Design The ISL95520 pulls PROCHOT# low.

2
(11) PM_SLP_S4# 2
1. ACLIM and CCLIM are devider voltage control. CCLIM_CHG ~ 120 degreeC.
2. Use 7X7 choke and 3X3 H/L side MOSFET
200K_0402_1%

*Change PR757 to 100K and PH701 to 0ohm to disable NTC function.

1

Charge current 3A ACLIM_CHG PQ308

BA
PR326

Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) PR327

3
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R LTC015EUBFS8TL_UMT3F
Power density : 0.61 (23X16) 200K_0402_1%
#Protect function COMP_CHG PR328 2_0402_5% BA
2

1
1. ACOVP : VCC voltage > 24V
499_0402_1%

Fs=614KHZ ~ +/- 15% PC321

86.6K_0402_1%

2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).

2 PR329 1

2 PR330 1

3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable). 0.1U_0402_25V6

2
PR331

4. CHGOCP : based on charge current setting

1

CSON_CHG 1 2 CSON_CHG_R
560P_0402_50V7K
1

5. BATOVP : 4.6V/Cell
PC322

6. BATLOWV : No. 65W@ PR325 @ PR332 0_0402_5%

1

1
102K_0402_1%

PR333 10K_0402_1%
7. TSHUT : 150C
2
1

PR334 PC11146 For A31 only.

0.033U_0402_16V7K

A A
2

VCIN1_BATT_TEMP <35,39>
69.8K_0402_1%

178K_0402_1% 0.1U_0402_25V6 Turn off Charger IC on battery only.

2

2
1

PC323

PR333 45W@ Depend on customer design for

@
53.6K_0402_1% BATGONE(BATT_TEMP) system power consumption.
2

logic high: above 2.4V

2
2

NVDC mode logic low: under 0.8V

Cell = 2s
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ) .
CC_LIM = VccLIM / 64 x Rs2
=============================================================
Security Classification Compal Secret Data Compal Electronics, Inc.
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ) . 2014/11/05 2014/12/15 Title
CC_LIM = VccLIM / 32 x Rs2
Issued Date Deciphered Date
PWR_CHARGER
============================================================= Battery current limimed by CCLIm ~ 7.3A. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AC_LIM = Vac_LIM / 32 x Rs1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Adapter current limimed by ACLIm ~ 4A.(65W) 3.3A(45W) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
(PR779 and PQ741 are for change ACLIm when AC in) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 40 of 53

5 4 3 2 1
 A B C D E

Module model information

SY8286B_V1.mdd

1 1

PU401 @ PR402
B+ EMI@ SY8286BRAC_QFN20_3X3 0_0603_5%
PL401
PC402
B+_3V BST_3V BST_3V_R

2200P_0402_50V7K
1 2 1 2 1 2

10U_0805_25V6K
@EMI@ PC401

EMI@ PC403
0.1U_0402_25V6
5A_Z120_25M_0805_2P 0.1U_0603_25V7K

1
PC404

BS
IN

IN

IN

IN
PL402

2
LX_3V6 20 LX_3V 1 2
LX LX +3VALWP

EMI@

PR403
7 19 1.5UH_6A_20%_5X5X3_M
GND LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
680P_0603_50V7K 4.7_1206_5%

1
8 18
+3VLP GND GND

PC405

PC406

PC407

PC408
9 17
+3VLPP

2
PG LDO

1 3V_SN
2
1
10 16
NC NC

1
Check pull up resistor of SPOK at HW side PC409

OUT
EN2

EN1
21

NC
4.7U_0603_6.3V6M

FF

2
PR401 GND

EMI@

PC410
100K_0402_5%

11

12

13

14

15

2
3.3V LDO 150mA~300mA

2
Vout is 3.234V~3.366V Ipeak=4.65A
2
<37,43> 3V/5VALW_PG ENLDO_3V5V
Imax=3.25A 2
PC411 PR404 TDC=6A
1000P_0402_25V8J 1K_0402_1% Iocp=10A
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2

EN :H>0.8V ; L<0.4V
EN1 and EN2 dont't be floating @ PJ401
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118

Module model information @ PJP402

SY8286C_V1.mdd JUMP_43X39
1 2
+3VLPP 1 2 +3VLP

B+ B+_5V @ PR405
EMI@ 0_0603_5%
PL403 PC412
PR407 PU402 SY8286CRAC_QFN20_3X3
499K_0402_1% 1 2 B+_5V BST_5V1 2 BST_5V_R 1 2
1 2 ENLDO_3V5V
B+ 5

1
5A_Z120_25M_0805_2P PL404
1
150K_0402_1%

0.1U_0603_25V7K

BS
IN

IN

IN

IN
1
PR408

3.3UH_MMD-05CZ-3R3M-M7L_5A_20%
LX_5V 6
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PC428 20
LX LX
1U_0402_16V6K
2

7 19 LX_5V 1 2 +5VALW
2

GND LX
1

1
PC413

PC414

EMI@ PC415

@EMI@ PC416

8 18
GND GND

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
3 PC417 4.7U_0603_6.3V6M 3
2

1
9 17 VCC_5V 1 2
PG VCC

1
PR406

PC418

PC420

PC421

PC429

PC430
4.7_1206_5%
EMI@
10 16

2
PR410 NC NC
OUT

LDO
EN2

EN1

2.2K_0402_5% 21
FF

1 2 SPOK GND
<34,35> EC_ON SPOK

2
@ PR411
11

12

13

14

15

0_0402_5%
+5VLP

15V_SN
4.7U_0603_6.3V6M

1 2 1 PR409 2
<35> VCOUT0_MAIN_PWR_ON +VL 5V LDO 150mA~300mA
1

680P_0603_50V7K
PC424

100K_0402_5%
ENLDO_3V5V

EMI@

PC425
2

5V_3V_EN

2
5V_3V_EN
Vout is 4.998V~5.202V
1M_0402_1%

4.7U_0402_6.3V6M
1

1
PR413

PC427

EN :H>0.8V ; L<0.4V TDC=6A Ipeak=9A

PC426 PR412
1000P_0402_25V8J 1K_0402_1% Imax=6.25A
2

EN1 and EN2 dont't be floating 5V_FB 1 2 5V_FB_1 1 2

Iocp=10A
2

B+_5V
1

PR341

560K_0402_5%
4 @ PJP404 4
2

JUMP_43X39
VCIN1_BATT_DROP <35> 1 2
+5VLP 1 2 +VL
1

PR342 PC327
1000P_0402_25V8J
2

105K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 3VALW/5VALW-SY8286B&C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 41 of 53
A B C D E
 A B C D E

Pin19 need pull separate from +1.35VP. 0.675Volt +/- 5%

If you have +1.35V and +0.675V sequence question, TDC 0.7A
EMI@ PL501 you can change from +1.35VP to +1.35VS.
B+ S SUPPRE_ 5A Z120 25M 0805 Peak Current 1A
1 2 +12.6VB_DDR PR501
2.2_0603_5%
BST_DDR_R 1 2 BST_DDR

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
+1.2VP

1
@EMI@ PC501

EMI@ PC502

PC503

PC504
UG_DDR +0.6VSP

2
1 1

5
LX_DDR

10U_0603_6.3V6M

10U_0603_6.3V6M
1

1
PC505
0.1U_0603_25V7K

PC506

PC507
16

17

18

19

20
2
PU501

2
PQ501 4

BOOT

VTT
VLDOIN
PHASE

UGATE
21
AON7408L_DFN8-5 PAD
LG_DDR 15 1
LGATE VTTGND

1
2
3
14 2
PL502 PR502 PGND VTTSNS
1UH_11A_20%_7X7X3_M 17.8K_0402_1%
1 2 1 2 CS_DDR 13 3
+1.2VP CS GND

5
PC508 RT8207PGQW_WQFN20_3X3

1
1U_0402_10V6K
1 2VDDP_DDR12 4 VTTREF_DDR
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

EMI@ PR503 PR504 VDDP VTTREF

1

4.7_1206_5% 5.1_0603_5%
PC509

PC510

PC511

PC512

PC513

PC514

PQ502 4 1 2 VDD_DDR 11 5
+5VALW +1.2VP

1 2
SNB_1.2VP VDD VDDQ

1
PGOOD
2

AON7406L_DFN8-5 PC516
+5VALW PR505

TON
1
EMI@ PC515 0.033U_0402_16V7K

FB
S5

S3

2
680P_0402_50V7K PC517 1 2

1
2
3
1U_0402_10V6K 5.1_0603_5%

10

6
FB_DDR
EN_DDR
TON_DDR

EN_0.6VSP
PR507
1 2 +1.2VP
PR508 470K_0402_1%
+12.6VB_DDR 1 2
6.04K_0402_1%

1
PR509
@ 10K_0402_1%
PR510 1 20_0402_5%
<13,35,37> SYSON

2
MOSFET: 3x3 DFN

1
@ PC518
2 H/S Rds(on): 27mohm(Typ), 34mohm(Max) 0.1U_0402_10V7K 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

2
L/S Rds(on): 19mohm(Typ), 23.5mohm(Max) @ PR511
Mode Level +0.675VSP VTTREF_1.35V Idsm: 11A@Ta=25C, 8.8A@Ta=70C 0_0402_1%
S5 L off off 1 2 @ PJ501
S3 L off on Choke: 7x7x3 <13,35,37,42> SUSP# +1.2VP 1 2 +1.2V
1 2
S0 H on on Rdc=6.7mohm(Typ), 7.4mohm(Max) @ PR518 0_0402_1% JUMP_43X118
@ PJ502
Note: S3 - sleep ; S5 - power off Switching Frequency:540kHz 1 2 1 2
<7> DDR_VTT_PG_CTRL 1 2
Ipeak=8A

1
JUMP_43X118
Iocp~9.6A @ PC519
OVP: 113%~120% 0.1U_0402_10V7K PJ503
@

2
VFB=0.75V, Vout=1.203V 1 2
+0.6VSP 1 2 +0.6VS
JUMP_43X39

3 3

Module model information

@ PR513
SY8003A_V1.mdd 0_0402_5%
1 2
+2.5V_EN <13,35,37,42>

PR512
@ 0_0402_5%
+1.8VSP_ON 1 2
PM_SLP_S4# <13,35,37,42>
0.1U_0402_16V7K

1
PC520
1

PR514
@ 1M_0402_5%
Note:Iload(max)=2.5A
2

PU502
2

9 @
PGND PJ504
1 8
FB SGND 1 2
PJ505 @ 2 7 1UH_1269AS-H-1R0M-P2_2.5A_20% +2.5VP 1 2 +2.5V
PG EN PL503
+3VALW 1 2 VIN_2.5VP 3 6 LX_2.5V 1 2 JUMP_43X79
1 2 IN LX +2.5VP
1

4 5
68P_0402_50V8J

JUMP_43X79 PGND NC
1

PC521 PR516
4.7_0603_5%

1
PR515

PC522
22U_0603_6.3V6M

1
1

36.5K_0402_1%
Rup
22U_0603_6.3V6M
22U_0603_6.3V6M

SY8003ADFC_DFN8_2X2 EMI@
PC524
PC523
2

2
2

FB_2.5V

SNB_2.5VP
1
1

FB=0.6V PR517
680P_0402_50V7K

Note:Iload(max)=3A Rdown
PC525

11.5K_0402_1%
2

EMI@
2

4 4
Vout=0.6V* (1+Rup/Rdown)
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.2VP/+0.6VSP/+2.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D471P 2.0

Date: Monday, June 06, 2016 Sheet 42 of 53

A B C D E
 A B C D

1 1

Module model information

APL5930_V2.mdd

+3VALW +5VALW

2
1
Ultra Low Dropout 0.23V(typical) at 3A Output Current 2

1
1 PC601
1U_0402_6.3V6K
JUMP_43X79

2
@ PJ601
2
2

PU601
APL5930KAI-TRG_SO8
1

PC602 6
4.7U_0603_6.3V6K VIN_1.8VALW P 5 VCNTL 3
9 VIN VOUT 4 PJ602
@
2

@ 0_0402_5% VIN VOUT

+1.8VALWP +1.8VALWP 1
1 2
2 +1.8VALW

1
PR601 1 2 EN_1.8VALW P 8

0.01U_0402_25V7K
<37,41> 3V/5VALW_PG EN

1
1 2 7 2 PR603 JUMP_43X79
POK GND FB

PC604
12.7K_0402_1%

22U_0603_6.3V6M
+3VALW
1

PR602
Rup
0.1U_0402_16V7K

1
PC603

@ PR604 100K_0402_5%
1

PC605
47K_0402_5%
2

FB_1.8VALW P

2
@
2

1
<42,44> PGOOD PR605
10K_0402_1%
Rdown

2
3 3

Vout=0.8V* (1+Rup/Rdown)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8V_PRIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 43 of 53
A B C D
 5 4 3 2 1

D D

C C

Module model information

SY8288_V1.mdd

Confirm HW side
B+_1.0VALWP EMI@ PR703 EMI@ PC702
4.7_1206_5% 680P_0603_50V7K
1 2 SNB_1V 1 2

@ PJ701 PU701
B+_1.0VALWP
B+ 1
1 2
2 2
IN PG
9 @ PR704
0_0402_5%
PC704
0.1U_0201_10V6K
(Common Part SH00000YE00)
0.1U_0402_25V6

10U_0805_25V6K

3 1 BST_1V 1 2 BST_1V_R 1 2 PL701

2200P_0402_50V7K

JUMP_43X79 IN BS
1
1

1UH_11A_20%_7X7X3_M
@EMI@ PC703
EMI@ PC701

PC705

LX_1V
4
IN LX
6 1 2
+1.0VALWP
2
2

5 19

15K_0402_1%

330P_0402_50V7K

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
IN LX

1
1

1
7 20

PR705

PC710
PC706

PC707

PC708

PC709
GND LX
8 14 FB_1V R1

2
2

2
2

2
GND FB

2
@ PR701 18 17 LDO_3V
0_0402_5% GND VCC
1 2 EN_1V 11 10 1
<42,43> PGOOD EN NC PC711 FB=0.6V

1
ILMT_1V 13 12 2.2U_0402_6.3V6M
2

ILMT NC
1
1

B B
@ PC712
PR706 0.1U_0402_25V6 15 16 PR707
1M_0402_1% +3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 20K_0402_1%
+3VALW
2

21 =0.6*(1+(14/20)) @ PJ702

2
PAD JUMP_43X118
2

SY8288RAC_QFN20_3X3 1 2
Vout=1.02V +1.0VALWP 1 2 +1.0VALW
1

EN :H>0.8V ; L<0.4V
PC713
1

1U_0402_6.3V6K
2

EN pin don't floating @ PR708

If have pull down resistor at HW side, 0_0402_5%
please delete PR601.
2
1

@ PR709
0_0402_5%
2

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.0VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z_SKL
Date: Monday, June 06, 2016 Sheet 44 of 53
5 4 3 2 1
 A B C D

1
Module model information 1

NB681_V1.mdd

2 2

U23E@
100K_0402_1%
PR802
MODE_+1.0VS_VCCIOP 1 2
@ PR801
0_0402_5% PR803 PC802 PR804 PC803

U23E_EMI@

U23E_EMI@
1 2 LPM#_+VCCIOP 2.2_0402_5% 0.1U_0402_25V6 4.7_1206_5% 680P_0402_50V7K
<17> LPM_ZVM# BST_+1.0VS_VCCIOP 1 2 BST_R_+1.0VS_VCCIOP 1 2 1 2SNUB_+1.0VS_VCCIOP 1 2
Note:Iload(max)=5.5A

U23E@

U23E@
PU801
IOCP=7A~8A(typ)

9
PL801 PL802
5A_Z120_25M_0805_2P 0.68UH_7.9A_20%_5X5X3_M

LP#

MODE

BST
B+_1.0VS_VCCIOP LX_+1.0VS_VCCIOP
B+ 1 2 1
VIN SW
8 1 2
+1.0VS_VCCOPCP
U23E_EMI@ PR805 EN_+1.0VS_VCCIOP 5 12

U23E@
0.1U_0402_25V6

20K_0402_1% EN VOUT 3
2200P_0402_50V7K

10U_0805_25V6K
1

2C1_+1.0VS_VCCIOP
PC801

@EMI@ PC806

PC808

1 3 2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
C1 PGND
+3VALW

1
C0_+1.0VS_VCCIOP 4 11

PC804

PC805

PC807
U23E@
2

C0 AGND

3V3
PG
1
U23E_EMI@

2
PR806 NB681GD-Z_QFN13_2X3
13

10
U23E@

U23E@

EN pin don't floating 20K_0402_1%

U23E@

U23E@

U23E@
If have pull down resistor at HW side, pls delete PR606
U23E@ 2

@
@ PR807 0_0402_5% PJ801
1 2 JUMP_43X118
<10,35> PCH_PWROK
+3VALW +1.0VS_VCCOPCP
1
1 2
2
+1.0VS_VCCOPC
1

1
@

PC810
1

PR808 PC809
0.1U_0402_25V6
2

1M_0402_1% 1U_0402_6.3V6K
U23E@ 2

EN Mode Voltage on EN
U23E@ 2

Ultra Sonic Mode 1.3v<EN<1.7v

Normal Mode 2.3v<EN<3.3v Switching frequency is 650KHz

4 4

Security Classification Compal Secret Data

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.0VS_VCCOPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 45 of 53
A B C D
 1 2 3 4 5

CPU CORE Due to U23e VCC_GT and GTX merged current spec is TBD in PDDG. IccMAX@SA= 5A
Please confirm FAE the setting of PRI23, PRI39 PRI63 for U23e GT and GTX merged. RIccMAX@SA= 15.8K --->PRI65

RIccMAX@SA= IccMAX*2V/10uA/64A
Module model information
IOUTSP@SA= 5A
NCP81208_U2223E_COLAY_V1A.mdd for IC portion RIOUTSP@SA=69.8K --->PRI14

NCP81208_U2223E_COLAY_V1B.mdd for SW portion RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR

/(RPHSP+Rth+RCSSP))
PSYS:
A Copy the schematic to new page, PMON_SKYLAKE Please confirm charger pull low resistance. OCP@SA= 9.5A A

the co-lay location maybe changed. <34> Charger side should be unpop. RLIMSP@SA=24K --->PRI5
8200P_0402_25V7K RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR
PRI1 /(RPHSP+Rth+RCSSP))
PCI1
1.5K_0402_1%
OCP for VCCSA 1 2 1 2
PRI2, PRI8 place near CPU side. Load line@SA= 10.3m
If the resisters are at HW side and POP. PRI2, PRI8 can be canceled. RDRPSP@SA=1.78K --->PRI4
PCI3 COMP_1b_CPU 1 2 PCI2
1000P_0402_50V7K 15P_0402_50V8J
+VCCSA PRI2 1 2 RDRPSP= Load line*(RPHSP+Rth+RCSSP)

1000P_0402_50V7K
100_0402_1% /(gm * DCR) /(Rth+RCSSP)
1 2 @ PRI3 PRI4

1
0_0402_5% 1.78K_0402_1% CSN_1b_VCCSA

24K_0402_1%

1
1 2 VSPP_1b_CPU_R 1 2 VSP_1b_CPU <11>

PRI5
VCCSA_SENSE
PHI1 Close to SA choke

PCI4
<33,37,43,46,48,50>

1200P_0402_50V7K
2
1
RDRPSP 100K_0402_1%_NCP15WF104F03RC

0.01U_0402_25V7K
@ PRI6 PCI5
PRI7 1K_0402_1%

2
0_0402_5% 1000P_0402_50V7K

PCI7
2

1 2
1

1
1 2 VSNN_1b_CPU_R 1 2 VSN_1b_CPU CSN_1b_VCCSA_NTC

PCI6
VSSSA_SENSE
<33,37,43,46,48,50>
1 2 1 2 PRI9

2
PRI8 100_0402_1% PCI8 2200P_0402_50V7K 12K_0402_1%
+VCCGT PRI10 CSP_1b_VCCSA +3VS
1 2 CSP_1b_VCCSA_R

2
1 2 @ PRI13 20K_0402_1% PRI14 1 2

1
PRI11 100_0402_1% 0_0402_5% 64.9K_0402_1% 7.5K_0603_1% <11>
1 2 VSP_2ph_CPU 1 2 PRI12 PRI15
VCCGT_SENSE
<33,37,43,46,48,50> 10K_0402_1%

1
1 2
VSSGT_SENSE @ PRI17 PCI9 PRI18 PCI10 470P_0402_50V7K

2
0_0402_5% 1000P_0402_50V7K 1K_0402_1% VR_PWRGD
<33,37,43,46,48,50>

2
1 2 1 2 VSN_2ph_CPU_R 1 2 VSN_2ph_CPU <34>
RIOUT@GT: PRI16 100_0402_1%

1
1 2 IMVP8_EN confirm with power sequence, @ESD@
U23e = 22.1K PRI23 PCI11 +1.0V_VCCST PCI35
U22 = 25.5K PRI23 Upper Threshold > 0.8V it need behind +5VS.
B 3300P_0402_50V7K 100P_0402_50V8J B

2
Lower Threshold < 0.3V

1
U23E@ PRI23 PRI26 and PRI33 pull high resistor are pop at the end of VR SVID.
22.1K_0402_1% PRI19 Other VR is unpop.

1
PRI11, PRI16 place near CPU side. 49.9_0402_1% @ PRI21
If the resisters are at HW side and POP. PRI11, PRI16 can be canceled. PRI20 0_0402_5%
604_0402_1% 1 2

110_0402_1%

100_0402_1%
45.3_0402_1%
1 2
VR_ON

IOUT_1b_CPU
RIOUT@GT <11>

ILIM_1b_CPU
RPH@GT:

470P_0402_50V7K
2
PCI12

EN_CPU
U23e = 130K PRI30,PRI38 PWM_1b_CPU

1
470P_0402_50V7K <34>
U22 =84.5K PRI30,PRI38(De-pop)

2
CSCOMP_2ph_CPU_R

Close to VGT1 choke DRVON <34>

1
1

1
U23E@ U23E@ PRI23 U22@ PRI24 @

PCI13
PRI30 PRI38 PRI39 U23E@ 26.7K_0402_1% PCI14 110_0402_1% PRI34

1
1

4.75K_0402_1%
130K_0603_1% 130K_0603_1% PHI2 14K_0402_1% 7.5K_0603_1%

49

48
47
46
45
44
43
42
41
40
39
38
37
0.1U_0402_25V6

2
THERM_ 220K 5% 0402 @ 1 2
CSP_1a_VCORE_R

PRI25

1
1
1 2 U22/U23e is the same

VSN_2ph
VSP_2ph

VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b

EN
TAB

PSYS

VR_RDY
<9>

2
PCI15 PUI1 VR_HOT# PRI29

PRI26

PRI27

PRI33
but OCP is dif f er ent. 15P_0402_50V8J NCP81208-MNTXG_QFN48_6X6 <34> 12K_0402_1%
OCP for VGT

1 2
2
PRI31 PRI32 IOUT_2ph_CPU 1 36 PCI17 1 2
165K_0402_1% 75K_0402_1% DIFFOUT_2ph_CPU 2 IOUT_2ph PWM_1b 35 PRI36 49.9_0402_1% 470P_0402_50V7K CSN_1a_VCORE_NTC

2200P_0402_25V7K
0.022U_0402_16V7K
1 2 1 2 1 2 PRI39 PCI16 FB_2ph_CPU 3 DIFFOUT_2ph DRVON 34 SCLK_CPU 1 2 1 2
CSP1_VGT1 VR_SVID_CLK <11>
1

FB_2ph

1
PRI30 U22@ 84.5K_0603_1% U22@ 12.4K_0402_1% 2200P_0402_50V7K COMP_2ph_CPU 4 SCLK 33 ALERT#_CPU PRI37 1@ 20_0402_5% Close to VCORE choke

PCI20

PCI21
<33,37,43,46,48,50> VR_ALERT# <11>
2

1 2 PCI18 PCI19 @ 1 2 ILIM_2ph_CPU 5 COMP_2ph ALERT# 32 SDIO_CPU PRI40 1 2 10_0402_1% PRI42 PHI3
CSP2_VGT2 ILIM_2ph SDIO VR_SVID_DATA <11>

1
PRI38 @ 84.5K_0603_1% 680P_0402_50V7K 1000P_0402_50V7K CSCOMP_2ph_CPU 6 31 VR_HOTL# PRI41 1 2 100_0402_1% 56.2K_0402_1% 100K_0402_1%_NCP15WF104F03RC
<33,37,43,46,48,50>
2

CSSUM_2ph_CPU 7 CSCOMP_2ph VR_HOT# 30 IOUT_1a_CPU 1 2

1 2 CSREF_2ph_CPU 8 CSSUM_2ph IOUT_1a 29 CSP_1a_VCORE
CSN2_VGT2

2
PRI43 U23E@ 10_0402_1% CSP2_2ph_CPU 9 CSREF_2ph CSP_1a 28
<33,37,43,46,48,50> CSP2_2ph CSN_1a CSN_1a_VCORE
1

1 2 CSP1_2ph_CPU 10 27 ILIM_1a_CPU

ROSC_COREGT
CSN1_VGT1 <9>
0.1U_0402_25V6

0.1U_0402_25V6

PRI44 10_0402_1% TSENSE_2ph_CPU_R 1 2 TSENSE_2ph_CPU 11 CSP1_2ph ILIM_1a 26 COMP_1a_CPU

ADDR_VBOOT
<33,37,43,46,48,50>
1

TSENSE_2ph COMP_1a

1
TSENSE_1ph
RSOC_SAUS

ICCMAX_2ph
@ PRI45 1 2 12 25
PCI22

U23E@ PCI23

ICCMAX_1a
ICCMAX_1b
PCI24
2

VRMP VSN_1a

PWM1_2ph
PWM2_2ph

1
1
PCI26 0_0402_5% PRI46 3300P_0402_50V7-K PCI27

VRMP_CPU
100K_0402_1%_NCP15WF104F03RC

B+_CPU

PWM_1a
1

1 2 VSN_1a_CPU_R

VSP_1a
0.1U_0402_25V6 1K_0402_1% PCI25 PCI29 1000P_0402_50V7K
2

2
PHI4 PRI48 15P_0402_50V8J 1500P_0402_50V7K

VCC

1 2
2
1

For U22: 61.9K_0402_1% PCI28 PRI49 PRI51

1
1000P_0402_50V7K 649_0402_1% @ PRI50 100_0402_1%
PRI43=De-pop

1
CSP1_VGT1 1 2 PCI30 RDRPSP VSN_1a_CPU
1 2 1 2 1 2 PRI52 PRI53
For U23e:
2

13
14
1ROSC_SAUS_CPU 15
16
17
18
19
20
21
22
23
24
PRI47 2K_0402_1% 0.01U_0402_50V7K ForU22: 2.49K_0402_1% 30.1K_0402_1%
PRI43,PRI38=Pop

1
CSP2_VGT2 1 2 PCI31 0_0402_5%
PRI56=2.1K VSSCORE_SENSE

2
C C
PRI54 U23E@ 2K_0402_1% For U23e: 1000P_0402_50V7K

ICCMAX_2ph_CPU
<9>

2
ADDR_VBOOT_CPU
VCC_CPU

ICCMAX_1a_CPU
ICCMAX_1b_CPU
Close to VGT1 MOS PRI56=1.87K

2
+5VS PRI55 PRI56 OCP for VCORE
1 2 2_0402_1% 2.1K_0402_1% @ PRI57
For U22: +5VS U22@ PRI116 1 2 1 2VSP_1a_CPU_R 1 2 +VCCCORE
VCCCORE_SENSE
PRI47=2K, PRI54=De-pop 1K_0402_1% <9>
VSP_1a_CPU 1

1ROSC_COREGT_CPU
2 1 2 0_0402_5% 1 2 PRI51, PRI58 place near CPU side.

24K_0402_1%
For U23e: 2.1K_0402_1% PRI58 100_0402_1%
PRI47,PRI54=2K For U22: If the resisters are at HW side and POP. PRI51, PRI58 can be canceled.
1

472mV/120uA=3.933K PCI32 PRI115

PRI60
PCI23=De-pop PCI33 1000P_0402_50V7K
For U23e: Active Point110 degreeC = 4.206K 1U_0603_10V6K @ PRI61 For U22:
2

PCI23=0.1u TSENSE_1ph_CPU 1 2 TSENSE_1ph_CPU_R

PRI115=2.1K U22 Load line@VCORE= 2.35m
2
For U23e: RDRPSP@VCORE=2.1K --->PRI56

1
U22 OCP@GT= 40A 0_0402_5% PRI115=1.87K

1000P_0402_50V7K
U23e Load line@VCORE= 2.1m
RLIM@GT=12.4K --->PRI39

61.9K_0402_1%
33.2K_0402_1%

1
Fsw for SA RDRPSP@VCORE=1.87K --->PRI56

2
U23e OCP@GT= 62A PWM_1a_CPU PHI5
PRI59

PCI34
RLIM@GT=12.4K --->PRI39 <34> 100K_0402_1%_NCP15WF104F03RC
RDRPSP= Load line*(RPHSP+Rth+RCSSP)

PRI62
10K_0402_1%
100K_0402_1%
48.7K_0402_1%

15.8K_0402_1%
Fsw for CORE & GT /(gm * DCR) /(Rth+RCSSP)
RLIM= IoutLIMIT * Load line/10

2
2

Close to VCORE MOS

U22 IccMAX@GT= 31A NCP81208 Operating Frequency Rosc=24K
RIccMAX2ph= 48.7K --->PRI63 I/A and GT are 450KHz and SA is 450KHz
1

1
1

U23e IccMAX@GT= 56A IccMAX@VCORE= 28A

472mV/120uA=3.933K RIccMAX@VCORE= 87.6K --->PRI64
RIccMAX2ph= 87.6k --->PRI63 RIccMAX2ph: Active Point110 degreeC = 4.206K
For U22:
RIccMAX@VCORE= IccMAX*2V/10uA/64A
U22@

PRI66
PRI63

PRI65
PRI64

RIccMAX2ph= (IccMAX2Ph+32)*200K Ohn/ 127 PRI63=48.7K

2

2
2

For U23e:
PRI63=100K
U22 Iout@GT= 31A IOUTSP@VCORE= 28A
PRI63 U23E@
RIOUT@GT=25.5K --->PRI23 100K_0402_1%
RIOUTSP@VCORE=64.9K --->PRI42
U23e Iout@GT= 56A VBOOT:
RIOUT@GT=22.1K --->PRI23 22.1K for debuge setting. RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR
/(RPHSP+Rth+RCSSP))
D D
RIOUT= 2* RLIM /(10 *IOUTICCMAX * Load line)
PWM2_2ph_CPU <34> OCP@VCORE= 35A
U22 Load line@GT= 3.1m PWM1_2ph_CPU RLIMSP@VCORE=33.4K --->PRI53
<34>
RPH@GT=84.5K --->PRI30,PRI38
U23e Load line@GT= 2m RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR
RPH@VGT=130K --->PRI30,PRI38 /(RPHSP+Rth+RCSSP))
Load line= (RCS2+(RCS1*Rth/(RCS1+Rth)))
*IOUTTOTAL * DCR/RPH
Title
NCP81208
Size Document Number Rev
2.0

Date: Tuesday, June 07, 2016 Sheet 46 of 53

1 2 3 4 5
 1 2 3 4 5

EMI@ PL1001
CPU POWER STAGES 5A_Z120_25M_0805_2P
1 2
InputCapacitor:
EMI@ PL1002
B+_CPU 10uF_0805_X5R_25V 5A_Z120_25M_0805_2P B+
1 2

2200P_0402_50V7K

68U_D2_16VM_R40M
10U_0805_25V6K

10U_0805_25V6K

@EMI@PC1004
0.1U_0402_25V6

EMI@PC1005
1 1

PC1016
1

1
PC1002

PC1003
+ + PC1006
68U_D2_16VM_R40M
PQ1001

2
AON6428L_DFN-8-5 2 2

5
PR1002 PC1007
2.2_0603_5% 0.22U_0603_16V7K
1 2 BST_VCORE_R 1 2
A A
@ PR1003
BST_VCORE
0_0603_5%
UG_VCORE 1 2 UG_VCORE_R 4 @

PU1002 VCC_CORE

3
2
1
NCP81253MNTBG_DFN8_2X2 FSW=450kHz
PL1003
1 8 0.24UH_22A_+-20%_7X7X3_M +VCCCORE DCR = 1.19 mohm +/- 5%
BST DRVH
2 7 LX_VCORE 1 4
TYP MAX
<46> PWM_1a_CPU PWM SW H/S Rds(on) :11.7mohm , 14mohm
DRVON 3 6 2 3
+5VS EN GND L/S Rds(on) :2.7mohm , 3.3mohm
4 5
PAD

VCC DRVL

1
PQ1002 EMI@
1

PR1004 CSN_1a_VCORE <46>

9

PC1008 4.7_1206_5%
2.2U_0603_16V6K
2

LG_VCORE 4

2
SNB_VCORE CSP_1a_VCORE_R <46>

1
AON6794_DFN5X6-8-5 EMI@

3
2
1
PC1009
680P_0603_50V7K

2
VCCGT(2 phase)
FSW=450kHz B+_CPU
B
DCR = 1.19 mohm +/- 5% B
TYP MAX
H/S Rds(on) :11.7mohm , 14mohm

10U_0603_25V6M

10U_0603_25V6M
PC1010 U23E@

PC1011 U23E@
L/S Rds(on) :2.7mohm , 3.3mohm
1 1
B+_CPU

2 2

2200P_0402_50V7K
10U_0603_25V6M

10U_0603_25V6M

@EMI@PC1014
0.1U_0402_25V6

EMI@ PC1015
PR1005U23E@
PR1001 1 1 2.2_0603_5%
BST2_VGT2 2 BST2_VGT2_R

1
PC1012

PC1013
2.2_0603_5% 1
BST1_VGT1 1 2 BST1_VGT1_R

2
2 2

1
PC1017 U23E@
1

0.22U_0603_16V7K

2
PC1018 U23E@
0.22U_0603_16V7K PU1003U23E@
2

PU1001 NCP81151MNTBG_DFN8_2X2 PQ1004

PQ1003

1
NCP81151MNTBG_DFN8_2X2 1 9 AON6992_DFN5X6D-8-7
BST FLAG
2

1 9 AON6992_DFN5X6D-8-7 U23E@ PL1005

D1

G1
<46> PWM1_2ph_CPU BST FLAG <46> PWM2_2ph_CPU UG_VGT2
PL1004 2 8 0.24UH_22A_+-20%_7X7X3_M
D1

G1

2 8 UG_VGT1 0.24UH_22A_+-20%_7X7X3_M +VCCGT PWM DRVH +VCCGT

PWM DRVH DRVON 3 7 LX_VGT2 7 LX_VGT2 1 4
3 7 LX_VGT1 7 LX_VGT1 1 4 EN SW D2/S1
<46> DRVON EN SW D2/S1

U23E_EMI@
+5VS 4 6 2 3
VCC GND

1
EMI@

4.7_1206_5%
4 6 2 3

330U_D1_2VY_R9M
G2
S2

S2

S2
VCC GND 5 LG_VGT2
G2
S2

S2

S2

LG_VGT1 DRVL 1 1
1

4.7_1206_5%

330U_D1_2VY_R9M
+5VS U22@ PC1021

6
DRVL

PR1006
+ PC1020 +
3

6
1

PR1007

PC1019U23E@

SNUB_VGT2 2
PC1022 2.2U_0603_16V6K LG_VGT2

2
2.2U_0603_16V6K LG_VGT1 CSN2_VGT2 <46> 2 2
SNUB_VGT1 2
2

CSN1_VGT1 <46>
C C

U23E_EMI@
680P_0603_50V7K
CSP2_VGT2 <46>
EMI@

PC1020U23E@
CSP1_VGT1 <46> 470U_X_2VY_R9M

1
680P_0603_50V7K

PC1024
1

PC1023

2
2

B+_CPU
10U_0805_25V6K

10U_0805_25V6K
1

1
PC1025

PC1026

PR1008 PC1027
2

2.2_0603_5% 0.22U_0603_16V7K
1 2 BST_VCCSA_R 1 2
VCCSA
BST_VCCSA

UG_VCCSA
FSW=450kHz
AON7934 DCR 6.2mohm(TYP), 6.51mohm(Max)
Rds(on)=12.4~15.8m ohm TYP MAX
PU1004 PQ1005 H/S Rds(on) :12.4mohm , 15.8mohm
4

NCP81253MNTBG_DFN8_2X2 AON7934_DFN3X3A8-10
L/S Rds(on) :9.1mohm , 11.6mohm
D1

D1

D1

G1

1 8
PL1006
+VCCSA
BST DRVH
2 7 10 9 LX_VCCSA 1 4
<46> PWM_1b_CPU PWM SW D1 D2/S1
D D
EMI@ PR1009

DRVON 3 6 2 3
+5VS EN GND
4.7_1206_5%
G2
S2

S2

S2

4 5
PAD

VCC DRVL 0.47UH_MMD05CZR47M_12A_20%

5

8
1

9
2.2U_0603_16V6K
PC1028

CSN_1b_VCCSA <46>
2

SNB_VCCSA
680P_0603_50V7K
PC1029

Security Classification Compal Secret Data Compal Electronics, Inc.

1

LX_VCCSA CSP_1b_VCCSA_R <46> Title

Issued Date 2015/07/27 Deciphered Date 2016/07/27
PWR-PROCESSOR_DECOUPLING
2

LG_VCCSA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EMI@

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, June 06, 2016 Sheet 47 of 53
1 2 3 4 5
 A
B
C
D

2
1
PC11121
22U_0603_6.3V6M

2
1
+VCCGT
PC11122
22U_0603_6.3V6M
+VCCCORE

2
1
PC11123
22U_0603_6.3V6M

2
1

5
5

PC11124
22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1

PC11125
22U_0603_6.3V6M PC11090 PC11075 PC11038 PC11002
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1

PC11126

U23E@
22U_0603_6.3V6M PC11091 PC11076 PC11039 PC11003
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1

PC11127
22U_0603_6.3V6M PC11092 PC11077 PC11040 PC11004
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1

PC11128

U23E@
22U_0603_6.3V6M PC11093 PC11078 PC11041 PC11005
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1

PC11129

U23E@
22U_0603_6.3V6M PC11094 PC11079 PC11042 PC11006
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1

PC11001
22U_0603_6.3V6M PC11095 PC11080 PC11043 PC11007
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1
22U_0603 * 28 pcs +1U_0201*35 pcs

PC11130

U23E@
22U_0603_6.3V6M PC11096 PC11081 PC11044 PC11008
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1
VCC_CORE Place on CPU Back Side @ V09

PC11131

U23E@
22U_0603_6.3V6M PC11097 PC11082 PC11045 PC11009
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1 2 1
2
1

PC11132
22U_0603_6.3V6M PC11098 PC11083 PC11046 PC11010
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2 1 2 1

4
4

2
1

PC11133

U23E@
22U_0603_6.3V6M 2 1 PC11084 PC11047 PC11011
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

2
1
2
1
+VCCSA
PC11099 2 1 2 1
PC11134 PC11102 0.1U_0402_25V6

U23E@
22U_0603_6.3V6M 22U_0603_6.3V6M PC11085 PC11048

@EMI@
2
1

2 1 1U_0201_6.3V6M 1U_0201_6.3V6M

2
1
2 1 2 1 PC11012

2@
PC11135 PC11103 PC11100 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 0.1U_0402_25V6 PC11086 PC11049
2
1

1U_0201_6.3V6M 1U_0201_6.3V6M

@EMI@

2
1
2 1 2 1 2 1 PC11013
PC11104 22U_0603_6.3V6M
22U_0603_6.3V6M PC11101 PC11087 PC11050
2
1

0.1U_0402_25V6 1U_0201_6.3V6M 1U_0201_6.3V6M

2
1
@EMI@ PC11014
PC11105 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1

1
PC11015

2@
PC11106 22U_0603_6.3V6M
22U_0603_6.3V6M
2
1

2
1

2
1
@

PC11016
PC11107 PC11051 22U_0603_6.3V6M

2
1
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

PC11140
1
1

22U_0603_6.3V6M PC11017

+VCCGT
2@
2@

PC11108 PC11052 22U_0603_6.3V6M

2
1
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

U23E@
PC11144
2
1
2
1

22U_0603_6.3V6M PC11018
PC11109 PC11053 22U_0603_6.3V6M

2
1
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

U23E@
PC11141
2
1

22U_0603_6.3V6M PC11019
PC11054 22U_0603_6.3V6M

2
1
22U_0603_6.3V6M
2
1
1

@
PC11142
2
1
2@

22U_0603_6.3V6M PC11110 PC11020

3
3

22U_0603_6.3V6M PC11055 22U_0603_6.3V6M

2
1
22U_0603_6.3V6M
2
1
2
1

PC11143
2
1

U23E@
22U_0603_6.3V6M PC11111 PC11021
22U_0603_6.3V6M PC11056 22U_0603_6.3V6M

2
1
22U_0603_6.3V6M
2
1

@
PC11138
1

22U_0603_6.3V6M PC11112
2@

22U_0603_6.3V6M PC11057

2
1
22U_0603_6.3V6M
2
1

U23E@
PC11139
2
1

22U_0603_6.3V6M PC11113

Issued Date
22U_0603_6.3V6M PC11058
2
1

2 1 22U_0603_6.3V6M
U23E@ PC11145

Security Classification
2
1
1

22U_0603_6.3V6M PC11114
2@

1U_0201_6.3V6M PC11059 PC11022

2 1 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
2
1

PC11115
1U_0201_6.3V6M PC11060 PC11023
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

PC11116
1U_0201_6.3V6M PC11024
2 1 22U_0603_6.3V6M

PC11117
VCC_SA Place on CPU Back Side @ V09

1U_0201_6.3V6M

2015/07/27
2 1

PC11118
+VCCGT

1U_0201_6.3V6M
2 1

PC11119
1U_0201_6.3V6M
2 1

PC11120

2
2

1U_0201_6.3V6M
Compal Secret Data 2 1 2 1
Deciphered Date
2
1

22U_0603 * 9 (4 CPU back+8 outside)pcs + 1U_0201*7

@

PC11088 PC11061 PC11025

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1

PC11089 PC11062 PC11026

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC11063 PC11027
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PC11064 PC11028
2016/07/27
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1

PC11065 PC11029
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1

PC11066 PC11030
1U_0201_6.3V6M 22U_0603_6.3V6M
Size
Title

Date:

2 1
2
1

PC11067 PC11031
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
1

PC11068 PC11032
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
Document Number
2
1

PC11069 PC11033
Monday, June 06, 2016

1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2
1
22U_0603 * 29 pcs +1U_0201*12 pcs

1
1

PC11070 PC11034
VCC_GT Place on CPU Back Side @ V09

1U_0201_6.3V6M 22U_0603_6.3V6M
2
1

2
1

PC11071 PC11035
22U_0603_6.3V6M 22U_0603_6.3V6M
Sheet
2
1
2
1

PC11072 PC11036
Compal Electronics, Inc.

48

22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

2
1

of

PC11073 PC11037
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1

53

PC11074
22U_0603_6.3V6M
PWR-PROCESSOR_DECOUPLING
Rev
2.0
A
B
C
D
 5 4 3 2 1

PSI :
1 phase with DEM 0V to 0.8V
1 phase with CCM 1.2V to 1.8V
2 phase with CCM 2.4V to 5.5V
PSI <22>

EN High Threshold = 1.6V

<22>
+3VS

GPU_VID0

@VGA@ PR1202
10K_0402_5%

10K_0402_5%
2

2
@ PR1203

@VGA@ PR1201
0_0402_5%
D D
B+_VGA
unmount PRV5 for 2 phase select PL1201
VGA_EMI@

1
S SUPPRE_ 5A Z120 25M 0805
+3VS_DGPU_AON B+_VGA 2 1
B+

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
VGA@ PC1202

VGA@ PC1203

VGA@ PC1204

VGA@ PC1205
NOGC6@PR1204

@VGA_RF@ PC1206

PC1207
68P_0402_50V8J
0.1U_0402_25V6
1 1 1 1

1
EN_VGA 1 2

VGA@ PC1208
.1U_0402_16V7K
VGA@ PR1205 20K_0402_1%

2
1
20K_0402_1% @GC6@ PR1206 2 2 2 2
2 1 1 2
VREF_VGA_R DGPU_MAIN_EN <22,24>

@VGA_RF@
2
0_0402_5%
VGA@ PR1207 VGA@ PR1208
2K_0402_1% 20K_0402_1% @VGA@ PR1209
2 1 2 1 0_0603_5%
PSI_VGA UG1_VGA 1 2 UG1_VGA_R UG1_VGA_R
1

VGA@ PR1210
@VGA@ PR1211 PQ1205
18K_0402_1%

1
0_0603_5% AON6992_DFN5X6D-8-7
BST1_VGA 1 2 BST1_VGA_R

D1

G1
2

REFIN_VGA_R
PL1202
+VGA_CORE
1

VGA@ PC1209
1

1
LX1_VGA

VGA@
2700P_0402_50V7K VGA@ PC1210 7 1 4
@ PR1212 D2/S1

VID

PSI

EN

UGATE1

BOOT1
2

680P_0402_50V7K 4.7_1206_5%
VGA_EMI@
0_0402_5% 0.1U_0603_25V7K 2 3

G2
S2

S2

S2
REFADJ_VGA LX1_VGA

PR1213
6 20
2

REFADJ PHASE1 0.24UH_22A_20%_ 7X7X3_M

1 1 1

6
VGA@

330U_D1_2VY_R9M
330U_D1_2VY_R9M

330U_D1_2VY_R9M
1SNUB_VGA1 1
REFIN_VGA 7 19 LG1_VGA + PC1211 + PC1212 + PC1245

LG1_VGA
C REFIN LGATE1 @ PR1214 C

0_0402_5%
VREF_VGA PVCC_VGA 2 2 2

VGA_EMI@
8 PU1201 18 1 2
VREF PVCC +5VS

1
VGA@

1
1

PC1215
RT8812AGQW_WQFN20_3X3 VGA@ PC1214 VGA@
VGA@ PC1213 B+_VGA 2 1TON_VGA 9 17 LG2_VGA 1U_0603_10V6K PR1216
.1U_0603_25V7K
B+_VGA VGA@ PR1215 TON LGATE2
PR1214: OCP setting

2
2

VGA@
VGA@

VGA@
499K_0402_1%
from 50A to 25A

2
10 16 16.9K_0402_1%
RGND PHASE2

UGATE2
PGOOD

BOOT2
VSNS
GND

LX2_VGA
SS

PR1217 B+_VGA
100_0402_1%
21

11

12

13

14

15
1 2

1
VGA@ PC1201 B+_VGA
0.1U_0603_25V7K
SS_VGA

@ PR1219

2
0_0402_5% @VGA@ PR1218
1 2 NVVDD_GND_SENSE_R 0_0603_5%
<19> GND_SENSE_GPU BST2_VGA 1 2 BST2_VGA_R
1

@VGA@ PC1217

UG2_VGA_R
1

@VGA@ PC1216 @VGA@ PR1220

.1U_0402_16V7K 0_0603_5%
2

@ PR1221 1000P_0402_50V7K UG2_VGA 1 2 UG2_VGA_R

2

0_0402_5% PQ1206

1
1 2 NVVDD_SENSE_R AON6992_DFN5X6D-8-7
<19> VDD_SENSE_GPU

D1

G1
DGPU_PWROK <11,19,23,24>
PL1203
+VGA_CORE

VGA@
PR1222
100_0402_1% @VGA@ PR1223 7LX2_VGA 1 4
D2/S1

4.7_1206_5%
VGA_EMI@
1 2 10K_0402_5%
+VGA_CORE

2
2 1 +3VS 2 3

PR1224
G2
S2

S2

S2
B B
0.24UH_22A_20%_ 7X7X3_M

6
Pull high at HW side.(20150831) VGA@

1SNUB_VGA2 1
LG2_VGA

680P_0402_50V7K
VGA_EMI@
PC1218
+VGA_CORE Under GPU Core +VGA_CORE
GB4-128 package

2
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

H/L side Rds(on): 12.2mohm(Typ), 15mohm(Max)

VGA@ PC1219

VGA@ PC1221

VGA@ PC1224

VGA@ PC1225

VGA@ PC1227
VGA@ PC1220

VGA@ PC1223

VGA@ PC1228
VGA@ PC1222

VGA@ PC1226

Idsm: 11A@Ta=25C, 14A@Ta=70C

PC1230
PC1229

PC1231

PC1232
0.1U_0402_25V6
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1

1
1

1
1

CHOKE:0.36uH, DCR 1.4m ohm, L/2 over 36A

2

2
2

2
2

2
2

FSW = 245.55KHz
Iripple = 12.74A
@VGA_RF@
@VGA_RF@

@VGA_RF@

@VGA_RF@

OCP = 50A
OVP=Vout*(145%~155%)
1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K
1U_0402_16V6K

VGA@ PC1234

VGA@ PC1235

VGA@ PC1236
VGA@ PC1233

1
1

2
2

A +VGA_CORE Near GPU Core A

47U_0805_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
22U_0603_6.3V6M

VGA@ PC1239

VGA@ PC1243
VGA@ PC1237

VGA@ PC1238

VGA@ PC1240

VGA@ PC1241

VGA@ PC1242

VGA@ PC1244
1

1
1

1
2

2
2

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2014/12/31 Deciphered Date 2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NVIDIA VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 49 of 53
5 4 3 2 1
 5 4 3 2 1

D D

EN pin don't floating

If have pull down resistor at HW side, pls delete PR702 +1.35VGS_PGOOD
+1.35VGS_PGOOD <34>

B+_1.5V

VGA_EMI@

VGA_EMI@
VGA@ PR1302 PC1302
4.7_1206_5% 680P_0603_50V7K
1 2 SNUB_1.5V 1 2
PL1301
B+ B+_1.5V
PU1301 (Common Part)

@
1 2 2 9 PR1303
C IN PG 0_0603_5%
PC1305 SH00000Z200 C

10U_0805_25V6K
0.1U_0402_25V6
HCB2012KF-121T50_0805 3 1 BST_1.5V 1 2 BST_1.5V_R 1 2
2200P_0402_50V7K

PL1303
1

1
1

IN BS
@EMI@PC1304
VGA_EMI@PC1301

PC1303
VGA_EMI@

LDO_3V_1.5V LX_1.5V
2 4
IN LX
6
0.1U_0603_25V7K
1 4
+1.35VGSP
2
2

5 19 2 3

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VGA@
IN LX
1

1
@

7 20

PC1306

PC1307

PC1308

PC1309

PC1310
PR1301 VGA@ 1UH_6.6A_20%_5X5X3_M PR1309
GND LX
Rup

VGA@
8 14 FB_1.5V
0_0402_5%

2
GND FB 24.9K_0402_1%

1 VGA@ 2
2

ILMT_1.5V 18 17 LDO_3V_1.5V
change PL601 GND VCC
1

1
EN_1.5V
SM01000C000 to comm

VGA@

VGA@

VGA@

VGA@

VGA@
11 10
EN NC
@

PR1305
part SM01000P200 ILMT_1.5V
PC1311 FB = 0.6V
13 12 2.2U_0402_6.3V6M

VGA@ 2
ILMT NC PR1306
0_0402_5%
15 16
+3VALW Rdown
2

BYP NC 20K_0402_1%
21

VGA@ 2
PAD
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1

The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
PC1312
is pull low, floating or pull high 1U_0402_6.3V6K
VGA@ 2

Vout=0.6V* (1+Rup/Rdown)
=0.6*(1+(30.1/20))

VGA@ PR1307
B
1K_0402_1%
Vout=1.35V B

EN_1.5V

@
1 2 PJ1301
1.35V_PWR_EN <23,24>
JUMP_43X118
1 2
+1.35VGSP 1 2 +1.35VS_VRAM
1

PC1313
PR1308
0.22U_0402_10V6K
2

1M_0402_1%

22U_0603_6.3V6M
22U_0603_6.3V6M
VGA@ 2

1
1

PC11137
PC11136

2
2

VGA@
VGA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/04 Deciphered Date 2015/01/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE/CPU_CORE_NB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D471P
Date: Monday, June 06, 2016 Sheet 50 of 53
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1
request by HW P49 change PR1206 to 0 ohm 2015/11/10 SIV
D D

2 request by HW P50 change PR1307 to 1K ohm 2015/11/10 SIV

3 avoid 1V0 voltage drop P44 change PR705 to 15K ohm 2015/11/10 SIV

4
adjust charge current limit P40 change PR334 to 178K ohm 2015/11/10 SIV

reduce 5v ripple voltage P41 add PC423 on schematic 2015/11/10 SIV

6

7
adjust component bom structure of U23E P47 PQ1004->U23E@,PC1020->U23E@,PC1021->POP 2015/11/10 SIV

8 adjust DDR over current protect value P42 change PR502 to 17.8K ohm 2015/11/10 SIV
C C
9 request by part count P40,42-45 PR319,PR321,PR510,PR601,PR701,PR807 change to 0 ohm short pad
2015/11/10 SIV

10 change below value: PCI18->680P,PRI23->26.7K ohm,PRI14->64.9K ohm,

optimize cpu transient PRI42 ->59K ohm,PCI21->2200P,PRI49->649 ohm
P47/48 change pop and up pop CPU OUTPUT CAP location:
PC11138,PC11140,PC11142,PC11143->POP
2015/11/10 SIV
PC11126,PC11128,PC11129,PC11133->U23E@
11

12
request by EMI P40 PC317,PR318,PC304->POP
change PR312 to 2.2 ohm
2015/11/10 SIV

13 P40-50 PR318,PR403,PR406,PR503,PR515,PR703,PR804,PR1004,PR1007,PR1006,
PR1009,PR1213,PR1224,PR1302 ->POP 2015/11/10
request by RF
PC317,PC410,PC425,PC515,PC525,PC702,PC803,PC1009,PC1023PC1024, SIV
PC1029,PC1215,PC1218,PC1302->POP
14 reduce power consumption P40 Del PR335,Add:PR336,PQ307,PQ308 2015/11/13 SIV
15 charger ac in detect P40 change PC306 to 0.1uA 2015/11/16 SIV
B B

16 reduce Aucostic noise P40,47,49 Change 10u_0805(SE00000QK00) to 10u_0603(SE00000X200) 2015/12/05 SIT

17
When battery connector first touch positive pin can't P41 Reserve PC428 and change PR409 to 100K pull high +VL 2015/12/14 SIT
power on

18
reduce Aucostic noise P47 change PC1006 from 33u to 68u, del PC1016 2015/12/18 SIT
19 request by EMI P38 change PL102 and PL102 PN to SM010014520 2015/12/23 SIT
20 reduce ripple current P41 change PC419,PC422,PC423 from 22u 0603 to 47u 0805 2016/01/19 SVT
change PL404 from 1.5uH to 3.3uH
21 solve ISL95521 didn't protect function (dc prochot) P41 change PU301 from ISL95521 to ISL95520 2016/01/19 SVT
change PR306 from 392K to 287K

22 resive PC1016 for acustic noise P47 resive PC1016 for acustic noise 2016/04/21 CIUY7-SIT
PRI53 form 33.2k to 30.3k
23
Modify PRI53,PRI64,PRI42 for cpu transient test PRI42 form 59k to 56.2k
P46 PRI64 form 90.9k to 100k 2016/04/21 CIUY7-SIT
A A
PQ1001 from SB00000S800 to SB00000JZ00
24
change for cost priority change AOS to
main source on PQ1001 and PQ1002
P46 PQ1002 from SB00000SD00 to SB000017Q00 2016/06/03 CIUY7-SVT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z_BDW
Date: Monday, June 06, 2016 Sheet 51 of 53
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

Item Reason for change PG# Modify List
for HW Date Phase

1 27

2 33
D D

33
3 35

4 11

5 32

6 18

7 32

C 8 32 C

10 32

11 32

12 27

13 12
34

14 35
B 36 B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (HW)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D475P
Date: Monday, June 06, 2016 Sheet 52 of 53
5 4 3 2 1
 A B C D E

Conn. Moat 1
JIOS1
1
LEDS1 HGNDAS 2
White 3 2
RS175 3
MIC/HP HGNDBS 4
BATT_CHG_LED#S 1 2 2 5 4
FDS1 FDS2 100_0402_5% HPOUT_LS 6 5
ZZZ 1 1 1 HPOUT_RS 7 6
BATT_LOW _LED#S +3VLPS PLUG_INS 7
1 RS176 2 3 8
330_0402_5% 9 8
FDS3 FDS4 BATT_CHG_LED#S 10 9
1 1 Amber 11 10
+3VLPS BATT_LOW _LED#S 11
HT-210UD5-BP5_AMBER-W HITE BATT LED 12
13 12
1 LS-D471P 13 1
PCIE_CTX_C_DRX_P9S 14
DA800169000 PCIE_CTX_C_DRX_N9S 15 14
16 15
SW S1 PCIE_CRX_DTX_P9S 17 16
NOVO#S 1 3 PCIE_CRX_DTX_N9S 18 17
HS1 HS3 HS2 HS4 HS5 19 18
HOLEA HOLEA HOLEA HOLEA HOLEA CardReader CLK_PCIE_CRS
CLK_PCIE_CR#S
20
21
19
20
21

2
22
ESD 2 4 +3VSS 23 22
1

1
DS24 CRCLK_REQ#S 24 23
H_2P6X3P2N H_2P6X3P2N H_2P3N @ESD@ NTC311-EA1T-A160T_4P PCI_RST#S 25 24
NOVO#S 26 25
MESC5V02BD03 3P C/A SOT23 ESD 27 26

1
28 GND
H_2P5 H_3P0 GND
ACES_51522-02601-001
ME@
SP01001AO00
AGNDS

+3VSS
Card Reader 1
CCS109 2 4.7U_0603_6.3V6K +AV12S +DV12SS

1 1 1 1
CCS105 CCS106 CCS107 CCS108
2 1 2 UCRS1 2
CCS110 0.1U_0201_10V6K 9

0.1U_0201_10V6K

0.1U_0201_10V6K
+DV33_18S 15 3V3_IN 2 2 2 2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
+AV12S 7 DV33_18
+Card_3V3S +DV12SS 11 AV12
DV12_S
+Card_3V3S LCS31 @ 2 0_0603_5% +Card_3V3_RS 10
Card_3V3 25
1 2 8 GND Close to UCR1
RCS76 6.2K_0402_1% RREF Close to UCR1
PCIE_CTX_C_DRX_P9S
PCIE_CTX_C_DRX_N9S
1
2 HSIP SP1
12
13
RCS68 @
RCS69 @
1
1
2 0_0402_5%
2 0_0402_5%
SD_D1S
SD_D0S
EMI EMI@
PCIE_CRX_DTX_P9S CCS111 1 2 0.1U_0402_25V6 PCIE_CRX_C_DTX_P9S 5 HSIN SP2 14 SD_CLK_RS RCS652 1 33_0402_5% SD_CLKS
PCIE_CRX_DTX_N9S CCS112 1 2 0.1U_0402_25V6 PCIE_CRX_C_DTX_N9S 6 HSOP SP3 16 RCS56 @ 1 2 0_0402_5% SD_CMDS
HSON SP4 17 RCS57 @ 1 2 0_0402_5% SD_D3S
SP5 1
18 RCS58 @ 1 2 0_0402_5% SD_D2S EMI@ +DV33_18S
CLK_PCIE_CRS 3 SP6 CCS13
CLK_PCIE_CR#S 4 REFCLKP 5.6P 50V D NPO 0402
REFCLKN 2
2

1U_0402_6.3V6K
PCI_RST#S 23 20 SD_W PS CCS103
PERST# SP7

2 1
CRCLK_REQ#S

SD_GPIO1S
24

19
CLK_REQ# SD_CD#
21

22
SD_CD#S
EMI 1
+3VSS GPIO NC
RCS64 10K_0402_5%
RTS5220-GRT_QFN24_4X4
SA000085G00
3 3

+Card_3V3S
Audio Combo Jack ME@ JHPS1 SD_CD#S 1
JSDS1
CD_SW
HGNDAS 3 SD_D2S 2
HPOUT_LS 1 SD_D3S 3 DAT2
SD_CMDS 4 CD/DAT3
PLUG_INS 5 5 CMD
6 6 VSS
HPOUT_RS 2 SD_CLKS 7 VDD
HPOUT_LS
ESD SCA00002900 CLK
ZZZ5 @
HGNDBS 4 8
7 SD_D0S 9 VSS 13
HPOUT_RS HPOUT_LS GND SD_D1S DAT0 GND_SW
CCS1131 1 0.1U_0201_10V6K 10 12
SINGA_2SJ3108-000111F CCS114 SD_W PS 11 DAT1 GND_SW
4.7U_0603_6.3V6K

HGNDBS HPOUT_RS DC23000C400 WP_SW

T-SOL_156-1001902600 BARCODE_5X5
HGNDAS HGNDBS 2 2

For EMI HGNDAS

ME@

AGNDS
3

2
L03ESDL5V0CC3-2_SOT23-3

L03ESDL5V0CC3-2_SOT23-3

1 EMI@ 1 EMI@ 1 EMI@ 1 EMI@ DAS1 DAS2

CAS31 CAS32 CAS33 CAS34 ESD@ @ESD@
For EMI
RAS211 2 0_0402_5%
470P_0402_50V7K
470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

4 2 2 2 2 4

RAS241 2 0_0402_5%
1

AGNDS RAS251 2 0_0402_5%

Moat Security Classification Compal Secret Data Compal Electronics, Inc.
AGNDS 2011/05/17 2012/05/30 Title
Issued Date Deciphered Date
Moat THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Combo jack & CR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-D471P 2.0
AGNDS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
GNDS
Date: Monday, June 06, 2016 Sheet 53 of 53
A B C D E