Test on Digital design using Verilog
Total Marks : 40
1. Which of the following statement(s) is/are true about the following verilog module?
(2 marks)
module fun (f,a,b,c,d);
input a,b,c,d;
output reg f;
always @(*)
begin
f=1’b0;
casex({a,b,c,d})
4’b11xx, 4’bx10x, 4’b1x00: f=1’b1;
endcase
end
endmodule
(a) The module realizes a sequential circuit and variable f infers a D-latch during
synthesis.
(b) The module realizes a pure combinational circuit.
(c) For the input {a,b,c,d} = 4’b1000, the function will provide an output logic 1
during simulation.
(d) None of the above.
Ans: option c
2. Given the following verilog code: (1 mark)
integer x,y;
reg clk;
always #5 clk=~clk;
initial begin
#5 clk=1’b0; x=0;
#70 $finish;
end
initial begin
#5 y=17;
forever #8 x=x+y;
end
The final value of x will be 136 .
3. Design a combinational logic subsystem with five inputs, I4, I3, I2, I1, I0, and three
outputs, O2, O1, O0, which behaves as follows. The outputs indicate the count of the inputs
that are currently true. For example, if I4 and I3 are 0, and I2, I1, and I0 are 1, then O2, O1,
O0 would be 011 (i.e., three of the five inputs are 1). Develop the Verilog code using only
Data Flow Modeling (4 marks)
Code:
module test_ex4(i0,i1,i2,i3,i4,o0,o1,o2);
input i0, i1, i2, i3, i4;
output o0, o1, o2;
assign o2= (i0&i1&i2&i3)|(i0&i1&i3&i4)|(i1&i2&i3&i4)|(i0&i2&i3&i4)|(i0&i1&i2&i4);
assign o1= (i0&i1&~i3&~i4) |(i0&~i2&i3&~i4) | (~i1&i2&i3&~i4) | (~i0&i1&i3&~i4) |
(~i0&i1&i2&~i3) | (i0&~i1&i2&~i3) | (~i0&~i1&i2&i4) | (~i0&~i2&i3&i4) | (i1&~i2&~i3&i4)
| (i0&~i1&~i2&i4);
assign o0= (~i0&i1&~i2&~i3&~i4) | (i0&~i1&~i2&~i3&~i4) |(~i0&~i1&~i2&i3&~i4) |
(i0&i1&~i2&i3&~i4) |(~i0&i1&i2&i3&~i4) + (i0&~i1&i2&i3&~i4) |
(~i0&~i1&i2&~i3&~i4) | (i0&i1&i2&~i3&~i4) |
(~i0&~i1&~i2&~i3&i4) | (i0&i1&~i2&~i3&i4) | (~i0&i1&~i2&i3&i4) |
(i0&~i1&~i2&i3&i4) | (~i0&~i1&i2&i3&i4) | (i0&i1&i2&i3&i4) |
(~i0&i1&i2&~i3&i4) | (i0&~i1&i2&~i3&i4)
endmodule
4. Design a 4 bit adder/ subtractor circuit. Develop the Verilog code in Structural Modeling
(4 marks)
Code:
module rc_N #(parameter N=4)(input [N-1:0]a,input [N-1:0]b,input cin, output [N-
1:0]sum, output cout);
wire [N:0]c;
genvar i;
assign c[0]=cin;
assign cout=c[N];
generate
for(i=0;i<N;i=i+1)
begin
full_adder aa(.a(a[i]),.b(b[i]),.c_in(c[i]),.sum(sum[i]),.c_out(c[i+1]));
end
endgenerate
endmodule
simulation:
5. Design a 64x8 RAM in behavioral modeling. Use $readmemb and $readmemh system
functions to read the contents from the memory text file (4 marks)
reg [7:0] mem [0:63];
$readmemb(“text.txt”, mem);
module ram64X8(input clk,we,input di,input[5:0]a,output do
);
reg[7:0]mem[0:63];
always @(posedge clk)
if(we)
initial
$readmemb(“C:/Users/naren/OneDrive/Desktop/vivado
projects/projects/rom_10x32bit/text.txt”, mem);
endmodule
6. Write a verilog code to implement Euclidean algorithm. Description of the Euclidean
algorithm is as follows, (5 marks)
a. Input: two positive integers, a and b.
b. Output: The greatest common divisor, g, of a and b.
c. Internal computation:
i. If a<b, exchange a and b.
ii. Divide a by b and get the remainder, r. If r=0, report b as the GCD of a
and b
iii. Else replace a by b and replace b by r. Return to the previous step.
Code:
module gcd#( parameter W = 16 ) // parameterize for better reuse
(
input [W-1:0] a,b,
output reg [W-1:0] g
);
reg [W-1:0] swap;
reg r,bcd;
always @(*)
begin
if ( a < b )
swap = a;
a = b;
b = swap;
else if ( r=a/b )
if(r==0)
b=gcd(a,b);
else
a=b;
b=r;
end
g = a;
end
endmodule
