AXI to AXI Asynchronous Bridge

Cycle Model
Version 9.0.0

User Guide
Non-Confidential

Copyright © 2016 ARM Limited. All rights reserved.

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 AXI to AXI Asynchronous Bridge Cycle Model
User Guide
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 Contents

Chapter 1.
Using the Model in SoC Designer
Asynchronous AXI to AXI Bridge Model Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Asynchronous AXI to AXI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Model Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Component Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Component Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Available Profiling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

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 Preface

A Cycle Model component is a library that is generated through Cycle Model Studio™. The
Cycle Model then can be used within a virtual platform tool, for example, SoC Designer.

About This Guide

This guide provides all the information needed to configure and use this Cycle Model in SoC
Designer.

Audience
This guide is intended for experienced hardware and software developers who create compo-
nents for use with SoC Designer. You should be familiar with the following products and tech-
nology:

• SoC Designer
• Hardware design verification
• Verilog or SystemVerilog programming language

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Conventions
This guide uses the following conventions:

Convention Description Example

courier Commands, functions, sparseMem_t SparseMemCreate-

variables, routines, and New();
code examples that are set
apart from ordinary text.
italic New or unusual words or Transactors provide the entry and exit
phrases appearing for the points for data ...
first time.
bold Action that the user per- Click Close to close the dialog.
forms.
<text> Values that you fill in, or <platform>/ represents the name of
that the system automati- various platforms.
cally supplies.
[ text ] Square brackets [ ] indicate $CARBON_HOME/bin/modelstudio
optional text. [ <filename> ]

[ text1 | text2 ] The vertical bar | indicates $CARBON_HOME/bin/modelstudio

“OR,” meaning that you [<name>.symtab.db |
can supply text1 or text 2. <name>.ccfg ]

Also note the following references:

• References to C code implicitly apply to C++ as well.
• File names ending in .cc, .cpp, or .cxx indicate a C++ source file.

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Further reading
This section lists related publications.

The following publications provide information that relate directly to SoC Designer:

• SoC Designer Installation Guide

• SoC Designer User Guide
• SoC Designer Standard Component Library Reference Manual
• SoC Designer AHBv2 Protocol Bundle User Guide
The following publications provide reference information about ARM® products:

• AMBA Design Kit Technical Reference Manual

• AMBA Specification
• AMBA AHB-Lite Protocol Specification
• AMBA AHB Protocol Specification
• Architecture Reference Manual
See http://infocenter.arm.com/help/index.jsp for access to ARM documentation.

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Glossary
Table 1:
AMBA Advanced Microcontroller Bus Architecture. The ARM open standard
on-chip bus specification that describes a strategy for the interconnec-
tion and management of functional blocks that make up a System-on-
Chip (SoC).
AHB Advanced High-performance Bus. A bus protocol with a fixed pipeline
between address/control and data phases. It only supports a subset of
the functionality provided by the AMBA AXI protocol.
APB Advanced Peripheral Bus. A simpler bus protocol than AXI and AHB.
It is designed for use with ancillary or general-purpose peripherals
such as timers, interrupt controllers, UARTs, and I/O ports.
AXI Advanced eXtensible Interface. A bus protocol that is targeted at high
performance, high clock frequency system designs and includes a num-
ber of features that make it very suitable for high speed sub-micron
interconnect.
Cycle Model A software object created by the Cycle Model Studio from an RTL
design. The Cycle Model contains a cycle- and register-accurate model
of the hardware design.
Cycle Model Graphical tool for generating, validating, and executing hardware-
Studio accurate software models. It creates a Cycle Model, and it also takes a
Cycle Model as input and generates a component that can be used in
SoC Designer, Platform Architect, or Accellera SystemC for simula-
tion.
CASI Cycle Accurate Simulation Interface, is based on the SystemC commu-
nication library and manages the interconnection of components and
communication between components.
CADI Cycle Accurate Debug Interface, enables reading and writing memory
and register values and also provides the interface to external debug-
gers.
CAPI Cycle Accurate Profiling Interface, enables collecting historical data
from a component and displaying the results in various formats.
Component Building blocks used to create simulated systems. Components are
connected together with unidirectional transaction-level or signal-level
connections.
ESL Electronic System Level. A type of design and verification methodol-
ogy that models the behavior of an entire system using a high-level lan-
guage such as C or C++.
HDL Hardware Description Language. A language for formal description of
electronic circuits, for example, Verilog.
RTL Register Transfer Level. A high-level hardware description language
(HDL) for defining digital circuits.

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 Table 1:
SoC Designer The full name is SoC Designer. A high-performance, cycle accurate
simulation framework which is targeted at System-on-a-Chip hardware
and software debug, as well as architectural exploration.
SystemC SystemC is a single, unified design and verification language that
enables verification at the system level, independent of any detailed
hardware and software implementation, as well as enabling co-verifi-
cation with RTL design.
Transactor Transaction adaptors. You add transactors to your component to con-
nect your component directly to transaction level interface ports for
your particular platform.

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 Chapter 1

Using the Model in SoC Designer

This chapter describes the functionality of the Model, and how to use it in SoC Designer. It con-
tains the following sections:

• Asynchronous AXI to AXI Bridge Model Overview

• Component Ports
• Component Parameters
• Debug Features
• Available Profiling Data

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1.1 Asynchronous AXI to AXI Bridge Model Overview
The Asynchronous AXI to AXI Bridge Cycle Model enables two AXI clock domains to com-
municate.
This is illustrated in Figure 1-1.

Domain 1 AXI to AXI Domain 2

Asynchronous
AXI AXI
bridge
Master Master

AXI AXI
Master Master

AXI AXI
Slave Slave
AXI Slave AXI Master
interface interface

Figure 1-1 Connection of AXI Subsystems through a Asynchronous AXI to AXI Bridge
The available models are described in the next section.

1.1.1 Asynchronous AXI to AXI Bridge

The AXI to AXI Asynchronous Bridge is provided in three versions that support different data
bus widths:
Table 1-1 Asynchronous AXI to AXI Bridge Components

Component Description

CM_Bridge_Axi_Axi_ASync_32 Converts transactions for a 32-bit wide data bus.

CM_Bridge_Axi_Axi_ASync_64 Converts transactions for a 64-bit wide data bus.

CM_Bridge_Axi_Axi_ASync_128 Converts transactions for a 128-bit wide data bus.

Figure 1-2 shows a simple configuration using the Asynchronous AXI to AXI Bridge.

Domain 1 Domain 2
AXI AXI
AXI AXI
Master Master

AXI AXI to AXI AXI

AXI AXI Asynchronous AXI AXI
Master Master
bridge
AXI AXI
AXI AXI
Slave Slave
AXI Slave AXI Master
interface interface

Figure 1-2 AXI to AXI Asynchronous Bridge Configuration

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1.1.2 Model Features
The Asynchronous AXI to AXI Bridges provide the following features:

• Support for 32-, 64, and 128-bit data bus widths.

• Channel-specific variable-depth payload buffers.
• FIFO buffer depth set to 8 for each AXI channel.

1.2 Component Ports

Table 1-2 describes the ESL ports that are exposed in SoC Designer for the Asynchronous AXI
to AXI Bridge.
Table 1-2 ESL Component Ports

ESL Port Description Direction Type

ACLKS Slave interface clock. This clock times all bus Input Clock slave
transfers. All signal timings on the Slave inter-
face are related to the rising edge of ACLKS.
ARESETSn Reset port for resetting the Slave interface. Input Signal slave
axi_s AXIv2 transaction slave port. Input Transaction
slave
ACLKM Master interface clock. This clock times all bus Input Clock slave
transfers. All signal timings on the Master inter-
face are related to the rising edge of ACLKM.
ARESETMn Reset port for resetting the Master interface. Input Signal slave
axi_m AXIv2 transaction master port. Output Transaction
master
clk-in Input clock. The component is clocked at the fre- Input Clock slave
quency of the clock connected to the clk-in port.
If the clk-in port is not connected, clocking is
taken from SoC Designer System Properties.
If it is connected, then it must be connected to
the fastest clock. For example, if ACLKM is the
faster domain, then ACLKM and clk-in should be
connected to the same source.

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1.3 Component Parameters
You can change the settings of all the component parameters in SoC Designer Canvas, and of
some of the parameters in SoC Designer Simulator. Table 1-3 describes the component parame-
ters that are available for the Asynchronous AXI to AXI Bridge.

Parameters that may be modified at runtime are identified with Yes in the Runtime column, oth-
erwise the parameter values are fixed and must be set before the start of simulation.
Table 1-3 Component Parameters

Allowed Default
Name Description Runtime
Values Value
Align Waveforms When set to true, waveforms dumped true, false true No
from Cycle Model components are
aligned with the SoC Designer simu-
lation time. The reset sequence, how-
ever, is not included in the dumped
data.
When false, the reset sequence is
dumped to waveform data, however,
the component time is not aligned
with the SoC Designer time.
axi_m Enable Debug When set to true, writes AXI master true, false false Yes
Messages debug messages to the SoC Designer
output window.

axi_s axi_size[0-5] 1 These parameters are obsolete and 0x0 - size 0 default is No
should be left at their default values.2 0xFFFFFFFF 0x100000000, size
1-5 default is 0x0
axi_s axi_start[0-5] 0x0 - 0x0 No
0xFFFFFFFF
axi_s Enable Debug When set to true, writes AXI slave true, false false Yes
Messages debug messages to the SoC Designer
output window.
Carbon DB Path Sets the directory path to the database Not Used empty No
file.
Dump Waveforms Whether SoC Designer dumps wave- true, false false Yes
forms for this component.
Enable Debug Enable or disable the capture of debug true, false false Yes
Messages messages for the component.

Waveform File 3 Name of the waveform file. string arm_CM_Bridge_ No

Axi_Axi_ASync_<
data_width>.vcd
Waveform Format The format of the waveform dump VCD, FSDB VCD No
file.
Waveform Timescale Sets the timescale to be used in the Many values 1 ns No
waveform. in drop-down

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 1. The square brackets specify that a range of numbers that are available. For example, the parameter name for
the start addresses “axi_s axi_start[0-5]” will be expanded to 6 parameter name combinations that range from
“axi_s axi_start 0” to “axi_s axi_start 5”. The size of a memory region depends on the “axi_s axi_start” and
“axi_s axi_size” parameters. The end address is calculated as Start + Size -1. The size of the memory region
must not exceed the value of 0x100000000. If the sum of Start+Size is greater than 0x100000000, the size of
the memory region is reduced to the difference: 0x100000000-Start.
2. ARM recommends using the Memory Map Editor (MME) in SoC Designer, which provides centralized view-
ing and management of the memory regions available to the components in a system. For information about
migrating existing systems to use the MME, refer to Chapter 9 of the SoC Designer User Guide.
3. When enabled, SoC Designer writes waveforms to the waveform file at the following times: when the wave-
form buffer fills, when validation is paused and when validation finishes, and at the end of each validation run.

1.4 Debug Features

The Asynchronous AXI to AXI Bridge has a debug interface (CADI) that allows you to track
the values of the applicable AXI signals. A view can be accessed in SoC Designer by right-
clicking on the component and choosing the appropriate menu entry.

Transactions can be visualized using the transaction monitors attached to connections. By right
clicking on any of the connections in SoC Designer, a transaction monitor probe can be
attached.

1.4.1 Register Information

The available signals are listed in the following sections:

• AXI Slave Port Signals Registers

• AXI Master Port Signals Registers

1.4.1.1 AXI Slave Port Signals Registers

Table 1-4 shows the AXI slave port signals. See the ARM AMBA AXI Protocol Specification for
more information about these signals.

Table 1-4 AXI Slave Port Signal Registers

Name Description Type

ARIDS The read address ID. read-only

ARADDRS The read address. read-only
ARVALIDS Indicates whether the read address is available. read-only
ARREADYS Indicates whether the slave is ready to accept the read address. read-only
ARLENS The burst length. read-only
ARSIZES The burst size. read-only
ARBURSTS The burst type. read-only
ARLOCKS The lock type. read-only
ARCACHES The cache type. read-only
ARPROTS The protection type. read-only
AWIDS The write address ID. read-only

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 Table 1-4 AXI Slave Port Signal Registers (continued)

Name Description Type

AWADDRS The write address. read-only

AWVALIDS Indicates whether the write address is available. read-only
AWREADYS Indicates whether the slave is ready to accept the write address. read-only
AWLENS The burst length. read-only
AWSIZES The burst size. read-only
AWBURSTS The burst type. read-only
AWLOCKS The lock type. read-only
AWCACHES The cache type. read-only
AWPROTS The protection type. read-only
WIDS The write ID tag. read-only
WDATAS The write data. read-only
WSTRBS The write strobes. read-only
WLASTS The last transfer in a write burst. read-only
WVALIDS Indicates whether the write data and strobes are available. read-only
WREADYS Indicates whether the slave is ready to accept the write data. read-only
RIDS The read ID tag. read-only
RDATAS The read data. read-only
RLASTS The last transfer in a read burst. read-only
RVALIDS Indicates whether the read data is available. read-only
RREADYS Indicates whether the master is ready to accept the read data read-only
and response information.
RRESPS The read response. read-only
BIDS The response ID. read-only
BRESPS The write response. read-only
BVALIDS Indicates whether the write response is available. read-only
BREADYS Indicates whether the master is ready to accept the response read-only
information.
AWUSERS Additional master interface signals for the write address chan- read-only
nel.
WUSERS Additional master interface signals for the write data channel. read-only
BUSERS Additional master interface signals for the write response chan- read-only
nel.
ARUSERS Additional master interface signals for the read address chan- read-only
nel.
RUSERS Additional master interface signals for the read data channel. read-only

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1.4.1.2 AXI Master Port Signals Registers
Table 1-5 shows the AXI master port signals. See the ARM AMBA AXI Protocol Specification
for more information about these signals.

Table 1-5 AXI Master Port Signal Registers

Name Description Type

ARIDM The read address ID. read-only

ARADDRM The read address. read-only
ARVALIDM Indicates whether the read address is available. read-only
ARREADYM Indicates whether the slave is ready to accept the read address. read-only
ARLENM The burst length. read-only
ARSIZEM The burst size. read-only
ARBURSTM The burst type. read-only
ARLOCKM The lock type. read-only
ARCACHEM The cache type. read-only
ARPROTM The protection type. read-only
AWIDM The write address ID. read-only
AWADDRM The write address. read-only
AWVALIDM Indicates whether the write address is available. read-only
AWREADYM Indicates whether the slave is ready to accept the write address. read-only
AWLENM The burst length. read-only
AWSIZEM The burst size. read-only
AWBURSTM The burst type. read-only
AWLOCKM The lock type. read-only
AWCACHEM The cache type. read-only
AWPROTM The protection type. read-only
WIDM The write ID tag. read-only
WDATAM The write data. read-only
WSTRBM The write strobes. read-only
WLASTM The last transfer in a write burst. read-only
WVALIDM Indicates whether the write data and strobes are available. read-only
WREADYM Indicates whether the slave is ready to accept the write data. read-only
RIDM The read ID tag. read-only
RDATAM The read data. read-only
RLASTM The last transfer in a read burst. read-only
RVALIDM Indicates whether the read data is available. read-only

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 Table 1-5 AXI Master Port Signal Registers (continued)

Name Description Type

RREADYM Indicates whether the master is ready to accept the read data read-only
and response information.
RRESPM The read response. read-only
BIDM The response ID. read-only
BRESPM The write response. read-only
BVALIDM Indicates whether the write response is available. read-only
BREADYM Indicates whether the master is ready to accept the response read-only
information.
AWUSERM Additional master interface signals for the write address chan- read-only
nel.
WUSERM Additional master interface signals for the write data channel. read-only
BUSERM Additional master interface signals for the write response chan- read-only
nel.
ARUSERM Additional master interface signals for the read address chan- read-only
nel.
RUSERM Additional master interface signals for the read data channel. read-only

1.5 Available Profiling Data

This model does not provide profiling streams, and hence, does not provide profiling informa-
tion. Transaction related information can be retrieved from the respective bus components.

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