Cortex-M0+ instruction set PM0223

3 Cortex-M0+ instruction set

3.1 Instruction set summary

The processor implements a version of the Thumb instruction set. Table 14 lists the
supported instructions.
In Table 14
• Angle brackets, <>, enclose alternative forms of the operand.
• Braces, {}, enclose optional operands and mnemonic parts.
• The Operands column is not exhaustive.
For more information on the instructions and operands, see the instruction descriptions.

Table 14. Cortex-M0+ instructions

Mnemonic Operands Brief description Flags Section

ADCS {Rd,} Rn, Rm Add with Carry N,Z,C,V 3.5.1 on page 54.
ADD{S} {Rd,} Rn, <Rm|#imm> Add N,Z,C,V 3.5.1 on page 54.
PC-relative Address to
ADR Rd, label - 3.4.1 on page 46.
Register
ANDS {Rd,} Rn, Rm Bitwise AND N,Z 3.5.2 on page 56.
ASRS {Rd,} Rm, <Rs|#imm> Arithmetic Shift Right N,Z,C 3.5.3 on page 57.
B{cc} label Branch {conditionally} - 3.6.1 on page 66.
BICS {Rd,} Rn, Rm Bit Clear N,Z 3.5.2 on page 56.
BKPT #imm Breakpoint - 3.7.1 on page 69.
BL label Branch with Link - 3.6.1 on page 66.
Branch indirect with
BLX Rm - 3.6.1 on page 66.
Link
BX Rm Branch indirect - 3.6.1 on page 66.
CMN Rn, Rm Compare Negative N,Z,C,V 3.5.4 on page 59.
CMP Rn, <Rm|#imm> Compare N,Z,C,V 3.5.4 on page 59.
Change Processor
CPSID i State, Disable - 3.7.2 on page 70.
Interrupts
Change Processor
CPSIE i State, Enable - 3.7.2 on page 70.
Interrupts
DMB - Data Memory Barrier - 3.7.3 on page 71.
Data Synchronization
DSB - - 3.7.4 on page 72.
Barrier
EORS {Rd,} Rn, Rm Exclusive OR N,Z 3.5.2 on page 56.

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Table 14. Cortex-M0+ instructions (continued)

Mnemonic Operands Brief description Flags Section

Instruction
ISB - Synchronization - 3.7.5 on page 73.
Barrier
Load Multiple
LDM Rn{!}, reglist registers, increment - 3.4.5 on page 50.
after
Load Register from
LDR Rt, label - 3.4.2 on page 47.
PC-relative address
Load Register with
LDR Rt, [Rn, <Rm|#imm>] - 3.4.2 on page 47.
word
Load Register with
LDRB Rt, [Rn, <Rm|#imm>] - 3.4.2 on page 47.
byte
Load Register with
LDRH Rt, [Rn, <Rm|#imm>] - 3.4.2 on page 47.
halfword
Load Register with
LDRSB Rt, [Rn, <Rm|#imm>] - 3.4.2 on page 47.
signed byte
Load Register with
LDRSH Rt, [Rn, <Rm|#imm>] - 3.4.2 on page 47.
signed halfword
LSLS {Rd,} Rn, <Rs|#imm> Logical Shift Left N,Z,C 3.5.3 on page 57.
LSRS {Rd,} Rn, <Rs|#imm> Logical Shift Right N,Z,C 3.5.3 on page 57.
MOV{S} Rd, Rm Move N,Z 3.5.5 on page 60.
Move to general
MRS Rd, spec_reg register from special - 3.7.6 on page 74.
register
Move to special
MSR spec_reg, Rm register from general N,Z,C,V 3.7.7 on page 75.
register
MULS Rd, Rn, Rm Multiply, 32-bit result N,Z 3.5.6 on page 61.
MVNS Rd, Rm Bitwise NOT N,Z 3.5.5 on page 60.
NOP - No Operation - 3.7.8 on page 76.
ORRS {Rd,} Rn, Rm Logical OR N,Z 3.5.2 on page 56.
Pop registers from
POP reglist - 3.4.6 on page 52.
stack
Push registers onto
PUSH reglist - 3.4.6 on page 52.
stack
REV Rd, Rm Byte-Reverse word - 3.5.7 on page 62.
Byte-Reverse packed
REV16 Rd, Rm - 3.5.7 on page 62.
halfwords
Byte-Reverse signed
REVSH Rd, Rm - 3.5.7 on page 62.
halfword
RORS {Rd,} Rn, Rs Rotate Right N,Z,C 3.5.3 on page 57.

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Table 14. Cortex-M0+ instructions (continued)

Mnemonic Operands Brief description Flags Section

RSBS {Rd,} Rn, #0 Reverse Subtract N,Z,C,V 3.5.1 on page 54.

SBCS {Rd,} Rn, Rm Subtract with Carry N,Z,C,V 3.5.1 on page 54.
SEV - Send Event - 3.7.9 on page 77.
Store Multiple
STM Rn!, reglist registers, increment - 3.4.5 on page 50.
after
Store Register as
STR Rt, [Rn, <Rm|#imm>] - 3.4.2 on page 47.
word
STRB Rt, [Rn, <Rm|#imm>] Store Register as byte - 3.4.2 on page 47.
Store Register as
STRH Rt, [Rn, <Rm|#imm>] - 3.4.2 on page 47.
halfword
SUB{S} {Rd,} Rn, <Rm|#imm> Subtract N,Z,C,V 3.5.1 on page 54.
3.7.10 on page
SVC #imm Supervisor Call -
78.
SXTB Rd, Rm Sign extend byte - 3.5.8 on page 63.
SXTH Rd, Rm Sign extend halfword - 3.5.8 on page 63.
Logical AND based
TST Rn, Rm N,Z 3.5.9 on page 64.
test
UXTB Rd, Rm Zero extend a byte - 3.5.8 on page 63.
Zero extend a
UXTH Rd, Rm - 3.5.8 on page 63.
halfword
WFE - Wait For Event - 3.7.11 on page 79.
3.7.12 on page
WFI - Wait For Interrupt -
80.

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3.2 Intrinsic functions

ISO/IEC C code cannot directly access some Cortex-M0+ instructions. This section
describes intrinsic functions that can generate these instructions, provided by the CMSIS
and that might be provided by a C compiler. If a C compiler does not support an appropriate
intrinsic function, you might have to use inline assembler to access the relevant instruction.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C
code cannot directly access:

Table 15. CMSIS intrinsic functions to generate some Cortex-M0+ instructions

Instruction CMSIS intrinsic function
CPSIE i void __enable_irq(void)

CPSID i void __disable_irq(void)

ISB void __ISB(void)

DSB void __DSB(void)

DMB void __DMB(void)

NOP void __NOP(void)

REV uint32_t __REV(uint32_t int value)

REV16 uint32_t __REV16(uint32_t int value)

REVSH uint32_t __REVSH(uint32_t int value)

SEV void __SEV(void)

WFE void __WFE(void)

WFI void __WFI(void)

The CMSIS also provides a number of functions for accessing the special registers using
MRS and MSR instructions
:

Table 16. CMSIS intrinsic functions to access the special registers

Special register Access CMSIS function
Read uint32_t __get_PRIMASK (void)
PRIMASK
Write void __set_PRIMASK (uint32_t value)
Read uint32_t __get_CONTROL (void)
CONTROL
Write void __set_CONTROL (uint32_t value)
Read uint32_t __get_MSP (void)
MSP void __set_MSP (uint32_t
Write
TopOfMainStack)
Read uint32_t __get_PSP (void)
PSP void __set_PSP (uint32_t
Write
TopOfProcStack)

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3.3 About the instruction descriptions

The following sections give more information about using the instructions:
• Operands.
• Restrictions when using PC or SP.
• Shift operations.
• Address alignment.
• PC-relative expressions.
• Conditional execution.

3.3.1 Operands
An instruction operand can be an Arm® register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination
register. When there is a destination register in the instruction, it is usually specified before
the other operands.

3.3.2 Restrictions when using PC or SP

Many instructions are unable to use, or have restrictions on whether you can use, the
Program Counter (PC) or Stack Pointer (SP) for the operands or destination register. See
instruction descriptions for more information.
Note: When you update the PC with a BX, BLX, or POP instruction, bit[0] of any address must be 1
for correct execution. This is because this bit indicates the destination instruction set, and
the Cortex-M0+ processor only supports Thumb instructions. When a BL or BLX instruction
writes the value of bit[0] into the LR it is automatically assigned the value 1.

3.3.3 Shift operations

Register shift operations move the bits in a register left or right by a specified number of bits,
the shift length. Register shift can be performed directly by the instructions ASR, LSR, LSL,
and ROR and the result is written to a destination register.
The permitted shift lengths depend on the shift type and the instruction, see the individual
instruction description. If the shift length is 0, no shift occurs. Register shift operations
update the carry flag except when the specified shift length is 0. The following sub-sections
describe the various shift operations and how they affect the carry flag. In these
descriptions, Rm is the register containing the value to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by
n places, into the right-hand 32-n bits of the result, and it copies the original bit[31] of the
register into the left-hand n bits of the result. See Figure 9 on page 41.
You can use the ASR operation to divide the signed value in the register Rm by 2n, with the
result being rounded towards negative-infinity.
When the instruction is ASRS the carry flag is updated to the last bit shifted out, bit[n-1], of
the register Rm
Note: If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.

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Figure 9. ASR#3

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LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result, and it sets the left-hand n bits of the result
to 0. See Figure 10 on page 41.
You can use the LSR operation to divide the value in the register Rm by 2n, if the value is
regarded as an unsigned integer.
When the instruction is LSRS, the carry flag is updated to the last bit shifted out, bit[n-1], of
the register Rm.
Note: If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.

Figure 10. LSR#3

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LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n
places, into the left-hand 32-n bits of the result, and it sets the right-hand n bits of the result
to 0. See Figure 11 on page 42.
You can use the LSL operation to multiply the value in the register Rm by 2n, if the value is
regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur
without warning.
When the instruction is LSLS the carry flag is updated to the last bit shifted out, bit[32-n],
of the register Rm. These instructions do not affect the carry flag when used with LSL#0.

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Note: If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.

Figure 11. LSL #3

  

      
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ROR
Rotate right by n bits moves the left-hand 32-nbits of the register Rm, to the right by n places,
into the right-hand 32-n bits of the result, and it moves the right-hand n bits of the register
into the left-hand n bits of the result. See Figure 12 on page 42.
When the instruction is RORS the carry flag is updated to the last bit rotation, bit[n-1], of the
register Rm.
Note: If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is
updated, it is updated to bit[31] of Rm.
If ROR with shift length, n, greater than 32 is the same as ROR with shift length n-32

Figure 12. ROR #3

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3.3.4 Address alignment

An aligned access is an operation where a word-aligned address is used for a word, or
multiple word access, or where a halfword-aligned address is used for a halfword access.
Byte accesses are always aligned.
There is no support for unaligned accesses on the Cortex-M0+ processor. Any attempt to
perform an unaligned memory access operation results in a HardFault exception.

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3.3.5 PC-relative expressions

A PC-relative expression or label is a symbol that represents the address of an instruction or
literal data. It is represented in the instruction as the PC value plus or minus a numeric
offset. The assembler calculates the required offset from the label and the address of the
current instruction. If the offset is too big, the assembler produces an error.
Note: For most instructions, the value of the PC is the address of the current instruction plus 4
bytes.
Your assembler might permit other syntaxes for PC-relative expressions, such as a label
plus or minus a number, or an expression of the form [PC,#imm].

3.3.6 Conditional execution

Most data processing instructions update the condition flags in the Application Program
Status Register (APSR) according to the result of the operation, see Application Program
Status Register on page 15. Some instructions update all flags, and some only update a
subset. If a flag is not updated, the original value is preserved. See the instruction
descriptions for the flags they affect.
You can execute a conditional branch instruction, based on the condition flags set in another
instruction, either:
• Immediately after the instruction that updated the flags.
• After any number of intervening instructions that have not updated the flags.
On the Cortex-M0+ processor, conditional execution is available by using conditional
branches.
This section describes:
• The condition flags on page 43.
• Condition code suffixes on page 44.

The condition flags

The APSR contains the following condition flags:

N Set to 1 when the result of the operation was negative, cleared to 0 otherwise
Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR see Program Status Register on page 14.
A carry occurs:
• If the result of an addition is greater than or equal to 232.
• If the result of a subtraction is positive or zero.
• As the result of a shift or rotate instruction.

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Overflow occurs when the sign of the result, in bit[31], does not match the sign of the result
had the operation been performed at infinite precision, for example:
• If adding two negative values results in a positive value.
• If adding two positive values results in a negative value.
• If subtracting a positive value from a negative value generates a positive value.
• If subtracting a negative value from a positive value generates a negative value.
The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that
the result is discarded. See the instruction descriptions for more information.

Condition code suffixes

Conditional branch is shown in syntax descriptions as B{cond}. A branch instruction with a
condition code is only taken if the condition code flags in the APSR meet the specified
condition, otherwise the branch instruction is ignored. Table 17 shows the condition codes
to use.
Table 17 also shows the relationship between condition code suffixes and the N, Z, C, and V
flags
.

Table 17. Condition code suffixes

Suffix Flags Meaning

EQ Z=1 Equal, last flag setting result was zero.

NE Z=0 Not equal, last flag setting result was non-zero.
CS or HS C=1 Higher or same, unsigned.
CC or LO C=0 Lower, unsigned.
MI N=1 Negative.
PL N=0 Positive or zero.
VS V=1 Overflow.
VC V=0 No overflow.
HI C = 1 and Z = 0 Higher, unsigned.
LS C = 0 or Z = 1 Lower or same, unsigned.
GE N=V Greater than or equal, signed.
LT N != V Less than, signed.
GT Z = 0 and N = V Greater than, signed.
LE Z = 1 or N != V Less than or equal, signed.
AL Can have any value Always. This is the default when no suffix is specified.

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3.4 Memory access instructions

Table 18 shows the memory access instructions
:

Table 18. Memory access instructions

Mnemonic Brief description See

ADR Generate PC-relative address 3.4.1: ADR on page 46.

LDM Load Multiple registers 3.4.5: LDM and STM on page 50.
3.4.2: LDR and STR, immediate offset on
LDR{type} Load Register using immediate offset
page 47.
3.4.3: LDR and STR, register offset on
LDR{type} Load Register using register offset
page 48.
Load Register from PC-relative
LDR 3.4.4: LDR, PC-relative on page 49.
address
POP Pop registers from stack 3.4.6: PUSH and POP on page 52.
PUSH Push registers onto stack 3.4.6: PUSH and POP on page 52.
STM Store Multiple registers 3.4.5: LDM and STM on page 50.
3.4.2: LDR and STR, immediate offset on
STR{type} Store Register using immediate offset
page 47.
3.4.3: LDR and STR, register offset on
STR{type} Store Register using register offset
page 48.

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3.4.1 ADR
Generates a PC-relative address.
Syntax
ADR Rd, label
where:

Rd Is the destination register.

label Is a PC-relative expression. See 3.3.5: PC-relative expressions on page 43.

Operation
ADR generates an address by adding an immediate value to the PC, and writes the result to
the destination register.
ADR facilitates the generation of position-independent code, because the address is
PC-relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure
that bit[0] of the address you generate is set to 1 for correct execution.
Restrictions
In this instruction Rd must specify R0-R7. The data-value addressed must be word aligned
and within 1020 bytes of the current PC.
Condition flags
This instruction does not change the flags.
Examples
ADR R1, TextMessage ; Write address value of a location labelled as;
TextMessage to R1
ADR R3, [PC,#996] ; Set R3 to value of PC + 996.

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3.4.2 LDR and STR, immediate offset

Load and Store with immediate offset.
Syntax
LDR Rt, [<Rn | SP> {, #imm}]
LDR<B|H> Rt, [Rn {, #imm}]
STR Rt, [<Rn | SP>, {,#imm}]
STR<B|H> Rt, [Rn {,#imm}]
where:

Rt Is the register to load or store.

Rn Is the register on which the memory address is based
imm Is an offset from Rn. If imm is omitted, it is assumed to be zero.

Operation
LDR, LDRB and LDRH instructions load the register specified by Rt with either a word, byte
or halfword data value from memory. Sizes less than word are zero extended to 32-bits
before being written to the register specified by Rt.
STR, STRB and STRH instructions store the word, least-significant byte or lower halfword
contained in the single register specified by Rt in to memory. The memory address to load
from or store to is the sum of the value in the register specified by either Rn or SP and the
immediate value imm.

Restrictions
In these instructions:
• Rt and Rn must only specify R0-R7.
• imm must be between:
– 0 and 1020 and an integer multiple of four for LDR and STR using SP as the base
register.
– 0 and 124 and an integer multiple of four for LDR and STR using R0-R7 as the
base register.
– 0 and 62 and an integer multiple of two for LDRH and STRH.
– 0 and 31 for LDRB and STRB.
• The computed address must be divisible by the number of bytes in the transaction, see
3.3.4: Address alignment on page 42.

Condition flags
These instructions do not change the flags.

Examples
LDR R4, [R7 ; Loads R4 from the address in R7.
STR R2,[R0,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-1020.

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3.4.3 LDR and STR, register offset

Load and Store with register offset.

Syntax
LDR Rt, [Rn, Rm]
LDR<B|H> Rt, [Rn, Rm]
LDR<SB|SH> Rt, [Rn, Rm]
STR Rt, [Rn, Rm]
STR<B|H> Rt, [Rn, Rm]
where:
Rt Is the register to load or store.
Rn Is the register on which the memory address is based
Rm s a register containing a value to be used as the offset

Operation
LDR, LDRB, LDRH, LDRSB and LDRSH load the register specified by Rt with either a
word, zero extended byte, zero extended halfword, sign extended byte or sign extended
halfword value from memory.
STR, STRB and STRH store the word, least-significant byte or lower halfword contained in
the single register specified by Rt into memory.
The memory address to load from or store to is the sum of the values in the registers
specified by Rn and Rm.

Restrictions
In these instructions:
• Rt, Rn, and Rm must only specify R0-R7.
• The computed memory address must be divisible by the number of bytes in the load or
store, see 3.3.4: Address alignment on page 42.

Condition flags
These instructions do not change the flags.

Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
; sum of R5 and R1
LDRSH R1, [R2, R3] ; Load a halfword from the memory address
; specified by (R2 + R3), sign extend to 32-bits
; and write to R1.

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3.4.4 LDR, PC-relative

Load register (literal) from memory.

Syntax
LDR Rt, label
where:
Rt Is the register to load
label Is a PC-relative expression. See 3.3.5: PC-relative expressions on page 43.

Operation
Loads the register specified by Rt from the word in memory specified by label.

Restrictions
In these instructions, label must be within 1020 bytes of the current PC and word aligned.

Condition flags
These instructions do not change the flags.

Examples
LDR R0, LookUpTable ; Load R0 with a word of data from an address
; labelled as LookUpTable.
LDR R3, [PC, #100] ; Load R3 with memory word at (PC + 100).

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3.4.5 LDM and STM

Load and Store Multiple registers.
Syntax
LDM Rn{!}, reglist
STM Rn!, reglist
where:

Rn Is the register on which the memory addresses are based.

! Writeback suffix.
reglist Is a list of one or more registers to be loaded or stored, enclosed in braces. It
can contain register ranges. It must be comma separated if it contains more
than one register or register range, see Examples on page 51.

LDMIA and LDMFD are synonyms for LDM. LDMIA refers to the base register being
Incremented After each access. LDMFD refers to its use for popping data from Full
Descending stacks.
STMIA and STMEA are synonyms for STM. STMIA refers to the base register being
Incremented After each access. STMEA refers to its use for pushing data onto Empty
Ascending stacks.

Operation
LDM instructions load the registers in reglist with word values from memory addresses
based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses
based on Rn.
The memory addresses used for the accesses are at 4-byte intervals ranging from the value
in the register specified by Rn to the value in the register specified by Rn + 4 * (n-1), where n
is the number of registers in reglist. The accesses happens in order of increasing
register numbers, with the lowest numbered register using the lowest memory address and
the highest number register using the highest memory address. If the writeback suffix is
specified, the value in the register specified by Rn + 4 *n is written back to the register
specified by Rn.

Restrictions
In these instructions:
• reglist and Rn are limited to R0-R7.
• The writeback suffix must always be used unless the instruction is an LDM where reglist
also contains Rn, in which case the writeback suffix must not be used.
• The value in the register specified by Rn must be word aligned. See 3.3.4: Address
alignment on page 42 for more information.
• For STM, if Rn appears in reglist, then it must be the first register in the list.

Condition flags
These instructions do not change the flags.

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Examples
LDM R0,{R0,R3,R4} ; LDMIA is a synonym for LDM
STMIA R1!,{R2-R4,R6}

Incorrect examples
STM R5!,{R4,R5,R6} ;Value stored for R5 is unpredictable
LDM R2,{} ;There must be at least one register in the list

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3.4.6 PUSH and POP

Push registers onto, and pop registers off a full-descending stack.

Syntax
PUSH reglist
POP reglist
where:
reglist Is a non-empty list of registers, enclosed in braces. It can contain register
ranges. It must be comma separated if it contains more than one register or
register range.

Operation
PUSH stores registers on the stack, with the lowest numbered register using the lowest
memory address and the highest numbered register using the highest memory address.
POP loads registers from the stack, with the lowest numbered register using the lowest
memory address and the highest numbered register using the highest memory address.
PUSH uses the value in the SP register minus four as the highest memory address, POP
uses the value in the SP register as the lowest memory address, implementing a full-
descending stack. On completion, PUSH updates the SP register to point to the location of
the lowest store value, POP updates the SP register to point to the location above the
highest location loaded.
If a POP instruction includes PC in its reglist, a branch to this location is performed when
the POP instruction has completed. Bit[0] of the value read for the PC is used to update the
APSR T-bit. This bit must be 1 to ensure correct operation.

Restrictions
In these instructions:
• reglist must use only R0-R7.
• The exception is LR for a PUSH and PC for a POP.

Condition flags
These instructions do not change the flags.

Examples
PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack
PUSH {R2,LR} ; Push R2 and the link-register onto the stack
POP {R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to
; the new PC.

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3.5 General data processing instructions

Table 19 shows the data processing instructions:

Table 19. Data processing instructions

Mnemonic Brief description See

3.5.1: ADC, ADD, RSB, SBC, and SUB on

ADCS Add with Carry
page 54.
3.5.1: ADC, ADD, RSB, SBC, and SUB on
ADD{S} Add
page 54.
ANDS Logical AND 3.5.2: AND, ORR, EOR, and BIC on page 56.
ASRS Arithmetic Shift Right 3.5.3: ASR, LSL, LSR, and ROR on page 57.
BICS Bit Clear 3.5.2: AND, ORR, EOR, and BIC on page 56.
CMN Compare Negative 3.5.4: CMP and CMN on page 59.
CMP Compare 3.5.4: CMP and CMN on page 59.
EORS Exclusive OR 3.5.2: AND, ORR, EOR, and BIC on page 56.
LSLS Logical Shift Left 3.5.3: ASR, LSL, LSR, and ROR on page 57.
LSRS Logical Shift Right 3.5.3: ASR, LSL, LSR, and ROR on page 57.
MOV{S} Move 3.5.5: MOV and MVN on page 60.
MULS Multiply 3.5.6: MULS on page 61.
MVNS Move NOT 3.5.5: MOV and MVN on page 60.
ORRS Logical OR 3.5.2: AND, ORR, EOR, and BIC on page 56.
REV Reverse byte order in a word 3.5.7: REV, REV16, and REVSH on page 62.
REV16 Reverse byte order in each halfword 3.5.7: REV, REV16, and REVSH on page 62.
Reverse byte order in bottom halfword
REVSH 3.5.7: REV, REV16, and REVSH on page 62.
and sign extend
RORS Rotate Right 3.5.3: ASR, LSL, LSR, and ROR on page 57.
3.5.1: ADC, ADD, RSB, SBC, and SUB on
RSBS Reverse Subtract
page 54.
3.5.1: ADC, ADD, RSB, SBC, and SUB on
SBCS Subtract with Carry
page 54.
3.5.1: ADC, ADD, RSB, SBC, and SUB on
SUBS Subtract
page 54.
SXTB Sign extend a byte 3.5.8: SXT and UXT on page 63.
SXTH Sign extend a halfword 3.5.8: SXT and UXT on page 63.
UXTB Zero extend a byte 3.5.8: SXT and UXT on page 63.
UXTH Zero extend a halfword 3.5.8: SXT and UXT on page 63.
TST Test 3.5.9: TST on page 64.

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3.5.1 ADC, ADD, RSB, SBC, and SUB

Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.

Syntax
ADCS {Rd,} Rn, Rm
ADD{S} {Rd,} Rn, <Rm|#imm>
RSBS {Rd,} Rn, Rm, #0
SBCS {Rd,} Rn, Rm
SUB{S} {Rd,} Rn, <Rm|#imm>
Where:
S Causes an ADD or SUB instruction to update flags.
Rd Specifies the result register.
reglist Specifies the first source register.
Imm Specifies a constant immediate value.

When the optional Rd register specifier is omitted, it is assumed to take the same value as
Rn, for example ADDS R1,R2 is identical to ADDS R1,R1,R2.

Operation
The ADCS instruction adds the value in Rn to the value in Rm, adding another one if the carry
flag is set, places the result in the register specified by Rd and updates the N, Z, C, and V
flags.
The ADD instruction adds the value in Rn to the value in Rm or an immediate value specified
by imm and places the result in the register specified by Rd.
The ADDS instruction performs the same operation as ADD and also updates the N, Z, C and
V flags.
The RSBS instruction subtracts the value in Rn from zero, producing the arithmetic negative
of the value, and places the result in the register specified by Rd and updates the N, Z, C
and V flags.
The SBCS instruction subtracts the value of Rm from the value in Rn, if the carry flag is clear,
the result is reduced by one. It places the result in the register specified by Rd and updates
the N, Z, C and V flags.
The SUB instruction subtracts the value in Rm or the immediate specified by imm. It places
the result in the register specified by Rd.
The SUBS instruction performs the same operation as SUB and also updates the N, Z, C and
V flags.
Use ADC and SBC to synthesize multiword arithmetic, see Examples on page 55.
See also 3.4.1: ADR on page 46.

Restrictions
Table 20 lists the legal combinations of register specifiers and immediate values that can be
used with each instruction.

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Table 20. ADC, ADD, RSB, SBC and SUB operand restrictions
Instruction Rd Rn Rm imm Restrictions

ADCS R0-R7 R0-R7 R0-R7 - Rd and Rn must specify the same register.
Rd and Rn must specify the same register.
R0-R15 R0-R15 R0-PC -
Rn and Rm must not both specify PC.
SP or Immediate value must be an integer multiple of
ADD R0-R7 - 0-1020
PC four.
Immediate value must be an integer multiple of
SP SP - 0-508
four.
R0-R7 R0-R7 - 0-7 -
ADDS R0-R7 R0-R7 - 0-255 Rd and Rn must specify the same register.
R0-R7 R0-R7 R0-R7 - -
RSBS R0-R7 R0-R7 - - -
SBCS R0-R7 R0-R7 R0-R7 - Rd and Rn must specify the same register.
Immediate value must be an integer multiple of
SUB SP SP - 0-508
four.
R0-R7 R0-R7 - 0-7 -
SUBS R0-R7 R0-R7 - 0-255 Rd and Rn must specify the same register.
R0-R7 R0-R7 R0-R7 - -

Examples
Example 1 shows two instructions that add a 64-bit integer contained in R0 and R1 to
another 64-bit integer contained in R2 and R3, and place the result in R0 and R1.

Example 164-bit addition

ADDS R0, R0, R2 ; add the least significant words
ADCS R1, R1, R3 ; add the most significant words with carry

Multiword values do not have to use consecutive registers. Example 2 shows instructions
that subtract a 96-bit integer contained in R1, R2, and R3 from another contained in R4, R5,
and R6. The example stores the result in R4, R5, and R6.

Example 296-bit subtraction

SUBS R4, R4, R1 ; subtract the least significant words
SBCS R5, R5, R2 ; subtract the middle words with carry
SBCS R6, R6, R3 ; subtract the most significant words with carry
Example 3 shows the RSBS instruction used to perform a 1's complement of a single
register.

Example 3Arithmetic negation

RSBS R7, R7, #0 ; subtract R7 from zero

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3.5.2 AND, ORR, EOR, and BIC

Logical AND, OR, Exclusive OR, and Bit Clear.

Syntax
ANDS {Rd,} Rn, Rm
ORRS {Rd,} Rn, Rm
EORS {Rd,} Rn, Rm
BICS {Rd,} Rn, Rm
where:

Rd Is the destination register.

Rn Is the register holding the first operand and is the same as the destination
register.
Rm Second register

Operation
The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and inclusive
OR operations on the values in Rn and Rm.
The BIC instruction performs an AND operation on the bits in Rn with the logical negation of
the corresponding bits in the value of Rm.
The condition code flags are updated on the result of the operation, see Condition flags on
page 47.

Restrictions
In these instructions, Rd, Rn, and Rm must only specify R0-R7.

Condition flags
These instructions:
Update the N and Z flags according to the result.
Do not affect the C or V flag.

Examples
ANDS R2, R2, R1
ORRS R2, R2, R5
ANDS R5, R5, R8
EORS R7, R7, R6
BICS R0, R0, R1

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3.5.3 ASR, LSL, LSR, and ROR

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.

Syntax
ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs

where:

Rd Is the destination register. If Rd is omitted, it is assumed to take the same

value as Rm.
Rm Is the register holding the value to be shifted.
Rs Is the register holding the shift length to apply to the value in Rm
Imm Is the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32.

Note: MOVS Rd, Rm is a pseudonym for LSLS Rd, Rm, #0.

Operation
ASR, LSL, LSR, and ROR perform an arithmetic-shift-left, logical-shift-left, logical-shift-
right or a right-rotation of the bits in the register Rm by the number of places specified by the
immediate imm or the value in the least-significant byte of the register specified by Rs.
For details on what result is generated by the different instructions, see 3.3.3: Shift
operations on page 40.

Restrictions
In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate
instructions, Rd and Rm must specify the same register.

Condition flags
These instructions update the N and Z flags according to the result.
The C flag is updated to the last bit shifted out, except when the shift length is 0, see 3.3.3:
Shift operations on page 40. The V flag is left unmodified.

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Examples
ASRS R7, R5, #9 ; Arithmetic shift right by 9 bits
LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSRS R4, R5, #6 ; Logical shift right by 6 bits
RORS R4, R4, R6 ; Rotate right by the value in the bottom byte of R6.

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3.5.4 CMP and CMN

Compare and Compare Negative.

Syntax
CMN Rn, Rm
CMP Rn, #imm
CMP Rn, Rm
where:

Rn Is the register holding the first operand.

Rm Is the register to compare with.
Imm Is the immediate value to compare with.

Operation
These instructions compare the value in a register with either the value in another register or
an immediate value. They update the condition flags on the result, but do not write the result
to a register.
The CMP instruction subtracts either the value in the register specified by Rm, or the
immediate imm from the value in Rn and updates the flags. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Rm to the value in Rn and updates the flags. This is the
same as an ADDS instruction, except that the result is discarded.

Restrictions
For the:
• CMN instruction Rn, and Rm must only specify R0-R7.
• CMP instruction:
– Rn and Rm can specify R0-R14.
– Immediate must be in the range 0-255.

Condition flags
These instructions update the N, Z, C and V flags according to the result.

Examples
CMP R2, R9
CMN R0, R2

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3.5.5 MOV and MVN

Move and Move NOT.

Syntax
MOV{S} Rd, Rm
MOVS Rd, #imm
MVNS Rd, Rm
where:

S Is an optional suffix. If S is specified, the condition code flags are updated on

the result of the operation, see 3.3.6: Conditional execution on page 43.
Rd Is the destination register.
Rm Is a register.
Imm Is any value in the range 0-255.

Operation
The MOV instruction copies the value of Rm into Rd.
The MOVS instruction performs the same operation as the MOV instruction, but also updates
the N and Z flags.
The MVSN instruction takes the value of Rm, performs a bitwise logical negate operation on
the value, and places the result into Rd.

Restrictions
In these instructions, Rd, and Rm must only specify R0-R7.
When Rd is the PC in a MOV instruction:
• Bit[0] of the result is discarded.
• A branch occurs to the address created by forcing bit[0] of the result to 0. The T-bit
remains unmodified.
Note: Though it is possible to use MOV as a branch instruction, Arm® strongly recommends the
use of a BX or BLX instruction to branch for software portability.

Condition flags
If S is specified, these instructions:
• update the N and Z flags according to the result
• do not affect the C or V flags.

Example
MOVS R0, #0x000B ; Write value of 0x000B to R0, flags get updated
MOVS R1, #0x0 ; Write value of zero to R1, flags are updated
MOV R10, R12 ; Write value in R12 to R10, flags are not updated
MOVS R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, R0 ; Write inverse of R0 to the R2 and update flags

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3.5.6 MULS
Multiply using 32-bit operands, and producing a 32-bit result.

Syntax
MULS Rd, Rn, Rm
where:

Rd Is the destination register.

Rn, Rm Ire registers holding the values to be multiplied.

Operation
The MUL instruction multiplies the values in the registers specified by Rn and Rm, and places
the least significant 32 bits of the result in Rd. The condition code flags are updated on the
result of the operation, see 3.3.6: Conditional execution on page 43.
The results of this instruction does not depend on whether the operands are signed or
unsigned.

Restrictions
In this instruction:
• Rd, Rn, and Rm must only specify R0-R7.
• Rd must be the same as Rm.

Condition flags
This instruction:
• Updates the N and Z flags according to the result.
• Does not affect the C or V flags.

Examples
MULS R0, R2, R0 ; Multiply with flag update, R0 = R0 x R2

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3.5.7 REV, REV16, and REVSH

Reverse bytes.

Syntax
REV Rd, Rn
REV16 Rd, Rn
REVSH Rd, Rn
where:

Rd Is the destination register.

Rn Is the source register.

Operation
Use these instructions to change endianness of data:
RER
REV Converts 32-bit big-endian data into little-endian data or 32-bit little-endian
data into big-endian data.
REV16 Converts two packed 16-bit big-endian data into little-endian data or two
packed 16-bit little-endian data into big-endian data.
REVSH Converts 16-bit signed big-endian data into 32-bit signed little-endian data or
16-bit signed little-endian data into 32-bit signed big-endian data.

Restrictions
In these instructions, Rd, and Rn must only specify R0-R7.

Condition flags
These instructions do not change the flags.

Examples
REV R3, R7 ; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5 ; Reverse signed halfword

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3.5.8 SXT and UXT

Sign extend and Zero extend.

Syntax
SXTB Rd, Rm
SXTH Rd, Rm
UXTB Rd, Rm
UXTH Rd, Rm

where:
Rd Is the destination register.
Rm Is the register holding the value to be extended.

Operation
• These instructions extract bits from the resulting value:
• SXTB extracts bits[7:0] and sign extends to 32 bits.
• UXTB extracts bits[7:0] and zero extends to 32 bits.
• SXTH extracts bits[15:0] and sign extends to 32 bits.
• UXTH extracts bits[15:0] and zero extends to 32 bits.

Restrictions
In these instructions, Rd and Rm must only specify R0-R7.

Condition flags
These instructions do not affect the flags.

Examples
SXTH R4, R6 ; Obtain the lower halfword of the
; value in R6 and then sign extend to
; 32 bits and write the result to R4.
UXTB R3, R1 ; Extract lowest byte of the value in R10 and zero
; extend it, and write the result to R3

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3.5.9 TST
Test bits.

Syntax
TST Rn, Rm

where:
Rn Is the register holding the first operand.
Rm The register to test against.

Operation
This instruction tests the value in a register against another register. It updates the condition
flags based on the result, but does not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value in
Rm. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with a register that has that bit
set to 1 and all other bits cleared to 0.

Restrictions
In these instructions, Rn and Rm must only specify R0-R7.

Condition flags
This instruction:
• updates the N and Z flags according to the result
• does not affect the C or V flags.

Examples
TST R0, R1 ; Perform bitwise AND of R0 value and R1 value,
; condition code flags are updated but result is discarded

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3.6 Branch and control instructions

Table 21 shows the branch and control instructions:

Table 21. Branch and control instructions

Mnemonic Brief description See

B{cc} Branch {conditionally} 3.6.1: B, BL, BX, and BLX on page 66.
BL Branch with Link 3.6.1: B, BL, BX, and BLX on page 66.
BLX Branch indirect with Link 3.6.1: B, BL, BX, and BLX on page 66.
BX Branch indirect 3.6.1: B, BL, BX, and BLX on page 66.

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3.6.1 B, BL, BX, and BLX

Branch instructions.

Syntax
B{cond} label
BL label
BX Rm
BLX Rm

where:
Cond Is an optional condition code, see 3.3.6: Conditional execution on page 43.
label Is a PC-relative expression. See 3.3.5: PC-relative expressions on page 43.
Rm Is a register providing the address to branch to.

Operation
All these instructions cause a branch to the address indicated by label or contained in the
register specified by Rm. In addition:
• the BL and BLX instructions write the address of the next instruction to LR, the link
register R14.
• the BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.
BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is suitable
for use by a subsequent POP {PC} or BX instruction to perform a successful return branch.
Table 22 shows the ranges for the various branch instructions
.

Table 22. Branch ranges

Instruction Branch range

B label −2 KB to +2 KB.
Bcond label −256 bytes to +254 bytes.
BL label −16 MB to +16 MB.
BX Rm Any value in register.
BLX Rm Any value in register.

Restrictions
In these instructions:
• Do not use SP or PC in the BX or BLX instruction.
• For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update the
EPSR T-bit and is discarded from the target address.

Note: Bcond is the only conditional instruction on the Cortex-M0+ processor.

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Condition flags
These instructions do not change the flags.

Examples
B loopA ; Branch to loopA
BL funC ; Branch with link (Call) to function funC, return address
; stored in LR
BX LR ; Return from function call
BLX R0 ; Branch with link and exchange (Call) to a address stored
; in R0
BEQ labelD ; Conditionally branch to labelD if last flag setting
; instruction set the Z flag, else do not branch.

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3.7 Miscellaneous instructions

Table 23 shows the remaining Cortex-M0+ instructions
:

Table 23. Miscellaneous instructions

Mnemonic Brief description See

BKPT Breakpoint 3.7.1: BKPT on page 69.

CPSID Change Processor State, Disable Interrupts 3.7.2: CPS on page 70.
CPSIE Change Processor State, Enable Interrupts 3.7.2: CPS on page 70.
DMB Data Memory Barrier 3.7.3: DMB on page 71.
DSB Data Synchronization Barrier 3.7.4: DSB on page 72.
ISB Instruction Synchronization Barrier 3.7.5: ISB on page 73.
MRS Move from special register to register 3.7.6: MRS on page 74.
MSR Move from register to special register 3.7.7: MSR on page 75.
NOP No Operation 3.7.7: MSR on page 75.
SEV Send Event 3.7.9: SEV on page 77.
SVC Supervisor Call 3.7.10: SVC on page 78.
WFE Wait For Event 3.7.11: WFE on page 79.
WFI Wait For Interrupt 3.7.12: WFI on page 80.

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3.7.1 BKPT
Breakpoint.

Syntax
BKPT #imm

where:
Imm Is an integer in the range 0-255.

Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use this
to investigate system state when the instruction at a particular address is reached.
Imm is ignored by the processor. If required, a debugger can use it to store additional
information about the breakpoint.
The processor might also produce a HardFault or go in to Lockup if a debugger is not
attached when a BKPT instruction is executed. See 2.4.1: Lockup on page 33 for more
information.

Restrictions
There are no restrictions.

Condition flags
This instruction does not change the flags.

Examples
BKPT #0 ; Breakpoint with immediate value set to 0x0.

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3.7.2 CPS
Change Processor State.

Syntax
CPSID i
CPSIE i

Operation
CPS changes the PRIMASK special register values. CPSID causes interrupts to be disabled
by setting PRIMASK. CPSIE cause interrupts to be enabled by clearing PRIMASK. See
Exception mask register on page 17 for more information about these registers.

Restrictions
If the current mode of execution is not privileged, then this instruction behaves as a NOP and
does not change the current state of PRIMASK.

Condition flags
This instruction does not change the condition flags.

Examples
CPSID i ; Disable all interrupts except NMI (set PRIMASK.PM)
CPSIE i ; Enable interrupts (clear PRIMASK.PM)

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3.7.3 DMB
Data Memory Barrier.

Syntax
DMB

Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear
in program order before the DMB instruction are observed before any explicit memory
accesses that appear in program order after the DMB instruction. DMB does not affect the
ordering of instructions that do not access memory.

Restrictions
There are no restrictions.

Condition flags
This instruction does not change the flags.

Examples
DMB ; Data Memory Barrier

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3.7.4 DSB
Data Synchronization Barrier.

Syntax
DSB

Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the
DSB, in program order, do not execute until the DSB instruction completes. The DSB
instruction completes when all explicit memory accesses before it complete.

Restrictions
There are no restrictions.

Condition flags
This instruction does not change the flags.

Examples
DSB ; Data Synchronisation Barrier

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3.7.5 ISB
Instruction Synchronization Barrier.

Syntax
ISB

Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so
that all instructions following the ISB are fetched from cache or memory again, after the ISB
instruction has been completed.

Restrictions
There are no restrictions.

Condition flags
This instruction does not change the flags.

Examples
ISB ; Instruction Synchronisation Barrier

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3.7.6 MRS
Move the contents of a special register to a general-purpose register.

Syntax
MRS Rd, spec_reg

where:
Rd Is the general purpose destination register.
spec_reg Is one of the special purpose registers: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.

Operation
MSR stores the contents of a special-purpose register to a general purpose register. The MSR
instruction can be combined with the MSR instruction to produce read-modify-write
sequences, which are suitable for modifying a specific flag in the PSR.
See 3.7.7: MSR on page 75.

Restrictions
In this instruction, Rd must not be SP or PC.
If the current mode of execution is not privileged, then the values of all registers other than
the APSR read as zero.

Condition flags
This instruction does not change the flags.

Examples
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0

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3.7.7 MSR
Move the contents of a general-purpose register into the specified special register.

Syntax
MSR spec_reg, Rn

where:
Rn Is the general-purpose source register.
spec_reg Is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.

Operation
MSR updates one of the special registers with the value from the register specified by Rn.
See 3.7.6: MRS on page 74.

Restrictions
In this instruction, Rn must not be SP and must not be PC.
If the current mode of execution is not privileged, then all attempts to modify any register
other than the APSR are ignored.

Condition flags
This instruction updates the flags explicitly based on the value in Rn.

Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register

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3.7.8 NOP
No Operation.

Syntax
NOP

Operation
NOP performs no operation and is not guaranteed to be time consuming. The processor
might remove it from the pipeline before it reaches the execution stage.

Restrictions
There are no restrictions.

Condition flags
This instruction does not change the flags.

Examples
NOP ; No operation

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3.7.9 SEV
Send Event.

Syntax
SEV

Operation
SEV causes an event to be signaled to all processors within a multiprocessor system. It also
sets the local event register, see2.5: Power management on page 33.
See also 3.7.11: WFE on page 79.

Restrictions
There are no restrictions.

Condition flags
This instruction does not change the flags.

Examples
SEV ; Send Event

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3.7.10 SVC
Supervisor Call.

Syntax
SVC #imm
where:
Imm Is an integer in the range 0-255.

Operation
The SVC instruction causes the SVC exception.
Imm is ignored by the processor. If required, it can be retrieved by the exception handler to
determine what service is being requested.

Restrictions
Executing the SVC instruction, while the current execution priority level is greater than or
equal to that of the SVCall handler, results in a fault being generated.

Condition flags
This instruction does not change the flags.

Examples
SVC #0x32 ; Supervisor Call (SVC handler can extract the immediate
value
; by locating it through the stacked PC)

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3.7.11 WFE
Wait For Event.

Syntax
WFE

Operation
If the event register is 0, WFE suspends execution until one of the following events occurs:
• An exception, unless masked by the exception mask registers or the current priority
level.
• An exception enters the Pending state, if SEVONPEND in the System Control Register is
set.
• A Debug Entry request, if debug is enabled.
• An event signaled by a peripheral or another processor in a multiprocessor system
using the SEV instruction.
If the event register is 1, WFE clears it to 0 and completes immediately.
For more information see 2.5: Power management on page 33.

Note: WFE is intended for power saving only. When writing software assume that WFE might
behave as NOP.

Restrictions
There are no restrictions.

Condition flags
This instruction does not change the flags.

Examples
WFE ; Wait for event

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3.7.12 WFI
Wait for Interrupt.

Syntax
WFI

Operation
WFI suspends execution until one of the following events occurs:
• An exception.
• An interrupt becomes pending which would preempt if PRIMASK.PM was clear.
• A Debug Entry request, regardless of whether debug is enabled.

Note: WFI is intended for power saving only. When writing software assume that WFI might
behave as a NOP operation.

Restrictions
There are no restrictions.

Condition flags
This instruction does not change the flags.

Examples
WFI ; Wait for interrupt

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