EE5311- Digital IC Design

Module 1 - The Transistor

Janakiraman V
Assistant Professor
Department of Electrical Engineering
Indian Institute of Technology Madras
Chennai

August 20, 2018

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 1/43

Learning Objectives

◮ Explain short channel effects(SCE) like Drain Induced

Barrier Lowering, Gate Induced Drain Leakage,
Sub-threshold leakage, Channel length modulation
◮ Derive the equation for ON current of a CMOS transistor
with first order SC
◮ Estimate various capacitance values for a transistor
◮ Estimate the equivalent ON resistance of a transistor

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 2/43

Outline
◮ Silicon and Doping
◮ P-N Junction
◮ CMOS Transistor
◮ Threshold Voltage
◮ ON Current (ION )
◮ Channel length modulation
◮ Velocity saturation
◮ Sub-threshold leakage
◮ Drain Induced Barrier Leakage
◮ Gate Induced Drain leakage
◮ (Reverse) Short Channel Effect
◮ Other leakage mechanisms
◮ Capacitance
◮ Resistance

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 3/43

Silicon and Doping
Si

Si Si Si

Si

Si Si
Unbound Electron Missing Electron

Si P Si Si B Si

Si Si

N−Type − Donor P−Type − Acceptor

◮ ni - Intrinsic electron/ hole concentration

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 4/43
Device Physics Abstraction
1. Law of Mass Action - Product of concentrations remains
constant

np = ni2
Where
◮ n/p = Electron/ hole concentration after doping
◮ ni = Intrinsic electron/ hole concentration
2. Maxwell Boltzmann Equation -
n1 Ψ12
= e kT /q
n2
Where
◮ kT /q - Thermal voltage = 26mV @ 300K
◮ n1 , n2 - Charge concentration across a potential ψ12
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 5/43
PN Junction

N+ P
Wn Wp

Figure: PN Junction Diode

W n ND = W p NA

◮ Conservation of charge
◮ Note: ND ≫ NA =⇒ Wp ≫ Wn
◮ Current is due to diffusion of minority carriers
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 6/43
NMOS Transistor
VG
VS VD
Le
Tox
W

N+ N+
P

VB

Figure: NMOS transistor

◮ VGS < 0 - Accumulation (Surface becomes more P type

than bulk)
◮ 0 ≤ VGS < VTH - Depletion (Surface is less P type than
bulk)
◮ VGS ≥ VTH - Inversion (Surface is more N than the bulk
is P)
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 7/43
Threshold Voltage
B S G D

ΨS
N+ N+

nSurf
e
ace
= NA
n2i
nBulk
e = NA

Figure: Inversion

@VG = VTH - Channel is as N-type as the body is P-type

kT NA
ΨS = 2 ln( )
q ni

VGB = ψOX + ψS
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 8/43
Threshold Voltage
WD = Depletion width and QD = Depletion charge per unit
area
s
2ǫsi |ψs |
WD =
qNA
p
QD = −qNA WD = − 2qNA |ψs |
−(QD + QI )
ψOX =
Cox
ǫox
Cox =
tox
QD
VTH = ψS −
Cox

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 9/43

Threshold Voltage

◮ VB 6= 0
◮ Body effect alters depletion region charge

p
QD = 2qNA ǫSi |ΨS + VSB |

p p
VTH = VTH0 + γ( |ΨS + VSB | − |(ΨS )|)
Technolopgy parameters
◮ VTH0 - Threshold voltage without body effect

◮ γ - Body effect coefficient

◮ ΨS - Positive (Negative) for NMOS (PMOS) transistors

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 10/43

NMOS Transistor
B S VGS VDS
ID

Vx
N+ N+

x
L

Figure: NMOS Transistor

◮ VGS ≤ 0 - OFF
◮ VGS > VTH and VDS < VGS − VTH - Linear
◮ VGS > VTH and VDS > VGS − VTH - Saturation

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 11/43

NMOS - ON Current - Linear Region
B S VGS VDS
ID

Vx
N+ N+

x
L

Figure: NMOS Transistor

Qi (x) = −COX [VGS − Vx − VTH ]

ǫOX
COX =
tOX
ID = −vn Qi (x)W
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 12/43
NMOS - ON Current - Linear Region

vn = −µn E (x)
dVx
v n = µn
dx
Substituting we get
dVx
ID = COX [VGS − Vx − VTH ]W µn
dx
Z L Z VDS
ID dx = COX [VGS − Vx − VTH ]W µn dVx
0 0
′ W V2
I D = kn [(VGS − VTH )VDS − DS ]
L 2

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 13/43

NMOS - ON Current - Saturation
B S VGS VDS
ID

VP
N+ N+

x
L

Figure: NMOS Transistor under pinch off voltage (VP ) condition

′
kn W
ID = [(VGS − VTH )2 ]
2 L

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 14/43

Short Channel Effects
∆L
B S VGS VDS
ID

N+ L N+

VDS = VDD VDS = 0

VDS << VDD
P

Figure: NMOS Transistor with Short Channel Effects

◮ Drain is very close to the source (L is very small)

◮ The depletion regions in the drain and source are
comparable to the channel length
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 15/43
Channel Length Modulation
∆L
B S VGS VDS
ID

N + L N +

VDS = VDD VDS = 0

VDS << VDD
P

Figure: NMOS Transistor with Short Channel Effects

′
kn W
ID = [(VGS − VTH )2 ]
2 L − ∆L
′
kn W ∆L
ID = [(VGS − VTH )2 ](1 + )
2 L L
′
kn W
ID = [(VGS − VTH )2 ](1 + λVDS )
2 L
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 16/43
Velocity Saturation

vn = µn ELat

◮ Not entirely correct - Velocity does not linearly increase

with lateral field for ever
◮ It saturates beyond a critical field ECrit
◮ Electrons encounter more collisions and hence don’t pick
up speed
◮ Maximum velocity of electrons/ holes = 105 m/s

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 17/43

Velocity Saturation

0.8
v (m/s)(×105 )

0.6

0.4

0.2

0
0 1 2 3 4 5
E (V /µm)


µE

1+ EE
if E ≤ EC
v= C
vsat if E > EC

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 18/43

Velocity Saturation- Simplified
Velocity: (
µE if E ≤ EC
v=
vsat = µEC if E > EC
VDS Saturation :
LvSAT
VDS−SAT = L ∗ EC =
µ
Velocity Saturated Drain Current:

IDS−SAT = IDS (VDS = VDS−SAT )

 2 
W VDS−SAT
IDS−SAT = µn COX (VGS − VTH )VDS−SAT −
L 2

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 19/43

Unified Current Model
◮ Useful to combine all effects into one equation
◮ Voltage values determine the governing equations

(
0  |VGS | < |VTH |
IDS =  2
Vmin
k ′ WL (VGS − VTH )Vmin − 2
)(1 + λVDS |VGS | > |VTH |

Where

Vmin = min(VDS , (VGS − VTH ), VDS−SAT ) . . . NMOS

Vmin = max(VDS , (VGS − VTH ), VDS−SAT ) . . . PMOS
p p
VTH = VTH0 + γ( |VSB + ΨS | − ΨS )

(VTH0 , k ′ , VDSAT , γ, λ) - Technology parameters

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 20/43
Sub-threshold Leakage
B S VGS = 0 VDS
IOF F

+ +
N N

Thin Base

Emitter Collector

Figure: NMOS Transistor Sub-Threshold Leakage

◮ In a short channel transistor, the thin channel acts like a

thin base of a BJT.
◮ Diffusion current flows even when VGS = 0.
◮ Exponential dependence on VGS
VGS −VTH  VDS 
IOFF = IS e nkT /q 1 − e − kT /q (1 + λVDS )

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 21/43

Sub-threshold Slope
IDS
mA

Log

nA IOF F
GIDL

VGS
Linear

1
S= d(log10 (IOFF ))
dVGS
kT
S =n ln(10)
q

◮ Ideal transistor n = 1, Smin = 60mV /decade

◮ Actual transistors n ≈ 1.5 and hence S = 90mV /decade
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 22/43
Gate Induced Drain Leakage (GIDL)
B S VGS << 0 VDS = VDD

N+ P+ N+

IGIDL

Figure: NMOS Transistor with Halo Implant

◮ Negative VGS exponentially reduces sub-threshold leakage

◮ But beyond a point GIDL kicks in
◮ Surface is in deep accumulation causing a deeper
depletion in the diffusion
◮ Tunneling current from drain to substrate
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 23/43
Drain Induced Barrier Lowering (DIBL)
B S VGS VDS
ID

N + L N +

VDS = VDD VDS = 0

VDS << VDD
P

Figure: NMOS Transistor DIBL

◮ Drain controls amount of depletion in the channel

◮ Easier for the gate to invert with higher VDS
◮ Gate effectively has lesser control

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 24/43

Drain Induced Barrier Lowering (DIBL)
B S VGS VDS
ID

N+ L N+
P+ P+

Figure: NMOS Transistor with Halo Implant

◮ P + halo added near diffusion

◮ Depletion layer now goes deeper into the diffusion rather
than channel
◮ Gate has better control now
V (V =V H )−V (VDS =VDD
L )
◮ DIBL = TH DS VDDH −VTH L
DD DD

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 25/43

Reverse Short Channel Effect

RSCE

SCE
VT H

L
Halo implant makes it harder to invert the channel

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 26/43

Substrate Leakage
B S VGS VDS

N+ N+

ISU B−LEAK

Reverse biased P − N + junction leakage

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 27/43

Gate Leakage
tOX = 4nm

B S VGS VDS

N+ N+

P
Scaling

tOX = 1nm
B S

N+ N+

IGAT E
P

◮ Quantum mechanical tunneling across the gate oxide

◮ Use of HfO2 - HiK dielectric since 45nm technology

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 28/43

Capacitance

D
Cgd Cdb

G B
Cgb
Cgs Csb
S
Figure: Capacitance Model

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 29/43

Gate Capacitance
G
C
C0

Depletion
Accumulation Inversion

VGB

Figure: Capacitance Model

ǫWL
C0 =
tox
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 30/43
Gate Capacitance

Parameter Cutoff Linear Saturation

Cgb C0 0 0
Cgs 0 C0 /2 (2/3)C0
Cgd 0 C0 /2 0
Cg = Cgb + Cgs + Cgd C0 C0 (2/3)C0

ǫox WL
C0 =
tox
For all practical purposes Cg ≈ C0

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 31/43

Overlap Capacitance
Cross Section

N+ L N+

W
xd
Ld
Top View

Figure: Overlap Capacitance

ǫox Wxd
Coverlap = = Cov W
tox
CG = COX WL + 2Cov W
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 32/43
Diffusion Capacitance

xj ND+ ND+

LS NA

Figure: Diffusion Capacitance

◮ Bottom plate capacitance

◮ Sidewall capacitance

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 33/43

Diffusion Capacitance

Side Wall

W all Bottom
W ND
de
Si Source

Channel
xj Side Wall
Substrate NA
LS

Figure: Diffusion Capacitance

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 34/43

Bottom Plate Diffusion Capacitance
W

xj ND+ ND+

LS NA

CBottom = Cj WLS
Cj0
Cj =
(1 + VSB /φ0 )m
r
ǫsi q NA ND
Cj0 = ( )φ−1
2 NA + ND 0
kT NA ND
φ0 = ln( 2 )
q ni
m ≈ 0.5
Cj is charge per unit area. Similar expressions hold for the
drain side (VSB → VDB ) as well.
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 35/43
Side wall Diffusion Capacitance

xj ND+ ND+

LS NA

Figure: Diffusion Capacitance

′
CSide−wall = Cjsw xj (W + 2LS )
′
Cjsw = Cjsw xj
Cdiff = Cbottom + Csw = Cj LS W + Cjsw (W + 2LS )

Cjsw is capacitance per unit length.

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 36/43

Capacitance Summary
D
Cgd Cdb

G B
Cgb
Cgs Csb
S

Figure: NMOS Capacitance

CG = CGS + CGD + CGB + 2Coverlap = COX WL + 2Cov W

CDB = Cj LS W + Cjsw (W + 2LS )
CSB = Cj LS W + Cjsw (W + 2LS )

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 37/43

Resistance
VDS (VDD − VDD /2)

VDD
ID

Figure: NMOS Equivalent Resistance

Z VDD /2
1
Req = R(V )dV
VDD /2 − VDD VDD
Z VDD /2
1 V
Req = dV
−VDD /2 VDD IDSAT (1 + λV )
 
3VDD 7
Req ≈ 1 − λVDD
4IDSAT 9
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 38/43
Resistance



3VDD 7
Req ≈ 1 − λVDD
4IDSAT 9
W V2
IDSAT = k ′ ((VDD − VTH )VDSAT − DSAT )
L 2

1
◮ Resistance Req ∝ W /L
- Doubling W =⇒ Req halves
◮ If VDD >> VTH + VDSAT /2, Req is independent of VDD .
Minor dependence due to CLM (λ)
◮ As VDD → VTH , resistance goes up significantly

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 39/43

BSIM SPICE Level 1 Model
VTH0 γ(V 0.5 ) VDSAT (V ) k ′ (µA/V 2 ) λ(V −1 )
NMOS 0.43 0.4 0.63 115 0.06
PMOS -0.4 -0.4 -1 -30 -0.1
Table: Parameters of a 0.25µm CMOS process for a minimum
length device

◮ Calculate the drain current of a PMOS transistor in

0.25µm technology whose W /L = 0.5µ/0.25µ when
biased at VGS = −0.6V , VDS = −0.3V and VSB = 0V
◮ Repeat the above calculation this time with
VDS = −1.1V and VGS = −2V
◮ Calculate the threshold voltage of a NMOS device when
the body is biased at VSB = 0.11V . Assume that
ψS = 0.25V
Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 40/43
Capacitance Model

COX Cov Cj mj φb Cjsw mjsw φbsw

(fF /µm2 ) (fF /µm) (fF /µm2 ) (V fF /µm) (V )
NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9
PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9

Table: Capacitance parameters of a 0.25µm CMOS process

◮ Calculate variaous capacitances of an NMOS transistor

with W /L = 0.36µm/0.24µm in a 0.25µm technology
where LD = LS = 0.625µm under zero-bias condition
◮ Calculate the equivalent resistance of an NMOS transistor
with a W /L = 1 when connected to a VDD = 1.5V

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 41/43

Summary
◮ A transistor operates in 4 regions - cut-off, linear, velocity
saturation and saturation.
◮ Identify the region using the unified current model
◮ Level-1 SPICE model parameters - (k ′ , λ, VDSAT , VTH0 , γ)
◮ All positive for NMOS and all negative for PMOS
VGS −VTH
◮ Sub-threshold leakage is proportional to e n(kT /q)
◮ Beware of forward biasing any junction
◮ All capacitance components change linearly with W
◮ Diffusion and overlap capacitances of a transistor don’t
depend on L
◮ Equivalent resistance of a transistor is proportional to W1

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 42/43

References

The material presented here is based on the following books/

lecture notes
1. Digital Integrated Circuits Jan M. Rabaey, Anantha
Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice
Hall India

Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 43/43