Zynq UltraScale+ MPSoC

Product Tables and Product Selection Guide

 Zynq® UltraScale+™ MPSoCs
Smarter Control and Vision Smarter Network
Device Name(1) ZU2EG ZU3EG ZU4EV ZU5EV ZU7EV ZU6EG ZU9EG ZU15EG ZU11EG ZU17EG ZU19EG
Application Processor Core Quad-core ARM® Cortex™-A53 MPCore™ up to 1.5GHz
Processor Unit Memory w/ECC L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB
Real-Time Processor Core Dual-core ARM Cortex-R5 MPCore™ up to 600MHz
Processing System (PS)

Processor Unit Memory w/ECC L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core
Graphic & Video Graphics Processing Unit Mali™-400 MP2 up to 667MHz
Acceleration Memory L2 Cache 64KB
Dynamic Memory Interface x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 with ECC
External Memory
Static Memory Interfaces NAND, 2x Quad-SPI
High-Speed Connectivity PCIe® Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet
Connectivity
General Connectivity 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
Power Management Full / Low / PL / Battery Power Domains
Integrated Block
Security RSA, AES, and SHA
Functionality
AMS - System Monitor 10-bit, 1MSPS - Temperature, Voltage, and Current Monitor
PS to PL Interface 12 x 32/64/128b AXI Ports
System Logic Cells (K) 103 154 192 256 504 469 600 747 653 926 1,143
Programmable
CLB Flip-Flops (K) 94 141 176 234 461 429 548 682 597 847 1,045
Functionality
CLB LUTs (K) 47 71 88 117 230 215 274 341 299 423 523
Max. Distributed RAM (Mb) 1.2 1.8 2.6 3.5 6.2 6.9 8.8 11.3 9.1 8.0 9.8
Programmable Logic (PL)

Memory Total Block RAM (Mb) 5.3 7.6 4.5 5.1 11.0 25.1 32.1 26.2 21.1 28.0 34.6
UltraRAM (Mb) - - 14.0 18.0 27.0 - - 31.5 22.5 28.7 36.0
Clocking Clock Management Tiles (CMTs) 3 3 4 4 8 4 4 4 8 11 11
DSP Slices 240 360 728 1,056 1,728 1,973 2,520 3,528 2,928 1,590 1,968
Video Codec Unit (VCU) - - 1 1 1 - - - - - -
PCI Express® Gen3x16 / Gen4x8 - - 2 2 2 - - - 4 4 5
Integrated IP
150G Interlaken - - - - - - - - 2 2 4
100G Ethernet MAC/PCS w/RS-FEC - - - - - - - - 1 2 4
AMS - System Monitor 1 1 1 1 1 1 1 1 1 1 1
Extended(2) -1 -2L -3 -1 -2L -3
Speed Grades
Industrial -1 -1L -2 -1 -1L -2
Notes:
1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview.
2.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview.

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 Zynq® UltraScale+™ MPSoCs
PS I/Os(1), 3.3V High-Density (HD) I/O, 1.8V High-Performance (HP) I/Os
PS-GTR 6Gb/s, GTH 16.3Gb/s, GTY 32.75Gb/s
Smarter Control and Vision Smarter Network
Pkg Dimensions
Footprint(2) (mm) ZU2EG ZU3EG ZU4EV ZU5EV ZU7EV ZU6EG ZU9EG ZU15EG ZU11EG ZU17EG ZU19EG
170, 24, 52 170, 24, 52
A484(3) 19x19
4, 0, 0 4, 0, 0
170, 24, 156 170, 24, 156
A625(3) 21x21
4, 0, 0 4, 0, 0
214, 96, 156 214, 96, 156 214, 96, 156 214, 96, 156
C784(3, 4) 23x23
4, 0, 0 4, 0, 0 4, 4, 0 4, 4, 0
214, 48, 156 214, 48, 156 214, 48, 156
B900 31x31
4, 16, 0 4, 16, 0 4, 16, 0
214, 48, 156 214, 48, 156 214, 48, 156
C900 31x31
4, 16, 0 4, 16, 0 4, 16, 0
214, 120, 208 214, 120, 208 214, 120, 208
B1156 35x35
4, 24, 0 4, 24, 0 4, 24, 0
214, 48, 312 214, 48, 312
C1156 35x35
4, 20, 0 4, 20, 0
214, 72, 416 214, 72, 572 214, 72, 572
B1517 40x40
4, 16, 0 4, 16, 0 4, 16, 0
214, 48, 416 214, 48, 416
F1517 40x40
4, 24, 0 4, 32, 0
214, 96, 416 214, 96, 416 214, 96, 416
C1760 42.5x42.5
4, 32, 16 4, 32, 16 4, 32, 16
214, 48, 260 214, 48, 260
D1760 42.5x42.5
4, 44, 28 4, 44, 28
214, 96, 572 214, 96, 572
E1924 45x45
4, 44, 0 4, 44, 0
Important: Verify all data in this document with the device data sheets found at www.xilinx.com
Notes:
1. PS I/O is a combination of PS MIO and PS DDRIO.
2. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview.
3. These packages are only offered in 0.8mm ballpitch. All other packages are offered in 1.0mm ball pitch.
4. GTH transceivers in the C784 package support data rates up to 12.5Gb/s.
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 Zynq® UltraScale+™ MPSoC Ordering Information

Footprint

XC Z U # E G -1 F F V A # E
Xilinx Zynq UltraScale Value Processor Engine Type Speed Grade F: Flip-chip F: Lid V: RoHS 6/6 Package Package Temperature
Commercial Index System G: General Purpose -1: Slowest w/ 1.0mm B: Lidless Designator Pin Count Grade
Identifier V: Video -L1: Low Power Ball Pitch (E, I)
E: Quad APU -2: Mid S: Flip-chip
Dual RPU -L2: Low Power w/ 0.8mm
Single GPU -3: Fastest Ball Pitch
E = Extended (Tj = 0°C to +100°C)
I = Industrial (Tj = –40°C to +100°C)
Note: -L2E (Tj = 0°C to +110°C). Refer to DS891, Zynq UltraScale+ MPSoC Overview for additional information.

Important: Verify all data in this document with the device data sheets found at www.xilinx.com

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Memory
Zynq® UltraScale+™ MPSoCs include block RAM and UltraRAM (high density, dual-port, synchronous memory
block), which increase performance, device utilization, and power efficiency. These new features are designed to
provide highly efficient solutions for applications that require heterogeneous processing.

Total Memory (Mb) Block RAM UltraRAM

ZU2EG 5.3
ZU3EG 7.6
ZU4EV 4.5 14.0
ZU5EV 5.1 18.0
ZU7EV 11.0 27.0
ZU6EG 25.1
ZU9EG 32.1
ZU15EG 26.2 31.5
ZU11EG 21.1 22.5
ZU17EG 28.0 28.7
ZU19EG 34.6 36.0

Important: Verify all data in this document with the device data sheets found at www.xilinx.com
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 Transceiver Count and Bandwidth
UltraScale™ architecture serial transceivers include the proven on-chip circuits required to provide optimal signal
integrity in real world environments, at data rates up to 6.0Gb/s (PS-GTR), 16.3Gb/s (GTH), and 32.75Gb/s (GTY).

Total Transceiver Count and Bandwidth PS-GTR GTH GTY

ZU2EG 4 24.0Gb/s PS-GTR = 6.0Gb/s

GTH = 16.3Gb/s
ZU3EG 4 24.0Gb/s
GTY = 32.75Gb/s
ZU4EV 4 16 224Gb/s

ZU5EV 4 16 224Gb/s

ZU7EV 4 24 415.2Gb/s

ZU6EG 4 24 415.2Gb/s

ZU9EG 4 24 415.2Gb/s

ZU15EG 4 24 415.2Gb/s

ZU11EG 4 32 16 1069.6Gb/s

ZU17EG 4 44 28 1658.2Gb/s

ZU19EG 4 44 28 1658.2Gb/s

Important: Verify all data in this document with the device data sheets found at www.xilinx.com
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 I/O Count
The I/Os are classified as PS I/O, high-density (HD) I/O, and high-performance (HP) I/O. The PS I/Os are composed
of multi-use I/O (MIO) and DDR I/O, which support 1.8V to 3.3V standards. The HD I/Os are reduced-feature I/Os,
providing voltage support from 1.2V to 3.3V. The HP I/Os are optimized for highest performance operation, from
1.0V to 1.8V.

PS I/O HD I/O HP I/O

I/O Counts
ZU2EG 214 96 156
ZU3EG 214 96 156
ZU4EV 214 96 156
ZU5EV 214 96 156
ZU7EV 214 48 416
ZU6EG 214 120 208
ZU9EG 214 120 208
ZU15EG 214 120 208
ZU11EG 214 96 416
ZU17EG 214 96 572
ZU19EG 214 96 572

Notes:
1. The PS I/O count is composed of 78 I/Os, which are used to communicate to external components, referred to as multi-use I/O (MIO) and an additional 136 I/Os, which are used to
communicate to DDRs, referred to as DDR I/O.
Important: Verify all data in this document with the device data sheets found at www.xilinx.com

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References

DS890, UltraScale™ Architecture and Product Overview

DS891, Zynq® UltraScale+™ MPSoC Overview
DS925, Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics
UG1075, Zynq UltraScale+ MPSoC Packaging and Pinouts
UG1085, Zynq UltraScale+ MPSoC Technical Reference Manual
UG1087, Zynq UltraScale+ MPSoC Register Reference
UG1137, Zynq UltraScale+ MPSoC: Software Developers Guide
UG1169, Zynq UltraScale+ MPSoC QEMU: User Guide
UG1186, Zynq UltraScale+ MPSoC OpenAMP: Getting Started Guide
UG571, UltraScale Architecture SelectIO™ Resources User Guide
UG572, UltraScale Architecture Clocking Resources User Guide
UG573, UltraScale Architecture Memory Resources User Guide
UG574, UltraScale Architecture Configurable Logic Block User Guide
UG576, UltraScale Architecture GTH Transceivers User Guide
UG578, UltraScale Architecture GTY Transceivers User Guide
UG579, UltraScale Architecture DSP Slice User Guide
UG580, UltraScale Architecture System Monitor User Guide
UG583, UltraScale Architecture PCB and Pin Planning User Guide
PG150, LogiCORE™ IP UltraScale Architecture-Based FPGAs Memory Interface Solutions
PG182, UltraScale FPGAs Transceivers Wizard Product Guide Important: Verify all data in this document with the device data sheets found at www.xilinx.com
XMP104 (v1.7)

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