®

RT8899A

Dual-Output PWM Controller with 3 Integrated Drivers for

AMD SVI2 GPU CORE Power Supply
General Description Features
The RT8899A is a 3 + 2 phases PWM controller, and is  3/2/1-Phase (VDDC) + 2/1-Phase (VDDCI) PWM
compliant with AMD SVI2 GPU Specification to support Controller
both GPU core power (VDDC) and I/O bus (VDDCI). The  3 Embedded MOSFET Drivers
RT8899A features CCRCOT (Constant Current Ripple  G-NAVPTM Topology
Constant On-Time) with G-NAVP (Green-Native AVP),  Support Dynamic Load-Line and Zero Load-Line
which is Richtek's proprietary topology. The G-NAVP  Diode Emulation Mode at Light Load Condition
makes it an easy setting controller to meet all AMD AVP  SVI2 Interface to Comply with AMD Power
(Adaptive Voltage Positioning) VDDC/VDDCI requirements. Management Protocol
The droop is easily programmed by setting the DC gain of  Build-in ADC for VOUT and IOUT Reporting
the error amplifier. With proper compensation, the load  Immediate OV, UV and NV Protections and UVLO
transient response can achieve optimized AVP  Programmable Dual OCP Mechanism
performance. The controller also uses the interface to  0.5% DAC Accuracy
issue VOTF Complete and to send digitally encoded  Fast Transient Response
voltage and current values for the VDDC and VDDCI  Power Good Indicator
domains. It can operate in single phase and diode emulation  Over-Current Indicator
mode and reach up to 90% efficiency in different modes  52-Lead WQFN Package
according to different loading conditions. The RT8899A  RoHS Compliant and Halogen Free
provides special purpose offset capabilities by pin setting.
The RT8899A also provides power good indication, over- Applications
current indication (OCP_L) and dual OCP mechanism for
 AMD SVI2 GPU Core Power
AMD SVI2 GPU core power (VDDC) and I/O bus (VDDCI).
 Laptop Computer
It also features complete fault protection functions
including over-voltage, under-voltage and negative-voltage
protections.

Simplified Application Circuit

RT8899A
OCP_L PHASE1 MOSFET VVDDC

PHASE2 MOSFET
SVC
To GPU PWM3 RT9610 MOSFET
SVD
PHASEA1 MOSFET VVDDCI

SVT PWMA2 RT9610 MOSFET

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RT8899A
Ordering Information Pin Configurations
RT8899A (TOP VIEW)
Package Type

UGATEA1

TONSETA
PHASEA1
LGATEA1

BOOTA1
UGATE1
PHASE2

PHASE1
LGATE2

LGATE1

PWMA2
BOOT1
QW : WQFN-52L 6x6 (W-Type)

PVCC
Lead Plating System
G : Green (Halogen Free and Pb Free) 52 51 50 49 48 47 46 45 44 43 42 41 40

Note : UGATE2 1 39 PGOOD

Richtek products are : BOOT2 2 38 PGOODA
PWM3 3 37 EN
 RoHS compliant and compatible with the current require- TONSET 4 36 ISENA1P
ments of IPC/JEDEC J-STD-020. ISEN2P 5 35 ISENA1N
ISEN2N 6 34 ISENA2N
 Suitable for use in SnPb or Pb-free soldering processes. ISEN1N 7 GND 33 ISENA2P
ISEN1P 8 32 VSENA
ISEN3P 9 31 FBA
ISEN3N 10 30 COMPA
Marking Information VSEN 11
53
29 IBIAS
RT8899AGQW : Product Number FB 12 28 VCC
RT8899A COMP 13 27 OCP_L
YMDNN : Date Code
GQW 14 15 16 17 18 19 20 21 22 23 24 25 26

OFSA
RGND
IMON
V064

VDDIO

SVC
SVD

SET1
SET2
IMONA

PWROK

SVT
OFS
YMDNN

WQFN-52L 6x6

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 RT8899A
Functional Pin Description
Pin No. Pin Name Pin Function
3 PWM3 PWM Outputs for Channel 3 VDDC Controller.
VDDC Controller On-Time Setting. Connect this pin to the converter input
4 TONSET voltage, VIN, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDDC controller.
5, 8, 9 ISEN1P to ISEN3P Positive Current Sense Input of Channel 1, 2 and 3 for VDDC Controller.
6, 7, 10 ISEN1N to ISEN3N Negative Current Sense Input of Channel 1, 2 and 3 for VDDC Controller.
VDDC Controller Voltage Sense Input. This pin is connected to the terminal
11 VSEN
of VDDC controller output voltage.
Output Voltage Feedback Input of VDDC Controller. This pin is the
12 FB
negative input of the error amplifier for the VDDC controller.
13 COMP Compensation Node of the VDDC Controller.
Return Ground of VDDC and VDDCI Controller. This pin is the common
14 RGND negative input of output voltage differential remote sense for VDDC and
VDDCI controllers.
Current Monitor Output for the VDDC Controller. This pin outputs a voltage
15 IMON
proportional to the output current.
Fixed 0.64V Output Reference Voltage Output. This voltage is only used to
16 V064 offset the output voltage of IMON pin and IMONA pin. Connect a 0.47F
capacitor from this pin to GND.
Current Monitor Output for the VDDCI Controller. This pin outputs a voltage
17 IMONA
proportional to the output current.
Processor Memory Interface Power Rail and Serves as the Reference for
18 VDDIO PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
19 PWROK
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
20 SVC Serial VID Clock Input from Processor.
21 SVD Serial VID Data input from Processor. This pin is a serial data line.
22 SVT Serial VID Telemetry Input from VR. This pin is a push-pull output.
23 OFS Over Clocking Offset Setting for the VDDC Controller.
24 OFSA Over Clocking Offset Setting for the VDDCI Controller.
1st Platform Setting. Platform can use this pin to set OCP_TDC threshold,
25 SET1
DVID compensation bit1 and internal ramp slew rate.
2st Platform Setting. Platform can use this pin to set quick response
26 SET2 threshold, OCP_TDC trigger delay time, DVID compensation bit0, VDDCI
zero load-line enable setting and over clocking offset enable setting.
Over-Current Indicator for Dual OCP Mechanism. This pin is an open-drain
27 OCP_L
output.
Controller Power Supply Input. Connect this pin to 5V with an 1F or
28 VCC
greater ceramic capacitor for decoupling.

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RT8899A
Pin No. Pin Name Pin Function
Internal Bias Current Setting. Connect only a 100k resistor from this pin to
29 IBIAS GND to generate bias current for internal circuit. Place this resistor as close to
the IBIAS pin as possible.
30 COMPA Compensation Node of the VDDCI Controller.
Output Voltage Feedback Input of VDDCI Controller. This pin is the negative
31 FBA
input of the error amplifier for the VDDCI controller.
VDDCI Controller Voltage Sense Input. This pin is connected to the terminal of
32 VSENA
VDDCI controller output voltage.
ISENA2P,
33, 36 Positive Current Sense Input of Channel 1 and 2 for VDDCI Controller.
ISENA1P
ISENA2N,
34, 35 Negative Current Sense Input of Channel 1 and 2 for VDDCI Controller.
ISENA1N
37 EN Controller Enable Control Input. A logic high signal enables the controller.
Power Good Indicator for the VDDCI Controller. This pin is an open-drain
38 PGOODA
output.
Power Good Indicator for the VDDC Controller. This pin is an open-drain
39 PGOOD
output.
VDDCI Controller On-Time Setting. Connect this pin to the converter input
40 TONSETA voltage, VIN, through a resistor, RTONA, to set the on-time of UGATEA and
also the output voltage ripple of VDDCI controller.
41 PWMA2 PWM Output for Channel 2 of VDDCI Controller.
BOOT1,
Bootstrap Supply for High-Side MOSFET. This pin powers high-side MOSFET
46, 2, 42 BOOT2,
driver.
BOOTA1
UGATE1,
High-Side Gate Driver Outputs. Connect this pin to Gate of high-side
47, 1, 43 UGATE2,
MOSFET.
UGATEA1
PHASE1,
Switch Nodes of High-Side Driver. Connect this pin to high-side MOSFET
48, 52, 44 PHASE2,
Source together with the low-side MOSFET Drain and the inductor.
PHASEA1
LGATE1,
49, 51, 45 LGATE2, Low-Side Gate Driver Outputs. This pin drives the Gate of low-side MOSFET.
LGATEA1
50 PVCC Driver Power. Connect this pin to GND by ceramic capacitor larger than 1F.
Ground. The exposed pad must be soldered to a large PCB and connected to
53 (Exposed Pad) GND
GND for maximum power dissipation.

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 RT8899A
Function Block Diagram

PGOODA
PWROK

PGOOD
VSENA

OCP_L
VDDIO
VSEN
OFSA
SET1

SET2

VCC
OFS

SVD

SVT
SVC

EN
IMONAI
IMONI
UVLO
MUX GND

ADC

SVI2 Interface OFS/OFSA

IBIAS Loop Control
Configuration Registers
Load Line Protection Logic
Control Logic /Load Line A
From Control Logic
RSET/RSETA
RGND TONSETA
DAC OCP Threshold
ERROR PWMA2
Soft-Start & Slew VSETA AMP
+ Offset + TON
Rate Control BOOTA1
- Cancellation + - QRA GENA PWMA1
PWM UGATEA1
CMPA 1-PH
FBA TONA Driver PHASEA1
COMPA Current mirror
LGATEA1
ISENA1P +
x2 IBA1 +
ISENA1N - 0.4
V064 - Current
Balance
Current mirror RSETA
ISENA2P + Average IMONAI IBA1 IBA2
x2 IBA2
ISENA2N -
Driver
PVCC
IMONA + OCA POR
OCP_TDCA, To Protection Logic
OCP_SPIKEA -
From Control Logic
VSENA OV/UV/NV TONSET
RGND DAC
ERROR PWM1 BOOTx
Soft-Start & Slew Rate AMP UGATEx
VSET Offset 2-PH
Control + + PWM2
Cancellation TON Driver PHASEx
FB - + - GEN LGATEx
PWM QR
COMP CMP PWM3
Current mirror TON
ISEN1P +
x1 IB1
ISEN1N - +
0.4
-
Current mirror RSET
ISEN2P +
x1 IB2
ISEN2N - Current Balance
Average IMONI
Current mirror IB1 IB2 IB3
ISEN3P +
x1 IB3
ISEN3N -

+ OC
OCP_TDC, To Protection Logic
-
OCP_SPIKE
VSEN OV/UV/NV

IMON V064

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RT8899A
Operation
MUX and ADC Error Amplifier
The MUX supports the inputs from SET1, SET2, OFS, The Error amplifier generates COMP/COMPA signal by
OFSA, IMON, IMONA, VSEN, or VSENA. The ADC the difference between VSET/VSETA and FB/FBA.
converts these analog signals to digital codes for reporting
or performance adjustment. Offset Cancellation
This block cancels the output offset voltage from voltage
SVI2 Interface ripple and current ripple to achieve accurate output voltage.
The SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with GPU. The RT8899A's performance and PWM CMPx
behavior can be adjusted by commands sent by GPU or The PWM comparator compares COMP signal and current
platform. feedback signal to generate a signal for TONGENx.

UVLO TONGEN/TONGENA
The UVLO detects the VCC pin voltages for under voltage This block generates an on-time pulse which high interval
lockout protection and power on reset operation. is based on the on-time setting and current balance.

Loop Control Protection Logic Current Balance

Loop control protection logic detects EN and UVLO signals Per-phase current is sensed and adjusted by adjusting
to initiate soft-start function and control PGOOD, on-time of each phase to achieve current balance for each
PGOODA and OCP_L signals after soft-start is finished. phase.
When dual OCP event occurs, the OCP_L pin voltage will
OC/OV/UV/NV
be pulled low.
VSEN/VSENA and output current are sensed for over-
DAC current, over-voltage, under-voltage, and negative-voltage
The DAC receives VID codes from the SVI2 control logic protections.
to generate an internal reference voltage (VSET/VSETA)
RSET/RSETA
for controller.
The Ramp generator is designed to improve noise immunity
Soft-Start and Slew-Rate Control and reduce jitter.
This block controls the slew rate of the internal reference
voltage when output voltage changes.

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 RT8899A
Table 1. Serial VID Codes
SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V)
0000_0000 1.55000 0010_0111 1.30625 0100_1110 1.06250 0111_0101 0.81875
0000_0001 1.54375 0010_1000 1.30000 0100_1111 1.05625 0111_0110 0.81250
0000_0010 1.53750 0010_1001 1.29375 0101_0000 1.05000 0111_0111 0.80625
0000_0011 1.53125 0010_1010 1.28750 0101_0001 1.04375 0111_1000 0.80000
0000_0100 1.52500 0010_1011 1.28125 0101_0010 1.03750 0111_1001 0.79375
0000_0101 1.51875 0010_1100 1.27500 0101_0011 1.03125 0111_1010 0.78750
0000_0110 1.51250 0010_1101 1.26875 0101_0100 1.02500 0111_1011 0.78125
0000_0111 1.50625 0010_1110 1.26250 0101_0101 1.01875 0111_1100 0.77500
0000_1000 1.50000 0010_1111 1.25625 0101_0110 1.01250 0111_1101 0.76875
0000_1001 1.49375 0011_0000 1.25000 0101_0111 1.00625 0111_1110 0.76250
0000_1010 1.48750 0011_0001 1.24375 0101_1000 1.00000 0111_1111 0.75625
0000_1011 1.48125 0011_0010 1.23750 0101_1001 0.99375 1000_0000 0.75000
0000_1100 1.47500 0011_0011 1.23125 0101_1010 0.98750 1000_0001 0.74375
0000_1101 1.46875 0011_0100 1.22500 0101_1011 0.98125 1000_0010 0.73750
0000_1110 1.46250 0011_0101 1.21875 0101_1100 0.97500 1000_0011 0.73125
0000_1111 1.45625 0011_0110 1.21250 0101_1101 0.96875 1000_0100 0.72500
0001_0000 1.45000 0011_0111 1.20625 0101_1110 0.96250 1000_0101 0.71875
0001_0001 1.44375 0011_1000 1.20000 0101_1111 0.95625 1000_0110 0.71250
0001_0010 1.43750 0011_1001 1.19375 0110_0000 0.95000 1000_0111 0.70625
0001_0011 1.43125 0011_1010 1.18750 0110_0001 0.94375 1000_1000 0.70000
0001_0100 1.42500 0011_1011 1.18125 0110_0010 0.93750 1000_1001 0.69375
0001_0101 1.41875 0011_1100 1.17500 0110_0011 0.93125 1000_1010 0.68750
0001_0110 1.41250 0011_1101 1.16875 0110_0100 0.92500 1000_1011 0.68125
0001_0111 1.40625 0011_1110 1.16250 0110_0101 0.91875 1000_1100 0.67500
0001_1000 1.40000 0011_1111 1.15625 0110_0110 0.91250 1000_1101 0.66875
0001_1001 1.39375 0100_0000 1.15000 0110_0111 0.90625 1000_1110 0.66250
0001_1010 1.38750 0100_0001 1.14375 0110_1000 0.90000 1000_1111 0.65625
0001_1011 1.38125 0100_0010 1.13750 0110_1001 0.89375 1001_0000 0.65000
0001_1100 1.37500 0100_0011 1.13125 0110_1010 0.88750 1001_0001 0.64375
0001_1101 1.36875 0100_0100 1.12500 0110_1011 0.88125 1001_0010 0.63750
0001_1110 1.36250 0100_0101 1.11875 0110_1100 0.87500 1001_0011 0.63125
0001_1111 1.35625 0010_0110 1.11250 0110_1101 0.86875 1001_0100 0.62500
0010_0000 1.35000 0100_0111 1.10625 0110_1110 0.86250 1001_0101 0.61875
0010_0001 1.34375 0100_1000 1.10000 0110_1111 0.85625 1001_0110 0.61250
0010_0010 1.33750 0100_1001 1.09375 0111_0000 0.85000 1001_0111 0.60625
0010_0011 1.33125 0100_1010 1.08750 0111_0001 0.84375 1001_1000 0.60000
0010_0100 1.32500 0100_1011 1.08125 0111_0010 0.83750 1001_1001 0.59375
0010_0101 1.31875 0100_1100 1.07500 0111_0011 0.83125 1001_1010 0.58750
0010_0110 1.31250 0100_1101 1.06875 0111_0100 0.82500 1001_1011 0.58125

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RT8899A
SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V)
1001_1100 0.57500 1011_0101 * 0.41875 1100_1110 * 0.26250 1110_0111* 0.10625
1001_1101 0.56875 1011_0110 * 0.41250 1100_1111 * 0.25625 1110_1000* 0.10000
1001_1110 0.56250 1011_0111 * 0.40625 1101_0000 * 0.25000 1110_1001* 0.09375
1001_1111 0.55625 1011_1000 * 0.40000 1101_0001 * 0.24375 1110_1010* 0.08750
1010_0000 0.55000 1011_1001 * 0.39375 1101_0010 * 0.23750 1110_1011* 0.08125
1010_0001 0.54375 1011_1010 * 0.38750 1101_0011 * 0.23125 1110_1100* 0.07500
1010_0010 0.53750 1011_1011 * 0.38125 1101_0100 * 0.22500 1110_1101* 0.06875
1010_0011 0.53125 1011_1100 * 0.37500 1101_0101 * 0.21875 1110_1110* 0.06250
1010_0100 0.52500 1011_1101 * 0.36875 1101_0110 * 0.21250 1110_1111* 0.05625
1010_0101 0.51875 1011_1110 * 0.36250 1101_0111 * 0.20625 1111_0000* 0.05000
1010_0110 0.51250 1011_1111 * 0.35625 1101_1000 * 0.20000 1111_0001* 0.04375
1010_0111 0.50625 1100_0000 * 0.35000 1101_1001 * 0.19375 1111_0010* 0.03750
1010_1000 * 0.50000 1100_0001 * 0.34375 1101_1010 * 0.18750 1111_0011* 0.03125
1010_1001 * 0.49375 1100_0010 * 0.33750 1101_1011 * 0.18125 1111_0100* 0.02500
1010_1010 * 0.48750 1100_0011 * 0.33125 1101_1100 * 0.17500 1111_0101* 0.01875
1010_1011 * 0.48125 1100_0100 * 0.32500 1101_1101 * 0.16875 1111_0110* 0.01250
1010_1100 * 0.47500 1100_0101 * 0.31875 1101_1110 * 0.16250 1111_0111* 0.00625
1010_1101 * 0.46875 1100_0110 * 0.31250 1101_1111 * 0.15625 1111_1000* 0.00000
1010_1110 * 0.46250 1100_0111 * 0.30625 1110_0000* 0.15000 1111_1001* OFF
1010_1111 * 0.45625 1100_1000 * 0.30000 1110_0001* 0.14375 1111_1010* OFF
1011_0000 * 0.45000 1100_1001 * 0.29375 1110_0010* 0.13750 1111_1011* OFF
1011_0001 * 0.44375 1100_1010 * 0.28750 1110_0011* 0.13125 1111_1100* OFF
1011_0010 * 0.43750 1100_1011 * 0.28125 1110_0100* 0.12500 1111_1101* OFF
1011_0011 * 0.43125 1100_1100 * 0.27500 1110_0101* 0.11875 1111_1110* OFF
1011_0100 * 0.42500 1100_1101 * 0.26875 1110_0110* 0.11250 1111_1111* OFF

* Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes

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 RT8899A
Table 2. SET1 Pin Setting for VDDC OCP_TDC Threshold, DVID Compensation and Ramp Setting (RSET)
SET1 Pin SET1 Pin
Voltage OCP_TDC Voltage OCP_TDC
DVID DVID
Before (Respect Before (Respect
Compensation RSET Compensation RSET
Current to OCP_ Current to OCP_
[1] [1]
Injection SPIKE) Injection SPIKE)
VSET1 (mV) VSET1 (mV)
34 145% 836 145%
59 130% 861 130%
85 115% 886 115%
60% 0 60% 1
110 100% 911 100%
135 85% 936 85%
160 70% 961 70%
235 145% 1036 145%
260 130% 1061 130%
285 115% 1086 115%
70% 0 70% 1
310 100% 1112 100%
335 85% 1137 85%
360 70% 1162 70%
435 145% 1237 145%
460 130% 1262 130%
485 115% 1287 115%
75% 0 75% 1
510 100% 1312 100%
535 85% 1337 85%
560 70% 1362 70%
636 145% 1437 145%
661 130% 1462 130%
686 115% 1487 115%
Disable 0 Disable 1
711 100% 1512 100%
736 85% 1537 85%
761 70% 1562 70%

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RT8899A
Table 3. SET1 Pin Setting for VDDCI OCP_TDCA Threshold, DVIDA Compensation and Ramp Setting (RSETA)
SET1 Pin SET1 Pin
Voltage Voltage
OCP_TDCA OCP_TDCA
Difference DVIDA Difference DVIDA
(Respect to (Respect to
VSET1 (Before Compensation RSETA VSET1 (Before Compensation RSETA
OCP_ OCP_
and After [1] and After [1]
SPIKEA) SPIKEA)
Current Current
Injection) (mV) Injection) (mV)
34 145% 836 145%
59 130% 861 130%
85 115% 886 115%
60% 0 60% 1
110 100% 911 100%
135 85% 936 85%
160 70% 961 70%
235 145% 1036 145%
260 130% 1061 130%
285 115% 1086 115%
70% 0 70% 1
310 100% 1112 100%
335 85% 1137 85%
360 70% 1162 70%
435 145% 1237 145%
460 130% 1262 130%
485 115% 1287 115%
75% 0 75% 1
510 100% 1312 100%
535 85% 1337 85%
560 70% 1362 70%
636 145% 1437 145%
661 130% 1462 130%
686 115% 1487 115%
Disable 0 Disable 1
711 100% 1512 100%
736 85% 1537 85%
761 70% 1562 70%

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 RT8899A
Table 4. SET2 Pin Setting for VDDC QR Threshold, DVID Compensation, VDDCI ZLL and OCP Trigger Delay

SET2 Pin Voltage QRTH DVID VDDCI OLL OCPTRGDELAY

Before Current Injection VSET2 (mV) (for VDDC) Compensation [0] Setting (for VDDC/VDDCI)

19 0 10ms
72 0 40ms
Disable 0
122 1 10ms
172 1 40ms
222 0 10ms
272 0 40ms
39mV 0
323 1 10ms
373 1 40ms
423 0 10ms
473 0 40ms
47mV 0
523 1 10ms
573 1 40ms
623 0 10ms
673 0 40ms
55mV 0
723 1 10ms
773 1 40ms
823 0 10ms
874 0 40ms
Disable 1
924 1 10ms
974 1 40ms
1024 0 10ms
1074 0 40ms
39mV 1
1124 1 10ms
1174 1 40ms
1224 0 10ms
1274 0 40ms
47mV 1
1324 1 10ms
1375 1 40ms
1425 0 10ms
1475 0 40ms
55mV 1
1525 1 10ms
1575 1 40ms

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RT8899A
Table 5. SET2 Pin Setting for Offset Function, DVIDA Compensation and VDDCI QR Threshold
DVIDA
SET2 Pin Voltage Difference VSET2 QRTHA
OFSENABLE OFSAENABLE Compensation
(Before and After Current Injection) (mV) (for VDDCI)
[0]
19 Disable
72 39mV
0
122 47mV
172 55mV
0
222 Disable
272 39mV
1
323 47mV
373 55mV
0
423 Disable
473 39mV
0
523 47mV
573 55mV
1
623 Disable
673 39mV
1
723 47mV
773 55mV
823 Disable
874 39mV
0
924 47mV
974 55mV
0
1024 Disable
1074 39mV
1
1124 47mV
1174 55mV
1
1224 Disable
1274 39mV
0
1324 47mV
1375 55mV
1
1425 Disable
1475 39mV
1
1525 47mV
1575 55mV

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 RT8899A
Table 6. DVID Boost Compensation Setting
DVID Compensation [1] DVID Compensation [0] DVID Boost Compensation
0 0 22.5mV
0 1 18mV
1 0 13.5mV
1 1 9mV

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RT8899A
Absolute Maximum Ratings (Note 1)
 VCC to GND --------------------------------------------------------------------------------------------------------- −0.3V to 6V
 PVCC to GND ------------------------------------------------------------------------------------------------------- −0.3V to 6V
 RGND to GND ------------------------------------------------------------------------------------------------------- −0.3V to 0.3V
 TONSET, TONSETA to GND ------------------------------------------------------------------------------------- −0.3V to 28V
 BOOTx to PHASEx ------------------------------------------------------------------------------------------------ −0.3V to 6V
 PHASEx to GND
DC ---------------------------------------------------------------------------------------------------------------------- −0.3V to 32V
< 20ns ---------------------------------------------------------------------------------------------------------------- −8V to 38V
 LGATEx to GND
DC ---------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
< 20ns ---------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V
 UGATEx to PHASEx
DC ---------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
< 20ns ---------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V
 Other Pins ------------------------------------------------------------------------------------------------------------ −0.3V to (VCC + 0.3V)
 Power Dissipation, PD @ TA = 25°C
WQFN-52L 6x6 ----------------------------------------------------------------------------------------------------- 3.77W
 Package Thermal Resistance (Note 2)
WQFN-52L 6x6, θJA ------------------------------------------------------------------------------------------------ 26.5°C/W
WQFN-52L 6x6, θJC ----------------------------------------------------------------------------------------------- 6.5°C/W
 Junction Temperature ---------------------------------------------------------------------------------------------- 150°C
 Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260°C
 Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Supply Voltage, VCC, PVCC ------------------------------------------------------------------------------------ 4.5V to 5.5V
 Input Voltage, VIN -------------------------------------------------------------------------------------------------- 4.5V to 26V
 Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Power Supply
Supply Current IVCC EN = 3V, Not Switching -- 12 -- mA
Shutdown Current ISHDN EN = 0V -- -- 5 A
PVCC Supply Voltage VPVCC 4.5 -- 5.5 V
PVCC Supply Current IPVCC VBOOTx = 5V, Not Switching -- 150 -- A

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14
 RT8899A
Parameter Symbol Test Conditions Min Typ Max Unit
Driver Power On Reset (Driver POR)
VPOR_r PVCC Rising -- 3.85 4.1
Driver POR Threshold V
VPOR_f PVCC Falling 3.4 3.65 --
Driver POR Hysteresis VPOR_Hys -- 200 -- mV
Reference and DAC
VFB = 1.0000  1.5500
0.5 0 0.5 %SVID
(No Load, CCM Mode )
DC Accuracy VFB VFB = 0.8000  1.0000 5 0 5
VFB = 0.3000  0.8000 8 0 8 mV
VFB = 0.2500  0.3000 80 0 80
RGND Current
RGND Current IRGND EN = 3V, Not Switching -- 200 -- A
Slew Rate
Dynamic VID Slew Rate SR SetVID Fast 7.5 12 -- mV/s
Error Amplifier
Input Offset VEAOFS -- -- 2 mV
DC Gain ADC RL = 47k 70 80 -- dB
Gain-Bandwidth Product GBW CLOAD = 5pF -- 10 -- MHz
Output Voltage Range VCOMP 0.3 -- 3.6 V
Maximum Source Current IEA, SRC 1 -- -- mA
Maximum Sink Current IEA, SNK 1 -- -- mA
Current Sense Amplifier
Input Offset Voltage VOSCS 0.2 -- 0.2 mV
Current Mirror Gain for
AMIRROR, VDDC 97 -- 103 %
VDDC
Current Mirror Gain for
AMIRROR, VDDCI 194 -- 206 %
VDDCI
Internal Sum Current
Ai, VDDC VDDC Controller -- 0.4 -- V/V
Sense DC Gain for VDDC
Internal Sum Current
Ai, VDDCI VDDCI Controller -- 0.8 -- V/V
Sense DC Gain for VDDCI
Maximum Source Current ICS, SRC 0 < VFB < 2.35 100 -- -- A
Maximum Sink Current ICS, SNK 0 < VFB < 2.35 10 -- -- A
Zero Current Detection
Zero Current Detection
VZCD_TH VZCD_TH = GND  VPHASEx -- 1 -- mV
Threshold
Ton Setting
TONSETx Pin Minimum
VTON, MIN -- 0.5 -- V
Voltage
TONSETx Ton TON IRTON = 80A, VFB = 1.1V 270 305 340 ns
TONSETx Input Current
IRTON VFB = 1.1V 25 -- 280 A
Range
Minimum TOFF TOFF -- 250 -- ns

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15
RT8899A
Parameter Symbol Test Conditions Min Typ Max Unit
IBIAS
IBIAS Pin Voltage VIBIAS RIBIAS = 100k 1.97 2 2.03 V
V064
Reference Voltage Output V064 0.61 0.64 0.67 V
Sink Current Capability IV064, SNK V064 = 0.64V 800 -- -- A
Source Current Capability IV064, SRC -- -- 100 A
Board OFSx
VFB Limit VFB, LIMIT 0 -- 2.35 V
OFS Update Rate FOFS -- 50 -- kHz
Board Offset Resolution VOFS -- 6.25 -- mV
Logic Inputs
EN Input Logic-High VIH_EN 2 -- --
V
Voltage Logic-Low VIL_EN -- -- 0.8
Leakage Current of EN ILEK_EN 1 -- 1 A
SVC, SVD, Logic-High VIH_SVI Respect to VDDIO 70 -- 100
%
SVT, PWROK Logic-Low VIL_SVI Respect to VDDIO 0 -- 35
Hysteresis of SVC, SVD,
V Respect to VDDIO 10 -- -- %
SVT, PWROK Input Voltage HYS_SVI
Protection
Under-Voltage Lockout
VUVLO VCC Falling edge 4 4.2 4.4 V
Threshold
Under-Voltage Lockout
VUVLO -- 100 -- mV
Hysteresis
Under-Voltage Lockout VCC Rising above UVLO
TUVLO -- 3 -- s
Delay Threshold
VID VID VID
Over-Voltage Protection VID Higher than 0.9V
VOVP + 275 + 325 + 375 mV
Threshold
VID Lower than 0.9V 1175 1225 1275
Over-Voltage Protection
TOVP VSEN Rising above Threshold -- 1 -- s
Delay
Under-Voltage Protection
VUVP Respect to VID Voltage 575 500 425 mV
Threshold
Under-Voltage Protection
TUVP VSEN Falling below Threshold -- 3 -- s
Delay
Negative-Voltage
VNV -- 0 -- mV
Protection Threshold
I Per-Phase OCP
Per Phase OCP Threshold IOCP_PERPHASE ISENxN -- 10 -- A
Threshold.
Delay of Per Phase OCP TPHOCP -- 1 -- s
DCR = 1.1m, RSENSE = 1.1k,
OCP_SPIKE Threshold IOCP_SPIKE 68 75 83 A
RIMON = 34.3k
TOCPSPIKE
OCP_SPIKE Action Delay 6 -- 12 s
_ACTION_DLY

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16
 RT8899A
Parameter Symbol Test Conditions Min Typ Max Unit
T OCPTDC
OCP_TDC Action Delay 12 -- 24 s
_ACTION_DLY

OCP_L, PGOOD and PGOODA

Output Low Voltage at
VOCP_L I OCP_L = 4mA 0 -- 0.2 V
OCP_L
OCP_L Assertion Time T OCP_L 2 -- -- s
Output Low Voltage at VPGOOD
I PGOOD = 4mA, IPGOODA = 4mA 0 -- 0.2 V
PGOOD, PGOODA VPGOODA
PGOOD and PGOODA VTH_PGOOD
Respect to VBOOT -- 300 -- mV
Threshold Voltage VTH_PGOODA
PGOOD and PGOODA T PGOOD VSEN = VBOOT to
70 100 130 s
Delay Time T PGOODA PGOOD/PGOODA High
Current Report
Maximum Reported Current % OCP
-- 100 -- _SPIKE
(FFh = OCP)
Minimum Reported Current % OCP
-- 0 --
(00h) _SPIKE
Spike Current Accuracy -- -- 3 %
Voltage Report
Maximum Reported Voltage
(0_00h) -- 3.15 -- V
Minimum Reported Voltage
-- 0 -- V
(1_F8h)
Voltage Accuracy 2 -- 2 LSB
PWM Driving Capability
PWMx Source Resistance RPWM_SRC -- 20 -- 
PWMx Sink Resistance RPWM_SNK -- 10 -- 
Switching Time
UGATEx Rise Time tUGATEr 3nf Load -- 8 -- ns
UGATEx Fall Time tUGATEf 3nf Load -- 8 -- ns
LGATEx Rise Time tLGATEr 3nf Load -- 8 -- ns
LGATEx Fall Time tLGATEf 3nf Load -- 4 -- ns
UGATEx Turn-On
tPDHU Outputs Unloaded -- 20 -- ns
Propagation Delay
LGATEx Turn-On
tPDHL Outputs Unloaded -- 20 -- ns
Propagation Delay

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RT8899A
Parameter Symbol Test Conditions Min Typ Max Unit
Output
UGATEx Driver Source
RUGATEsr 100mA Source Current -- 1 -- 
Resistance
UGATEx Driver Source
IUGATEsr VUGATE VPHASE = 2.5V -- 2 -- A
Current
UGATEx Driver Sink
RUGATEsk 100mA Sink Current -- 1 -- 
Resistance
UGATEx Driver Sink
IUGATEsk VUGATE VPHASE = 2.5V -- 2 -- A
Current
LGATEx Driver Source
RLGATEsr 100mA Source Current -- 1 -- 
Resistance
LGATEx Driver Source
ILGATEsr VLGATE = 2.5V -- 2 -- A
Current
LGATEx Driver Sink
RLGATEsk 100mA Sink Current -- 0.5 -- 
Resistance
LGATEx Driver Sink
Current
ILGATEsk VLGATE = 2.5V -- 4 -- A

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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18
 2.2 50 VDDIO
5V PVCC
2.2µF RT8899A 18 2.2
VCC5 VDDIO
10 28 1µF
5V VCC 4.7k 4.7k 3.3V
2.2µF OCP_L 27

DS8899A-02
20k 19
VCC5 23 OFS
PWROK 10k 10k
20k 24 OFSA
VCC5
PGOOD 39
124k 1k
VCC5 25 SET1
PGOODA 38
43k 20
124k 1k 26 SVC
VCC5 SET2 21 To GPU
470 1.47k SVD
6.32k 0.1µF 6.32k 0.1µF
22
SVT
0 RIBIAS
29 100k

September 2014
RTON IBIAS
4.7 150k 4 TONSET
VIN GND 53 (Exposed Pad)
0.1µF RTONA
4.7 137k 40
VIN TONSETA 0
VSEN 11
0.1µF
22pF 270pF VVDDC_SENSE
Typical Application Circuit

37 EN
Enable VSS_SENSE
16 13 65.48k 10k
V064 COMP
0.47µF 18.7k
RNTC RIMON FB 12 VIN
7.999k 100k 18.432k 15
IMON 10 10
46 2.2 0.1µF

Copyright © 2014 Richtek Technology Corporation. All rights reserved.

16k BOOT1 270µF
0
UGATE1 47
RNTC RIMONA 0.36µH/1.1m 
10.47k 100k 11.665k 17 48 VVDDC
IMONA PHASE1
0 49 0
VVDDCI_SENSE LGATE1 1 1µF LOAD
32 VSENA 330
270pF 22pF
3.3nF

10k 51.28k POSCAP : 330µF x 4

30 ISEN1P 8
COMPA RSENSE1
VSS_SENSE MLCC : 22µF x 15
31 FBA 1.1k
14 RGND ISEN1N 7
VIN 0.1µF
VIN
5V
10 10 0.1µF 2 2.2 0.1µF
2.2 BOOT2
BOOT VCC 270µF
270µF 0
0 1µF UGATE2 1
UGATE PGND 0.36µH/1.1m 
VVDDCI 0.36µH/1.1m PHASE2 52
PHASE PWM
41 PWMA2
51 0 1µF
1µF 0 LGATE2 1 330
LOAD 330 1 LGATE EN 5V
RT9610 3.3nF
3.3nF
36 ISEN2P 5
POSCAP : 330µF x 2 ISENA1P RSENSE2
RSENSEA1
1.1k ISEN2N 6 1.1k
MLCC : 22µF x 10 35 ISENA1N
0.1µF 5V 0.1µF VIN
VIN
0.1µF 2.2 0.1µF
2.2 VCC BOOT
42 BOOTA1 270µF
270µF 1µF 0
0 43 PGND UGATE
UGATEA1 0.36µH/1.1m 
0.36µH/1.1m  3 PHASE
44 PWM3 PWM
PHASEA1 0
0 5V EN LGATE 1 1µF
1µF 45 330
330 1 LGATEA1 RT9610
3.3nF
3.3nF
33 ISENA2P ISEN3P 9
RSENSE3

is a registered trademark of Richtek Technology Corporation.

RSENSEA2
1.1k 1.1k
34 ISENA2N ISEN3N 10
0.1µF 0.1µF

19
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RT8899A
 RT8899A
Typical Operating Characteristics
VDDC Power On from EN VDDC Power Off from EN

V VDDC V VDDC
(500mV/Div) (500mV/Div)

EN EN
(4V/Div) (4V/Div)
PGOOD PGOOD
(2V/Div) (2V/Div)

UGATE1 UGATE1
(30V/Div) Boot VID = 0.8V (30V/Div) Boot VID = 0.8V

Time (200μs/Div) Time (200μs/Div)

VDDC OCP_TDC VDDC OCP_SPIKE

I LOAD I LOAD
(40A/Div) (40A/Div)
OCP_L OCP_L
(2V/Div) (2V/Div)

PGOOD PGOOD
(2V/Div) (2V/Div)
UGATE1 UGATE1
(30V/Div) ILOAD = 20A to 60A (30V/Div) ILOAD = 25A to 80A

Time (5ms/Div) Time (10μs/Div)

VDDC OVP and NVP VDDC UVP

V VDDC V VDDC
(1V/Div) (1V/Div)
PGOOD PGOOD
(2V/Div) (2V/Div)

UGATE1 UGATE1
(50V/Div) (50V/Div)
LGATE1 LGATE1
(10V/Div) VID = 1.1V (10V/Div) VID = 1.1V

Time (20μs/Div) Time (10μs/Div)

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20
 RT8899A

VDDC Dynamic VID Up VDDC Load Transient

V VDDC V VDDC
(1V/Div) (50mV/Div)

I LOAD
(5A/Div)
SVD
(2V/Div)

SVT I LOAD
(2V/Div) VID = 0.4V to 1V, ILOAD = 3.6A (25A/Div) fLOAD = 10kHz, ILOAD = 18A to 50A

Time (20μs/Div) Time (5μs/Div)

VDDC Load Transient VDDCI Power On from EN

V VDDC V VDDCI
(50mV/Div) (500mV/Div)

EN
(4V/Div)
PGOODA
(2V/Div)

I LOAD UGATEA1
(25A/Div) (30V/Div)
fLOAD = 10kHz, ILOAD = 50A to 18A Boot VID = 0.8V

Time (5μs/Div) Time (200μs/Div)

VDDCI Power Off from EN VDDCI OCP_TDC

V VDDCI
(500mV/Div)
I LOAD
(25A/Div)
EN
(4V/Div) OCP_L
(2V/Div)
PGOODA
(2V/Div)
PGOODA
(2V/Div)
UGATEA1 UGATEA1
(30V/Div) (50V/Div)
Boot VID = 0.8V ILOAD = 10A to 45A

Time (200μs/Div) Time (5ms/Div)

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21
RT8899A

VDDCI OCP_SPIKE VDDCI OVP and NVP

I LOAD V VDDCI
(40A/Div) (1V/Div)
OCP_L PGOODA
(2V/Div) (2V/Div)

PGOODA UGATEA1
(2V/Div) (50V/Div)
UGATEA1 LGATEA1
(50V/Div) ILOAD = 20A to 60A (10V/Div) VID = 1.1V

Time (10μs/Div) Time (20μs/Div)

VDDCI UVP VDDCI Dynamic VID Up

V VDDCI
(1V/Div)
V VDDCI
(1V/Div)
I LOAD
PGOODA (5A/Div)
(2V/Div)
SVD
(2V/Div)
UGATEA1
(50V/Div)
LGATEA1 SVT
(10V/Div) VID = 1.1V (2V/Div) VID = 0.4V to 1V, ILOAD = 2.5A

Time (10μs/Div) Time (20μs/Div)

VDDCI Load Transient VDDCI Load Transient

V VDDCI V VDDCI
(40mV/Div) (40mV/Div)

I LOAD I LOAD
(20A/Div) fLOAD = 10kHz, ILOAD = 13A to 33A (20A/Div) fLOAD = 10kHz, ILOAD = 33A to 13A

Time (5μs/Div) Time (5μs/Div)

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22
 RT8899A
Application Information
Power Ready (POR) Detection
During start-up, the RT8899A will detect the voltage at Current
Mirror
the voltage input pins : VCC, PVCC and EN. When VCC
2V
> 4.2V and PVCC > 3.85V, the IC will recognize the power

+
+

-
state of system to be ready (POR = high) and wait for -
enable command at the EN pin. After POR = high and VEN IBIAS
> 2V, the IC will enter start-up sequence for both VDDC
100k
rail and VDDCI rail. If the voltage at the pins of VCC and
EN drop below low threshold, the IC will enter power down
sequence and all the functions will be disabled. Normally, Figure 2. IBIAS Setting
connecting system power to the EN pin is recommended.
The SVID will be ready in 2ms (max) after the chip has Boot VID
been enabled. All the protection latches (OVP, OCP, UVP)
When EN goes high, both VDDC and VDDCI output begin
will be cleared only after POR = low. The condition of VEN
to soft-start to the boot VID in CCM. Table 7 shows the
= low will not clear these latches.
Boot VID setting. The Boot VID is determined by the SVC
CMP and SVD input states at EN rising edge and it is stored in
VCC +
4.2V - the internal register. The digital soft-start circuit ramps up
CMP
PVCC + POR the reference voltage at a controlled slew rate to reduce
3.85V - inrush current during start-up. When all the output voltages
CMP
EN + Chip EN are above power good threshold (300mV below Boot VID)
2V - at the end of soft-start, the controller asserts power good
Figure 1. Power Ready (POR) Detection after a time delay.

Precise Reference Current Generation Table 7. 2-Bit Boot VID Code

The RT8899A includes complicated analog circuits inside Initial Startup VID (Boot VID)
the controller. The IC needs very precise reference voltage/ SVC SVD VDDC/VDDCI Output Voltage (V)
current to drive these analog circuits. The IC will auto 0 0 1.1
generate a 2V voltage source at the IBIAS pin, and a 100kΩ 0 1 1.0
resistor is required to be connected between IBIAS and 1 0 0.9
analog ground, as shown in Figure 2. Through this 1 1 0.8
connection, the IC will generate a 20μA current from the
IBIAS pin to analog ground, and this 20μA current will be
Start-Up Sequence
mirrored for internal use. Note that other type of connection
or other values of resistance applied at the IBIAS pin may After EN goes high, the RT8899A starts up and operates
cause functional failure, such as slew rate control, OFS according to the initial settings. Figure 3 shows the
accuracy, etc. In other words, the IBIAS pin can only be simplified sequence timing diagram. The detailed operation
connected with a 100kΩ resistor to GND. The resistance is described in the following.
accuracy of this resistor is recommended to be 1% or
higher.

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23
RT8899A
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

PVCC, VCC
SVID
SVID
Send
Send
SVC Byte
Byte

SVD

VOTF VOTF
Complete Complete

SVT

EN

PWROK
Boot VID Boot VID
CCM VID VID
CCM
CCM CCM CCM CCM CCM
VDDC/
VDDCI

PGOOD/
PGOODA
Figure 3. Simplified Sequence Timing Diagram

Description of Figure 3 :
T0 : The RT8899A waits for VCC and PVCC POR. T7 : The PWROK pin goes low and the SVI2 interface
T1 : The SVC pin and SVD pin set the Boot VID. Boot VID stops running. All output voltages go back to the boot VID
is latched at EN rising edge. SVT is driven high by the in CCM.
RT8899A. T8 : The PWROK pin goes high again and the SVI2
T2 : The enable signal goes high and all output voltages interface starts running. The RT8899A waits for SVID
ramp up to the Boot VID in CCM. The soft-start slew rate command from processor.
is 3mV/μs. T9 : A valid SVID command transaction occurs between
T3 : All output voltages are within the regulation limits and the processor and the RT8899A.
the PGOOD and PGOODA signal goes high. T10 : The RT8899A starts VID on-the-Fly transition
T4 : The PWROK pin goes high and the SVI2 interface according to the received SVID command and send a
starts running. The RT8899A waits for SVID command VOTF Complete if the VID reaches target VID.
from processor. T11 : The enable signal goes low and all output voltages
T5 : A valid SVID command transaction occurs between enter soft-shutdown mode.
the processor and the RT8899A.
T6 : The RT8899A starts VOTF (VID on-the-Fly) transition
according to the received SVID command and send a
VOTF Complete if the VID reaches target VID.

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24
 RT8899A
Power-Down Sequence SVI2 Wire Protocol
If the voltage at the EN pin falls below the enable falling The RT8899A complies with AMD's Voltage Regulator
threshold, the controller is disabled. The voltage at the Specification, which defines the Serial VID Interface 2
PGOOD and PGOODA pins will immediately go low at (SVI2) protocol. With SVI2 protocol, the processor directly
the loss of enable signal at the EN pin and the controller controls the reference voltage level of each individual
executes soft-shutdown operation. The internal digital controller channel and determines which controller
circuit ramps down the reference voltage at the same slew operates in power saving mode. The SVI2 interface is a
rate as that of in soft-start, making VDDC and VDDCI three-wire bus that connects a single master to one or
output voltages gradually decrease in CCM. Each of the above slaves. The master initiates and terminates SVI2
controller channels stops switching when the voltage at transactions and drives the clock, SVC, and the data, SVD,
the voltage sense pin VSEN/VSENA, cross about 0.2V. The during a transaction. The slave drives the telemetry, SVT
Boot VID information stored in the internal register is during a transaction. The AMD processor is always the
cleared at IC POR. This event forces the RT8899A to check master. The voltage regulator controller (RT8899A) is
the SVC and SVD inputs for a new boot VID when the EN always the slave. The RT8899A receives the SVID code
voltage goes high again. and acts accordingly. The SVI protocol supports 20MHz
high speed mode I2C, which is based on SVD data packet.
PGOOD and PGOODA Table 8 shows the SVD data packet. A SVD packet
The PGOOD and PGOODA are open-drain logic outputs. consists of a “Start” signal, three data bytes after each
The two pins provide the power good signal when VDDC byte, and a “Stop” signal. The 8-bit serial VID codes are
and VDDCI output voltage are within the regulation limits listed in Table1. After the RT8899A has received the stop
and no protection is triggered. These pins are typically sequence, it decodes the received serial VID code and
tied to 3.3V or 5V power source through a pull-high executes the command. The controller has the ability to
resistor. During shutdown state (EN = low) and the soft- sample and report voltage and current for the VDDC and
start period, the PGOOD and PGOODA voltages are pulled VDDCI domains. The controller reports this telemetry
low. After a successful soft-start and VDDC and VDDCI serially over the SVT wire which is clocked by the
output voltages are within the regulation limits, the PGOOD processor driven SVC. A bit TFN at SVD packet along
and PGOODA are released high individually. with the VDDC and VDDCI domain selector bits are used
The voltages at the PGOOD and PGOODA pins are pulled by the processor to change the telemetry functionality.
low individually during normal operation when any of the The telemetry bit definition is listed in Figure 4. The detailed
following events occurs : over-voltage protection, under- SVI2 specification is outlined in the AMD Voltage Regulator
voltage protection, over-current protection, and logic low and Voltage Regulator Module (VRM) and Serial VID
EN voltage. If one rail triggers protection, another rail's Interface 2.0 (SVI2) Specification.
PGOOD will be pull low after 5μs delay.
Table 8. SVD Data Packet
Bit Time Description
1:5 Always 11000b
VDDC domain selector bit, if set then the following two data bytes contain the VID for VDDC,
6
the PSI state for VDDC, and the load-line slope trim and offset trim state for VDDC.
VDDCI domain selector bit, if set then the following two data bytes contain the VID for VDDCI,
7
the PSI state for VDDCI, and the load-line slope trim and offset trim state for VDDCI.
8 Always 0b
10 PSI0_L
11 : 17 VID Code bits [7:1]
19 VID Code bit [0]

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RT8899A
Bit Time Description
20 PSI1_L
21 TFN (Telemetry Functionality)
22 : 24 Load Line Slope Trim [2:0]
25 : 26 Offset Trim [1:0]

Voltage and Current VDDCI Voltage Bit in Voltage Only Mode;

VDDC Voltage Bits
Mode Selection Current Bit in Voltage and Current Mode

Bit Time…… START STOP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

SVC

SVT

Figure 4. Telemetry Bit Definition

PWROK and SVI2 Operation VID on-the-Fly Transition

The PWROK pin is an input pin, which is connected to After the RT8899A has received a valid SVID code, it enters
the global power good signal from the platform. Logic high CCM mode and executes the VID on-the-Fly transition by
at this pin enables the SVI2 interface, allowing data stepping up/down the reference voltage of the required
transaction between processor and the RT8899A. Once controller channel(s) in a controlled slew rate, hence
the RT8899A receives a valid SVID code, it decodes the allowing the output voltage(s) to ramp up/down to the target
information from processor to determine which output VID. The output voltage slew rate during the VID on-the-
plane is going to move to the target VID. The internal DAC Fly transition is faster than that in a soft-start/soft-shutdown
then steps the reference voltage in a controlled slew rate, operation. If the new VID level is higher than the current
making the output voltage shift to the required new VID. VID level, the controller begins stepping up the reference
Depending on the SVID code, more than one controller voltage with a typical slew rate of 12.5mV/μs upward to
channel can be targeted simultaneously in the VID the target VID level. If the new level is lower than the current
transition. For example, VDDC and VDDCI voltages can VID level, the controller begins stepping down the reference
ramp up/down at the same time. voltage with a typical slew rate of −12.5mV/μs downward
If the PWROK input goes low during normal operation, to the target VID level.
the SVI2 protocol stops running. The RT8899A During the VID on-the-Fly transition, the RT8899A will force
immediately drives SVT high and modifies all output the controller channel to operate in CCM mode. If the
voltages back to the boot VID, which is stored in the internal controller channel operates in the power-saving mode prior
register right after the controller is enabled. The controller to the VID on-the-Fly transition, it will be in CCM mode
does not read SVD and SVC inputs after the loss of during the transition and then back to the power saving
PWROK. If the PWROK input goes high again, the SVI2 mode at the end of the transition. The voltage at the
protocol resumes running. The RT8899A then waits to PGOOD and PGOODA pins will keep high during the VID
decode the SVID command from processor for a new VID on-the-Fly transition. The RT8899A checks the output
and acts as previously described. The SVI2 protocol is voltage for voltage-related protections and send a VOTF
only runs when the PWROK input goes high after the complete at the end of VID on-the-Fly transition. In the
voltage at the EN pin goes high; otherwise, the RT8899A event of receiving a VID off code, the RT8899A steps the
will not soft-start due to incorrect signal sequence. reference voltage of required controller channel down to
zero, hence making the required output voltage decrease
to zero. The voltage at the PGOOD pin and PGOODA pin
will remain high since the VID code is valid.
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 RT8899A
Power State Transition Table 10. VDDCI VR Power State
The RT8899A supports power state transition function in Full Phase
PSI0_L : PSI1_L Mode
Number
VDDC and VDDCI rail for the PSI[x]_L and command from
11 or 10 2 phase CCM
AMD processor. The PSI[x]_L bit in the SVI2 protocol
2 01 1 phase DEM
controls the operating mode of the RT8899A controller
channels. The default operation mode of VDDC and VDDCI 00 1 phase DEM
rail is CCM. 11 or 10 1 phase CCM
1 01 1 phase DEM
When the VDDC rail is in N phase configuration and receives
00 1 phase DEM
PSI0_L = 0 and PSI1_L = 1, the VDDC rail will entries
single-phase diode emulation mode. When the VDDC rail Differential Remote Sense Setting
receives PSI0_L = 0 and PSI1_L = 0, the VDDC rai remains
The VDDC and VDDCI controllers have differential, remote-
diode emulation mode. In reverse, the VDDC rail goes
sense inputs to eliminate the effects of voltage drops along
back to N phase operation in CCM upon receiving PSI0_L
the PC board traces, processor internal power routes and
= 1 and PSI1_L = 0 or 1, see Table 9. When the VDDCI
socket contacts. The processor contains on-die sense
rail receives PSI0_L = 0 and PSI1_L = 1, it enters single-
pins, VDDC_SENSE, VDDCI_SENSE and VSS_SENSE.
phase diode emulation mode, when the VDDCI rail
Connect RGND to VSS_SENSE. For VDDC controller,
receives PSI0_L = 0 and PSI1_L = 0, it remains single-
connect FB to VDDC_SENSE with a resistor to build the
phase diode emulation mode. When the VDDCI rail goes
negative input path of the error amplifier. Connect FBA to
back to full-phase CCM operation after receiving PSI0_L
VDDCI_SENSE with a resistor using the same way in
= 1 and PSI1_L = 0 or 1, see Table 10.
VDDC controller. Connect VSS_SENSE to RGND using
Table 9. VDDC VR Power State separate trace as shown in Figure 5. The precision
reference voltages refer to RGND for accurate remote
Full Phase
PSI0_L : PSI1_L Mode sensing.
Number
Processor
11 or 10 3 phase CCM
VDDC_SENSE VDDCI_SENSE
3 01 1 phase DEM FB FBA
VDDC VDDCI
00 1 phase DEM Controller Controller
RGND RGND
11 or 10 2 phase CCM
VSS_SENSE
2 01 1 phase DEM
00 1 phase DEM Figure 5. Differential Remote Voltage Sense Connection
11 or 10 1 phase CCM
SET1 and SET2 Pin Setting
1 01 1 phase DEM
The RT8899A provides the SET1 pin for platform users to
00 1 phase DEM
set the VDDC and VDDCI controller OCP_TDC threshold,
DVIDx compensation bit1 and internal ramp amplitude
(RSET & RSETA), and the SET2 pin to set VDDC and
VDDCI controller OCP trigger delay (OCPTRGDELAY),
DVIDx compensation bit0, external offset function VDDCI
zero load-line and quick response threshold (QRTH &
QRTHA). To set these pin, platform designers should use
resistive voltage divider on these pins, refer to Figure 6
and Figure 7. The voltages at the the SET1 and SET2
pins are : RSET1,D
VSET1  VCC  (1)
RSET1,U  RSET1,D

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RT8899A
RSET2,D VDDC Controller
VSET2  VCC  (2)
RSET2,U  RSET2,D
Active Phase Determination
The ADC monitors and decodes the voltage at this pin
The number of active phases is determined by the internal
only once after power up. After ADC decoding (only once),
circuitry that monitors the ISENxN voltages during start-
a 40μA current (when VCC = 5V) will be generated at the
up. Normally, the VDDC controller operates as a 3-phase
SET1 and SET2 pin for internal use. That is the voltage at
PWM controller. Pulling ISEN3N to VCC programs a 2-
SET1 and SET2 pin is
phase operation, and pulling ISEN2N to VCC programs a
RSET1,U  RSET1,D
VSET1  40A  (3) 1-phase operation. At EN rising edge, VDDC controller
RSET1,U  RSET1,D
detects whether the voltages of ISEN2N and ISEN3N are
RSET2,U  RSET2,D higher than “VCC − 0.5V” respectively to decide how
VSET2  40A  (4)
RSET2,U  RSET2,D many phases should be active. Phase selection is only
From equation (1) to equation (4) and Table 2 to Table 5, active during IC POR. When POR = high, the number of
platform users can set the OCP_TDC threshold, OCP active phases is determined and latched. The unused
trigger delay, internal ramp amplitude, DVIDx compensation ISENxP pins are recommended to be connected to VCC
parameter, VDDCI zero load-line setting and quick and unused PWM pins can be left floating.
response threshold for VDDC and VDDCI controller.
Loop Control
The VDDC controller adopts Richtek's proprietary G-
DVIDx
Compensation NAVPTM topology. The G-NAVPTM is based on the finite
OCPTDCx
40µA gain peak current mode with CCRCOT (Constant Current
RSETx (VCC = 5V)
Ripple Constant On-Time) topology. The output voltage,
VCC
ADC 2.24V
VVDDC will decrease with increasing output load current.
VSET1 The control loop consists of PWM modulators with power
RSET1,U
SET1 SET1 stages, current sense amplifiers and an error amplifier as
Register
shown in Figure 8.
 VSET1 RSET1,D
RT8899A Similar to the peak current mode control with finite
Figure 6. SET1 Pin Setting compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
DVIDx Compensation
VCS increases, the steady state COMP voltage also
and VDDCI zero LL increases and induces VOUT,VDDC to decrease, thus
OCPTR
GDELAY 40µA achieving AVP. A near-DC offset canceling is added to the
QRTHx OFSx (VCC = 5V)
output of EA to eliminate the inherent output offset of finite
VCC gain peak current mode controller.
ADC 2.24V
VSET2
RSET2,U
SET2 SET2
Register
VSET2 RSET2,D
RT8899A

Figure 7. SET2 Pin Setting

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 RT8899A
VIN
Loop Compensation
HS_FET VVDDC
CCRCOT L RSENSE Optimized compensation of the VDDC controller allows
PWM3 Driver
PWM
RX CX for best possible load step response of the regulator's
CMP

Logic
RC
+
-

LS_FET output. A type-I compensator with one pole and one zero
COMP2

ISENxP C
0.4
+
RCSx
is adequate for proper compensation. Figure 10 shows
x1 ISENxN
VCS -
RIMON
the compensation circuit. Previous design procedure
Offset IMON
Canceling
VREF
shows how to select the resistive feedback components
C2 C1
for the error amplifier gain. Next, C1 and C2 must be
COMP R2 R1
VVDDC_SENSE calculated for compensation. The target is to achieve
FB
-
EA RGND constant resistive output impedance over the widest
+

+ VSS_SENSE
-

VDAC,VDDC possible frequency range.

Figure 8. VDDC Controller : Simplified Schematic for The pole frequency of the compensator must be set to
Droop and Remote Sense in CCM compensate the output capacitor ESR zero :
fP  1
(8)
Droop Setting 2   C  RC
Where C is the capacitance of output capacitor, and RC is
It is very easy to achieve Active Voltage Positioning (AVP)
the ESR of output capacitor. C2 can be calculated as
by properly setting the error amplifier gain due to the native
follows :
droop characteristics as shown in Figure 9. This target is
C  RC
to have C2  (9)
R2
VVDDC = VDAC, VDDC − ILOAD x RDROOP (5) The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Then solving the switching condition VCOMP2 = VCS in
Such that,
Figure 8 yields the desired error amplifier gain as
C1  1
(10)
A V  R2 
GI
(6) R1   fSW
R1 RDROOP C2 C1
R
GI  SENSE  RIMON  4 (7) R2 R1
RCSx 10 COMP
VVDDC_SENSE
where GI is the internal current sense amplifier gain. RSENSE FB
-
EA RGND
is the current sense resistor. If no external sense resistor VSS_SENSE
+

+
-

present, it is the equivalent resistance of the inductor. VDAC

RDROOP is the equivalent load-line resistance as well as Figure 10. VDDC Controller : Compensation Circuit
the desired static output impedance.
TON Setting
VVDDC
AV2 > AV1
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra portable
AV2
devices where the load currents are lower and the
AV1
controller is powered from a lower voltage supply. Low
0 Load Current frequency operation offers the best overall efficiency at
Figure 9. VDDC Controller : Error Amplifier gain (AV) the expense of component size and board space. Figure
Influence on VVDDC Accuracy 11 shows the On-Time setting circuit. Connect a resistor
(RTON) between VIN and TONSET to set the on-time of
UGATE :

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RT8899A
12 Current Sense Setting
24.4  10  RTON
tON (0.5V  VDAC  1.8V)  (11)
VIN  VDAC The current sense topology of the VDDC controller is
where tON is the UGATE turn-on period, VIN is Input voltage continuous inductor current sensing. Therefore, the
of the VDDC controller, and VDAC is the DAC voltage. controller has less noise sensitive. Low offset amplifiers
are used for current balance, loop control and over current
When VDAC is larger than 1.8V, the equivalent switching
detection. The ISENxP and ISENxN pins denote the
frequency may be over 500kHz, and this too fast switching
positive and negative input of the current sense amplifier
frequency is unacceptable. Therefore, the VDDC controller
of each phase.
implements a pseudo constant frequency technology to
avoid this disadvantage of CCRCOT topology. When VDAC Users can either use a current sense resistor or the
is larger than 1.8V, the on-time equation will be modified inductor's DCRL for current sensing. Using the inductor's
to : DCRL allows higher efficiency as shown in Figure 12.
12 IL VVDDC
13.55  10  RTON  VDAC (12)
tON (VDAC  1.8V) 
VIN  VDAC L DCRL

RX CX
On-time translates only roughly to switching frequencies.
ISENxN
ISENxP
For better efficiency of the given load range, the maximum +
- RCSx
switching frequency is suggested to be : ISENxN
fSW(MAX) 
VDAC(MAX)  ILOAD(MAX)  DCRL  RON_LS-FET  RDROOP 
 VIN(MAX)  ILOAD(MAX)  RON_LS-FET  RON_HS-FET     TON  TD  TON, VAR   ILOAD(MAX)  RON_LS-FET   TD
Figure 12. VDDC Controller : Lossless Inductor Sensing
 

(13) In order to optimize transient performance, RX and CX must

Where fS(MAX) is the maximum switching frequency, TD is be set according to the equation below :
the driver dead time, TON,VAR is the TON variation value. L  R C (14)
X X
DCRL
VDAC(MAX) is the Maximum VDAC of application, VIN(MAX) is
the Maximum application Input voltage, ILOAD(MAX) is the Then the proportion between the phase current, IL, and
maximum load of application, R ON_LS-FET is the on- the sensed current, ISENxN, is driven by the value of the
resistance of low side FET RDS(ON), RON_HS-FET is the of effective sense resistance, RCSx, and the DCRL of the
resistance of high side FET RDS(ON) , DCRL is the equivalent inductor. The resistance value of RCSx is limited by the
resistance of the inductor, and RDROOP is the load-line internal circuitry. The recommended value is from 500Ω
setting. to 1.2kΩ.
DCRL
ISENxN  IL  (15)
RTON
RCSx
CCRCOT TONSET R1
VIN
On-Time
Computer VDAC Considering the inductance tolerance, the resistor RX has
C1
to be tuned on board by examining the transient voltage.
On-Time If the output voltage transient has an initial dip below the
minimum load-line requirement and the response time is
Figure 11. VDDC Controller : On-Time Setting with RC
too fast causing a ring back, the value of resistance should
Filter
be increased. Vice versa, with a high resistance, the output
voltage transient has only a small initial dip with a slow
response time.

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 RT8899A
Using current sense resistor in series with the inductor Initial Offset and External Offset (Over Clocking
can have better accuracy, but the efficiency is a trade-off. Offset Function)
Considering the equivalent inductance (LESL) of the current The VDDC controller features over clocking offset function
sense resistor, an RC filter is recommended. The RC filter which provides the possibility of wide range offset of output
calculation method is similar to the above mentioned voltage. The initial offset function can be implemented
inductor equivalent resistance sensing method. through the SVI interface. When the OFS pin voltage
< 0.3V at EN rising edge, the initial offset is disabled. The
Per-Phase Over Current Protection
external offset function can be implemented by the SET2
The VDDC controller provides over current protection in pin setting. For example, referring to Table 11, when the
each phase. For VDDC controller in three-phase both rail external offset functions are enabled, the output
configuration, either phase can trigger Per-Phase Over voltage is :
Current Protection (PHOCP). VVDDC  VDAC  ILOAD x RDROOP + VExternal _ OFS
The VDDC controller senses each phase inductor current + VInitial _ OFS (18)
IL, and PHOCP comparator compares sensed current with VInitial_OFS is the initial offset voltage set by SVI interface,
PHOCP threshold current, as shown in Figure 13. and the external offset voltage, VExternal_OFS is set by
supplying a voltage into the OFS pin.
Current Mirror
1 I
8 SENAxN
It can be calculated as below :
PHOCP trigger VExternal _ OFS = VOFS  1.2V (19)
10µA ISENAxN
If supplying 1.3V at OFS pin, it will achieve 100mV offset
at the output. Connecting a filter capacitor between the
OFS and GND pins is necessary. Designers can design
Figure 13. VDDC Controller : Per-Phase OCP Setting
the offset slew rate by properly setting the filter bandwidth.

The resistor RCSx determines PHOCP threshold. Table 11. External Offset Function Setting for VDDC
DCRL 1 and VDDCI Controller
IL,PERPHASE(MAX)   = 10A (16)
RCSx 8 VDDC_ VDDCI_
OFFSET_ OFFSET_ Description
IL,PERPHASE(MAX)  DCRL EN EN
RCSx  (17)
8  10A
0 0 Disable external offset function.

The controller will turn off all high-side/low-side MOSFETs VDDC rail external offset is set
by OFS pin voltage, and
to protect GPU if the per-phase over current protection is 1 1
VDDCI rail external offset is set
triggered. by OFSA pin voltage.

Current Balance
Dynamic VID Enhancement
The VDDC controller implements internal current balance
During a dynamic VID event, the charging (dynamic VID
mechanism in the current loop. The VDDC controller
up) or discharging (dynamic VID down) current causes
senses and compares per-phase current signal with
unwanted load-line effect which degrades the settling time
average current. If the sensed current of any particular
performance. The RT8899A will hold the inductor current
phase is larger than average current, the on-time of this
to hold the load-line during a dynamic VID event. The VDDC
phase will be adjusted to be shorter.
controller will always enter three-phase configuration when
VDDC controller receives dynamic VID up and VDDC
controller will hold the operating state when VDDC
controller receives dynamic VID down.

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RT8899A
The RT8899A also has DVID compensation which can boost VVDDC_SENSE voltage drops abruptly due to load apply
up the Dynamic VID slew rate and adjust the voltage on- transient, the mirrored current flowing into quick response
the-fly complete timing. The DVID compensation parameter circuit will also increase instantaneously.
can be selected by DVIDx compensation bits using the The QR threshold setting for VDDC controller refers to
SET1 and SET2 pins. Table 4.

Ramp Amplitude Adjust QRTH

QR Pulse

+
+ VVDDC_SENSE

-
When the VDDC controller takes phase shedding operation Generation CMP
Circuit -
and enters diode emulation mode, the internal ramp of
VDDC controller will be modified for the reason of stability.
In case of smooth transition into DEM, the CCM ramp
Figure 14. VDDC Controller : Quick Response Triggering
amplitude should be designed properly. The RT8899A
Circuit
provides the SET1 pin for platform users to set the ramp
amplitude of the VDDC controller in CCM. When quick response is triggered, the quick response
circuit will generate a quick response pulse. The pulse
Current Monitoring and Current Reporting
width of quick response is almost the same as tON.
The VDDC controller provides current monitoring function
After generating a quick response pulse, the pulse is then
via inductor current sensing. In the G-NAVPTM technology,
applied to the on-time generating circuit, and all the active
the output voltage is dependent on output current, and
phases' on-time will be overridden by the quick response
the current monitoring function is achieved by this
pulse.
characteristic of output voltage. The equivalent output
current will be sensed from inductor current sensing and Over-Current Protection
mirrored to the IMON pin. The resistor connected to the
The RT8899A has dual OCP mechanism. The dual OCP
IMON pin determines voltage of the IMON output.
mechanism has two types of thresholds. The first type,
DCRL
VIMON = IL,SUM   RIMON  0.64 (20) referred to as OCP-TDC, is a time and current based
RCSx
threshold. OCP-TDC should trip when the average output
Where IL is the phase current, RCSx is the effective sense current exceeds TDC by some percentage and for a period
resistance, and RIMON is the current monitor current setting of time. This period of time is referred to as the trigger
resistor. Note that the IMON pin cannot be monitored. delay. The second type, referred to as OCP-SPIKE, is a
The ADC circuit of the VDDC controller monitors the current based threshold. OCP-SPIKE should trip when
voltage variation at the IMON pin from 0V to 3.19375V, the cycle-by-cycle output current exceeds OCP_SPIKE
and this voltage is decoded into digital format and stored by some percentage. If either mechanism trips, then the
into Output_Current register. The ADC divides 3.19375V VDDC controller asserts OCP_L and delays any further
into 511 levels, so LSB = 3.19375V / 511 = 6.25mV. action. This delay is called an action delay. Refer to action
delay time. After the action delay has expired and the
Quick Response VDDC controller has allowed its current sense filter to
The VDDC controller utilizes a quick response feature to settle out and the current has not decreased below the
support heavy load current demand during instantaneous threshold, then the VDDC controller will turn off both high-
load transient. The VDDC controller monitors the current side MOSFETs and low-side MOSFETs of all channels.
of the VVDDC_SENSE, and this current is mirrored to internal
quick response circuit. At steady state, this mirrored
current will not trigger a quick response. When the

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 RT8899A
Users can set OCP-SPIKE threshold, IL,SUM(SPIKE), by the Under-Voltage Lock Out (UVLO)
current monitor resistor RIMON of the following equation : During normal operation, if the voltage at the VCC pin

IL,SUM (SPIKE) = 3.19375  0.64  CSx

R drops below IC POR threshold, the VDDC controller will
(21)
DCRL RIMON trigger UVLO. The UVLO protection forces all high-side
And set the OCP-TDC threshold, IL(TDC), refer to some MOSFETs and low-side MOSFETs off by shutting down
percentage of OCP-SPIKE through Table 2. internal PWM logic drivers. A 3μs delay is used in UVLO
detection circuit to prevent false trigger.
Over-Voltage Protection (OVP)
The over-voltage protection circuit of the VDDC controller VDDCI Controller
monitors the output voltage via the VSEN pin after IC POR.
Active Phase Determination
When VID is lower than 0.9V, once VSEN voltage exceeds
The number of active phases is determined by the internal
“0.9V + 325mV”, OVP is triggered and latched. When
circuitry that monitors the ISENA2N voltage during start-
VID is larger than 0.9V, once VSEN voltage exceeds the
up. Normally, the VDDCI controller operates as a 2-phase
internal reference by 325mV, OVP is triggered and latched.
PWM controller. Pulling ISENA2N to VCC programs a
The VDDC controller will try to turn on low-side MOSFETs
1-phase operation. At EN rising edge, VDDCI controller
and turn off high-side MOSFETs of all active phases of the
detects whether the voltages of ISENA2N is higher than
VDDC controller to protect the GPU. When OVP is
“VCC − 0.5V” respectively to decide how many phases
triggered by one rail, the other rail will also enter soft shut
should be active. Phase selection is only active during IC
down sequence. A 1μs delay is used in OVP detection
POR. When POR = high, the number of active phases is
circuit to prevent false trigger.
determined and latched. The unused ISENA2P pin is
Negative-Voltage Protection (NVP) recommended to be connected to VCC and unused PWM
During OVP latch state, the VDDC controller also monitors pin can be left floating.
the VSEN pin for negative voltage protection. Since the
Loop Control
OVP latch continuously turns on all low-side MOSFETs
The VDDCI controller adopts Richtek's proprietary G-
of the VDDC controller, the VDDC controller may suffer
NAVPTM topology. The G-NAVPTM is based on the finite
negative output voltage. As a consequence, when the VSEN
gain peak current mode with CCRCOT (Constant Current
voltage drops below 0V after triggering OVP, the VDDC
Ripple Constant On-Time) topology. The output voltage,
controller will trigger NVP to turn off all low-side MOSFETs
VVDDCI will decrease with increasing output load current.
of the VDDC controller while the high-side MOSFETs
The control loop consists of PWM modulators with power
remains off. After triggering NVP, if the output voltage rises
stages, current sense amplifiers and an error amplifier as
above 0V, the OVP latch will restart to turn on all low-side
shown in Figure 15.
MOSFETs. The NVP function will be active only after OVP
is triggered. Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
Under-Voltage Protection (UVP) CCRCOT on-time generator. When load current increases,
The VDDC controller implements under-voltage protection VCS increases, the steady state COMPA voltage also
of VOUT,VDDC. If VSEN voltage is less than the internal increases and induces VVDDCI to decrease, thus achieving
reference by 500mV, the VDDC controller will trigger UVP AVP. A near-DC offset canceling is added to the output of
latch. The UVP latch will turn off both high-side and low- EA to eliminate the inherent output offset of finite gain
side MOSFETs. When UVP is triggered by one rail, the peak current mode controller.
other rail will also enter soft shutdown sequence. A 3μs
delay is used in UVP detection circuit to prevent false
trigger.

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RT8899A
VIN Loop Compensation
HS_FET VVDDCI Optimized compensation of the VDDCI controller allows
CCRCOT L RSENSE
PWMA2 Driver
PWM
RX CX
for best possible load step response of the regulator’s
CMP

Logic
RC
output. A type-I compensator with one pole and one zero
+
-

LS_FET
COMP2

ISENAxP C
0.4
+
RCSx
is adequate for proper compensation. Figure 17 shows
x2 ISENAxN
VCS -
the compensation circuit. Previous design procedure
Offset IMONA RIMONA
Canceling
VREF shows how to select the resistive feedback components
C2 C1
for the error amplifier gain. Next, C1 and C2 must be
COMPA R2 R1
VVDDCI_SENSE calculated for compensation. The target is to achieve
FBA
-
EA RGND
constant resistive output impedance over the widest
+

+ VSS_SENSE
-

VDAC, VDDCI
possible frequency range.
Figure 15. VDDCI Controller : Simplified Schematic for The pole frequency of the compensator must be set to
Droop and Remote Sense in CCM compensate the output capacitor ESR zero :
fP  1
(25)
Droop Setting 2   C  RC
It is very easy to achieve Active Voltage Positioning (AVP) Where C is the capacitance of output capacitor, and RC is
by properly setting the error amplifier gain due to the native the ESR of output capacitor. C2 can be calculated as
droop characteristics as shown in Figure 16. This target follows :
is to have C x RC
C2  (26)
R2
VVDDCI = VDAC,VDDCI − ILOAD x RDROOP (22)
The zero of compensator has to be placed at half of the
Then solving the switching condition VCOMP2 = VCS in switching frequency to filter the switching related noise.
Figure 15 yields the desired error amplifier gain as Such that,
GI 1
A V  R2  (23) C1  (27)
R1 RDROOP R1   fSW
RSENSE C2 C1
where GI   RIMON  8 (24)
RCSx 10 R2 R1
COMPA
VVDDCI_SENSE
where GI is the internal current sense amplifier gain. RSENSE FBA
-
is the current sense resistor. If no external sense resistor EA RGND
VSS_SENSE
+

+
-

present, it is the equivalent resistance of the inductor. VDAC,VDDCI

RDROOP is the equivalent load-line resistance as well as
Figure 17. VDDCI Controller : Compensation Circuit
the desired static output impedance.

VVDDCI TON Setting

AV2 > AV1
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra portable
AV2 devices where the load currents are lower and the
AV1 controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
0 Load Current the expense of component size and board space. Figure
Figure 16. VDDCI Controller : Error Amplifier gain (AV) 18 shows the On-Time setting circuit. Connect a resistor
Influence on VVDDCI Accuracy (RTON) between VIN and TONSETA to set the on-time of
UGATEA :

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 RT8899A
24.4  1012  RTON Current Sense Setting
tON (0.5V  VDAC  1.8V)  (28)
VIN  VDAC,VDDCI The current sense topology of the VDDCI controller is
continuous inductor current sensing. Therefore, the
where tON is the UGATEA turn-on period, VIN is Input
controller has less sensitive noise. Low offset amplifiers
voltage of the VDDCI controller, and VDAC,VDDCI is the DAC
are used for current balance, loop control and over current
voltage.
detection. The ISENAxP and ISENAxN pins denote the
When VDAC,VDDCI is larger than 1.8V, the equivalent positive and negative input of the current sense amplifier
switching frequency may be over 500kHz, and this too of each phase.
fast switching frequency is unacceptable. Therefore, the
Users can either use a current sense resistor or the
VDDCI controller implements a pseudo constant frequency
inductor's DCRL for current sensing. Using the inductor's
technology to avoid this disadvantage of CCRCOT
DCRL allows higher efficiency as shown in Figure 19.
topology. When VDAC,VDDCI is larger than 1.8V, the on-
IL VVDDCI
time equation will be modified to :
tON (VDAC  1.8V) L DCRL
12
13.55  10  RTON  VDAC,VDDCI
 RX CX
VIN  VDAC,VDDCI (29) ISENAxN
ISENAxP
+
On-time translates only roughly to switching frequencies. - ISENAxN RCSx

For better efficiency of the given load range, the maximum

Figure 19. VDDCI Controller : Lossless Inductor Sensing
switching frequency is suggested to be :
fSW(MAX) 
VDAC(MAX)  ILOAD(MAX)  DCRL  RON_LS-FET  RDROOP  In order to optimize transient performance, RX and CX must
 VIN(MAX)  ILOAD(MAX)  RON_LS-FET  RON_HS-FET     TON  TD  TON, VAR   ILOAD(MAX)  RON_LS-FET   TD
  be set according to the equation below :
(30) L  R C (31)
X X
DCRL
Where fS(MAX) is the maximum switching frequency,
Then the proportion between the phase current, IL, and
TD is the driver dead time, TON,VAR is the TON variation
the sensed current, ISENAxN, is driven by the value of the
value. VDAC(MAX) is the Maximum VDAC,VDDNB of application,
effective sense resistance, RCSx, and the DCRL of the
V IN(MAX) is the Maximum application Input voltage,
inductor. The resistance value of RCSx is limited by the
ILOAD(MAX) is the maximum load of application, RON_LS-FET
internal circuitry. The recommended value is from 500Ω
is the on-resistance of low side FET RDS(ON) , RON_HS-FET
to 1.2kΩ.
is the on-resistance of high side FET RDS(ON), DCRL is the
DCRL
inductor equivalent resistance of the inductor, and RDROOP ISENAxN  IL  (32)
RCSx
is the load-line setting.
Considering the inductance tolerance, the resistor RX has
RTON
to be tuned on board by examining the transient voltage.
CCRCOT TONSETA R1
VIN If the output voltage transient has an initial dip below the
On-Time
Computer C1 minimum load-line requirement and the response time is
VDAC,VDDCI
On-Time
too fast causing a ring back, the value of resistance should
be increased. Vice versa, with a high resistance, the output
Figure 18. VDDCI Controller : On-Time Setting with RC voltage transient has only a small initial dip with a slow
filter response time.

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RT8899A
Using current sense resistor in series with the inductor VVDDCI  VDAC,VDDCI  ILOAD  RDROOP
can have better accuracy, but the efficiency is a trade-off. + VExternal _ OFSA + VInitial _ OFSA (35)
Considering the equivalent inductance (LESL) of the current
VInitial_OFSA is the initial offset voltage set by SVI interface,
sense resistor, an RC filter is recommended. The RC filter
and the external offset voltage, VExternal_OFSA is set by
calculation method is similar to the above mentioned
supplying a voltage into the OFSA pin.
inductor equivalent resistance sensing method.
It can be calculated as below :
Per-Phase Over Current Protection VExternal _ OFSA = VOFSA  1.2V (36)
The VDDCI controller provides over current protection in
If supplying 1.3V at OFSA pin, it will achieve 100mV offset
each phase. For VDDCI controller in two-phase
at the output. Connecting a filter capacitor between the
configuration, either phase can trigger Per-Phase Over
OFSA and GND pins is necessary. Designers can design
Current Protection (PHOCP).
the offset slew rate by properly setting the filter bandwidth.
The VDDCI controller senses each phase inductor current
IL, and PHOCP comparator compares sensed current with Dynamic VID Enhancement
PHOCP threshold current, as shown in Figure 20. During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
Current Mirror
1 I unwanted load-line effect which degrades the settling time
8 SENAxN
PHOCP trigger performance. The RT8899A will hold the inductor current
10µA ISENAxN to hold the load-line during a dynamic VID event. The
VDDCI controller will always enter two-phase configuration
when VDDCI controller receives dynamic VID up and VDDCI
Figure 20. VDDCI Controller : Per-Phase OCP Setting controller will hold the operating state when VDDCI
controller receives dynamic VID down.
The resistor RCSx determines PHOCP threshold.
The RT8899A also has DVID compensation which can boost
DCRL 1
IL,PERPHASE(MAX)   = 10A (33) up the Dynamic VID slew rate and adjust the voltage on-
RCSx 8
the-fly complete timing. The DVID compensation parameter
IL,PERPHASE(MAX)  DCRL
RCSx  (34) can be selected by DVIDx compensation bits using the
8  10A
SET1 and SET2 pins.
The controller will turn off all high-side/low-side MOSFETs
to protect GPU if the per-phase over current protection is Ramp Amplitude Adjust
triggered. When the VDDCI controller takes phase shedding
operation and enters diode emulation mode, the internal
Initial Offset and External Offset (Over Clocking ramp of VDDCI controller will be modified for the reason of
Offset Function) stability. In case of smooth transition into DEM, the CCM
The VDDCI controller features over clocking offset function ramp amplitude should be designed properly. The RT8899A
which provides the possibility of wide range offset of output provides the SET1 pin for platform users to set the ramp
voltage. The initial offset function can be implemented amplitude of the VDDCI controller in CCM.
through the SVI interface. When the OFSA pin voltage
< 0.3V at EN rising edge, the initial offset is disabled.
The external offset function can be implemented by the
SET2 pin setting. For example, referring to Table 11, when
the both rail external offset functions are enabled, the
output voltage is :

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 RT8899A
Current Monitoring and Current Reporting After generating a quick response pulse, the pulse is then
The VDDCI controller provides current monitoring function applied to the on-time generation circuit, and all the active
via inductor current sensing. In the G-NAVPTM technology, phases' on-times will be overridden by the quick response
the output voltage is dependent on output current, and pulse.
the current monitoring function is achieved by this
Over-Current Protection
characteristic of output voltage. The equivalent output
current will be sensed from inductor current sensing and The RT8899A has dual OCP mechanism. The dual OCP
mirrored to the IMONA pin. The resistor connected to the mechanism has two types of thresholds. The first type,
IMONA pin determines voltage of the IMONA output. referred to as OCP-TDCA, is a time and current based
threshold. OCP-TDCA should trip when the average output
DCRL
VIMONA = IL,SUM  2   RIMONA  0.64 (37) current exceeds TDCA by some percentage and for a
RCSx
period of time. This period of time is referred to as the
Where IL is the phase current, RCSx is the effective sense
trigger delay. The second type, referred to as OCP-
resistance, and RIMONA is the current monitor current setting
SPIKEA, is a current based threshold. OCP-SPIKEA
resistor. Note that the IMONA pin cannot be monitored.
should trip when the cycle-by-cycle output current
The ADC circuit of the VDDCI controller monitors the exceeds OCP_SPIKEA by some percentage. If either
voltage variation at the IMONA pin from 0V to 3.19375V, mechanism trips, then the VDDCI controller asserts
and this voltage is decoded into digital format and stored OCP_L and delays any further action. This delay is called
into Output_Current register. The ADC divides 3.19375V an action delay. Refer to action delay time. After the action
into 511 levels, so LSB = 3.19375V / 511 = 6.25mV. delay has expired and the VDDCI controller has allowed
its current sense filter to settle out and the current has
Quick Response
not decreased below the threshold, then the VDDCI
The VDDCI controller utilizes a quick response feature to
controller will turn off both high-side MOSFETs and low-
support heavy load current demand during instantaneous
side MOSFETs of all channels.
load transient. The VDDCI controller monitors the current
of the VVDDCI_SENSE, and this current is mirrored to internal Users can set OCP-SPIKEA threshold, IL,SUM(SPIKEA), by
quick response circuit. At steady state, this mirrored the current monitor resistor RIMONA of the following equation :

IL,SUM (SPIKE) = 3.19375  0.64  CSx

current will not trigger a quick response. When the R
(38)
2  DCR RIMONA
VVDDCI_SENSE voltage drops abruptly due to load apply
transient, the mirrored current flowing into quick response And set the OCP-TDCA threshold, IL(TDCA), refer to some
circuit will also increase instantaneously. percentage of OCP-SPIKEA through Table 3.

The QR threshold setting for VDDCI controller refers to Over-Voltage Protection (OVP)
Table 5. The over-voltage protection circuit of the VDDCI controller
QRTHA monitors the output voltage via the VSENA pin after IC
QR Pulse
+

+ VVDDCI_SENSE POR. When VID is lower than 0.9V, once VSENA voltage
-

Generation CMP
Circuit -
exceeds “0.9V + 325mV”, OVP is triggered and latched.
When VID is larger than 0.9V, once VSENA voltage
exceeds the internal reference by 325mV, OVP is triggered
Figure 21. VDDCI Controller : Quick Response
and latched. The VDDCI controller will try to turn on low-
Triggering Circuit
side MOSFETs and turn off high-side MOSFETs of all active
When quick response is triggered, the quick response phases of the VDDCI controller to protect the GPU. When
circuit will generate a quick response pulse. The pulse OVP is triggered by one rail, the other rail will also enter
width of quick response is almost the same as tON. soft shut down sequence. A 1μs delay is used in OVP
detection circuit to prevent false trigger.

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37
RT8899A
Negative-Voltage Protection (NVP) where TJ(MAX) is the maximum junction temperature, TA is
During OVP latch state, the VDDCI controller also monitors the ambient temperature, and θJA is the junction to ambient
the VSENA pin for negative voltage protection. Since the thermal resistance.
OVP latch continuously turns on all low-side MOSFETs For recommended operating condition specifications, the
of the VDDCI controller, the VDDCI controller may suffer maximum junction temperature is 125°C. The junction to
negative output voltage. As a consequence, when the ambient thermal resistance, θJA, is layout dependent. For
VSENA voltage drops below 0V after triggering OVP, the WQFN-52L 6x6 package, the thermal resistance, θJA, is
VDDCI controller will trigger NVP to turn off all low-side 26.5°C/W on a standard JEDEC 51-7 four-layer thermal
MOSFETs of the VDDCI controller while the high-side test board. The maximum power dissipation at TA = 25°C
MOSFETs remains off. After triggering NVP, if the output can be calculated by the following formula :
voltage rises above 0V, the OVP latch will restart to turn
PD(MAX) = (125°C − 25°C) / (26.5°C/W) = 3.77W for
on all low-side MOSFETs. The NVP function will be active
WQFN-52L 6x6 package
only after OVP is triggered.
The maximum power dissipation depends on the operating
Under-Voltage Protection (UVP) ambient temperature for fixed T J(MAX) and thermal
The VDDCI controller implements under-voltage protection resistance, θJA. The derating curve in Figure 22 allows
of VOUT,VDDCI. If VSENA voltage is less than the internal the designer to see the effect of rising ambient temperature
reference by 500mV, the VDDCI controller will trigger UVP on the maximum power dissipation.
latch. The UVP latch will turn off both high-side and low- 4.0
Four-Layer PCB
Maximum Power Dissipation (W)1

side MOSFETs. When UVP is triggered by one rail, the 3.6

other rail will also enter soft shutdown sequence. A 3μs 3.2

delay is used in UVP detection circuit to prevent false 2.8

trigger. 2.4
2.0
Under-Voltage Lock Out (UVLO) 1.6
During normal operation, if the voltage at the VCC pin 1.2
drops below IC POR threshold, the VDDCI controller will 0.8
trigger UVLO. The UVLO protection forces all high-side 0.4
MOSFETs and low-side MOSFETs off by shutting down 0.0
internal PWM logic drivers. A 3μs delay is used in UVLO 0 25 50 75 100 125

detection circuit to prevent false trigger. Ambient Temperature (°C)

Figure 22. Derating Curve of Maximum Power
Thermal Considerations Dissipation
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA

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38
 RT8899A
Outline Dimension

2 1 2 1

DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min. Max. Min. Max.
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 5.950 6.050 0.234 0.238
D2 4.650 4.750 0.183 0.187
E 5.950 6.050 0.234 0.238
E2 4.650 4.750 0.183 0.187
e 0.400 0.016
L 0.350 0.450 0.014 0.018
L1 0.300 0.400 0.012 0.016

W-Type 52L QFN 6x6 Package

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RT8899A

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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