+

Lec03 - Processor
Structure and Function
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Contents

Processor organization

Register organization

Instruction cycle

Instruction pipelining

The x86 processor family

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Processor Organization
Processor Requirements:
Fetch instruction
The processor reads an instruction from memory (register, cache, main memory)

Interpret instruction
The instruction is decoded to determine what action is required

Fetch data
The execution of an instruction may require reading data from memory or an I/O
module

Process data
The execution of an instruction may require performing some arithmetic or logical
operation on data

Write data
The results of an execution may require writing data to memory or an I/O module

In order to do these things the processor needs to store some data

temporarily and therefore needs a small internal memory
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CPU With the System Bus
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CPU With the System Bus

Major components of the processor are

Arithmetic and logic unit (ALU)
does the actual computation or processing of data
Control unit (CU)
controls the movement of data and instructions into and
out of the processor and controls the operation of the
ALU
Registers
a set of storage locations
CPU Internal Structure 6
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CPU Internal Structure

Internal processor bus

Used to transfer data between various registers and ALU –
because the ALU in fact operates only on data in the
internal processor memory

Note the similarity between the internal structure

of the computer as a whole and the internal
structure of the processor.
In both cases, there is a small collection of major
elements (computer: processor, I/O, memory;
processor: control unit, ALU, registers) connected
by data paths.
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Register Organization
Within the processor there is a set of registers
that function as a level of memory above main
memory and cache in the hierarchy

The registers in the processor perform two

roles:
Control and Status
User-Visible Registers
Registers
Enable the machine or Used by the control unit to
assembly language control the operation of the
programmer to minimize processor and by
main memory references privileged operating
by optimizing use of system programs to control
registers the execution of programs
 9
User-Visible Registers

Categories:

• General purpose
• Can be assigned to a variety of functions by
Referenced by means of the programmer
the machine language • Data
that the processor
executes • May be used only to hold data and cannot be
employed in the calculation of an operand
address
• Address
• May be somewhat general purpose or may be
devoted to a particular addressing mode
• Examples: segment pointers, index registers,
stack pointer
• Condition codes
• Also referred to as flags
• Bits set by the processor hardware as the
result of operations
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Table 14.1
Condition Codes
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Control and Status Registers

Four registers are essential to instruction execution:

Program counter (PC)

Contains the address of an instruction to be fetched

Instruction register (IR)

Contains the instruction most recently fetched

Memory address register (MAR)

Contains the address of a location in memory

Memory buffer register (MBR)

Contains a word of data to be written to memory or the
word most recently read
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Program Status Word (PSW)

Register or set of registers that contain status information

Common fields or flags include:

Sign: Contains the sign bit of the result of the last arithmetic
operation.
Zero: Set when the result is 0.
Carry: Set if an operation resulted in a carry (addition) into or
borrow (sub- traction) out of a high-order bit.
Equal: Set if a logical compare result is equality.
Overflow: Used to indicate arithmetic overflow.
Interrupt Enable/Disable: Used to enable or disable interrupts.
Supervisor: Indicates whether the processor is executing in
supervisor or user mode. Certain privileged instructions can be
executed only in supervisor mode, and certain areas of memory
can be accessed only in supervisor mode.
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Example
Microprocessor
Register
Organizations
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Example Microprocessor Register

Organizations
MC68000
32-bit registers - 8 data registers and 9 address registers
Data registers are used primarily for data manipulation and addressing
as index registers
32-bit program counter and a 16-bit status register

Intel 8086
16-bit
Every register is special purpose
4 data, 4 pointer and index, and 4 segment registers

Intel 80386
32-bit - extension of the 8086

There is NO universally accepted philosophy concerning the best

way to organize processor registers
 15

Includes the
following
Instruction
stages:
Cycle

Fetch Execute Interrupt

If interrupts are
enabled and an
Read the next
Interpret the opcode interrupt has
instruction from
and perform the occurred, save the
memory into the
indicated operation current process state
processor
and service the
interrupt
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Instruction Cycle
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Indirect stage

The execution of an instruction may involve one or

more operands in memory, each of which requires
a memory access.

After an instruction is fetched, it is examined to

determine if any indirect addressing is involved.

If so, the required operands are fetched using

indirect addressing.
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Instruction Cycle State Diagram

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Data Flow, Fetch Cycle

1
2 3 4
5
6

5 5
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Data Flow, Fetch Cycle (2)

In general, steps during fetch cycle are :

1. PC contains address of next instruction
2. Address moved to MAR
3. Address placed on address bus and memory
location is identified
4. Control unit sends memory read control signal
5. Result placed on data bus, copied to MBR, then to
IR
6. Meanwhile PC incremented by 1, preparing for
the next fetch.
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Data Flow, Indirect Cycle

1
2
3

1 3
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Data Flow, Indirect Cycle (2)

After the fetch cycle, IR is examined

If indirect addressing, indirect cycle is
performed as follows:
1. Right most N bits of MBR transferred to MAR, placed on
the address bus and memory location is identified
2. Control unit sends memory read control signal
3. Result (address of operand) moved to MBR

FETCH & INDIRECT Cycles are predictable.

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Data Flow, Interrupt Cycle

2 2

1 3
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Data Flow, Interrupt Cycle

Simple and predictable

Current PC saved to allow resumption after
interrupt
To process interrupt:
1. Contents of PC copied to MBR
2. Special memory location (e.g. stack pointer) loaded to
MAR, places the stack address on the address bus, and
stack location is identified.
3. MBR written to memory
4. PC loaded with address of interrupt handling routine
Now, next instruction (first of interrupt handler routine)
can be fetched
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Pipelining Strategy
To apply this
concept to
instruction
Similar to the use of execution we must
an assembly line in recognize that an
a manufacturing instruction has a
plant number of stages

New inputs are

accepted at one
end before
previously accepted
inputs appear as
outputs at the other
end
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Two-Stage Instruction Pipeline
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Additional Stages – increase

speedup
Fetch operands (FO)
Fetch instruction (FI) Fetch each operand from
Read the next expected memory
instruction into a buffer
Operands in registers
Decode instruction (DI) need not be fetched
Determine the opcode and
the operand specifiers
Execute instruction (EI)
Perform the indicated
Calculate operands (CO) operation and store the
Calculate the effective result, if any, in the
address of each source specified destination
operand operand location
This may involve
displacement, register Write operand (WO)
indirect, indirect, or other
forms of address Store the result in
calculation memory
Timing Diagram for Instruction 28

Pipeline Operation
The Effect of a Conditional Branch 29

on Instruction Pipeline Operation

Assume that
instruction 3 is a
conditional
branch to
instruction 15
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Six Stage
Instruction Pipeline
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Alternative Pipeline
Depiction
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Calculating Performance

Cycle time (ττ) of an instruction pipeline

τ = max [ττi] + d = τm + d 1<=i <=k

τm = delay through stage which experiences the

largest delay

k = number of stages in the instruction pipeline

d = time delay of a latch, needed to advance

signals and data from one stage to the next
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Calculating Performance (2)

Total time units for the instruction pipeline is:

Tk ,n = [k + (n − 1)]τ
k = stages of the pipeline
n = number of instructions
τ = cycle time
The speedup factor for the instruction pipeline
compared to execution without the pipeline is
defined as:
T1, n nk τ nk
Sk = = =
Tk , n [k + (n − 1)]τ k + (n − 1)
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Calculating Performance - Example

Given number of stages (k) = 6, number of

instructions (n) = 9, τ = 1 sec.

The total time units required for the pipeline is:

Tk ,n = [6 + (9 − 1)]1 = 14 sec
The speedup factor for the instruction pipeline
compared to execution without the pipeline is
defined as:

Sk =
T1, n
=
(9 )(6 )(1)
=
54
= 3 .86
Tk , n [6 + (9 − 1)]1 14
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Speedup Factors
with Instruction
Pipelining

• The larger the

number of pipeline
stages, the greater
the potential for
speedup
• However, in practical,
increases in cost and
delays between
stages
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Pipeline Hazards
Occur when the
pipeline, or some
portion of the There are three
pipeline, must stall types of hazards:
because conditions • Resource
do not permit • Data
continued execution • Control

Also referred to as a
pipeline bubble
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Resource Hazards

A resource hazard occurs

when two or more
instructions that are
already in the pipeline
need the same resource

The result is that the

instructions must be
executed in serial rather
than parallel for a portion
of the pipeline

A resource hazard is
sometimes referred to as
a structural hazard
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Data

Data Hazards Hazard

• A data hazard occurs when there is a conflict in
the access of an operand location
+ • Two instructions in a program are to be executed
in sequence and both access a particular
memory or register operand.
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Types of Data Hazard

Read after write (RAW), or true dependency
An instruction modifies a register or memory location
Succeeding instruction reads data in memory or register location
Hazard occurs if the read takes place before write operation is
complete

Write after read (WAR), or antidependency

An instruction reads a register or memory location
Succeeding instruction writes to the location
Hazard occurs if the write operation completes before the read
operation takes place

Write after write (WAW), or output dependency

Two instructions both write to the same location
Hazard occurs if the write operations take place in the reverse
order of the intended sequence
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Control Hazard
Also known as a branch hazard

Occurs when the pipeline makes the wrong

decision on a branch prediction

Brings instructions into the pipeline that must

subsequently be discarded

Dealing with Branches:

Multiple streams
Prefetch branch target
Loop buffer
Branch prediction
Delayed branch
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Multiple Streams
A simple pipeline suffers a penalty for
a branch instruction because it must
choose one of two instructions to fetch
next and may make the wrong choice

A brute-force approach is to replicate

the initial portions of the pipeline and
allow the pipeline to fetch both
instructions, making use of two streams

Drawbacks:
• With multiple pipelines there are contention delays
for access to the registers and to memory
• Additional branch instructions may enter the
pipeline before the original branch decision is
resolved
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Prefetch Branch Target

When a conditional branch is
recognized, the target of the branch is
prefetched, in addition to the
instruction following the branch

Target is then saved until the branch

instruction is executed

If the branch is taken, the target has

+ already been prefetched

IBM 360/91 uses this approach

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Loop Buffer
Small, very-high speed memory maintained by the
instruction fetch stage of the pipeline and containing the n
most recently fetched instructions, in sequence

Benefits:
Instructions fetched in sequence will be available without the
usual memory access time
If a branch occurs to a target just a few locations ahead of the
address of the branch instruction, the target will already be in the
buffer
This strategy is particularly well suited to dealing with loops

Similar in principle to a cache dedicated to instructions

Differences:
The loop buffer only retains instructions in sequence
Is much smaller in size and hence lower in cost
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Branch Prediction

Various techniques can be used to predict whether

a branch will be taken:
These approaches are static
1. Predict never taken
They do not depend on the
2. Predict always taken execution history up to the time
3. Predict by opcode of the conditional branch
instruction

1. Taken/not taken switch These approaches are dynamic

2. Branch history table They depend on the execution history
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Branch Prediction (2)

Predict never taken (Static)
Assume that jump will not happen
Always fetch instructions in sequence

Predict always taken (Static)

Assume that jump will happen
Always fetch target instruction
Analysis of program behavior-more than 50% of the time,
conditional branch is taken

Predict by Opcode (Static)

Decide by opcode of the branch instruction
CPU assumes that the branch will be taken from certain
branch opcodes, not others
Reported to have 75% success rates
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Taken/not taken switch

Based on previous history.
Using 1 or more bits associated with each conditional branch
instruction to reflect the recent history
These bits are called as taken/not taken switch
Helps CPU to make a particular decision for the next time the instruction
is encountered
Kept in temporary high-speed storage
Associate the history bits with any conditional branch instruction in a
cache (or)
Maintain a small table for recently executed branch instructions with one
or more history bits in each entry.
Using 1 bit - record whether the last execution of this
instruction resulted in a branch or not – prediction error may
occur twice for each use of the loop, once on entering the
loop and one on exiting
Using 2 bits- record the last 2 instances of the execution of
the associated instruction (or) record state in other ways.
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Taken/not taken
switch
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Branch Prediction State Diagram
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Branch History Table

A small cache memory

Associated with instruction fetch stage of the

pipeline

Each entry in table contains 3 elements:

The address of a branch instruction
Some number of history bits recording the use-state of the
instruction
Information about target instruction
Either target address or target instruction
Storage of target address results in a smaller table but
greater instruction fetch time compared with storing
target instruction
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Branch History Table (2)

(a) Predict never taken strategy
Instruction fetch stage always fetches the next
sequential address
If branch is taken, flush the pipeline and fetch the next
instruction from the target address

(b) Branch History table strategy

Each prefetch triggers a lookup in the branch history
table
If no match is found, next sequential address is used for
the fetch
If a match is found, prediction is made based on the state
of the instruction
Next sequential address or branch target address is
fed to the select logic
When the branch instruction is executed, the execute
stage sends the result to branch history table logic.
State of the instruction is updated
If prediction is incorrect, select logic is redirected to
correct address for next fetch
If the conditional branch instruction is not in table, it is
added to the table replacing one of the entry.
+ Intel 80486 Pipelining 51

Fetch
Objective is to fill the prefetch buffers with new data as soon as the old
data have been consumed by the instruction decoder
Operates independently of the other stages to keep the prefetch buffers
full

Decode stage 1
All opcode and addressing-mode information is decoded in the D1 stage
3 bytes of instruction are passed to the D1 stage from the prefetch buffers
D1 decoder can then direct the D2 stage to capture the rest of the
instruction

Decode stage 2
Expands each opcode into control signals for the ALU
Also controls the computation of the more complex addressing modes

Execute
Stage includes ALU operations, cache access, and register update

Write back
Updates registers and status flags modified during the preceding execute
stage
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80486
Instruction
Pipeline
Examples
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Interrupt Processing
Interrupts and Exceptions
Interrupts
Generated by a signal from hardware and it may occur at random
times during the execution of a program
Maskable
Nonmaskable

Exceptions
Generated from software and is provoked by the execution of an
instruction
Processor detected
Programmed

Interrupt vector table

Every type of interrupt is assigned a number
Number is used to index into the interrupt vector table
 Table 14.3
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x86 Exception and Interrupt Vector Table

Unshaded: exceptions Shaded: interrupts

+ Summary
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Processor Structure
and Function
Lec03
Instruction pipelining
Processor organization
Pipelining strategy
Register organization Pipeline performance
User-visible registers Pipeline hazards
Control and status registers Dealing with branches
Intel 80486 pipelining
Instruction cycle
The indirect cycle
Data flow

The x86 processor family

Register organization
Interrupt processing