IEEE SENSORS JOURNAL, VOL. 8, NO.

4, APRIL 2008 325

Charge-Based Capacitive Sensor Array for

CMOS-Based Laboratory-on-Chip Applications
Ebrahim Ghafar-Zadeh and Mohamad Sawan, Fellow, IEEE

Abstract—In this paper, we present a capacitive sensor array in microchannel or other error sources. On the other hand, a ca-
for highly integrated lab-on-chip (LoC) applications using the pacitive sensor for LoC applications can be performed through
charge-based capacitance measurement method (CBCM). The very low-speed architecture so that, an average-based technique
core-CBCM sensor chip is designed and implemented in 0.18
micron CMOS process featuring an array of capacitive sensors; such as CBCM can effectively be employed with much more sim-
an offset cancellation module and a low complexity analog-to-dig- plicity [6]. This simplicity is an important issue for the design and
ital converter (ADC). This sensor chip is incorporated with a implementation of a large capacitive sensor array [7], which is
microfluidic channel using direct-write fabrication process. We not the case of a microelectromechanical systems (MEMS) ap-
demonstrate the testing results using chemical solvents with
known dielectric constants in order to show the viability of the plication with only one single sensing capacitor.
proposed sensor chip for LoCs. CBCM is a simple and efficient method which was origi-
Index Terms—Capacitive sensor, CMOS technology, direct-write
nally proposed in 1996 for subfemto Farad interconnects capac-
microfluidic packaging, lab-on-chip (LoC), sigma delta ADC. itance measurements in deep CMOS chip. Up to date, several
researchers have made further efforts to improve the precision
of CBCM or to introduce new applications of this promising
I. INTRODUCTION method. In this paper, we address the challenging issue of hybrid
MOS CAPACITIVE sensors have recently received sig- microfluidic/CMOS system by proposing a core-CBCM capac-
C nificant interest for a range of biochemical testing LoCs
such as antibody–antigen recognition, DNA detection, and cell
itive sensor chip. This sensor features an array of three sensing
electrodes realized on the topmost metal layer of the CMOS
monitoring [1]–[3]. To date, several successful readout tech- process, three capacitance to voltage converters (CVCs) corre-
niques with different levels of complexity have been reported sponding to the sensing electrodes, a low complexity ADC,
for autonomous microelectromechanical-based capacitive and an OC module implemented in 0.18 m CMOS process and
sensor (MBCS) systems (e.g., accelerometer [4]), but there is integrated with microfluidic channel. In fact, a CMOS-based
little published research on the custom design of an on-chip LoC sensor would require efficient microfluidic packaging to
capacitive sensor for LoC applications. protect circuitry from biological and chemical analytes. This
In fact, a different design strategy should be taken into account often-neglected issue in CMOS-based LoC applications is also
for aforementioned LoC capacitive sensors in comparing with critical to direct the fluids towards the sensors for analysis. We
MBCS applications. For example, for continuous and long time have already proposed a direct-write microfluidic fabrication
sensing in a MBCS, a build-in self calibration module [5] is incor- procedure (DWFP) [8] suitable for highly integrated CMOS-
porated to correct the accumulating errors, whereas LoC capaci- based LoCs. This technique is employed to fabricate the mi-
tive sensors do not suffer from such a problem. Actually, in these crofluidic channel on the sensor chip in this paper.
applications, the sensing capacitances in the presence rather than The organic solvents with known dielectric constants are a
in the absence of analyte are extracted through a differential pro- good alternative to modulate the sensing capacitor based on
cedure. Alternatively, a MBCS by using an appropriate encap- dielectric change in proximity of sensing sites. We characterize
sulation process can easily be isolated from the ambient condi- the proposed hybrid sensor and show its viability for LoC
tions and direct contact with external environment (e.g., air, dust, applications through such low conductivity chemical solvents
and fluids) in spite of LoC capacitive sensors which are always including dichloromethane, acetone, and methanol with the
exposed to liquid analytes in microfluidc channel. For this, an dielectric constants equal to 10.2, 20.7, and 32.2@28 C, re-
offset cancellation (OC) procedure should be performed prior spectively. It is worth it to mention that an application-specific
to each capacitance measurement to cancel accordingly the er- biofunctionalized sensing layer (e.g., DNA immobilization
rors resulting from the presence of remnants parts (e.g., analyte) [2]) is sometimes formed on the sensing sites for selectively
detection purposes and it is not the case of this paper.
We believe the design of a generic capacitive sensor system
Manuscript received November 13, 2007; revised December 17, 2007; ac-
cepted December 17, 2007. This work was supported in part by the Canadian should be highlighted for new LoCs similar to MEMS systems
Research Chair on Smart Medical Devices, NSERC, and CMC Microsystems. [9]. Of course, this new multidisciplinary approach is in its early
The associate editor coordinating the review of this paper and approving it for stage of understanding, and it needs huge efforts to transient
publication was Prof. Evgeny Katz.
The authors are with Polystim Neurotechnologies Laboratory, Department from this level of research to the optimum design and imple-
of Electrical Engineering, Polytechnique de Montreal, QC H3C 3A7, Canada mentation of fully automated sensor system.
(e-mail: [email protected]; [email protected]). The reminder of this paper is organized as follows. In
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. Section II, the related works are described and in Section III,
Digital Object Identifier 10.1109/JSEN.2008.917485 the analysis and design of proposed core-CBCM capacitive

1530-437X/$25.00 © 2008 IEEE

326 IEEE SENSORS JOURNAL, VOL. 8, NO. 4, APRIL 2008

Fig. 2. SEM image of implemented sensing electrode on CMOS chip (scale

bare 5 micron).

Fig. 1. Core-CBCM sensor. (a) CBCM structure. (b) On-chip CVC unit.
differential amplifier into the nonlinear region that therefore
derogates the resolution of capacitive sensor.A simple solution
sensor array is discussed. The simulation and experimental to avoid both the above mentioned problems is to subtract the
results are demonstrated in Section IV followed by a conclusion charging currents resulting from sensing and reference capaci-
in Section V. tances prior to injection in . We put forward on this topology
[Fig. 1(b)] by proposing a differential current method and fur-
II. RELATED WORKS ther digital readout circuitry as seen in the next section.
As shown in Fig. 1(a), CBCM is a simple method to extract
III. PROPOSED CORE-CBCM CAPACITIVE SENSOR SYSTEM
the capacitance ( ) standing on node “A” through a linear re-
lationship where , and are the power This section describes the principle of proposed array of ca-
supply voltage, frequency, and DC charging currents, respec- pacitive sensors and dedicated ADC, after a brief introduc-
tively. Moreover, CBCM continues to command the attention tion on implemented sensing electrode.
of researcher for on-chip characterization applications [10], [11]
A. Sensing Electrode
and considerable efforts have recently been placed on the design
and implementation of core-CBCM capacitive sensors. An interdigitated capacitor is realized on the topmost metal
Among the works using CBCM for capacitive sensors, layer and the passivation layer in between the fingers is re-
Guiducci et al. proposed a DNA detection technique using two moved using a pad-etch technique in standard CMOS process.
electrodes instead of traditional three-electrode method [12]. A SEM image of this capacitor is shown in Fig. 2, where the
Based on this report, the DNA hybridization was capacitively metal layer 5 is employed to connect the fingers of the same
measured through an off-chip circuitry consisting of a CBCM electrode of interdigitated capacitor. The presence of a noncon-
structure along with an opamp in order to convert the charging ductive analyte above and in between the fingers of electrodes
current into the output voltage. As a follow up of this work, they can be detected through the interface circuit. For this, an elec-
successfully realized the same methodology of DNA sensing on trode is grounded and another one is connected to the drain sides
CMOS chip. In this work, CBCM structure was implemented of n/pMOS pair ( and ) in Fig. 1(b). As already men-
on chip and the gold electrodes are realized through a sputtering tioned in Section I, a specific sensing layer is often formed on
procedure, however, the readout circuitry is still realized by the sensing electrode to trap the corresponding molecules/cells.
using discreet devices [13]. Obviously, in order to employ the capacitive sensors for bio-
In another effort, Evans et al. reported an interesting fully chemical applications, it is required to remove the nonbonded
on-chip circuitry using CBCM for particle detection [14]. As charged molecules/cells through an appropriate rinsing process
seen in Fig. 1(b), a current mirror and an integrating [2] or temperature treatment [1]. As the very low conductivity
capacitor are used to convert the charging current to output organic solvents are employed to modulate the capacitance of
voltage (CVC unit). In fact, this circuit is employed to mon- sensing electrodes and show the functionality of the proposed
itor the sensing capacitance instead of the off-chip measure- interface circuit, the sensing and reference electrodes
ment device shown in Fig. 1(a). The proposed interface circuit are modeled with and , respectively, where and
in Fig. 1(b) along with a voltage buffer was employed as one are the variable and fixed values of integrated capacitors.
of two similar units to convert the sensing and reference capac-
itances into the voltages. These voltages are thereafter applied B. Improved CVC
into a simple differential voltage amplifier in order to monitor Let us first make an analysis on the circuit shown in Fig. 1(b)
the capacitance variation accordingly. and thereafter apply our proposed improvements. As seen in
As the sensing capacitance is lower than , a low dy- this figure, a simple current mirror ( - ) is employed to
namic range output voltage is expected for each CVC unit. Fur- sense and amplify the CBCM charging current with a cur-
thermore, another problem is arisen from the voltage differen- rent gain equal to . Once is low and the voltage on
tial amplifier. The higher the sensitivity and, consequently, the starts rising rapidly, the following relation
higher output voltage of each CVC unit, pushes the voltage is established in between the charging
GHAFAR-ZADEH AND SAWAN: CHARGE-BASED CAPACITIVE SENSOR ARRAY FOR CMOS-BASED LABORATORY-ON-CHIP APPLICATIONS 327

current of , drain current of , and charging current of

. In this relation, depends on the parameters of process.
Also, and are the gate source voltage and the threshold
voltage of channel MOSFET, respectively. Also, the switch-on
and off resistances of and have been discounted. By sub-
stituting instead of in this equation and also by
assuming at (discharging) when and are
high, can be expressed by

(1)

Therefore, can easily be obtained based on the

combination of above mentioned relations

(2)

This time-variant current signal can be considered as the

equivalent model of the circuit shown in Fig. 1(b) with a
capacitive load . By combining (1), (2), and the relation
can be ideally obtained in (3) for

(3)

where and are aspect ratios of and ,

respectively. As , it is obvious, the dynamic
range of [see (1)] remains limited due to . As
shown in Fig. 3(a), our solution is to generate a reference current
by employing a replica of CVC unit with instead of .
The differential current is injected into . Thanks to
its symmetry and differential operation, is expressed by (4) Fig. 3. Adjustable reference current (a) proposed circuit topology using (b) a
switching method.
(4)

where is the residual offset voltage mainly resulting from In fact, instantaneously charges resulting in a DC voltage
the mismatch error of current mirrors and CBCM structures, as change on . After a few iterations corresponding to
well as the mechanical arifacts and remnants in microchannel. can be larger than so that is closed and falls down
For this, by applying an adjustable reference current and a to another level lower than [see Fig. 4(b)]. The sample-based
simple OC procedure, can effectively be diminished. As relation of this modulator is ( ,
shown in Fig. 3(b), where , corresponding to each digital and are the th sample of output, input and integrator) for
input D1-Dm (D - ) the reference current is generated through each period/sample of its operation which is comparable with
with the aspect ratios the ideal relation of DC input first-order modulators,
[15]. The digital input [16].
data (-D) in this design is generated in an off-chip The different indexes of the above relationships only results
programmable platform. It should be mentioned; any residual in a difference between four primary bits of output sequences,
offset even after applying the OC procedure is automatically so that the circuit shown in Fig. 4(a) can still be considered a
eliminated in the subtractions of two subsequent measurements new realization of the first-order DC input ADC. By consid-
prior and after analyte injection. Therefore, it has no significant ering and node as the input signal, low-pass
effect on the accuracy of capacitive detection. filter and the summation device of a first-order modulator,
respectively [see Fig. 4(b) and (c)], the current mirror (Q1, Q2),
C. Readout Circuit and are together constituted a 1-bit DAC for this first-
The proposed readout circuit is realized by incorporating order ADC [see Fig. 4(c)]. As the output sequence of the
a voltage comparator to the circuit shown in Fig. 3(a). As seen in first-order DC input ADCs are periodic and the period ( )
Fig. 4(a), the integrated voltage on is compared with a refer- of sequence is dependent on the input value, the Fourier series
ence voltage and, consequently, the output pulse of comparator of such periodic sequences for each input constant value is
is applied on the switch in series with . is gener- limited to a number of harmonics, and it is not really similar to
ated by adding a transistor to circuit shown Fig. 3(b). noise-shaped spectra oversampling s. For this, in Section IV,
328 IEEE SENSORS JOURNAL, VOL. 8, NO. 4, APRIL 2008

Fig. 6. Implemented voltage comparator which is incorporated with 61

modulator.

Fig. 4.61 capacitive sensor: (a) new realization method; (b) waveforms of
clock pulses and integrated V ; and (c) simplified diagram of DC input first-
order 61 ADC.

Fig. 7. Fabrication results: (a) optical microscope images of the top view of die
and (b) microfluidic packaging of sensor chip.

Fig. 8. Measurement setup including oscilloscope, microscope, syringe pump,

power supply, FPGA platform, and CMOS sensor.
Fig. 5. Fully implemented capacitive sensor system.
where and [17]. It is obvious that the
noise contribution and the consequent accuracy of the decoded
the functionality of this ADC is revealed by a linear rela- output are dependent on the length of bit-stream , allowed
tion between the decoded value of the output bit stream and the for the conversion that is not necessarily equal to actual period
input capacitance variation. of sequence. We have programmed an FPGA platform to de-
By applying a summation operation on both sides of code the bit stream based on the above simple method to
, we can obtain demonstrate the testing results.
GHAFAR-ZADEH AND SAWAN: CHARGE-BASED CAPACITIVE SENSOR ARRAY FOR CMOS-BASED LABORATORY-ON-CHIP APPLICATIONS 329

Fig. 9. Simulation results of current-based CVC unit: (a) V versus time for different values of 1C and (b) variation of V versus 1C .

D. Realization of Sensor System platform), a stereo microscope is employed to observe the

liquid injected into the channel through a syringe pump.
As shown in Fig. 5, the embedded sensor system in the
CMOS chip features three interdigitated electrodes which are
used as the sensing capacitors , three CVCs, an IV. RESULTS AND DISCUSSIONS
adjustable current mirror (ACM), and a voltage comparator.
Both OC module and 1-bit DAC for the ADC are integrated A. Simulations
in the ACM module [see Fig. 3(b) and (c)]. The post-layout simulation of (SpectreS) versus time for
A voltage comparator followed by a RS flip flop is shown in five different values of input capacitance variation is demon-
Fig. 6 [18]. This track and latch comparator consists of a differ- strated in Fig. 9(a). In this simulation, is connected to
ential amplifier (M15-16) sensing the input differential voltage. in order to bypass the comparator and show the linearity of im-
The logic states of M19-20 results from the generated drain cur- proved CVC for input capacitance variation. In another simula-
rent on M15-16, where is high and is low. Once tion result in Fig. 9(b), the variation of output voltage is shown
becomes high, the regenerative process starts on M19-20 re- versus the input capacitance, which reveals a significant im-
sulting from initializing M17-18 logic states. RS flip–flop op- provement comparing with [14].
erates as a latch to save the logic states of M19-M20 during Let us remove from and allow the sensor system
one clock pulse period. In this design shown in Fig. 4, the dig- return to its normal operation as a modulator [see also
ital addressing lines and (Š), control logic signals in- Fig. 4(b)]. As anticipated, the simulations in Fig. 10 show
cluding reset and clock signals are derived from the different pulse streams for different values of . In order to
programmed FPGA platform. Also, the OC procedure is real- validate that there is a unique bit-stream for each input , the
ized in this platform to find the optimum value of digital input average of each sequence (the number of one’s per the number
data -D prior to analyte injection. For this, the output bit stream of pulses in each sequence) is obtained and shown in Fig. 11.
of ADC is decoded (Ǔ) simply trough the digital counter and This figure reveals a linear relation between the output and
divider units, as described in Section III-B and used as decision input of decoding module especially for .
criterion in the OC algorithm. In each period of clock , if It should be mentioned that for the above simulations, the
is larger than a threshold voltage , -D is incremented until it value of each sensing electrode has already been extracted
reaches the desired value. Based on the considered aspect ratios through the post-layout procedure in SpectreS Cadence. This
of , initially, is less than , so the OC proce- value is approximately around 70fF for the sensing electrodes
dure always starts with a value of (Ǔ) larger than . As seen Of course, in this model provided by the standard software, the
in Fig. 6, -D, Š and clocks are supplied by off-chip effects of pad-etch patterning has not been involved that results
module implemented in FPGA. The digital signal (Ŭ) is finally a difference between simulation and experimental results.
acquired and stored in the PC.
B. Measurement Results and Discussions
E. Chip Fabrication and Measurement Setup
The proposed sensor chip is tested in two different modes.
The sensor chip was fabricated by the Taiwan Semiconductor In the first mode, the reset switch has been connected to
Manufacturing Company (TSMC) 0.18 micron CMOS process , and in the second mode, the ADC is allowed to operate
and incorporated by microfluidic channel using direct-write normally by connecting to another signal pulses with
fabrication process [8]. Fig. 7(a) and (b) show the optical .
microscopic of die and microfluidc packaged sensor chip re- As seen in Fig. 12(a) and (b), rises up in charging and
spectively. Also, as seen in Fig. 8, in addition to the electrical falls down during discharging periods for two different ana-
equipments (power supply, oscilloscope, and Xilinx FPGA lytes—dichloromethane and acetone in the microchannel. Of
330 IEEE SENSORS JOURNAL, VOL. 8, NO. 4, APRIL 2008

Fig. 10. Simulation results of the proposed 61: output bit stream for different capacitance variations (where C = C + 70fF and C = 1C + C ).
TABLE I
OC PROCEDURE RESULTS ON DIFFERENT DIES (V = 535 mV)

Fig. 11. Sensitivity of decoded output sequence versus input 1C (where

C =C and C =1 + C C. TABLE II
DECODED OUTPUT OF 61ADC FOR INJECTED
DICHLOROMETHANE IN CHANNEL

course, before the measurements, the OC procedure was per-

formed while the channel was empty. As seen in Table I, the
number of iteration and the residual voltage are different for
different dies which could be due to mismatch error in process
and/or nonuniformity of pad-etching.
In the second mode, once again, dichloromethane is used to
test the proposed system. Table II shows the decoded bit stream
in different times.
A cleaning procedure including the hot water washing and
air blowing along with temperature treatment is performed in
between each two measurements. As seen in this table, the num-
bers in the red columns are representative of nonstable logic
states. In other words, the resolution of the capacitive sensor is
not better than 6 bits. Fig. 13(a) shows the measurement results
of sensing capacitors , and for both empty and
Fig. 12. Measurement results of V in the first mode. filled channel with dichloromethane. Of course, these results are
GHAFAR-ZADEH AND SAWAN: CHARGE-BASED CAPACITIVE SENSOR ARRAY FOR CMOS-BASED LABORATORY-ON-CHIP APPLICATIONS 331

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M.Sc. degrees in electrical engineering from KNT
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332 IEEE SENSORS JOURNAL, VOL. 8, NO. 4, APRIL 2008

Mohamad Sawan (F’04) received the B.Sc. degree sembly and validation of advanced wirelessly powered and controlled moni-
in electrical engineering from Université Laval, toring and measurement techniques. These topics are oriented toward biomed-
Quebec City, QC, Canada, in 1984, and the M.Sc. ical implantable devices and telecommunications applications. He is holder of
and Ph.D. degrees, both in electrical engineering, the Canada Research Chair in Smart Medical Devices. He heads the Microsys-
from the Université de Sherbrooke, Sherbrooke, tems Strategic Alliance of Québec – ReSMiQ.
QC, Canada, in 1986 and 1990, respectively. He Dr Sawan is founder of the Eastern Canada Chapter of the IEEE-Solid State
then completed Postdoctoral training at Montréal’s Circuits Society. He also founded the International IEEE-NEWCAS Confer-
McGill University, Montreal, QC, Canada, in 1991. ence, co-founded the International Functional Electrical Stimulation Society,
In 1991, he joined École Polytechnique de Mon- and founded the Polystim Neurotechnologies Laboratory at Ecole Polytech-
tréal, where he is currently a Professor of Microelec- nique, Chair of the IEEE Biomedical CAS (BioCAS) Technical Committee, and
tronics. His scientific interests focus on the design member of the Biotechnology Council representing the IEEE-CAS Society. He
and testing of mixed-signal (analog, digital, and RF) circuits and systems; dig- is the Editor of Springer Mixed-Signal Letters.
ital and analog signal processing; and the modeling, design, integration, as-