IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO.

1, FEBRUARY 2006 67

Crosstalk-Based Capacitance Measurements:

Theory and Applications
Loris Vendrame, Luca Bortesi, Fabrizio Cattane, and Alessandro Bogliolo, Member, IEEE

Abstract—Geometry scaling increases the relative effect of cou- copper and low-k dielectrics has partially solved some of the
pling capacitances on performance, power, and noise so that they problems, postponed some others (gaining, for instance, a tech-
need to be carefully taken into account during process develop- nology generation in performance), and created new ones (like
ment, characterization, and monitoring. In the last decade, charge-
based capacitance measurements (CBCMs) have been widely used the need for dummy patterns to ensure a proper planarization
to estimate on-chip wiring and coupling capacitances because of and to increase critical dimension control [1]).
their accuracy and simplicity. We provide a thorough theoretical On-chip interconnects need to be accurately modeled as ac-
and experimental study of CBCMs applied to the selective extrac- tive devices and their features need to be kept under control as
tion of cross-coupling capacitances. We take a historical perspec- critical process parameters. On-silicon characterization of real-
tive starting from the original CBCM approach proposed by Chen
et al. in 1996, and we present a new technique for crosstalk-based istic test structures is required for this purpose. In this paper, we
capacitance measurements (CTCMs). CTCMs improve the accu- focus on accurate measurements of interconnect coupling ca-
racy and usability of CBCMs while reducing the complexity of the pacitances and on characterization of back-end structures and
test structures. We present the theory of CTCM, we provide ex- devices.
perimental results demonstrating its improved accuracy, and we Test structures for capacitive measurements can be roughly
discuss its application to a wide range of process monitoring and
testing tasks. Experimental results are used throughout the paper classified into three categories.
to support the discussion. 1) Simple configurations (like metal plates and single and
paired wires) are used to extract single parameters (e.g., the
Index Terms—Cross-coupling capacitance, interconnect capaci-
tance, matching, process monitoring, test structure. total capacitance) to characterize simple models for hand
calculations and to monitor intrametal dielectric thickness
and dielectric constant.
I. INTRODUCTION 2) Complex configurations (like buses and memory arrays
with different topologies, sizes, and environmental con-
T ECHNOLOGY scaling does not apply in the same way to
all process steps and circuit components, thus changing the
relative importance of the physical phenomena that determine
ditions) are representative of real layout configurations
possibly generated by place-and-route tools or by manual
the behavior of an integrated circuit. During the last decade, optimization. These test structures are often arranged in
process backend has become one of the major concerns of dedicated test chips [3], [4] and used to test the accuracy
process developers and is perceived as one of the most critical of extraction tools, to measure on-wafer critical back-end
challenges of technology scaling [1], [2]. At the physical level, configurations, and to validate interconnect models in
dense interconnect lines raise manufacturability, reliability, and terms of global and separate contributions (crossing, lat-
yield problems. At the electrical level, interconnects have a eral, shielding, overlap, fringe, etc.) of wire parameters.
large impact on propagation delay and signal integrity. At the 3) Back-end devices (such as capacitors) need to be char-
architectural level, routability limits the actual density of the acterized in order to be used as circuit components. Ex-
functional circuitry well below the physical limit. amples include metal–insulator–metal (MIM) capacitors,
The aspect ratio of an interconnect line (i.e., the ratio between which require an extra mask to allow the deposition of a
its height and width) increases while scaling down the minimum thin oxide between two metal plates, metal–oxide–metal
fringe capacitors, and stacked capacitors.
feature size of the active components. In fact, geometry scaling
is not directly applied to metal thickness in order to limit the im- All of them require careful and accurate capacitive measure-
pact of undesired phenomena like electromigration. As a conse- ments and the evaluation of process variations [5]–[8].
quence, wiring capacitance scales down much slower than tran- In this paper, we provide a thorough theoretical and ex-
perimental study of crosstalk-based capacitance measurement
sistor channel lengths, and capacitive coupling between adja-
cent lines increases its relative importance. The introduction of (CTCM) techniques [9], which are a particular type of
charge-based capacitance measurements (CBCM) [10]. The
remainder of the paper is organized according to a historical
Manuscript received July 29, 2005; revised November 4, 2005.
perspective. In Section II, we present the basic CBCM ap-
L. Vendrame, L. Bortesi, and F. Cattane are with FTM Advanced proach [10], we discuss its strengths and weaknesses, and we
R&D, STMicroelectronics, 20041 Agrate Brianza, Italy (e-mail: loris.ven- present modified versions that make use of improved capaci-
[email protected]). tance-to-current transducers [11]. In Section III, we discuss the
A. Bogliolo is with the Information Science and Technology Institute, Uni-
versity of Urbino, 61029 Urbino, Italy (e-mail: [email protected]). application of CBCM to extract mutual capacitances selectively
Digital Object Identifier 10.1109/TSM.2005.863263 by measuring crosstalk-induced currents [12]. In Section IV, we
0894-6507/$20.00 © 2006 IEEE
68 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO. 1, FEBRUARY 2006

Fig. 1. Differential test structure for extraction of cross-coupling capacitance

Cx by means of CBCM. C and C denote output parasitic capacitances of
transducers, C and C are sums of other wiring capacitances.

introduce CTCM techniques [9], and in Section V we propose

some nonconventional applications. Experimental data are used
throughout the paper to support the analysis and demonstrate
the feasibility of the proposed techniques.

II. CBCM
CBCM makes use of integrated capacitance-to-average cur-
rent transducers [10]. In the last several years, CBCM tech-
niques have gained importance for on-chip interconnect capac- Fig. 2. Mismatch between two unloaded CBCM transducers, expressed by
itance extraction due to their high resolution and simplicity, but standard deviation of Q plotted against reciprocal of square root of transistor
area. (a) Experimental results. (b) Monte Carlo SPICE simulations performed
discussions on their accuracy have not yet come to the end [10], with random variations of MOSFET thresholds and gains.
[13]–[18].
In their original version, CBCM transducers were im-
plemented by means of nMOS and pMOS transistors in a 1) It is difficult to guarantee the same boundary conditions for
pseudoinverter configuration (Fig. 1). The two MOSFETs the two structures. In Fig. 1, the lack of the lower intercon-
that compose each transducer are driven by nonoverlapping nect in the left-most structure affects the electric field con-
signals ( and ) in order to avoid cross-conduction currents figuration so that . Discrepancies can be greater
between and ground. The total capacitance at the than the accuracy of the transducer. A more effective solu-
output of the right-most pseudoinverter in Fig. 1 can be esti- tion is provided by the crosstalk-based approach outlined
mated by measuring the average current through the pMOS (or in Section III.
nMOS), according to 2) The output capacitance of the two pseudoinverters is not
exactly the same . In general, the output capac-
itance is made of various contributions like drain junctions,
(1) MOSFET overlapping capacitances, and interconnects be-
tween pMOS and nMOS drains. We measured the capac-
where is the supply voltage and is the fre- itive mismatch of two identical unloaded pseudoinverters
quency of the nonoverlapping periodic signals. Equation (1) is in the order of fractions of fF for minimum-size pseudoin-
valid if is low enough to allow a complete charge/discharge verters in a 0.18- m technology. In principle, increasing
of the total capacitance at the output of the pseudoinverter at MOSFET size should reduce the effect of the relative mis-
each working cycle. In order to extract a specific contribution match [15], but we did not appreciate this benefit in our ex-
selectively (e.g., the cross-coupling capacitance in Fig. 1), periments or in Monte Carlo simulations (in 0.18- m tech-
two identical capacitance-to-current transducers are used with nology). For this purpose, unloaded standard transducers
output loads differing only for the capacitance of interest [10]. with different MOSFET widths and lengths were realized
Referring to Fig. 1, the left-most transducer drives a total capac- and measured. The relative percentage mismatch, defined
itance , while the right-most transducer drives a as the standard deviation of
total capacitance . Assuming that , is plotted in Fig. 2 versus the inverse of the square
and , the cross-coupling capacitance can be esti- root of the transistor size, as in typical mismatch anal-
mated through a differential measurement as ysis [19]. Neither the experimental plot [Fig. 2(a)] nor the
simulation results [Fig. 2(b)] reveal a clear dependence on
MOSFET size. Notice that the simulated mismatch is much
(2) lower than the measured one, suggesting the relevance of
the additional mismatch sources, such as the ones related
Although in principle each transducer can sense capacitances to metal definition, that affect real silicon implementations.
in the aF range, the accuracy of the differential measurement is To avoid mismatch issues while measuring coupling capac-
actually limited by three main effects. itances, the single pattern drive (SPD) approach was pro-
VENDRAME et al.: CROSSTALK-BASED CAPACITANCE MEASUREMENTS: THEORY AND APPLICATIONS 69

posed by Froment et al. [16], [17]. A single test structure

is adopted at the cost of using independent pseudoinverters
and a complex signal sequence to drive each MOSFET in
the structure under test.
3) Charge injection phenomena in the capacitance under test
induce a systematic transducer error. Even in the ideal case
of zero mismatch, if we perform a SPICE simulation of the
average current in a fully differential CBCM test structure
with a known loading capacitance , by applying (2) we
obtain a measured capacitance different from the ac-
tual value of . This systematic error is due to the addi-
tional charge which is injected into when a MOSFET
transistor is turned off because channel charge must flow
out through the terminals [20]. The amount of charge in- Fig. 3. Schematic of improved CBCM transducer based on pass-gate switches.
jected at each terminal depends on the loading capacitance,
which is different by construction for the two transducers,
giving rise to an error that cannot be compensated by a dif-
ferential measure. Two main solutions have been proposed
to solve this problem: compensating positive and negative
charge injections and using crosstalk currents instead of
charge–discharge currents. The first approach is described
in the remainder of this section, while crosstalk-based mea-
surements will be discussed in Section III.

A. Pass-Gate Implementation

The error caused by unequal charge injections may be min-

imized, adopting a solution widely employed in switched ca- 3 0
Fig. 4. Error percentage C err = 100 (C sim C )=C of conventional and
pacitor circuits [20], i.e., by using pass gates instead of single pass-gate CBCMs with different sizes, plotted as a function of their loading
capacitance C . C sim is capacitance computed from simulation results by means
pMOS and nMOS transistors as pull-up and pull-down circuits of (2).
of the pseudoinverter. If the pass gate is properly sized, capac-
itance-dependent charge injections are minimized by compen-
sating holes and electrons coming from the channels of pMOS we see that the smaller the capacitance the larger the difference
and nMOS switching transistors [20]. between the corresponding curves.
The schematic of the proposed pass-gate CBCM differential Going back to Fig. 2(b), we observe that the MOSFET
circuit is shown in Fig. 3. Two input buffers are used to precon- mismatch is usually below the resolution limit due to residual
dition external signals and . The buffers must be properly charge injection phenomena, both for traditional and for
dimensioned in order to obtain the required slope at the inputs pass-gate implementations, demonstrating the critical impact of
of the pass gates, possibly adding lumped capacitances at their charge injection on measurement accuracy. Since charge injec-
outputs. It is known, in fact, that steep slopes increase charge tion depends on transistor size, while capacitive mismatch does
injection [11], [20]. Two further inverters are used to generate not, minimum-sized transistors have to be used to maximize
complementary control signals. From our simulations, the delay the accuracy.
introduced by the inverters does not impair the charge injec- As a general guideline, to increase the signal-to-noise ratio in
tion compensation. To avoid measurement noise, the wells of the measured current, i.e., to measure higher for a given
the pass gates are tied to the inverter bias pads. in (1), either or should be increased. The upper limit to
Different solutions based on series-connected transistors higher frequencies is more related to the bandwidth of the exper-
were also proposed [21], but pass gates provide a simpler imental bench (generally, a dc experimental bench is used with
solution to charge injection errors. a maximum frequency around 1 MHz) than to the frequency
To quantify the improvement of the pass gate over the conven- required to fully charge and discharge . Thick oxide MOS-
tional CBCM, we performed comparative SPICE simulations in FETs (the ones typically used for IOs) could be used to increase
0.18- m technology with both minimum sized and larger tran- . This approach has many additional benefits: 1) it reduces
sistors. Fig. 4 refers to simulations performed by keeping the the MOSFET leakage current in the OFF condition (which acts
left-most transducer of Figs. 1 and 3 unloaded while varying as an additional spurious contribution to ) and 2) it reduces
from 1 to 50 fF the load of the right-most one. The relative gate-drain overlap capacitance, thus reducing the output capac-
errors of pass-gate CBCM are highly reduced with respect to itance (despite the increased drain-junction capacitance due to
those of conventional CBCM for the same transistor geometry. the larger size of IO transistors) that contributes to the overall
As expected, the charge injection error is load dependent and capacitance to be subtracted to the real measurement.
70 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO. 1, FEBRUARY 2006

Fig. 5. Schematic and timing diagram of voltages and supply current I of crosstalk-based CBCM.

III. CROSSTALK-BASED CBCM Mismatch is not involved since the same structure is used for
Uncertainties due to boundary conditions, mismatch, and both measurements. It is also worth noting that the effect of
charge injection can be minimized by exploiting crosstalk-in- is not masked by the overall capacitance , even if . In
duced currents (instead of charge–discharge currents) to fact, ground coupling reduces the effect of crosstalk in terms of
measure intrawire coupling capacitance with a single pseudoin- voltage, but it does not mask its effect in terms of charge. How-
verter. ever, if , the difference in (4) is affected by the error
Fig. 5 shows a schematic representation of the crosstalk- propagation typical of the computation of small differences be-
based CBCM approach proposed by Bogliolo et al. in 2002 tween large quantities. In practice, the accuracy of provided
[12]. The unknown coupling capacitance is regarded as a by (4) is limited by the accuracy of the average current measure-
crosstalk capacitance between an aggressor and a victim. Two ments.
aggressors, aggr and aggr , are shown in Fig. 5. They can be We remark that (3) and (4) hold if and only if the input wave-
used for cross validation and accuracy assessment as explained forms satisfy the following conditions: 1) aggr, , and
at the end of this section. Here, let us assume that there is have the same period; 2) at each cycle when the tran-
only one aggressor, with coupling capacitance and sition of aggr occurs, the pull-down transistor is completely
represents all other contributions to the load of the transducer, switched off and the pull-up transistor is either switching on or
including its output capacitance. While the victim is driven by already switched on; and 3) the return transition of aggr oc-
the pseudoinverter that acts as a CBCM transducer (controlled curs when the pull-up transistor is completely switched off and
by signals and ), the aggressor is driven by a variable the pull-down transistor is either switching on or already turned
voltage source aggr that provides either a constant voltage or on. The above timing conditions are represented in the timing
a square waveform (with the same frequency of and ). diagram of Fig. 5 and symbolically expressed by
The timing diagram of Fig. 5 shows the signal waveforms of
, and aggr and the corresponding supply current .
The falling edge of causes a current pulse that charges
the overall capacitance with an amount of charge (5)
. If a falling transition of aggr occurs when In our implementation, preshaping CMOS inverters (dotted
the pull-up of the pseudoinverter is active, an additional cur- line in Fig. 5) were added to drive input signals avoiding pos-
rent pulse is supplied to compensate the effect of crosstalk. The sible voltage overshoots during on-wafer measurements. In par-
corresponding charge is , where is the ticular, the preshaping buffer on the aggressor line reduces the
voltage variation on the aggressor line. On the other hand, a tran- flexibility in the choice of aggr but increases the accuracy by
sition of aggr, occurring when the pull-down of the pseudoin- reducing the uncertainty on , which is now equal to the
verter is active and the pull-up is not, does not cause any addi- supply voltage of the buffer.
tional supply current. Hence, if signals , , and aggr In the actual implementation, two matched aggressors were
are repeatedly applied at frequency , the average measured cur- used to apply simultaneously voltage transitions aggr ,
rent is aggr independently set to be zero or . This
double-aggressor configuration provides many different ways
(3) of measuring the unknown coupling capacitance, giving the
opportunity of cross validation and error compensation.
If two experiments are performed with different values of , We can express the total measured capacitance as
capacitance can be obtained from , where according to the aggressor
configurations indicated in square brackets in Fig. 6. Defining a
new variable , which represents the expected weight
(4) of the contribution of to , we can plot versus and
VENDRAME et al.: CROSSTALK-BASED CAPACITANCE MEASUREMENTS: THEORY AND APPLICATIONS 71

Fig. 6. Plot of total capacitance measured by crosstalk-based CBCM versus

expected number of C x contributions (N ). R = 0:9997 and C x = 5:054 fF.
Aggressor configurations [aggr1; aggr2] are also shown for each experimental
point.
Fig. 8. (a) Basic CTCM configuration used for measuring coupling capaci-
tances C x and (b) timing diagram of input signals.

by Bogliolo et al. [12], but they use slightly different timing

diagrams and provide further results to demonstrate the benefits
of the approach [renamed charge-induced-error-free (CBCM)]
in terms of charge injection compensation.

IV. CROSSTALK-BASED CAPACITANCE MEASUREMENTS

Crosstalk-based capacitance measurements (CTCMs) im-
prove the crosstalk-based CBCM approach described in the
Fig. 7. Metal1 coupling capacitance versus coupling length R = 0:9906. previous section by avoiding charge injection errors and al-
lowing one-step (i.e., direct) measurements of the unknown
capacitance . This makes CTCM more suitable for many
compute a linear regression curve whose slope provides a good on-chip monitoring/testing applications that will be discussed
estimate of . Experimental results are shown in Fig. 6 for a in Section V.
Metal1 line coupled on both sides with 45- m Metal1 lines at a CTCM exploits the same principle of crosstalk-based CBCM
minimum spacing in 0.18- m Al technology. The accuracy of in that it extracts cross-coupling capacitances by measuring
the method is demonstrated by the regression coefficient strictly crosstalk currents, but it keeps the victim line always at the
close to one (namely, ) for a measured coupling same voltage. This solves many nonidealities of CBCM ap-
capacitance fF. proaches and provides new degrees of freedom in the design
The same results could be achieved by solving a system of of test structures for coupling-capacitance measurements [9],
two equations in two unknowns, obtained by applying two dif- [24].
ferent aggression configurations. However, this method is less The basic scheme is shown in Fig. 8(a). The aggressor (line2)
robust than the one that exploits all possible aggression config- is driven by a known periodic signal , while the victim (line1)
urations to compensate measurement errors. is kept at a constant voltage ref provided by an independent
Furthermore, to check the quality of the methodology we per- voltage source. Two switches provide two alternative paths to
formed similar measurements on test structures with different connect line1 to the voltage source. If we denote by the
coupling lengths. The values of the measured versus the difference between the high and the low levels of , whenever
nominal coupling length are shown in Fig. 7, which confirms there is a transition on line2 a charge is moved
the expected linear dependence. on line1 because of the coupling capacitance between line1
Assuming that the two-step measurement procedure achieves and line2.
a perfect compensation of charge injections, the accuracy of If the two switches connecting line1 to ref are switched in
crosstalk-based CBCM is limited only by the precision and sta- such a way that the victim is always connected through switch1
bility of the external instrumentation used to generate the bias (switch2) when the aggressor has a negative (positive) transi-
voltage to measure the average current and to generate the peri- tion, the average current that flows through switch1 (switch2) is
odic input waveforms with stable period . proportional to the coupling capacitance , which can be ob-
Crosstalk-based CBCM was independently reproposed by tained from
other authors as a suitable solution for reducing charge-in-
jection issues [18], [22], [23]. In particular, Chang et al. [18] avg
exploit the same principle and the same test structure introduced (6)
72 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO. 1, FEBRUARY 2006

3 0
Fig. 9. Capacitance error (percentage) Cerr = 100 (C sim Cx)=Cx of
CTCM method, plotted as function of coupling capacitance under test Cx.

Signal waveforms are schematically represented in Fig. 8(b).

Notice that signals and which drive the two switches
do not need, in principle, to be nonoverlapping, since the two
switches are connected to the same voltage source so that no
short-circuit currents are expected. Nevertheless, the use of
Fig. 10. Repeatability of CTCM.
nonoverlapping signals reduces the effects of switching noise
and mismatch, thus enhancing the accuracy of the measure-
ment.
The two amperemeters in Fig. 8(a) were used in our experi- First, the two switches work at exactly the same operating
mental setup for cross validation, but only one amperemeter is conditions so that, as long as they are implemented using
strictly required to measure the average current that appears in matched transistors, they properly compensate each other’s
(6). nonidealities, including channel charge injection. Second, input
In principle, CTCM avoids charge-injection noise by con- waveform synchronization is less critical, since short circuit
struction. In fact, if the MOSFETs used as switches are currents are avoided by construction. Third, cross-coupling
matched transistors of the same type (e.g., pMOS or pass contributions can be directly measured in one step. Although
gate), the channel charge injections compensate each other. If two-step differential measurements are attractive because of
the charge-injection error is not exactly compensated, it can their inherent capability for compensating systematic errors,
be precharacterized (by means of a calibration procedure) to one-step measurements are much more practical and make
correct the measure of the coupling capacitance as discussed it possible to fully exploit the resolution of the measurement
later on in this section. equipments by measuring only the quantities of interest. Fourth,
Furthermore, since no current is drawn from ref when the the enhanced simplicity of CTCM makes it a suitable solution
aggressor line does not switch, the current measured when the for a wider range of applications, as discussed in Section V.
aggressor switches can be directly used in (6), providing the
coupling capacitance without two-step differential measure-
ments. Differential measurements can still be used to further B. Practical Issues and Solutions
improve accuracy by compensating second-order nonidealities
through the calibration procedure. The advantages discussed so far come from the idea of con-
SPICE simulations performed for different values of necting the two switches of the transducer to the same bias
(ranging from 1 to 100 fF) and for a fixed value of (namely, voltage ref. From a practical point of view, this requires two
10 fF) are shown in Fig. 9. According to simulation results, the power supply lines, with independent amperemeters, to be avail-
error obtained in the estimate of is always below 0.03%. able to connect both ends of the transducer to the same voltage
The scheme of Fig. 8(a) was implemented in 0.18- and source.
0.09- m technologies from STMicroelectronics, using either Unfortunately, such a configuration is not directly provided
pMOS transistors or CMOS pass gates as switches. Typical by most of the equipment typically used for on-wafer semicon-
results of the experiments showing accuracy and repeatability ductor parametric testing, since they allow us only to measure
are reported in Fig. 10. The one-sigma variation was 8 aF for a the overall current supplied by each generator. If independent
measured mean coupling capacitance of 11.557 fF. current measures are required, independent voltage sources have
to be used to provide supply bias ref at the two ends of the
A. Advantages of CTCM Over CBCM transducer. In this case, great care must be devoted to obtain the
same supply voltage at both ends of the transducer in order to
As already mentioned, the key difference between CTCM and avoid nonnegligible systematic errors that may impair the ad-
crosstalk-based CBCM is that CTCM keeps the victim line at a vantages of CTCM and require two-step compensations. De-
constant bias voltage, achieving several benefits. noted by ref1 and ref2, the actual values of the bias voltages
VENDRAME et al.: CROSSTALK-BASED CAPACITANCE MEASUREMENTS: THEORY AND APPLICATIONS 73

provided to switches 1 and 2 of a CTCM transducer, the system- TABLE I

atic error made by the transducer can be computed as AGGRESSOR CONFIGURATION FOR CAPACITOR MATCHING ANALYSIS

unbal ref1 ref2 (7)

where is the total capacitance seen by the two

switches. An additional contribution may come from short-cir-
cuit currents in case of overlapping control signals. To reduce
bias voltage mismatches we are currently investigating the pos-
sibility of using floating source monitor units (SMUs) [25].
The standard deviation computed over several
A further nonideality might come from the mismatch between
dice and wafers is a measure of mismatch. It is generally found
the transistors used to implement switches 1 and 2, which may
that decreases for larger devices (i.e., for larger
impair the charge-injection compensation.
values of ).
The above-mentioned nonidealities cannot be measured sep-
The layout and the transistor-level schematic of the proposed
arately, but they can be taken into account and compensated by
CTCM test structure are shown in Fig. 11(a) and (b), while Fig.
means of a preliminary calibration of the CTCM transducer. The
11(c) and (d) shows a pictorial view of the three-dimensional
calibration is just a measurement of the average supply current
(3-D) structure of the M3/M2/M1 stacked capacitors under test
obtained with a quiet aggressor (kept at a fixed voltage). The av-
and a micrograph taken at the M1 process step. The internal
erage current err (theoretically zero) represents the systematic
plate of each capacitor is a square (of either 2 2 or 4 4 m )
error that has to be subtracted from the actual current measure
properly drawn for analog applications with stubs and guard
.
rings to reduce the effect of mask misalignment.
Notice that the calibration step can be regarded as the first step
The switches of the CTCM transducer are implemented by
of a two-step differential measurement. We remark, however,
CMOS pass gates. The outer plates of the capacitors under test
that in this case the result of the first measurement is much lower
are shorted together and connected to the CTCM transducer,
than the value of the target quantity, so that it does not impair
while the internal plates, acting as aggressors, are driven by
measurement resolution.
independent input signals. A key point for the evaluation of
To test the calibration procedure, we performed two CTCM
is the use of two independent aggressors. In fact, when
experiments on the same test structure, with slightly different
the aggressors have the same phase, the average crosstalk cur-
values of Vref1 and Vref2 generated by independent sources.
rent is proportional to ; when they have opposite phase,
The first time we obtained err and nA,
the average crosstalk current is proportional to , as
leading to a measured current after correction of 3.04 nA, while
shown in Table I.
the second time we obtained err pA and nA,
Since the proportionality coefficients ( and ) are the
corresponding to a corrected current of 3.033 nA.
same, the relative mismatch can be directly computed as the
ratio between the two measured currents. As a general remark,
V. NONCONVENTIONAL APPLICATIONS direct measurements of and (obtained
In this section, we propose nonconventional applications of by using both aggressors) provide more accurate results then
CTCM, discussing, in particular, the measurement of the mis- separate measurements of C1 and C2 (obtained using only one
match between stacked metal–metal capacitor pairs and the lo- aggressor at the time), since they reduce error propagation and
calization of a break on a wire. fully exploit the resolution of the measurement equipments.
From (6), we observe that the relation between and avg
A. On-Chip Metal–Metal Capacitor Mismatch depends on the actual value of . In order to make sure that
Mismatch deals with the uncorrelated random variations of both aggressors have the same , the external input signals
two identical devices drawn close together on the same die [19]. are buffered on chip using CMOS buffers with the same supply
The mismatch between a pair of matched devices is usually ex- voltage.
pressed as the standard deviation of the relative (percentage) dif- The proposed test structure was implemented in a
ference of the values taken by the same parameter for the two 0.18- m embedded flash technology with aluminum backend.
devices. High-voltage transistors were used to implement the CTCM in
In this section, we propose a CTCM technique that can order to increase the signal amplitude and reduce the leakage.
be used to measure the mismatch between a pair of stacked Crosstalk currents were measured at both sides of the CTCM
metal–metal capacitors. Denoted by and , for the actual transducers by means of a HP4155 parameter analyzer, while
capacitance values of the two capacitors (designed to have two synchronized HP8110s were used to generate input pulses.
the same nominal capacitance ) the percentage difference is The standard deviation of the relative mismatch measured over
defined as more than 50 dice is reported in Table II. The discrepancies
between the measurements taken from top and bottom pass
gates are well below 0.05%, which may be thought as the
(8) resolution of the methodology with the experimental setup and
configuration used to conduct the experiments.
74 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO. 1, FEBRUARY 2006

Fig. 11. Test structure for application of CTCM to matched capacitors. (a) Layout of matched capacitors including part of CTCM transducer. (b) Circuit-level
schematic. (c) Pictorial 3-D view of Metal3/Metal2/Metal1 stacked capacitor. (d) Micrograph of test structure at Metal1 process step.

TABLE II technology with a pseudofloating gate test structure [26]) ac-

MEASURED STANDARD DEVIATION OF RELATIVE CAPACITOR MISMATCH cording to the model

(9)

where and are the edges of the inner plate of the matched
capacitors.
B. Line-Break Localization
Further experiments were performed on larger capac- CTCM transducers, in the configuration shown in Fig. 12(a),
itors (i.e., 4 4 m ) to assess measurement robustness. can be applied to determine the position of a line break. The
First, the mismatch measurement was repeated obtaining line under test (line1) is connected at both ends to two CTCM
top . Second, and were di- transducers that may be used in many different configurations
rectly measured by applying a single aggressor at the time depending on the values of the fourvoltage sources and on the
while keeping the other aggressor grounded. The measure- waveforms of the four control signals.
ments were repeated twice and (8) was applied providing In particular, steady-state currents can be induced across line1
top and bottom . either to induce electromigration or to check the integrity of the
Third, an estimate of the mismatch between two subsequent line. Once a line break is detected, crosstalk currents induced
measurements of the same quantity was evaluated by applying at both ends by a parallel aggressor (line2) can be measured to
(8) using, in place of and , two measures of the same determine the position of the break.
capacitor (namely, ) made with a single aggressor. The value Two methodologies (hereafter called direct and indirect
obtained for the 50 dice was . methods) can be applied depending on the break configuration.
The mismatch values reported in Table II are aligned with a Direct Method: Let us assume that the line is affected by
matching coefficient of about 4% m (obtained for the same just one break of negligible length. We denote by the length
VENDRAME et al.: CROSSTALK-BASED CAPACITANCE MEASUREMENTS: THEORY AND APPLICATIONS 75

TABLE III
MEASURES OF SEGMENTS OF BROKEN LINE, ACCORDING TO DIRECT METHOD

In fact, the induced charge is proportional to the coupling length,

as shown in Fig. 12(b). It is also worth noting that each current
can be measured at both sides of each CTCM, providing the
opportunity for cross validation.
A test structure with an interrupted line was implemented in a
90-nm technology and used as a test case. The overall length of
the broken line (line1) is of 1595.68 m and a break of 0.16
m splits the line in an segment of 533 m and a seg-
ment of 1062.52 m. Line2 is placed at minimum distance from
line1. Measurement results obtained from six dice are reported
in Table III.
Experimental results confirm the good predictability of the
method; the uncertainty for the and length estimations are
about 5.5 and 2.7 m, respectively. We remark, however, that
the direct method described so far is applicable only under the
assumption that there is only one break and that (the
shorter the length of the break, the higher the accuracy).
Indirect Method: It is possible to overcome the limitation
of the direct method by simply using an additional (reference)
test structure to measure the cross-coupling capacitance per unit
length. The reference test structure is just a CTCM transducer
Fig. 12. (a) Test structure for localization of break on line. (b) Induced charge
that measures the crosstalk current induced on the victim line by
proportional to line lengths. (c) CTCM structure for indirect length measure- an aggressor of known length Lref placed at the same distance
ment. as line2 from line1 [Fig. 12(c)].
The coupling capacitance per unit length obtained from the
reference test structure can then be used to compute the length
of the two coupled lines and by and the distance of the of and by means of
break from the two ends of line1. Since the coupling capacitance
between two parallel lines is proportional to the length of their
overlapped regions, the coupling capacitance between
avg
the aggressor line and the portion of the victim line at the left ref ref (12)
(right) of the break is proportional to . Hence, the position ref ref
avg
of the break can be obtained from the measured capacitances as ref ref (13)
follows: ref ref
In case of multiple breaks affecting a single line, this allows us
to locate the first and the last break by computing their distances
(10) from the two ends of the line.
The method was tested using a test structure with ref
If the coupling capacitances are measured by the matched m. The results reported in Table IV for six dice show that
CTCMs connected at both ends of line1, the break position can the average error is about 10 and 25 m in and estimated
be directly obtained from the measured average currents lengths, respectively.
The indirect method is less accurate than the direct method
avg due to the additional uncertainty introduced by the reference
(11)
avg avg structure (e.g., ref is subject to uncertainty and the distance
76 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO. 1, FEBRUARY 2006

TABLE IV for in-line monitoring of the intrametal dielectric thickness,

MEASURES OF SEGMENTS OF BROKEN LINE, ACCORDING intrametal coupling capacitance, and bit-line/word-line ca-
TO INDIRECT METHOD
pacitance in nonvolatile memory arrays of the 90- and 65-nm
technology nodes.

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properties of Mos transistors,” IEEE J. Solid-States Circuits, vol. 34, engineering from the Politecnico di Milano, Milano,
pp. 1433–1439, 1989. Italy, in 1998.
[20] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits, for In 2000, he joined STMicroelectronics, Agrate,
Signals Processing. New York: Wiley, 1986. Italy, working in Central Research and Develop-
[21] C. T. Fan and J. H. Wang, “Chip capacitance measurement circuit,” , ment, Non-volatile Memory Group. He is in charge
U.S. patent 6 404 222 B1, 2002. of device and back-end modeling. His research
[22] R. Suaya and S. H. M. Billy, “Capacitance and transmission line interests include simulation, modeling, and on-chip
measurements for an integrated circuit,” , U.S. patent application US measurement of ULSI interconnects.
2002/0 116 696A1, 2002.
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vol. 18, pp. 235–238. Fabrizio Cattane received the Laurea degree in
[24] A. Bogliolo, F. Vaira, L. Vendrame, and L. Bortesi, “A new test struc- electrical engineering from the Politecnico di Mi-
ture for measuring on-chip cross-coupling capacitances,” in Proc. IEEE lano, Milano, Italy, in 2003.
Signal Propagation Interconnect Conf., 2004, pp. 165–166. In 2004, he joined STMicroelectronics, Agrate,
[25] L. Stauffer, “Tips, tricks, and traps for advanced SMU DC measure- Italy, working in Front End Manufacturing as a
ments,” in Overcoming the Measurement Challenges of Advanced member of the device and back-end modeling team
Semiconductor Technologies Keithley book series, 2005, pp. 100–110. in the Non-volatile Memory Advanced Research
[26] O. Roux dit Bouisson, G. Morin, F. Paillardet, and E. Mazaleyrat, “A Group. His research interests include back-end
new characterization method of accurate capacitor matching measure- modeling and simulation.
ments using pseudofloating gate test structure in submicron CMOS and
BiCMOS technologies,” in Proc. IEEE ICMTS Conf., 1998, vol. 11, pp.
223–337.

Alessandro Bogliolo (M’00) received the Laurea de-

gree in electrical engineering and the Ph.D. degree in
Loris Vendrame received the Laurea degree in elec- electrical engineering and computer science from the
trical engineering and the Ph.D. degree in electronic University of Bologna, Bologna, Italy, in 1992 and
instrumentation from the University of Padova, Italy, 1998, respectively.
in 1991 and 1995, respectively. From 1992 to 1999, he was with the Department of
In 1996, he was with CNET, France Telecom, Electronics, Computer Science and Systems (DEIS),
Grenoble, working on dc, ac, RF, and reliability University of Bologna. In 1995 and 1996, he was vis-
evaluation of BiCMOS BJTs. In 1997, he joined iting the Computer Systems Laboratory (CSL), Stan-
STMicroelectronics, Agrate, Italy, working in ford University, Stanford, CA. From 1999 to 2002,
Central Research and Development, Non-volatile he was an Assistant Professor with the Department
Memory Group. He is responsible for backend and of Engineering (DI), University of Ferrara, Ferrara, Italy. In 2002, he joined
analog characterization of stand-alone and embedded the University of Urbino, Urbino, Italy, as an Associate Professor. Currently,
NVM technologies. His research interests include device characterization, he is the Director of the Information Science and Technology Institute (ISTI),
physics and reliability, and electronic test and measurement techniques. University of Urbino. He His research interests include embedded low-power
Dr. Vendrame is a member of the Italian Electrotechnical Association (AEI). systems, dynamic power management, signal integrity, and bioinformatics.