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Microprocessing Mini Project Report

This document is a report on a mini project using a DE10 kit to control an LCD display and motor. It includes: 1) The project topic of building a system to blink text on an LCD and control a motor's PWM using switches. 2) Details on the hardware setup in Quartus including connecting a NIOS II processor, memory, GPIO pins for the LCD and motor driver, switches, and a timer. 3) Plans for the software processing using NIOS II to read the switches and control the LCD display and motor's duty cycle/frequency based on the switch states.

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132 views9 pages

Microprocessing Mini Project Report

This document is a report on a mini project using a DE10 kit to control an LCD display and motor. It includes: 1) The project topic of building a system to blink text on an LCD and control a motor's PWM using switches. 2) Details on the hardware setup in Quartus including connecting a NIOS II processor, memory, GPIO pins for the LCD and motor driver, switches, and a timer. 3) Plans for the software processing using NIOS II to read the switches and control the LCD display and motor's duty cycle/frequency based on the switch states.

Uploaded by

Athen Okiff
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY DEPARTMENT OF

ELECTRICAL AND ELECTRONICS ENGINEERING


--------------------------

Microprocessor (LAB)
Mini project Report

Lecturer: Nguyễn Trung Hiếu

Class Group: TT02 – Group 01


Student: Trương Huy Thịnh – 185xxxx
Nguyễn Ngọc Khánh – 185xxxx
Đặng Đức Toàn – 1951022
Microprocessor (Lab) Report

Table of Contents
MINI PROJECT TOPIC & THEOREM 3
Topic of mini project 3
Topic analysis 3
HARDWARE PROCESSING 3
Create VDHL file using DE10 Standard V1.0.1 3
Open VHDL file by Quartus 18.1 and set up Platform Designer 4
SOLFWARE PROCESSING 9
Type chapter title (level 2) 5

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Microprocessor (Lab) Report

A. MINI PROJECT TOPIC & TOPIC ANALYSIS:


1. Topic of mini project:
Build a system using NIOS II in kit DE10 to connect a LCD 16 x 2
and H-bridge to control a motor. This system can do the following
tasks:
- When SW0 is ON, LCD blinks the sentence “Hello Word !!! ” in the
middle of row 1 with frequency Hz. (Using timer)
- When SW1 is ON, NIOS II controls the motor by sending PWM pulses to
the H-bridge. LCD displays the duty cycle and the frequency of PWM rules.
- When SW0 and SW1 is OFF, turn off the system.
Reference:
- Datasheet of LCD 16x2
- An instruction of LCD interference
- L298_H_bridge datasheet

2.Topic analysis:
- Build Microprocessor using NIOS II in kit DE10.
- Switch (SW0 and SW1) is going to be used.
- For connection with LCD 16x2 and 2 ports for H bridge L298N, we use
GPIO of DE10 standard kit.
- A timer for blinking LCD with frequency Hz.

B. HARDWARE PROCESSING (VHDL):


1. Create VDHL file using DE10 Standard V1.0.1:
Choose option as follows:
- GIPO (default): need for connection with LCD 16x2 and 2 ports for H
bridge L298N.
- Switch: need switch to the cases like the topic (SWITCH 0 and 1).
- Clock.
- SDRAM: for NIOS II processing.

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Microprocessor (Lab) Report

Fig.1: DE10 Standard V1.0.1 set up

2. Open VHDL file by Quartus 18.1 and set up Platform Designer:


Open Platform Designer, we would need these blocks follow the order:
- System and SDRAM Clocks for DE-Series Boards (Fig.2)
- NIOS II Processor (Fig.3)
- On-chip Memory (RAM or ROM) Intel FPGA IP (Fig.4)
- SDRAM Controller Intel FPGA IP (Fig.5)
- JTAG UART Intel FPGA IP (Fig.6)
- PIO (Parallel I/O) Intel FPGA IP (x4) (Fig.7)
- System ID Peripheral Intel FPGA IP (Fig.8)
- Interval Timer Intel FPGA IP (Fig.9)

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Microprocessor (Lab) Report

Fig.2: System and SDRAM Clocks for DE-Series Boards


Fig.3.a: NIOS II Processor (Main)

Fig.3.b: NIOS II Processor (Vector)


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Microprocessor (Lab) Report

Fig.4: On-chip Memory (RAM or ROM) Intel FPGA IP

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Microprocessor (Lab) Report

Fig.5: SDRAM Controller Intel FPGA IP

Fig.6: JTAG UART Intel FPGA IP

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Microprocessor (Lab) Report

Fig.7: PIO (Parallel I/O) Intel FPGA IP (x4)

Fig.8: System ID Peripheral Intel FPGA IP


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Microprocessor (Lab) Report

Fig.9: Interval Timer Intel FPGA IP

C. SOLFWARE PROCESSING (NIOS – II):

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