Birla Institute of Technology & Science, Pilani

Work Integrated Learning Programmes Division

Second Semester 2019-2020
M.Tech (Data Science and Engineering)
Mid-Semester Exam (EC-2 Regular)

Course No. : DSEIDZG516

Course Title : Computer Organization and Software Systems
Nature of Exam : Open Book
Weightage : 30%
No. of Pages =3
Duration : 90 minutes
Date of Exam : 28/06/2020 (FN), 10:00 am to 11:30 am No. of Questions = 4
Note to Students:
1. All parts of a question should be answered consecutively. Each answer should start from a fresh
page.
2. Assumptions made if any, should be stated clearly at the beginning of your answer.
3. For all problems relevant steps are to be shown.

Q1: Answer the following questions. [8 MARKS]

A. “Mybenchmark” is a performance benchmarking organization that does benchmarking of CPUs before
they are released for commercial use. Their benchmarking programs consists of arithmetic operations
apart from memory operations. They run in a controlled environment with prescribed configuration
so that results can be analyzed and compared across CPUs. “Mybenchmark” business model is to sell
their analysis to CPU manufacturers so that they can improve their designs.
In 2019, a new processor was designed with frequency of 5 GHz. The table below gives instruction
frequencies as well as number of cycles the instructions take, for the different classes of instructions.
It is assumed that the processor only executes one instruction at a time. This exercise is tuned to execute
exactly 100 instructions. Following table summarizes the break-up:
Instruction Purpose Frequency Cycles
Type
Load & Store Memory access instructions 40% 5 cycles
take higher number of cycles ;
added to benchmark programs
to simulate industry scenarios
Arithmetic Floating point and integer 40% 3 cycles
Instructions arithmetic instructions are
predominantly used in business
transactions and programs
All others These are instructions such as 20% 4 cycles
program control transfer

This exercise of benchmarking looks at few critical parameters such as CPI, MIPS and cycle time, and
the organization wants you to answer the following so that they can validate their results.
i. Calculate the CPI . [1]
ii. What is the “MIPS” processor speed for the benchmark in millions of instructions per second?
[1]
iii. The hardware expert says that if you double the number of registers, the cycle time must be
increased by 30%. What would the new clock speed be (in GHz)? [2]

B. About 2.5 quintillion bytes of data created each day at our current pace, but that pace is only
accelerating with the growth of social media, and Internet of Things (IoT). The data gets stored in
various storage devices and subsequently gets analyzed for business decisions. Magnetic disk drive
continues to lead the market share. Size of data stored and access time continues to be a critical
performance metrics of storage devices.
“Bgate” company which manufactures Magnetic Disk Drives seeks your help in evaluating critical
performance metrics using the following inputs:
 Magnetic Disc pack has 32 surfaces, 256 tracks per surface and 512 sectors per track. There are 512
bytes per sector.
i. What is the capacity of disk pack? [1]
ii. What is the number of bits required to address a sector? [1]
iii. If the disk is rotating at 60 RPS (revolutions per second), what is the data transfer rate? [2]

Q2 . Answer the following questions. [8 MARKS]

A. A computer program is developed to run the DBSCAN algorithm on a processor with L1 cache and
main memory organization with hit ratio of 67%. The processor supports 64-bit address bus, an 8-bit
data bus and has a 256 KByte data cache memory with 4-way set associativity. The main memory is
logically divided into a block size of 256 Bytes. Each cache line entry contains, in addition to address
tag, 1 dirty bit.
i. What is the number of bits in the tag field of an address? [2]
ii. If the associativity in the above problem, is changed to 8-way, do you see any performance gain
and/ or drawback? Comment. [2]

B. Indian Meteorological Department’s computer data scientists contemplating the preference of using
LFU and FIFO replacement algorithms. The associative cache is having 4 lines and the address block
generated by the CPU is 2,3,6,4,3,2,5,7,6,5.
Help these Data scientists to choose the better of the two replacement algorithms. Justify your selection
with the help of the following table. [2+2 = 4]

Note: In LFU, in case of tie between cache lines for replacement, select the line which has been
there for longer time in the cache.
LFU
Time 0 1 2 3 4 5 6 7 8 9
Block # 2 3 6 4 3 2 5 7 6 5
L0
L1
L2
L3
Hit/Miss

FIFO
Time 0 1 2 3 4 5 6 7 8 9
Block # 2 3 6 4 3 2 5 7 6 5
L0
L1
L2
L3
Hit/Miss

Q3. Answer the following Questions. [7 Marks]

A. A RISC based CPU is to be designed to have 32 opcodes, source and destination operands referring to
64 registers, and a displacement of value such as 2ABCH. Specify the instruction format mentioning
the various fields and bits required by them. [2]

B. Consider a program with 50 instructions to be executed by a processor with two pipeline configurations
Mode 1 and Mode 2.
Mode 1 pipeline configuration consists of 5 stages: Instruction Fetch(IF), Instruction Decode(ID),
Fetch Operand(FO), Execution(EX), and Write Back(WB) with 12, 10, 25, 20 and 8 nano seconds (ns)
respectively. The inter-stage delay between each stage is 3 ns.
Mode 2 pipeline configuration is similar to that of Mode1 except the FO stage is divided into FO1,
FO2, FO3 with time duration 10ns, 8 ns, 7ns respectively and 3ns delay between stages.

i. Find out the time taken by the program using Mode1 pipeline configuration [1.5]
ii. Find out the time taken by the program using Mode2 pipeline configuration [1.5]
 iii. Find out and comment on the speedup achieved by mode2 configuration over
mode1configuration. [2]
Q4: Answer the following questions. [7 Marks]
The single cycle implementation of MIPS is as shown below. Answer the following questions with reference
to “beq $S1, $S2, 8H” instruction. Assume that the contents of the registers S1 = 10 H, S2 = 10H, and PC =
16H, pointing to the instruction under consideration.
i. What is the addressing mode of the instruction? [1]
ii. Which part of the instruction format, address of S1 and S2 are stored? [1]
iii. What is the status of different control signals to execute the instruction? Answer should be presented
in the form of table given below. Indicate Don’t care as X. [3.5]

Signal Status
RegDst
Branch
MemRead
MemtoReg
ALUOp
ALUSrc
RegWrite

iv. What is the value of Zero Flag ? [0.5]

v. What is the value of PC, after the execution of the instruction? [1]