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Microcode and Microsequencer Guide

This document provides a reference sheet for a microcode-controlled processor. It includes: - The functions of the microcode control fields like ASEL, BSEL, DSEL, and FSEL. - The ALU operation codes and next address/flag update codes. - A diagram of the processor data path showing how the microcode controls the register file, ALU and status flags. - Notes explaining how the microcode allows control of the register file and status flags.

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82 views2 pages

Microcode and Microsequencer Guide

This document provides a reference sheet for a microcode-controlled processor. It includes: - The functions of the microcode control fields like ASEL, BSEL, DSEL, and FSEL. - The ALU operation codes and next address/flag update codes. - A diagram of the processor data path showing how the microcode controls the register file, ALU and status flags. - Notes explaining how the microcode allows control of the register file and status flags.

Uploaded by

U K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Microcode and Microsequencer Reference Sheet

ASEL \ BSEL \ DSEL \ FSEL \ UPDF \ MUX1 \ MUX2 \ DATA \ MISC

Source Select ALU Address Data


000 INP Function 0 INT Field
001 R1 1 EXT
010 R2 0000 TSA
011 R3 0001 INC
100 R4 0010 DEC Next Address Misc. Field
101 R5 0011 ADD 0000 NEXT 000001 READ
110 R6 (SP) 0100 SUB 0001 LAD 000010 WRITE
111 R7 (PC) 0101 AND 0010 LC 000100 LDMAR
0110 OR 0011 LNC 001000 LDIR
0111 XOR 0100 LZ 001001 FETCH
Dest Select
1000 NOT 0101 LNZ 000101 DEREF
000 NONE
1001 SHL 0110 LS 010000 RFMUX
001 R1
1010 SHR 0111 LNS 100000 DMUX
010 R2
1011 ASR 1000 LV
011 R3
1100 RLC 1001 LNV
100 R4
1101 RRC 1010 LLT
101 R5
1110 RV1 1011 LGE
110 R6 (SP)
111 R7 (PC) 1111 RV2
Flag Update
0001 V UPV
0010 S UPS
0100 C UPC
1000 Z UPZ
1111 ZSCV UPALL
1010 ZS UPZS

MUX1
Control Control DATA
RD, WR RD, WR
MUX1

Address Memory
Reg. 2048 x 44 ASEL
IR[15:9] (CAR) (ROM) BSEL
MUX2
DSEL
FSEL
LD/INC DMUX
MUX2_OUT RFMUX
DATA
MUX2
UPZ
DATA_I UPS
UPV
UPC
0 1 C C Z Z S S V V LDMAR
Data LDIR
Status Bits Path

DATA_O
16 Bit Machine Instruction format
BIT# 15 98 65 32 0

IR: OPCODE ASEL BSEL DSEL

NOTE:
The OPCODE field is used as a jump to address in the
microcode. Each opcode can trigger a microcode subroutine at a
fixed location in the microcode ROM.

Processor Data Path


NOTE:
DMUX allows the register file to be DATA DATA_I
fed from a the data field of the IR LDIR
microcode ROM.
RFMUX allows the register file to be
controlled by bits in the fetched DMUX 1 0
instruction.

RFMUX
REGFILE RIN DIN

ASEL
BSEL 0
DSEL ASEL NOTE:
BSEL Microcode control
IR[8:0] 1 DSEL fields are highlighted
in BOLD

RST RST
CLK CLK

ABUS BBUS Processor


Status
LDMAR MAR Flags
ABUS BBUS

ALU ABUS BBUS Z UPZ


FSEL FSEL UPS
S
Z,S,C,V
C CIN
C UPC
FOUT
V UPV
FOUT

DATA_O

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