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Parallel Fault Simulation

This document provides instructions for an exercise on parallel fault simulation. Students are asked to: 1) Simulate two faults in parallel - a stuck-at-0 fault and a stuck-at-1 fault - on a 3-bit circuit using bit-parallel operations. 2) Upload a report including code, algorithms, and results. 3) Use the same problem as the previous week's series fault simulation exercise and perform parallel fault simulation similarly to the example, which inserts logic gates to represent faults and simulates them in parallel to test for detections.

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Aswin Raj
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485 views2 pages

Parallel Fault Simulation

This document provides instructions for an exercise on parallel fault simulation. Students are asked to: 1) Simulate two faults in parallel - a stuck-at-0 fault and a stuck-at-1 fault - on a 3-bit circuit using bit-parallel operations. 2) Upload a report including code, algorithms, and results. 3) Use the same problem as the previous week's series fault simulation exercise and perform parallel fault simulation similarly to the example, which inserts logic gates to represent faults and simulates them in parallel to test for detections.

Uploaded by

Aswin Raj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

DSTTD LAB

EXERCISES
2. PARALLEL FAULT SIMULATION
 UPLOAD REPORT INCLUDING CODE,
ALGORITHM AND SNAPSHOT OF RESULTS

2 bit adders different types


2 bit subtractor (2’s complement)
2 bit 3 o/p comparator
2 bit multipliers different types

Use the same problem as last week (Ex. 1. Series Fault


Simulation) and Perform Parallel Fault Simulation in a
similar way as for the example problem below.

• 2 faults: c stuck-at-0 and f stuck-at-1.


• 3-bit word – true value, c s-a-0, f s-a-1.
• a=b=1,not affected by fault, same values in all 3 ckts
• output of the circuit with c s-a-0 differs from that of the fault-free circuit, and that
fault is detected.
• f s-a-1 produces same output as fault-free circuit, hence not detected.
1
• Uses bit-parallelism of logical operations
• For w bit word, w – 1 faults simulated in parallel as 1st bit to store true signal value
• w – 1 faults are simulated with same CPU time as that of true-value simulation.
• In serial fault simulator, pass is terminated as soon as the single target fault is
detected.
• In parallel fault simulator, all w – 1 faults must be detected before a pass can be
terminated.
• Serial fault simulator gains more by fault dropping.

• Faults are simulated by inserting logic gates in the circuit.


• s-a-0 by AND, s-a-1 by OR
• input to AND (101) and OR (001)
• Can be (110) and (010) [s-a-1 first checked]

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