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19-1099; Rev 1; 9/96

Low-Power, +2.5V to +5.5V, Dual 8-Bit

Voltage-Output DAC in µMAX
_______________General Description ____________________________Features

MAX549
The MAX549 dual, serial 8-bit, voltage-output, digital-to- ♦ +2.5V to +5.5V Single-Supply Operation
analog converter (DAC) operates on a single +2.5V to
+5.5V supply. Its ±1LSB TUE specification is guaran- ♦ ±1LSB (max) TUE
teed over temperature. Operating current (supply cur- ♦ Low 150µA Operating Current (VDD = +2.5V)
rent plus reference current) is typically 150µA with VDD
= 2.5V and less than 1µA in shutdown mode. ♦ 1µA Shutdown Mode
The interface operates at clock rates up to 10MHz and is ♦ µMAX Package—50% Smaller than 8-Pin SO
compatible with 3-wire SPI™, QSPI™, and Microwire™
♦ 10MHz, 3-Wire Serial Interface
interface standards. The serial input shift register is 16
bits: 8 bits for DAC selection and shutdown control, and ♦ Internal Power-On Reset Clears All Registers
8 bits of DAC input data. to Zero
The MAX549’s ultra-low power consumption and small
µMAX package make it ideal for portable and battery-
powered applications.

______________Ordering Information
________________________Applications PART TEMP. RANGE PIN-PACKAGE
VCXO Control MAX549BCPA 0°C to +70°C 8 Plastic DIP
Comparator Level Settings MAX549BCUA 0°C to +70°C 8 µMAX
MAX549BC/D 0°C to +70°C Dice*
GaAs Amp Bias Control
MAX549BEPA -40°C to +85°C 8 Plastic DIP
Digital Gain and Offset Control MAX549BEUA -40°C to +85°C 8 µMAX
*Dice are specified at TA = +25°C, DC parameters only.

________________Functional Diagram

VDD
__________________Pin Configuration
8
DAC A DAC A OUTA
REGISTER R-2R LADDER
DIN
TOP VIEW
REF
SCLK
INPUT SHIFT REGISTER

CS 8 GND 1 8 VDD
DAC B DAC B OUTB
REGISTER R-2R LADDER
OUTA 2 7 REF
MAX549
CS 3 6 OUTB

DIN 4 5 SCLK

MAX549
DIP/µMAX

GND

SPI and QSPI are registered trademarks of Motorola, Inc.

Microwire is a registered trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products 1

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 Low-Power, +2.5V to +5.5V, Dual 8-Bit
Voltage-Output DAC in µMAX
ABSOLUTE MAXIMUM RATINGS
MAX549

VDD, SCLK, DIN, CS, OUTA, OUTB to GND.............-0.3V to +6V Operating Temperature Ranges
REF .............................................................-0.3V to (VDD + 0.3V) MAX549BC_A .....................................................0°C to +70°C
Maximum Current (any pin) ...............................................50mA MAX549BE_A ..................................................-40°C to +85°C
Continuous Power Dissipation Storage Temperature Range .............................-65°C to +150°C
Plastic DIP (derate 9.1mW/°C above +70°C) ..............727mW Lead Temperature (soldering, 10sec) .............................+300°C
µMAX (derate 4.1mW/°C above +70°C) ......................330mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE
Resolution N 8 Bits
Guaranteed MAX549BC_A/MAX549BEPA ±0.9
Differential Nonlinearity DNL LSB
monotonic MAX549BEUA (Note 1) ±0.9
MAX549BC_A/MAX549BEPA ±1
Total Unadjusted Error TUE LSB
MAX549BEUA (Note 1) ±1
Zero-Code Error ZCE TA = +25°C ±1 LSB
Full-Scale Error FSE ±1 LSB
REFERENCE INPUT
Reference Input Voltage VREF For specified performance 2.5 VDD V
Reference Input Resistance
RREF DAC code = 55 hex 16 kΩ
(Note 2)
Reference Input Current VDD = VREF = 5.5V 325 550
IREF DAC code = 55 hex µA
(Note 3) VDD = VREF = 2.5V 150 250
DAC OUTPUTS (OUTA, OUTB)
DAC Output Voltage Swing 0 REF V
DAC Output Resistance ROUT 32 kΩ
∆(ROUTA -
DAC Output Resistance Match ±0.2 %
ROUTB)
DIGITAL INPUTS (CS, SCLK, DIN)
Input High Voltage VIH 0.7VDD V
Input Low Voltage VIL 0.3VDD V
Input Current IIN VIN = 0V or VDD ±1 µA
Input Capacitance (Note 4) CIN 10 pF

2 _______________________________________________________________________________________
 Low-Power, +2.5V to +5.5V, Dual 8-Bit
Voltage-Output DAC in µMAX

MAX549
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE
Digital Feedthrough and
CS = high, all digital inputs from 0V to VDD 50 nV-sec
Crosstalk
Voltage-Output Settling Time To ±1/2LSB, CL = 20pF 4 µs
VDD = +2.5V 1.4
Voltage-Output Slew Rate SR CL = 20pF V/µs
VDD = +5.5V 3.1
Wake-Up Time CLOAD = 20pF 4 µs
POWER SUPPLIES
Supply Voltage Range VDD Outputs unloaded, all inputs = GND or VDD 2.5 5.5 V
VDD = +5.5V, outputs unloaded,
Supply Current IDD 0.3 10 µA
all inputs = GND or VDD
Shutdown Current Shutdown mode 0.3 µA
Note 1: 0°C to -40°C testing guaranteed by design using six sigma design limits.
Note 2: Worst-case input resistance at REF occurs at DAC code 55 hex.
Note 3: Worst-case reference input current occurs at DAC code 55 hex.
Note 4: Guaranteed by design. Not production tested.

TIMING CHARACTERISTICS (Note 5)

(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Digital inputs switching from 0V to VDD.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLK Pulse Width High tCH 40 ns
SCLK Pulse Width Low tCL 40 ns
DIN to SCLK High Setup tDS 30 ns
VDD = +2.5V 0
DIN to SCLK High Hold tDH ns
VDD = +5.5V 10
CS Low to SCLK High Setup tCSS0 30 ns
CS High to SCLK High Setup tCSS1 30 ns
VDD = 2.5V 10
SCLK High to CS Low Hold tCSH0 ns
VDD = 5.5V 20
Delay, SCLK High to CS High tCSH1 10 ns
CS Pulse Width High tCSW 40 ns
SCLK Period tCP 80 ns
VDD High to CS Low Power-on reset delay 5 µs
Note 5: Guaranteed by design. Not production tested.

_______________________________________________________________________________________ 3
 Low-Power, +2.5V to +5.5V, Dual 8-Bit
Voltage-Output DAC in µMAX
______________________________________________________________Pin Description
MAX549

PIN NAME FUNCTION

1 GND Ground
2 OUTA DAC A Output Voltage
Chip-Select Input. A logic low on CS enables serial data to be clocked into the input shift
3 CS
register. Programming commands are executed at CS’s rising edge.
4 DIN Serial Data Input. Data is clocked into the 16-bit input shift register on SCLK’s rising edge.
5 SCLK Serial Clock Input. Data is clocked in on SCLK’s rising edge.
6 OUTB DAC B Output Voltage
7 REF External Reference Voltage Input for DAC A and DAC B (2.5V to VDD)
8 VDD Positive Power Supply (+2.5V to +5.5V)

R R R R R R R

2R 2R 2R 2R 2R 2R 2R 2R 2R

REF OUT_

GND GND
LSB MSB

DAC_ REGISTER

NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FF HEX.

Figure 1. DAC Simplified Circuit Diagram

_______________Detailed Description Reference Input

The voltage applied at REF sets the full-scale output for
Analog Section both DACs and may range from 2.5V to VDD. The REF
The MAX549 is a dual, 8-bit, voltage-output digital-to- input resistance is code dependent, with the lowest
analog converter (DAC). Each DAC consists of an R-2R value (typically 16kΩ) occurring when both DAC regis-
ladder network that converts 8-bit digital inputs into ters are loaded with a code of 01010101 (55 hex). To
equivalent analog output voltages in proportion to the minimize INL errors, the reference voltage source
applied reference voltage (Figure 1). The MAX549’s should have less than 3Ω output impedance.
outputs are unbuffered and have a typical output resis-
tance of 32kΩ. The external reference is used by both
DACs. The power-supply range is from +2.5V to +5.5V.

4 _______________________________________________________________________________________
 Low-Power, +2.5V to +5.5V, Dual 8-Bit
Voltage-Output DAC in µMAX

MAX549
INSTRUCTION
EXECUTED

CS

OPTIONAL
SCLK 1 8 PAUSE 9 16

DIN

UB1 UB2 UB3 C2 C1 C0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 2. MAX549 Serial-Interface Timing Diagram

DAC Outputs Transmit data MSB first in one 16-bit word or two 8-bit
The MAX549’s outputs are unbuffered; each output bytes. The write cycle can be segmented when CS is
connects directly to an R-2R ladder. This configuration kept active (low) to allow two 8-bit-wide transfers. After
minimizes power consumption and reduces offset clocking all 16 bits into the input shift register, a rising
errors. For highest accuracy, apply high resistive loads edge on CS programs the DAC. The DAC outputs can
(1MΩ and up). Lower resistive loads can be driven, but be changed independently or simultaneously. The DAC
output loading increases full-scale error. The magni- outputs reflect the data stored in the DAC registers.
tude of the expected error is the ratio of the DAC output
resistance to the DC load resistance at the output. Initialization
The MAX549 has an internal power-on reset. At power-
Typically, an energy pulse is coupled into the DAC output up, all internal registers are reset to zero; therefore, an
on the rising edge of CS. Since the MAX549’s outputs are initialization write is not necessary.
unbuffered (connected directly to the R-2R ladder), con-
necting a small capacitor (200pF to 1000pF) from the out- Serial Input Data Format and Control Codes
put to ground creates a lowpass filter that effectively The control byte determines which DAC register is
suppresses the pulse for sensitive applications. updated (Table 1). Table 2 lists the MAX549’s serial-
input command format. The 16-bit input word consists
Shutdown Mode of an 8-bit control byte and an 8-bit data byte. The 8-bit
When the MAX549 is in shutdown mode, REF becomes control byte is not decoded internally; every control bit
high-impedance. The supply current is unchanged, but performs one function. Data is clocked in starting with
REF input current decreases to less than 1µA. This uncommitted bit 1 (UB1), followed by the remaining
allows the system reference to remain active with mini- control bits and the DAC data byte. The LSB (D0) of the
mal power consumption. data byte is the last bit clocked into the input shift regis-
When exiting shutdown mode, recovery time is equiva- ter (Figure 2).
lent to the DAC settling time. Table 3 is an example of a 16-bit word. It performs the
Serial Interface following functions:
The MAX549 interface is compatible with 3-wire SPI™, 1) Load 80 hex (128 decimal) into both DAC registers
QSPI™, and Microwire™ microprocessor (µP) interface 2) Update both DAC outputs on CS’s rising edge
standards. An active-low chip select (CS) enables the
input shift register to receive data from the serial input Table 4 shows how to calculate the output voltage
(DIN). Data is clocked into the input shift register on ris- based on the input code. Figure 3 gives detailed timing
ing edges of the serial clock signal (SCLK). The clock information.
frequency can be as high as 10MHz.

_______________________________________________________________________________________ 5
 Low-Power, +2.5V to +5.5V, Dual 8-Bit
Voltage-Output DAC in µMAX
MAX549

CS tCSH0 tCSW

tCSS0 tCSH1
tCH

SCLK

tDS tCL tCSS1

tDH

DIN

Figure 3. Detailed Serial-Interface Timing Diagram

Table 1. Control Byte/Input Word Bit Microprocessor Interfacing

The MAX549 serial interface is compatible with
Definitions Microwire, SPI, and QSPI interface standards. For SPI,
UB1* X Unassigned Bit 1 clear the CPOL and CPHA bits (CPOL = 0 and
UB2 X Unassigned Bit 2 CPHA = 0). CPOL = 0 sets the idle clock state to zero
UB3 X Unassigned Bit 3 and CPHA = 0 changes data at SCLK’s falling edge.
C2 0 Power-Up Mode
This setting allows SPI to run at full clock speeds
(1.5MHz). If a serial port is not available on your µP,
C2 1 Power-Down Mode three bits of a parallel port can be used to emulate a
C1 0
DAC Register Load Operation serial port by bit manipulation. Minimize digital
Disabled feedthrough at the DAC outputs by operating the serial
Control DAC Register Load Operation clock only when necessary.
C1 1
Byte Enabled
DAC Output Updated on Rising ––––––––––––––Applications Information
C0 0
Edge of CS
Power-Supply and Ground Considerations
C0 1 Unassigned Operation Connect GND to the highest-quality ground available.
A1 0 Do Not Address DAC B Bypass VDD with a 0.1µF to 0.22µF capacitor to GND.
A1 1 Address DAC B The reference input can be used without bypassing.
A0 0 Do Not Address DAC A However, for optimum line/load-transient response and
noise performance, bypass the reference input with
A0 1 Address DAC A
0.1µF to 4.7µF to GND.
D7 X DAC Data Bit 7 (MSB)
Careful PC board layout minimizes crosstalk among
D6 X DAC Data Bit 6
the DAC outputs, the reference, and the digital inputs.
D5 X DAC Data Bit 5 Separate analog traces by running ground traces
Data D4 X DAC Data Bit 4 between them. Make sure high-frequency digital lines
Byte D3 X DAC Data Bit 3 are not routed parallel to analog lines.
D2 X DAC Data Bit 2
D1 X DAC Data Bit 1
D0** X DAC Data Bit 0 (LSB)
*Clocked in first
**Clocked in last

6 _______________________________________________________________________________________
 Low-Power, +2.5V to +5.5V, Dual 8-Bit
Voltage-Output DAC in µMAX

MAX549
Table 2. Serial Interface Programming Commands
CONTROL BYTE DATA BYTE
Loaded First Loaded Last COMMAND
UB1 UB2 UB3 C2 C1 C0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Initial condition of all registers after
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
power-up.
On CS’s rising edge, wake up both DACs.
X X X 0 0 0 X X X X X X X X X X
DAC registers unchanged.
X X X X X 1 X X X X X X X X X X Unassigned command
On CS’s rising edge, load DAC A register.
X X X 0 1 0 0 1 8-bit DAC data
DAC B register unchanged.
On CS’s rising edge, load DAC B register.
X X X 0 1 0 1 0 8-bit DAC data
DAC A register unchanged.
On CS’s rising edge, load and update both
X X X 0 1 0 1 1 8-bit DAC data
DAC registers.
On CS’s rising edge, power down both
X X X 1 0 0 1 1 X X X X X X X X DACs. Both DAC outputs go to zero. DAC
registers unchanged.
On CS’s rising edge, power down both
X X X 1 1 0 1 1 8-bit DAC data DACs and update both DAC registers.
Both DAC outputs go to zero.
X = Don’t Care

Table 3. Example Input Word

Loaded First Loaded Last
UB1 UB2 UB3 C2 C1 C0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 1 0 1 1 1 0 0 0 0 0 0 0
X = Don’t Care

Table 4. Analog Output vs. Code

DAC CONTENTS ANALOG
D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT (V)
1 1 1 1 1 1 1 1 +VREF x (255/256)
1 0 0 0 0 0 0 1 +VREF x (129/256)
1 0 0 0 0 0 0 0 +VREF x (128/256) = +VREF/2
0 1 1 1 1 1 1 1 +VREF x (127/256)
0 0 0 0 0 0 0 1 +VREF x (1/256)
0 0 0 0 0 0 0 0 0
Note: 1LSB = VREF x 2-8 = VREF(1/256)
ANALOG OUTPUT = +VREF(I/256), where I = Integer Value of Digital Input

_______________________________________________________________________________________ 7
 Low-Power, +2.5V to +5.5V, Dual 8-Bit
Voltage-Output DAC in µMAX
MAX549

_____________________AC Considerations ___________________Chip Information

Digital Feedthrough TRANSISTOR COUNT: 1562
High-speed data at any of the digital input pins may
couple through the DAC’s internal stray package
capacitance and cause noise (digital feedthrough) at
the DAC’s output, even though CS is held high. This
digital feedthrough is tested by holding CS high and
toggling the digital inputs from all 1s to all 0s.
Analog Feedthrough
Due to internal stray capacitance, higher-frequency
analog input signals at REF may couple to the output,
even when the input digital code is all 0s. Test analog
feedthrough by setting all DAC outputs to 0V and
sweeping REF.

________________________________________________________Package Information
INCHES MILLIMETERS
DIM
MIN MAX MIN MAX
A 0.036 0.044 0.91 1.11
C A1 0.004 0.008 0.10 0.20
α
A B 0.010 0.014 0.25 0.36
C 0.005 0.007 0.13 0.18
0.101mm
D 0.116 0.120 2.95 3.05
e 0.004 in
E 0.116 0.120 2.95 3.05
B A1 L e 0.0256 0.65
H 0.188 0.198 4.78 5.03
L 0.016 0.026 0.41 0.66
α 0° 6° 0° 6°
21-0036D

E H

8-PIN µMAX
MICROMAX SMALL-OUTLINE
PACKAGE
D

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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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