MELSEC System Q/L Series

Programmable Logic Controllers

Programming Manual

21112011 INDUSTRIAL AUTOMATION

Version A
 Programming Manual for the
MELSEC System Q and L Series
Art. No.:

Version Changes / Additions / Corrections

A 11/2011 akl First edition
 About this Manual

The texts, illustrations, diagrams, and examples contained in this manual are
intended exclusively as support material for the explanation, handling,
programming, and operation of the programmable logic controllers of the
MELSEC System Q and L series.

If you have any questions concerning the programming and operation of the
equipment described in this manual, please contact your relevant sales office or
department (refer to back of cover).
Current information and answers to frequently asked questions are also
available through the Internet (www.mitsubishi-automation.com)

MITSUBISHI ELECTRIC EUROPE B.V. reserves the right for technical

changes and changes to this manual at any time without prior notice.

© 07/2011
 Contents

Contents
1 Introduction
1.1 Further manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 CPU types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.4 Finding an instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.5 PLC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6 Comparison between the software packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

2 Instruction Tables
2.1 Subdivision of instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Overview of instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 Description of the overview tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 Sequence instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.1 Input instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.2 Connection instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.3 Output instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3.4 Shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.5 Master control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.6 Program termination instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.7 Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4 Application instructions, Part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.4.1 Comparison operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.4.2 Arithmetic operation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4.3 Data conversion instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.4 Data transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.4.5 Program branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.4.6 Interrupt program execution control instructions. . . . . . . . . . . . . . . . . . . . . 2-25
2.4.7 Data refresh instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.4.8 Other convenient instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.5 Application instructions, Part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.5.1 Logical operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.5.2 Rotation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.5.3 Shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.5.4 Bit processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.5.5 Data processing instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.5.6 Structured program instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.5.7 Data table operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.5.8 Buffer memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.5.9 Display instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.5.10 Debugging and failure diagnosis instructions . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.5.11 Character string processing instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
2.5.12 Special function instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

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2.5.13 Data control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48

2.5.14 File register switching instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
2.5.15 Clock instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
2.5.16 Expansion clock instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
2.5.17 Program instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
2.5.18 Other instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
2.6 Data link instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
2.6.1 Instructions for network refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
2.6.2 Read/write routing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
2.7 Multiple CPU dedicated instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
2.7.1 Instructions for writing to the CPU shared memory of host CPU . . . . . . . . 2-59
2.7.2 Instructions for reading from the CPU shared memory of another CPU. . . 2-59
2.7.3 Multiple CPU high-speed transmission dedicated instructions . . . . . . . . . 2-60
2.8 System switching instruction for a redundant system . . . . . . . . . . . . . . . . . . . . . . . 2-61
2.9 Instructions for special function modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
2.9.1 Instructions for serial communication modules . . . . . . . . . . . . . . . . . . . . . . 2-62
2.9.2 Instructions for PROFIBUS/DP interface modules . . . . . . . . . . . . . . . . . . . 2-62
2.9.3 Instructions for ETHERNET interface modules. . . . . . . . . . . . . . . . . . . . . . 2-63
2.9.4 Instruction for MELSECNET/H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
2.9.5 Instructions for CC-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64

3 Configuration of Instructions
3.1 The structure of an instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 Source of data (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.2 Destination of data (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.3 Number (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Notation of instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.1 16/32-bit and pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.2 MELSEC and IEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.3 Further characteristics of the instruction notation . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.4 Specification of the notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3 Programming of dedicated instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4 Programming of variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.1 Programming with the GX IEC Developer. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.1 Processing of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.5.2 Addressing of arrays and registers in the GX IEC Developer. . . . . . . . . . . 3-22
3.5.3 Usage of character string data (STRING). . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.6 Index qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.7 Indirect designation (GX Works2 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.8 Reducing instruction processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.8.1 Subset processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.8.2 Operation processing with standard device registers (Z)
(Universal model QCPU and LCPU only) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

VIII
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3.9 Operation errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

3.9.1 Verification of the device range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
3.9.2 Verification of the device data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
3.9.3 Buffer memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
3.9.4 Multiple CPU shared memory access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
3.10 Execution conditions of the instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
3.10.1 Execution condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
3.10.2 EN input and ENO output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
3.11 Number of program steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
3.12 Multiple Instructions using the same device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61
3.12.1 OUT instructions using the same device . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61
3.12.2 SET/RST instructions using the same device . . . . . . . . . . . . . . . . . . . . . . 3-62
3.12.3 PLS instructions using the same device . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
3.12.4 PLF instructions using the same device . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
3.13 Precautions for use of file registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66

4 Layout and Structure of the Chapters

4.1 Overview of the instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 The CPU table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.3 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.4 Representation format of the instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4.1 Representation in the GX IEC Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4.2 Representation in GX Works2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.5 Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.6 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.7 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.8 Operation errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.9 Program examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

5 Sequence Instructions
5.1 Input instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.1 LD, LDI, AND, ANI, OR, ORI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.2 LDP, LDF, ANDP, ANDF, ORP, ORF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.3 LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.2 Connection instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.2.1 ANB, ORB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.2.2 MPS, MRD, MPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.2.3 INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.2.4 MEP, MEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.2.5 EGP, EGF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

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5.3 Output instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.3.1 OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.3.2 OUT T, OUTH T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.3.3 OUT C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.3.4 OUT F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5.3.5 SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
5.3.6 RST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.3.7 SET F, RST F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
5.3.8 PLS, PLF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5.3.9 FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
5.3.10 DELTA, DELTAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5.4 Shift instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
5.4.1 SFT, SFTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
5.5 Master control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
5.5.1 MC, MCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
5.6 Termination instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60
5.6.1 FEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60
5.6.2 END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
5.7 Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66
5.7.1 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66
5.7.2 NOP, NOPLF, PAGE n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68

6 Application Instructions, Part 1

6.1 Comparison operation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.1.1 =, < >, >, < =, <, > = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.1.2 D=, D<>, D>, D<=, D<, D>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.1.3 E=, E<>, E>, E< =, E<, E>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.1.4 ED=, ED<>, ED>, ED< =, ED<, ED>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.1.5 $ =, $ < >, $ >, $ < =, $ <, $ > = . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.1.6 BKCMP, BKCMPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6.1.7 DBKCMP, DBKCMPP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6.2 Arithmetic operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.2.1 +, +P, -, -P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
6.2.2 D+, D+P, D-, D-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42
6.2.3 x, xP, /, /P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
6.2.4 Dx, DxP, D/, D/P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
6.2.5 B+, B+P, B-, B-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
6.2.6 DB+, DB+P, DB-, DB-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
6.2.7 Bx, BxP, B/, B/P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60
6.2.8 DBx, DBxP, DB/, DB/P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63
6.2.9 E+, E+P, E-, E-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67
6.2.10 ED+, ED+P, ED-, ED-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-72
6.2.11 Ex, ExP, E/, E/P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77
6.2.12 EDx, EDxP, ED/, ED/P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80

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6.2.13 BK+, BK+P, BK-, BK-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83

6.2.14 DBK+, DBK+P, DBK-, DBK-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87
6.2.15 $+, $+P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91
6.2.16 INC, INCP, DEC, DECP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-94
6.2.17 DINC, DINCP, DDEC, DDECP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97
6.3 Data conversion instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-101
6.3.1 BCD, BCDP, DBCD, DBCDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103
6.3.2 BIN, BINP, DBIN, DBINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106
6.3.3 FLT, FLTP, DFLT, DFLTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-110
6.3.4 FLTD, FLTPD, DFLTD, DFLTPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113
6.3.5 INT, INTP, DINT, DINTP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-116
6.3.6 INTD, INTPD, DINTD, DINTPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-120
6.3.7 DBL, DBLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-123
6.3.8 WORD, WORDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-125
6.3.9 GRY, GRYP, DGRY, DGRYP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-127
6.3.10 GBIN, GBINP, DGBIN, DGBINP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-130
6.3.11 NEG, NEGP, DNEG, DNEGP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-133
6.3.12 ENEG, ENEGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-136
6.3.13 EDNEG, EDNEGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-138
6.3.14 BKBCD, BKBCDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-140
6.3.15 BKBIN, BKBINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-143
6.3.16 ECON, ECONP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-146
6.3.17 EDCON, EDCONP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-148
6.4 Data transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-150
6.4.1 MOV, MOVP, DMOV, DMOVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-151
6.4.2 EMOV, EMOVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-154
6.4.3 EDMOV, EDMOVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-156
6.4.4 $MOV, $MOVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-158
6.4.5 CML, CMLP, DCML, DCMLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-161
6.4.6 BMOV, BMOVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-166
6.4.7 FMOV, FMOVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-170
6.4.8 DFMOV, DFMOVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-173
6.4.9 XCH, XCHP, DXCH, DXCHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-176
6.4.10 BXCH, BXCHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-179
6.4.11 SWAP, SWAPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-182
6.5 Program branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-185
6.5.1 CJ, SCJ, JMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-186
6.5.2 GOEND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-190
6.6 Program execution control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-192
6.6.1 DI, EI, IMASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-193
6.6.2 IRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-200
6.7 Link refresh instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-202
6.7.1 RFS, RFSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-203

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6.8 Other convenient instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-205

6.8.1 UDCNT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-206
6.8.2 UDCNT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-209
6.8.3 TTMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-212
6.8.4 STMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-214
6.8.5 ROTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-218
6.8.6 RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-222
6.8.7 SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-225
6.8.8 PLSY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-228
6.8.9 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-230
6.8.10 MTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-232

7 Application Instructions, Part 2

7.1 Logical operation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.1.1 WAND, WANDP, DAND, DANDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.1.2 BKAND, BKANDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.1.3 WOR, WORP, DOR, DORP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.1.4 BKOR, BKORP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.1.5 WXOR, WXORP, DXOR, DXORP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.1.6 BKXOR, BKXORP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.1.7 WXNR, WXNRP, DXNR, DXNRP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
7.1.8 BKXNR, BKXNRP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
7.2 Data rotation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
7.2.1 ROR, RORP, RCR, RCRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39
7.2.2 ROL, ROLP, RCL, RCLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
7.2.3 DROR, DRORP, DRCR, DRCRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45
7.2.4 DROL, DROLP, DRCL, DRCLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
7.3 Data shift instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
7.3.1 SFR, SFRP, SFL, SFLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
7.3.2 BSFR, BSFRP, BSFL, BSFLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-55
7.3.3 SFTBR, SFTBRP, SFTBL, SFTBLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-58
7.3.4 DSFR, DSFRP, DSFL, DSFLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-61
7.3.5 SFTWR, SFTWRP, SFTWL, SFTWLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
7.4 Bit processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-67
7.4.1 BSET, BSETP, BRST, BRSTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-68
7.4.2 TEST, TESTP, DTEST, DTESTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-71
7.4.3 BKRST, BKRSTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-75
7.5 Data processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-79
7.5.1 SER, SERP, DSER, DSERP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-81
7.5.2 SUM, SUMP, DSUM, DSUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-87
7.5.3 DECO, DECOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-90
7.5.4 ENCO, ENCOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93
7.5.5 SEG, SEGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-96
7.5.6 DIS, DISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-100

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7.5.7 UNI, UNIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-103

7.5.8 NDIS, NDISP, NUNI, NUNIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-106
7.5.9 WTOB, WTOBP, BTOW, BTOWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-111
7.5.10 MAX, MAXP, DMAX, DMAXP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-116
7.5.11 MIN, MINP, DMIN, DMINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-119
7.5.12 SORT, DSORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-122
7.5.13 WSUM, WSUMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-126
7.5.14 DWSUM, DWSUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-128
7.5.15 MEAN, MEANP, DMEAN, DMEANP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-130
7.6 Structured program instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-133
7.6.1 FOR, NEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-134
7.6.2 BREAK, BREAKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-137
7.6.3 CALL, CALLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-140
7.6.4 RET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-146
7.6.5 FCALL, FCALLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-148
7.6.6 ECALL, ECALLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-153
7.6.7 EFCALL, EFCALLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-159
7.6.8 XCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-164
7.6.9 COM (Refresh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-170
7.6.10 COM (Selective Refresh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-173
7.6.11 CCOM, CCOMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-177
7.6.12 IX, IXEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-179
7.6.13 IXDEV, IXSET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-184
7.7 Data table operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-187
7.7.1 FIFW, FIFWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-188
7.7.2 FIFR, FIFRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-192
7.7.3 FPOP, FPOPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-196
7.7.4 FDEL, FDELP, FINS, FINSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-200
7.8 Buffer memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-207
7.8.1 FROM, FROMP, DFRO, DFROP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-208
7.8.2 TO, TOP, DTO, DTOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-212
7.9 Display instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-217
7.9.1 PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-218
7.9.2 PRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-223
7.9.3 LEDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-227
7.10 Failure diagnosis and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231
7.10.1 CHKST, CHK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-232
7.10.2 CHKCIR, CHKEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-240

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7.11 Character string processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-245

7.11.1 BINDA, BINDAP, DBINDA, DBINDAP . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-248
7.11.2 BINHA, BINHAP, DBINHA, DBINHAP . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-253
7.11.3 BCDDA, BCDDAP, DBCDDA, DBCDDAP . . . . . . . . . . . . . . . . . . . . . . . . 7-258
7.11.4 DABIN, DABINP, DDABIN, DDABINP . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-263
7.11.5 HABIN, HABINP, DHABIN, DHABINP . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-268
7.11.6 DABCD, DABCDP, DDABCD, DDABCDP . . . . . . . . . . . . . . . . . . . . . . . . 7-272
7.11.7 COMRD, COMRDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-276
7.11.8 LEN, LENP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-280
7.11.9 STR, STRP, DSTR, DSTRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-283
7.11.10 VAL, VALP, DVAL, DVALP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-290
7.11.11 ESTR, ESTRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-296
7.11.12 EVAL, EVALP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-306
7.11.13 ASC, ASCP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-312
7.11.14 HEX, HEXP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-315
7.11.15 RIGHT, RIGHTP, LEFT, LEFTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-319
7.11.16 MIDR, MIDRP, MIDW, MIDWP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-323
7.11.17 INSTR, INSTRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-329
7.11.18 STRINS, STRINSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-333
7.11.19 STRDEL, STRDELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-336
7.11.20 EMOD, EMODP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-339
7.11.21 EREXP, EREXPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-343
7.12 Special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-347
7.12.1 SIN, SINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-351
7.12.2 SIND, SINDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-354
7.12.3 COS, COSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-357
7.12.4 COSD, COSDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-360
7.12.5 TAN, TANP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-363
7.12.6 TAND, TANDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-366
7.12.7 ASIN, ASINP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-369
7.12.8 ASIND, ASINDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-372
7.12.9 ACOS, ACOSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-375
7.12.10 ACOSD, ACOSDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-378
7.12.11 ATAN, ATANP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-381
7.12.12 ATAND, ATANDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-384
7.12.13 RAD, RADP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-387
7.12.14 RADD, RADDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-390
7.12.15 DEG, DEGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-393
7.12.16 DEGD, DEGDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-396
7.12.17 POW, POWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-399
7.12.18 POWD, POWDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-402
7.12.19 SQR, SQRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-405
7.12.20 SQRD, SQRDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-408
7.12.21 EXP, EXPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-411

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7.12.22 EXPD, EXPDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-414

7.12.23 LOG, LOGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-417
7.12.24 LOGD, LOGDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-420
7.12.25 LOG10, LOG10P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-423
7.12.26 LOG10D, LOG10DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-426
7.12.27 RND, RNDP, SRND, SRNDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-429
7.12.28 BSQR, BSQRP, BDSQR, BDSQRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-431
7.12.29 BSIN, BSINP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-435
7.12.30 BCOS, BCOSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-438
7.12.31 BTAN, BTANP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-441
7.12.32 BASIN, BASINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-444
7.12.33 BACOS, BACOSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-447
7.12.34 BATAN, BATANP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-450
7.13 Data control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-453
7.13.1 LIMIT, LIMITP, DLIMIT, DLIMITP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-454
7.13.2 BAND, BANDP, DBAND, DBANDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-458
7.13.3 ZONE, ZONEP, DZONE, DZONEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-462
7.13.4 SCL, SCLP, DSCL, DSCLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-466
7.13.5 SCL2, SCL2P, DSCL2, DSCL2P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-471
7.14 File register switching instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-475
7.14.1 RSET, RSETP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-476
7.14.2 QDRSET, QDRSETP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-479
7.14.3 QCDSET, QCDSETP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-482
7.15 Clock instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-485
7.15.1 DATERD, DATERDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-487
7.15.2 DATEWR, DATEWRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-490
7.15.3 DATE+, DATE+P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-493
7.15.4 DATE-, DATE-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-498
7.15.5 SECOND, SECONDP, HOUR, HOURP . . . . . . . . . . . . . . . . . . . . . . . . . . 7-503
7.15.6 DT=, DT<>, DT>, DT<=, DT<, DT>= . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-509
7.15.7 TM=, TM<>, TM>, TM<=, TM<, TM>= . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-514
7.16 Expansion clock instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-519
7.16.1 S.DATERD, SP.DATERP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-520
7.16.2 S.DATE+, SP.DATE+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-524
7.16.3 S.DATE-, SP.DATE- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-528
7.17 Program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-532
7.17.1 PSTOP, PSTOPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-534
7.17.2 POFF, POFFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-536
7.17.3 PSCAN, PSCANP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-539
7.17.4 PLOW, PLOWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-541
7.17.5 PCHK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-543

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7.18 Other convenient instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-546

7.18.1 WDT, WDTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-547
7.18.2 DUTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-549
7.18.3 TIMCHK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-552
7.18.4 ZRRDB, ZRRDBP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-554
7.18.5 ZRWRB, ZRWRBP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-558
7.18.6 ADRSET, ADRSETP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-562
7.18.7 KEY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-564
7.18.8 ZPUSH, ZPUSHP, ZPOP, ZPOPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-570
7.18.9 UNIRD, UNIRDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-574
7.18.10 TYPERD, TYPERDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-580
7.18.11 TRACE, TRACER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-586
7.18.12 SP.FWRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-588
7.18.13 SP.FREAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-599
7.18.14 SP.DEVST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-612
7.18.15 S.DEVLD, SP.DEVLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-615
7.18.16 PLOADP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-617
7.18.17 PUNLOADP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-621
7.18.18 PSWAPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-624
7.18.19 RBMOV, RBMOVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-627
7.18.20 UMSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-634

8 Data Link Instructions

8.1 Categories of instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 Data refresh instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2.1 S.ZCOM, SP.ZCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.3 Reading and writing routing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.3.1 S.RTREAD, SP.RTREAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3.2 S.RTWRITE, SP.RTWRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

9 Multiple CPU Dedicated Instructions

9.1 Writing to the CPU shared memory of host CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.1.1 S.TO, SP.TO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.1.2 TO, TOP, DTO, DTOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.2 Read from CPU shared memory of another station . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.2.1 FROM, FROMP, DFRO, DFROP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

10 Multiple CPU Device Write/Read Instructions

10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 Multiple CPU high-speed transmission instructions . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.2.1 D.DDWR, DP.DDWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.2.2 D.DDRD, DP.DDRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

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11 Instructions for MELSEC System Q

11.1 Instruction for a redundant system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.1 SP.CONTSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

12 Instructions for Special Function Modules

12.1 Instructions for serial communication modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.1.1 BUFRCVS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.1.2 GETE, GETEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.1.3 PUTE, PUTEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.1.4 PRR, PRRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.2 Instructions for PROFIBUS/DP interface modules. . . . . . . . . . . . . . . . . . . . . . . . . 12-26
12.2.1 BBLKRD, BBLKRDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12.2.2 BBLKWR, BBLKWRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12.3 Instructions for ETHERNET interface modules . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
12.3.1 BUFRCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.3.2 BUFRCVS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
12.3.3 BUFSND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42
12.3.4 OPEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47
12.3.5 CLOSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56
12.3.6 ERRCLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61
12.3.7 ERRRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-67
12.3.8 UINI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-72
12.4 Instructions for MELSECNET/H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-78
12.4.1 PAIRSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-79
12.5 Instructions for CC-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-82
12.5.1 RLPASET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-83
12.5.2 RIRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-95
12.5.3 RIWT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-103
12.5.4 RIRCV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-111
12.5.5 RISEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-119
12.5.6 RITO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-126
12.5.7 RIFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-130

Programming MELSEC System Q and L series XVII

Contents

13 Error Codes
13.1 Error code list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.1 How to read the error code list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.2 Types of error codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.1.3 Clearing an error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2 Error code list (1000 to 1999). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3 Error code list (2000 to 2999). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.4 Error code list (3000 to 3999). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39
13.5 Error code list (4000 to 4999). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-57
13.6 Error code list (5000 to 5999). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-71
13.7 Error code list (6000 to 6999). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-73
13.8 Error code list (7000 to 10000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-81
13.9 Error codes returned to request source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-85

A Appendix A
A.1 Definition of the processing times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2 Processing times for MELSEC System Q CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2.1 Table of Processing Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.2.2 Instructions executable by the product with the first 5 digits
of the serial No. "04122" or higher (Basic model QCPU) . . . . . . . . . . . . . . A-22
A.2.3 Table of the time to be added (Basic model QCPU). . . . . . . . . . . . . . . . . . A-25
A.2.4 Instructions availabe from function version B
(High Performance model QCPU/Process CPU/Redundant CPU). . . . . . . A-26
A.2.5 Table of the time to be added
(High Performance model QCPU/Process CPU/Redundant CPU). . . . . . . A-27
A.2.6 Redundant system instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
A.3 Operation Processing Time of Universal Model QCPU . . . . . . . . . . . . . . . . . . . . . . A-28
A.3.1 Subset instruction processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-28
A.3.2 Processing time of instructions other than subset instruction . . . . . . . . . . . A-42
A.4 Operation Processing Time of LCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-79
A.4.1 Subset instruction processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-79
A.4.2 Processing time of instructions other than subset instruction . . . . . . . . . . . A-86
A.5 Comparison of the CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-102
A.5.1 Available devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-102
A.5.2 I/O control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-104
A.5.3 Data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-104
A.5.4 Timer comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-105
A.5.5 Comparison of counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-109
A.5.6 Comparison of display instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-110
A.5.7 QCPU, LCPU instructions whose designation format
has been changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-111
A.5.8 AnACPU and AnUCPU dedicated instructions . . . . . . . . . . . . . . . . . . . . . A-112

XVIII
 Contents

A.6 Table of special relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-113

A.6.1 Diagnostic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-114
A.6.2 System information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-117
A.6.3 System clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-122
A.6.4 Scan information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-124
A.6.5 I/O refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-124
A.6.6 Drive information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-125
A.6.7 Instruction related special relays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-128
A.6.8 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-131
A.6.9 Conversion from A series to System Q or L series . . . . . . . . . . . . . . . . . . A-132
A.6.10 Built-in Ethernet port and built-in Ethernet function . . . . . . . . . . . . . . . . . A-139
A.6.11 Process control instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-140
A.6.12 Redundant system (host system CPU information) . . . . . . . . . . . . . . . . . A-140
A.6.13 Redundant system (other system CPU information). . . . . . . . . . . . . . . . . A-144
A.6.14 Redundant system (tracking information) . . . . . . . . . . . . . . . . . . . . . . . . . A-145
A.6.15 Redundant power supply module information. . . . . . . . . . . . . . . . . . . . . . A-148
A.6.16 Built-in I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-149
A.6.17 Data logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-154
A.7 Table of special registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-156
A.7.1 Diagnostic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-157
A.7.2 System information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-170
A.7.3 System clocks/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-181
A.7.4 Scan information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-182
A.7.5 Memory cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-185
A.7.6 Instruction related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-194
A.7.7 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-198
A.7.8 Redundant CPU information (host system CPU information) . . . . . . . . . . A-198
A.7.9 Remote password count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-198
A.7.10 Conversion from A series to System Q or L series . . . . . . . . . . . . . . . . . . A-199
A.7.11 Built-in Ethernet port QCPU and built-in Ethernet function . . . . . . . . . . . . A-207
A.7.12 Fuse blown module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-210
A.7.13 I/O module verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-210
A.7.14 Process control instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-211
A.7.15 Redundant system (host system CPU information) . . . . . . . . . . . . . . . . . A-212
A.7.16 Redundant system (other system CPU information). . . . . . . . . . . . . . . . . A-214
A.7.17 Redundant system (tracking information) . . . . . . . . . . . . . . . . . . . . . . . . . A-217
A.7.18 Redundant power supply module information. . . . . . . . . . . . . . . . . . . . . . A-218
A.7.19 Built-in I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-219
A.7.20 Data logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-227

Programming MELSEC System Q and L series XIX

Contents

XX
Introduction Further manuals

1 Introduction
This manual describes the programming and processing of the sequence and application
instructions that are provided by the CPUs of the MELSEC System Q and L series.

1.1 Further manuals

Qn(H)/QnPH/QnPRHCPU User‘s Manual (Function Explanation, Program Fundamentals)
–Description of functions, methods, and devices for programming
QnUCPU User‘s Manual (Function Explanation, Program Fundamentals)
–Description of functions, methods, and devices for programming
QnUCPU User‘s Manual (Communication via Built-in Ethernet Port)
–Description of functions for the communication via built-in Ethernet port of CPU module
MELSEC-L CPU Module User‘s Manual (Function Explanation, Program Fundamentals)
–Description of functions, methods, and devices for programming
MELSEC-L CPU Module User‘s Manual (Communication via Built-in Ethernet Port)
–Description of functions for the communication via built-in Ethernet port of CPU module
MELSEC-L CPU Module User‘s Manual (Data Logging Function)
–Description of data logging functionality of CPU module
MELSEC-Q/L Programming Manual (Common Instructions)
–Description of how to use sequence instructions, basic instructions,
and application instructions
MELSEC-Q/L/QnA Programming Manual (SFC)
–Description of the instructions for sequential function charts (MELSAP3)
MELSEC-Q/L Programming Manual (MELSAP-L)
–Description of the instructions for sequential function charts (MELSAP-L)
MELSEC-Q/L Programming Manual (Structured Text)
–Description of programming methods using structured languages
MELSEC-Q/L/QnA Programming Manual (PID Control Instructions)
–Description of the PID control instructions
QnPH/QnPRHCPU Programming Manual (Process Control Instructions)
–Description of the dedicated instructions for performing process control

NOTE You can download all manuals as PDF from the MITSUBISHI ELECTRIC homepage (www.mit-
subishi-automation.com).

Programming MELSEC System Q and L series 1–1

CPU types Introduction

1.2 CPU types

The functions described in this manual can be transferred to all CPU types by the current ver-
sion of the GX Works2 provided that the according CPU supports the instructions.
The different PLC types with their specific CPU are listed below in detail:

PLC Type CPU Type CPU Module Model

Basic model Q00JCPU, Q00CPU, Q01CPU

High Performance Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU

model

Process model Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU

Redundant model Q12PRHCPU, Q25PRHCPU

MELSEC
System Q Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU,
Q03UDCPU, Q04UDHCPU, Q06UDHCPU,
Q10UDHCPU, Q13UDHCPU, Q20UDHCPU,
Q26UDHCPU,
Universal model
Q03UDECPU,
Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU,
Q13UDEHCPU, Q20UDEHCPU, Q26UDEHCPU,
Q50UDEHCPU, Q100UDEHCPU

L series L02CPU, L26CPU-BT

If, e.g. in tables, QCPU or LCPU is mentioned, all CPU types of the MELSEC System Q and L
series are included. Exceptions are marked separately.

1.3 Software
All the described instructions can be applied with the available software packages:
– GX Developer
– GX IEC Developer
– GX Works2
The program examples contained in this manual were created with the GX Works2.
Corresponding to the selected CPU only those instructions are available within the GX Works2
dialog box that can actually be processed by the CPU.

NOTE The programming tool GX IEC Developer does not support the CPU modules of the L series.

1–2
Introduction Finding an instruction

1.4 Finding an instruction

Advanced
If you are already familiar with the programming of instructions for the MELSEC System Q, look
up the instruction chapters 5 through 12. The header line contains the name of the instruction
as it is applied within GX Works2.

Beginners
If you are not really familiar with the handling of the instructions, proceed as follows:
● Read through chapter 3 regarding the differing representation of instructions within the
MELSEC and the IEC editor.
● Read through chapter 4 regarding the consistent layout and structure of each description
of instruction.
● Use
–- the tabular overview of instruction categories with brief descriptions in chapter 2
–- the index containing the entire instructions

NOTE All the instructions contained in this manual are also included within the online help of the
GX Works2 as detailed as here.

Programming MELSEC System Q and L series 1–3

PLC parameters Introduction

1.5 PLC parameters

Via parameters several functions, device ranges, etc. are set up. For the programming of the
functions described in this manual, the parameter settings can remain preset or customised to
the user´s needs. Refer to the according hardware manuals of the CPUs and programming
manuals for detailed descriptions of the PLC parameter settings.

Example: MELSEC System Q

1–4
Introduction PLC parameters

Example: L series

Programming MELSEC System Q and L series 1–5

Comparison between the software packages Introduction

1.6 Comparison between the software packages

The most important features of the GX IEC Developer, the GX Developer, and the GX Works2
are listed in the following table:

GX IEC Developer GX Developer GX Works2

Structured use Simple to use Simple and structured use
Programming in comply with — —
IEC (6)1131-3
Editors: Editors: Editors:
 Instruction List  Instruction List  Ladder Diagram
 Ladder Diagram  Ladder Diagram  Structured Text (ST)
 Structured Text (ST)  Sequential Function Chart  Sequential Function Chart
 Sequential Function Chart (SFC) (SFC)
(SFC)  Structured Ladder Diagram
 Function Block (FUB)
Functions and Function Function Blocks Functions and Function
Blocks (V 7.0 or later) Blocks
Program modifications in Program modifications in Program modifications in
online mode online mode online mode
Program change in online Program change in online
mode mode
Diagnostic functions for the Diagnostic functions for the Diagnostic functions for the
PLC PLC PLC
Diagnostic functions for Diagnostic functions for Diagnostic functions for
network systems network systems network systems

1–6
Instruction Tables Subdivision of instructions

2 Instruction Tables
2.1 Subdivision of instructions
The instructions are subdivided into the following categories:
● Sequence instructions
● Application instructions (Part 1 and Part 2)
● Data link instructions
● Multiple CPU dedicated instruction
● Multiple CPU high-speed transmission dedicated instructions
● Redundant system instruction
● Instructions for special function modules

The categories of instructions are described in detail in the following table:

Reference
Category of Instruction Description
Section
Input instructions Operation start, 5.1
series and parallel connection of contacts

Connection instructions Series and parallel block connection,

storage and processing of operation results,
inversion of operation results, 5.2
conversion of operation results into pulses,
setting of edge relays

Output instructions Bit devices, counter and timer contacts,

output, setting, and resetting of annunciators,
setting and resetting of devices, 5.3
Sequence leading edge and trailing edge output,
instructions
bit device output inversion, generating pulses
Shift instructions Shifting bit devices 5.4

Master control Setting and resetting single parts of a program 5.5

instructions

Termination End of a part of program, 5.6

instructions end of sequence and routine programs

Miscellaneous Sequence program stop, 5.7

instructions no operation

Comparison operation Compares data to data (e.g. =, >, ≥) 6.1

instructions

Arithmetic operation Adds, subtracts, multiplies, divides, increments, and

instructions decrements BIN and BCD data, floating point data, and 6.2
BIN block data, links character strings

Data convsersion Converts data types, e.g. 6.3

instruction BCD → BIN, BIN → BCD

Data transfer Transmits designated data 6.4

instructions
Application
instructions
Part 1 Program branch Program jump commands 6.5
instructions

Program execution Enables and disables program interrupts 6.6

control instructions

Refresh instructions Refreshes bit devices, links, and I/O interfaces 6.7

Other convenient Count 1- or 2-phase input up or down,

instructions teaching timer, special function timer,
rotary table near path rotation control, ramp signal, 6.8
pulse density measurement, fixed cycle pulse output,
pulse width modulation, matrix input

Programming MELSEC System Q and L series 2–1

Subdivision of instructions Instruction Tables

Reference
Category of Instruction Description Section

Logical operation Logical AND / OR, logical exclusive OR / exclusive NOR 7.1
instructions

Rotation instructions 16-bit and 32-bit data right / left rotation 7.2

Shift instructions Shift data by bit or word 7.3

Bit processing Set, reset, and test bits 7.4

instructions

Data processing Search, encode, and decode data at specified devices 7.5
instructions Disunite and unite data
Structured program Repeated operation, subroutine program calls,
instructions subroutine calls between program files, switching
between main and subprogram parts, micro computer 7.6
program calls, index qualification of entire ladders, store
index qualification values in data tables

Data table operation Write to and read data from a data table, delete and 7.7
instructions insert data blocks in a data table

Buffer memory access Buffer memory access of special function modules or 7.8
instructions remote modules
Display instructions Output ASCII characters to the outputs of a module or to 7.9
an LED display

Debugging and failure Failure checks, setting and resetting status latch, 7.10
diagnosis instructions sampling trace, program trace
Application Character string Character string (ASCII code) processing
instructions 7.11
Part 2 processing instructions

Special function Trigonometrical functions, square root and exponential 7.12

instructions calculation with BCD data and floating point data
Data control Upper and lower limit control and storage of checked 7.13
instructions data

File register switching Switching between file register blocks and files 7.14
instructions
Clock instructions Reading/writing of the values of year, month, day, hour,
minute, second, and day of the week; addition/
subtraction of the values of hour, minute, and second;
conversion of the values of hour, minute, and second 7.15
into second; comparison between the values of year,
month, and day; and comparison between the values of
hour, minute, and second.

Expansion clock Reading of the values of year, month, day, hour, minute,
instructions second, millisecond, and day of the week; addition/ 7.16
subtraction of the values of hour, minute, second, and
millisecond

Program instructions Select different program execution modes 7.17

Other instructions Reset watchdog timer (WDT), pulse generation, direct

read from indirect access file registers, numerical key
input from keyboard, batch save or recovery of index 7.18
registers, reading module information/model name, trace
set/trace reset, writing to and reading from files/standard
ROM, program instructions, data transfer, user message

2–2
Instruction Tables Subdivision of instructions

Reference
Category of Instruction Description Section

Network refresh Instructions for data refresh operations in network 8.2

instructions modules.
Data link
instructions Read/write routing Read and write routing parameters (network number and
information station number of relay station, station number of routing 8.3
station).
Data exchange instructions in a multi- Writing to the CPU shared memory 9.1
CPU system Reading from the CPU shared memory of another CPU 9.2

Multiple CPU high-speed transmission Writes/reads devices to/from another CPU. chapter 10
dedicated instructions

Instruction for a redundant system System switching (Active system/standby system) chapter 11

Instructions for special function modules Instructions for serial communication modules,
PROFIBUS/DP interface modules, ETHERNET interface chapter 12
modules, MELSECNET/H and CC-Link

Programming MELSEC System Q and L series 2–3

Overview of instructions Instruction Tables

2.2 Overview of instructions

2.2.1 Description of the overview tables

The following sections 2.3 through 2.6 include an overview of all instructions described in this
manual.
In the following the layout of the overview table is described in detail:

of steps
Number
Execution Reference

Subset
Category Instruction Variables Meaning
Condition Section

+
s, d (d)+(s) → (d) 3  6.2.1
Addition and +P
subtraction
of 16-bit
binary data +
s1, s2, d1 (s1)+(s2) → (d1) 4  6.2.1
+P

(1) (2) (3) (4) (5) (6) (7) (8)

Explanation of the different columns:

(1) Category of instruction
(2) Specification of instruction name ("command") for the programming
The instruction names are represented in MELSEC notation (refer to section 3.2 "Notation
of instructions" for explanation of the notation).
In general, 16-bit instructions are represented. All 32-bit instructions are indicated by a
leading "D".
Example: 16-bit instruction: +
32-bit instruction: D+

Pulse instructions, i.e. instructions that are only executed at leading edge of a signal are
indicated by an appended "P".
Example: Execution when ON: +
Execution at leading edge: +P

1)

2) 2)
1
Execution condition of instruction
P 2 One program scan
3 One execution
3) 3)

2–4
Instruction Tables Overview of instructions

Instructions processing character strings are indicated by a leading "$"

Example: Standard instructions: +
Character string instruction: $+P

(3) Specification of variables

Here, the variables to be used are specified. The data source is represented by an "s", the
data destination is represented by a "d".
Example:
s = if there is only one data source
s1, s2 = if there are several data sources
s+0, s+1, (s1)+0, (s1)+1 = for 32-bit instructions
e.g. s1 = data register D0, (s1)+1 = data register D1
s+0, s+1, s+2, s+3 = 4 successive devices, e.g. for an array

(4) Meaning and processing of the entire control instruction

(d+1,d) + (s+1, s) (d+1, d)

2) 2)
(d) + (s)

1)
(d)

d+1
{ 4)
3)

d
5)
1 Indicates

2
16 bits
16 bits

3 Indicates 32 bits

4 upper 16 bits

5
lower 16 bits

(5) Indication of the execution condition according to the following table

Symbol Execution condition

The instruction is executed continuously and independent from the prior execution
no indication
condition. If the precondition is not set, the instruction is not executed.

The instruction is executed as long as the precondition is ON. If the precondition is OFF,
the instruction is not executed and no processing is conducted.

This instruction is a pulsed instruction. It is only executed once and at leading edge of
the input signal (when the precondition alters from OFF to ON). Afterwards, the
instruction will not be executed any longer even if the input signal is still ON.

Executed during OFF; instruction is executed only while the precondition is OFF. If the
precondition is ON, the instruction is not executed, and no processing is conducted.

This instruction is a pulsed instruction as well. It is only executed once and at trailing
edge of the input signal (when the precondition alters from ON to OFF). Afterwards, the
instruction will not be executed any longer even if the input signal is still OFF.

(6) Indication of the number of program steps

Indicated is the number of steps that is required for the entire execution of the instruction.
Refer to section 3.11 for details.

(7) The  mark indicates instructions for which subset processing is possible.
Refer to section 3.8.1 for details on subset processing.

(8) Indication of the reference section

Indicates the chapter and section of this manual where the instruction is described in detail.

Programming MELSEC System Q and L series 2–5

Sequence instructions Instruction Tables

2.3 Sequence instructions

2.3.1 Input instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

Operation start
LD (Load (normally open
contact))
s
Operation start
LDI (Load (normally closed
contact))
Series connection 
AND (of NO contacts)  5.1.1
s
ANI Series connection
(of NC contacts)
Parallel connection
OR
(of NO contacts)
s
Input Parallel connection
ORI (of NC contacts)
instruction
LDP Pulse operation start
(leading edge)
s
LDF Pulse operation start
(trailing edge)
Pulse series connection
ANDP s
(leading edge) 
 5.1.2
Pulse series connection
ANDF s (trailing edge)

ORP s Pulse parallel connection

(leading edge)
Pulse parallel connection
ORF s
(trailing edge)
Starts leading edge pulse 3
LDPI s NOT operation

LDFI s Starts trailing edge pulse 3

NOT operation

ANDPI s
Leading edge pulse NOT 4
Input series connection
 5.1.3
instruction
ANDFI s
Trailing edge pulse NOT 4
series connection

ORPI s Leading edge pulse NOT 4

parallel connection

ORFI s
Trailing edge pulse NOT 4
parallel connection
 The number of program steps depends on the devices used.
 For the use of internal devices or file registers (R0 through R32767) :1
 For the use of a direct access input (DX) :2
 For the use of other devices :3

The number of program steps depends on the devices and types of CPU modules used.
 For the use of internal devices or file registers (R0 through R32767) :1
 For the use of a direct access input (DX) :1
 For the use of other devices :3
The number of program steps depends on the devices used.
 For the use of internal devices or file registers (R0 through R32767) : Number of basic steps
 Serial number access format file register (ZR), Extended data register (D),
Extended link register (W), Multiple CPU shared device (U3En\G10000) : Number of basic steps + 1
 For the use of a direct access input (DX) : Number of basic steps + 1
 For the use of other devices : Number of basic steps + 2

2–6
Instruction Tables Sequence instructions

2.3.2 Connection instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

Block series connection

ANB (Ladder block series
connection)
— 1 5.2.1
Block parallel connection
ORB (Ladder block parallel
connection)

Operation result processing

MPS (Store operation result
(memory push))

Operation result processing

MRD — (Read operation result 1 5.2.2
(memory read))
Operation result processing
MPP (Read and clear operation
result (memory pop))

Connection INV — Operation result inversion 1 5.2.3

instruction (Inversion instruction)

Operation result into pulse

conversion
MEP
(Pulse generation at leading
edge of operation result)
— 1 5.2.4
Operation result into pulse
conversion
MEF (Pulse generation at trailing
edge of operation result)

Setting of edge relays

EGP (Setting an edge relay with 1
leading edge of an operation
result)
d 5.2.5
Setting of edge relays
(Setting an edge relay with 
EGF
trailing edge of an operation
result)
 The number of program steps depends on the devices and types of CPU modules used.
 High Performance model QCPU, Process CPU, Redundant CPU, Universal model QCPU, LCPU :1
 Basic Model QCPU :2

Programming MELSEC System Q and L series 2–7

Sequence instructions Instruction Tables

2.3.3 Output instruction

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

Setting instructions for 

OUT d 5.3.1
outputs
OUT T
d Timers 4 5.3.2
OUTH T
OUT C d Counter 4 5.3.3
OUT F d Annunciator output 4 5.3.4


SET d Setting of devices 5.3.5
( )


RST d Resetting devices 5.3.6
( )
SET F
Output Setting and resetting the
instruction d 2 5.3.7
annunciators
RST F

PLS Output at leading edge

d 2 5.3.8
PLF Output at trailing edge

Inversion of bit output 2 5.3.9

FF s device

DELTA
Generating pulses at 2 5.3.10
d direct access outputs
DELTAP

The number of program steps depends on the devices and types of CPU modules used.
 When using internal device or file register (R): 1
 When using direct access outputs DY: 2
 When using serial number access format file register:
(Universal model QCPU and LCPU): 2
(Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU): 3
 Devices other than above: 3

This execution condition is only applied, if the annunciator (F) is used.

The number of program steps depends on the devices and types of CPU modules used.
 When using internal device or file register (R0 to R32767): 1
 When using direct access outputs DY or SFC program device (BL): 2
 When using serial number access format file register:
(Universal model QCPU and LCPU): 2
(Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU): 3
 Devices other than above: 3

The number of program steps depends on the devices and types of CPU modules used.
- For bit processing
 internal device (bit to be specified by bit device or word device): 1
 Direct access output: 2
 Timer, counter: 4
- For word processing
 internal device: 2
 Index register: 2
- For bit/word processing
 When using serial number access format file register:
(Universal model QCPU and LCPU): 2
(Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU): 3
 Devices other than above: 3

2–8
Instruction Tables Sequence instructions

2.3.4 Shift instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

SFT
Shift instruction d Shifting bit devices 2 5.4.1
SFTP

2.3.5 Master control instructions

of steps
Number

Subset
Category Instruction Variables Meaning Execution Reference
Condition Section

Activating indicated 2
MC n, d
Master control program parts
5.5.1
instruction Deactivating indicated
MCR n 1
program parts

2.3.6 Program termination instructions

of steps
Number

Subset
Category Instruction Variables Meaning Execution Reference
Condition Section

FEND End of program branches 5.6.1

Termination — 1
instruction End of sequence 5.6.2
END program

2.3.7 Miscellaneous instructions

of steps
Number

Subset

Execution Reference
Category Instruction Variables Meaning
Condition Section

Stop STOP — Stop instruction 1 5.7.1

NOP — No operation program

step

Ignored
NOPLF — (To change pages during
Other printouts) 1 5.7.2
instructions
Ignored
(Subsequent programs
PAGE n
will be controlled from
step 0 of page n)

Programming MELSEC System Q and L series 2–9

Application instructions, Part 1 Instruction Tables

2.4 Application instructions, Part 1

2.4.1 Comparison operation instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

LD=

AND= s1, s2 Sets the output, if 3 

s1 = s2
OR=

LD<>
AND<> s1, s2 Sets the output, if 3 
s1 ≠ s2
OR<>

LD>

AND> s1, s2 Sets the output, if 3 

s1 > s2
OR>
BIN 16-bit data 6.1.1
comparison
LD<=
Sets the output, if 3 
AND<= s1, s2 s1 <= s2
OR<=

LD<
Sets the output, if 3 
AND< s1, s2 s1 < s2
OR<

LD>=
Sets the output, if 3 
AND>= s1, s2 s1 >= s2
OR>=

LDD=
Sets the output, if 
ANDD= s1, s2 
s1 = s2
ORD=

LDD<>
Sets the output, if 
ANDD<> s1, s2 
s1 ≠ s2
ORD<>

LDD>
Sets the output, if 
ANDD> s1, s2 
s1 > s2
ORD>
BIN 32-bit data 6.1.2
comparison
LDD<=
Sets the output, if 
ANDD<= s1, s2 
s1 <= s2
ORD<=

LDD<
Sets the output, if 
ANDD< s1, s2 
s1 < s2
ORD<

LDD>=
Sets the output, if 
ANDD>= s1, s2 
s1 >= s2
ORD>=

2 – 10
Instruction Tables Application instructions, Part 1

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

LDE=
Sets the output, if 3
ANDE= s1, s2 s1 = s2
ORE=

LDE<>
Sets the output, if 3
ANDE<> s1, s2 s1 ≠ s2
ORE<>

LDE>
Sets the output, if 3
ANDE> s1, s2 s1 > s2
Floating point
data ORE>
comparison 6.1.3
(Single LDE<=
precision)
Sets the output, if 3
ANDE<= s1, s2 s1 <= s2
ORE<=

LDE<
Sets the output, if 3
ANDE< s1, s2 s1 < s2
ORE<

LDE>=
Sets the output, if 3
ANDE>= s1, s2
s1 >= s2
ORE>=

LDED=
Sets the output, if
(s1 + 3, s1 + 2, s1 + 1, s1) 3
ANDED= s1, s2
=
(s2 + 3, s2 + 2, s2 + 1, s2)
ORED=
LDED<>
Sets the output, if
(s1 + 3, s1 + 2, s1 + 1, s1) 3
ANDED<> s1, s2
≠
(s2 + 3, s2 + 2, s2 + 1, s2)
ORED<>
LDED>
Sets the output, if
(s1 + 3, s1 + 2, s1 + 1, s1) 3
ANDED> s1, s2
Floating point >
(s2 + 3, s2 + 2, s2 + 1, s2)
data ORED>
comparison 6.1.4
(Double LDED<=
Sets the output, if
precision) (s1 + 3, s1 + 2, s1 + 1, s1)
ANDED<= s1, s2 3
<=
(s2 + 3, s2 + 2, s2 + 1, s2)
ORED<=
LDED<
Sets the output, if
(s1 + 3, s1 + 2, s1 + 1, s1) 3
ANDED< s1, s2
<
(s2 + 3, s2 + 2, s2 + 1, s2)
ORED<

LDED>=
Sets the output, if
(s1 + 3, s1 + 2, s1 + 1, s1) 3
ANDED>= s1, s2
>=
(s2 + 3, s2 + 2, s2 + 1, s2)
ORED>=

Programming MELSEC System Q and L series 2 – 11

Application instructions, Part 1 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

LD$= Compares the character

strings in s1 and s2
AND$= s1, s2 character by character.  3
Sets the output, if
OR$= s1 = s2

LD$<> Compares the character

strings in s1 and s2
AND$<> s1, s2 character by character.  3
Sets the output, if
OR$<> s1 ≠ s2

LD$> Compares the character

strings in s1 and s2
AND$> s1, s2 character by character.  3
Sets the output, if
Character OR$> s1 > s2
string data 6.1.5
comparison LD$<= Compares the character
strings in s1 and s2
AND$<= s1, s2 character by character.  3
Sets the output, if
OR$<= s1 <= s2

LD$ < Compares the character

strings in s1 and s2
AND$< s1, s2 character by character.  3
Sets the output, if
OR$< s1 < s2
LD$>= Compares the character
strings in s1 and s2
AND$>= s1, s2 character by character.  3
Sets the output, if
OR$>= s1 >= s2

BKCMP= s1, s2, n, d1

BKCMP<> s1, s2, n, d1

BKCMP> s1, s2, n, d1

BKCMP<= s1, s2, n, d1

It compares the nth BIN
BKCMP< s1, s2, n, d1 16-bit block in s1 to the
nth BIN 16-bit block in s2,
BIN 16-bit BKCMP>= s1, s2, n, d1 beginning with the first
block data 5 6.1.6
number of device.
comparison BKCMP=P s1, s2, n, d1
The result of each block
BKCMP<>P s1, s2, n, d1 comparison is stored from
d1 onwards.
BKCMP>P s1, s2, n, d1

BKCMP<=P s1, s2, n, d1

BKCMP<P s1, s2, n, d1

BKCMP>=P s1, s2, n, d1

2 – 12
Instruction Tables Application instructions, Part 1

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

DBKCMP= s1, s2, n, d1

DBKCMP<> s1, s2, n, d1

DBKCMP> s1, s2, n, d1
This instruction compares
DBKCMP<= s1, s2, n, d1
BIN 32-bit data stored in
n-point devices starting
DBKCMP< s1, s2, n, d1 from the device specified
BIN 32-bit DBKCMP>= s1, s2, n, d1 by S1 with BIN 32-bit
data stored in n-point 6.1.7
block data devices starting from the 5
comparisons DBKCMP=P s1, s2, n, d1
device specified by a
constant and S2, and
DBKCMP<>P s1, s2, n, d1 then stores the result into
DBKCMP>P s1, s2, n, d1 the nth device specified
by (D) and up.
DBKCMP<=P s1, s2, n, d1

DBKCMP<P s1, s2, n, d1

DBKCMP>=P s1, s2, n, d1

The number of program steps depends on the devices used and the type of CPU.
 High Performance model QCPU, Process CPU, Redundant CPU
– Word device: internal word devices (except for file register ZR) : 5 (NOTE 1)
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification : 5 (NOTE 1)
– Constant; No limitations : 5 (NOTE 1)
Devices other than the above : 3 (NOTE 2)
 Basic model QCPU, Universal model QCPU, LCPU
– All devices that can be used : 3 (NOTE 2)
NOTE 1: For these models the number of steps increases but processing speed becomes faster.
NOTE 2: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

Conditions under which the character string comparison is processed:
 Match : All characters in the string must match.
 Larger string : If the character strings differ, the larger string is determined.
 Smaller string : If the character strings differ, the smaller string is determined.

Programming MELSEC System Q and L series 2 – 13

Application instructions, Part 1 Instruction Tables

2.4.2 Arithmetic operation instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

+
s, d (d)+(s) → (d) 3 

+P

+
s1, s2, d1 (s1)+(s2) → (d1) 4 

BIN 16-bit +P
addition and 6.2.1
subtraction
operations -
s, d (d)-(s) → (d) 3 

-P

-
s1, s2, d1 (s1)-(s2) → (d1) 4 

-P

D+
(d+1, d)+(s+1, s)  
s, d
→ (d+1, d)
D+P

D+
((s1)+1, s1)+((s2) +1, s2)  
s1, s2, d1
→ ((d1)+1, d1)
BIN 32-bit D+P
addition and 6.2.2
subtraction
operations D-
(d+1, d)-(s+1, s)  
s, d → (d+1, d)
D-P

D-
((s1)+1, s1)-((s2)+1, s2)  
s1, s2, d1
→ ((d1)+1, d1)
D-P

x

s1, s2, d1 (s1)x(s2) → ((d1)+1, d1) 

xP
BIN 16-bit
multiplication 6.2.3
and division
/
(s1)/(s2) →
s1, s2, d1 Quotient (d1), 4 
remainder ((d1)+1)
/P

2 – 14
Instruction Tables Application instructions, Part 1

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

Dx ((s1)+1, s1)x((s2)+1, s2)

s1, s2, d1 → 4 
((d1)+3, (d1)+2,
DxP (d1)+1, d1)
BIN 32-bit
multiplication 6.2.4
and division
D/ ((s1)+1, s1)/((s2)+1, s2)
→
s1, s2, d1 Quotient ((d1)+1, d1), 4 
remainder ((d1)+3,
D/P (d1)+2)

B+
s, d (d)+(s) → (d) 3 

B+P

B+
s1, s2, d1 (s1)+(s2) → (d1) 4

BCD 4-digit B+P

addition and 6.2.5
substraction
operations B-
s, d (d)-(s) → (d) 3 

B-P

B-
s1, s2, d1 (s1)-(s2) → (d1) 4
B-P

DB+
(d+1, d)+(s+1, s)
s, d → 3
(d+1, d)
DB+P

DB+
((s1)+1, s1)+((s2)+1, s2)
s1, s2, d1 → 4
((d1)+1, d1)
BCD 8-digit DB+P
addition and 6.2.6
subtraction
operations DB-
(d+1, d)+(s+1, s)
s, d → 3
(d+1, d)
DB-P

DB-
((s1)+1, s1)+((s2)+1, s2)
s1, s2, d1 → 4
((d1)+1, d1)
DB-P

Programming MELSEC System Q and L series 2 – 15

Application instructions, Part 1 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

B×
s1, s2, d1 (s1)x(s2) → ((d1)+1, d1) 4 

BCD 4-digit B×P

multiplication 6.2.7
and division
operations B/ (s1)/(s2)
→ 4 
s1, s2, d1 Quotient (d1),
B/P remainder ((d1)+1)

DB× ((s1)+1, s1)x((s2)+1, s2)

→ 4
s1, s2, d1
((d1)+3, (d1)+2,
DB×P (d1)+1, d1)
BCD 8-digit
multiplication 6.2.8
and division
operations DB/ ((s1)+1, s1)/((s2)+1, s2)
→
s1, s2, d1 Quotient ((d1)+1, d1), 4 
remainder ((d1)+3,
DB/P (d1)+2)

E+
(d+1, d)+(s+1, s)
s, d → 3 
(d+1, d)
E+P

E+
((s1)+1, s1)+((s2)+1, s2)
s1, s2, d1 → 4 
Floating point
data addition ((d1)+1, d1)
E+P
and
subtraction 6.2.9
operations
(Single E-
(d+1, d)-(s+1, s)
precision) s, d → 3 
(d+1, d)
E-P

E-
((s1)+1, s1)-((s2)+1, s2)
s1, s2, d1 → 4 
((d1)+1, d1)
E-P

2 – 16
Instruction Tables Application instructions, Part 1

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

ED+
(d+3, d+2, d+1, d)
s, d +(s+3, s+2, s+1, s) → 3 
(d+3, d+2, d+1, d)
ED+P

((s1)+3, (s1)+2, (s1)+1,

ED+ s1)
+((s2)+3, (s2)+2, (s2)+1, 4 
Floating point s1, s2, d1 s2) →
data addition ED+P ((d1)+3, (d1)+2, (d1)+1,
and d1)
subtraction 6.2.10
operations
(Double ED- (d+3, d+2, d+1, d)
precision) – (s+3, s+2, s+1, s) 3 
s, d
→
ED-P (d+3, d+2, d+1, d)

((s1)+3, (s1)+2, (s1)+1,

ED- s1)
s1, s2, d1 – ((s2)+3, (s2)+2, (s2)+1, 4 
s2) →
ED-P ((d1)+3, (d1)+2, (d1)+1,
d1)

Ex
((s1)+1, s1)x((s2)+1, s2)
s1, s2, d1 → 3 
Floating point ((d1)+1, d1)
data ExP
multiplication
and division 6.2.11
operations
(Single E/
((s1)+1, s1)/((s2)+1, s2)

precision) s1, s2, d1 → 4
Quotient ((d1)+1, d1)
E/P

((s1)+3, (s1)+2, (s1)+1,

EDx s1) x ((s2)+3, (s2)+2,

(s2)+1, s2) 4
Floating point s1, s2, d1 →
data EDxP ((d1)+3, (d1)+2, (d1)+1,
multiplication d1)
and division 6.2.12
operations ((s1)+3, (s1)+2, (s1)+1,
(Double ED/ s1)/((s2)+3, (s2)+2,

precision) (s2)+1, s2) 4
s1, s2, d1
→
ED/P Quotient ((d1)+3,
(d1)+2,(d1)+1, d1)

BK+
Adds the nth 16-bit block
s1, s2, d, n in s1 to the nth 16-bit 5
block in s2.
BIN block BK+P
addition and 6.2.13
subtraction
operations BK-
Subtracts the nth 16-bit
s1, s2, d, n block in s2 from the nth 5
16-bit block in s1.
BK-P

Programming MELSEC System Q and L series 2 – 17

Application instructions, Part 1 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

DBK+
Adds the nth 32-bit block
s1, s2, d, n in s1 to the nth 32-bit 5
BIN 32-bit block in s2.
DBK+P
block addition
and 6.2.14
subtraction
operations DBK-
Subtracts the nth 32-bit
s1, s2, d, n block in s2 from the nth 5
32-bit block in s1.
DBK-P

$+ Character string data in s

is appended to character
s, d data in d. 3
The linked character
$+P string is stored in d.
Character
string linking 6.2.15
operations
$+ Character string data in s
is appended to character
s1, s2, d1 data in d. 4
The linked character
$+P string is stored in d.

INC
d (d)+1→ (d) 2  6.2.16
INCP
BIN increment
operations
DINC

d (d+1, d)+1 → (d+1, d)  6.2.17
DINCP

DEC
d (d)-1→ (d) 2  6.2.16
DECP
BIN
decrement
operations
DDEC

d (d+1, d)-1 → (d+1, d)  6.2.17
DDECP

2 – 18
Instruction Tables Application instructions, Part 1

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section


The number of program steps depends on the devices used and the type of CPU.
 High Performance model QCPU, Process CPU, Redundant CPU
– Word device: internal word devices (except for file register ZR) : 5 (NOTE 1)
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification : 5 (NOTE 1)
– Constant; No limitations : 5 (NOTE 1)
Devices other than the above : 3 (NOTE 2)
 Basic model QCPU, Universal model QCPU, LCPU
– All devices that can be used : 3 (NOTE 2)
NOTE 1: For these models the number of steps increases but processing speed becomes faster.
NOTE 2: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

The number of program steps depends on the devices used and the type of CPU.
 High Performance model QCPU, Process CPU, Redundant CPU
– Word device: internal word devices (except for file register ZR) : 6 (NOTE 1)
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification : 6 (NOTE 1)
– Constant; No limitations : 6 (NOTE 1)
Devices other than the above : 4 (NOTE 2)
 Basic model QCPU
– All devices that can be used : 4 (NOTE 2)
 Universal model QCPU, LCPU
– All devices that can be used : 3 (NOTE 2)
NOTE 1: For these models the number of steps increases but processing speed becomes faster.
NOTE 2: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

The number of program steps depends on the devices used and the type of CPU.
 QCPU, LCPU
– Word device: internal word devices (except for file register ZR) :3
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification :3
– Constant; No limitations :3
Devices other than the above : 4 (NOTE 1)
NOTE 1: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

The number of steps is three for the Universal model QCPU and LCPU only.

The subset is effective only with Universal model QCPU and LCPU.

The number of program steps depends on the devices used and the type of CPU.
 High Performance model QCPU, Process CPU, Redundant CPU
– Word device: internal word devices (except for file register ZR) : 3 (NOTE 1)
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification : 3 (NOTE 1)
– Constant; No limitations : 3 (NOTE 1)
Devices other than the above : 2 (NOTE 2)
 Basic model QCPU, Universal model QCPU, LCPU
– All devices that can be used : 2 (NOTE 2)
NOTE 1: For these models the number of steps increases but processing speed becomes faster.
NOTE 2: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

Programming MELSEC System Q and L series 2 – 19

Application instructions, Part 1 Instruction Tables

2.4.3 Data conversion instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

BCD
BCD conversion
s, d (s) (d) 3 

BCDP BIN (0 to 9999)

Conversion
from BIN data 6.3.1
into BCD data
DBCD BCD conversion
s, d (s+1, s) (d+1, d) 3 

DBCDP BIN (0 to 99999999)

BIN
BIN conversion
s, d (s) (d) 3 

BINP BCD (0 to 9999)

Conversion
from BCD data 6.3.2
into BIN data
DBIN BIN conversion
s, d (s+1, s) (d+1, d) 3 

DBINP BCD (0 to 99999999)

FLT Floating point

conversion
s, d (s+1, s) (d) 3 
Conversion Binary value
from BIN data FLTP (-32768 to 32767)
into floating 6.3.3
point data
(Single DFLT Floating point
precision) conversion
s, d (s+1, s) (d+1, d) 3 

DFLTP Binary value

(-2147483648 to 2147483647)

FLTD Floating point conversion

s, d (s) (d+3, d+2, d+1, d) 4 
Conversion
FLTPD Binary value
from BIN data (-32768 to 32767)
into floating 6.3.4
point data
(Double Floating point
DFLTD conversion
precision)

(s+1, s) (d+3, d+2, d+1, d)
s, d 4
Binary value
DFLTPD (-2147483648 to 2147483647)

INT BIN conversion

s, d (s+1, s) (d) 3 
Conversion Floating point value
from floating INTP (-32768 to 32767)
point data into 6.3.5
BIN data
(Single DINT
precision)
s, d 3 

DINTP

2 – 20
Instruction Tables Application instructions, Part 1

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

INTD
Conversion to BIN
s, d (s+3, s+2, s+1, s) (d ) 3 
Conversion Real number ( 32768 to
from floating INTPD 32767)
point data into 6.3.6
BIN data
(Double DINTD Conversion
precision) to BIN
s, d (s+3, s+2, s+1, s) (d+1,d) 3 
Real number
DINTPD (–2147483648 to 2147483647)

Conversion DBL
from BIN 16- Conversion
bit data into s, d (s) (d+1, d) 3 6.3.7
BIN 32-bit
data DBLP BIN (-32768 to 32767)

Conversion WORD
from BIN 32- Conversion
bit data into s, d (s+1, s) (d) 3 6.3.8
BIN 16-bit
WORDP BIN (-32768 to 32767)
data

GRY Conversion
into Gray code
s, d (s) (d) 3
Binary value
Conversion GRYP (-32768 to 32767)
from BIN 16-/
32-bit data into 6.3.9
Gray code
data DGRY Conversion
into Gray code
s, d (s+1, s) (d+1, d) 3
Binary value
DGRYP (-2147483648 to 214748364 7)

GBIN BIN conversion

s, d (s) (d) 3
Gray code
Conversion GBINP (-32768 to 32767)
from Gray
code data into 6.3.10
BIN 16-/32-bit
data DGBIN BIN conversion
s, d (s+1, s) (d+1, d) 3
Gray code
DGBIN (-2147483648 to 214748364 7)

NEG
(d) (d)
d 2
Sign reversal BIN data
NEGP
for BIN
16-/32-bit data 6.3.11
(complement
of 2) DNEG
(d+1, d) (d+1, d)
d 2
BIN data
DNEGP

Programming MELSEC System Q and L series 2 – 21

Application instructions, Part 1 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

ENEG
(d+1, d) (d+1, d)
d 2 6.3.12
Floating point value
ENEGP
Sign reversal
for floating
point data
EDNEG Floating point number

d (d+3, d+2, d+1, d) 3 6.3.13

→
EDNEGP (d+3, d+2, d+1, d)

Conversion BKBCD s, d, n This instruction converts

each nth BIN 16-bit block
from BIN block in s into the nth BCD 4- 4 6.3.14
data into BCD
block data digit block. Converted
BKBCDP s, d, n data is stored in d.

This instruction converts

Conversion BKBIN s, d, n each nth BCD 4-digit
from BCD block in s into the nth 4 6.3.15
block data into BIN 16-bit block.
BIN block data BKBINP s, d, n Converted data is stored
in d.

Floating-point 32-bit floating-point real

Conversion ECON s, d number
from single (s+1, s)
precision to → 3 6.3.16
double Conversion to double
precision ECONP s, d precision
(d+3, d+2, d+1, d)

Floating-point 64-bit floating-point real

Conversion EDCON s, d number
from double (s+3, s+2, s+1, s)
precision to → 3 6.3.17
single precision Conversion to single
EDCONP s, d precision
(d+1, d)

The number of steps is two for the Universal model QCPU and LCPU only.

The subset is effective only with Universal model QCPU and LCPU.

2 – 22
Instruction Tables Application instructions, Part 1

2.4.4 Data transfer instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

MOV s, d
BIN 16-bit data  
transfer (s) (d)
MOVP s, d
6.4.1
DMOV s, d
BIN 32-bit data  
transfer (s+1, s) (d+1, d)
DMOVP s, d

Floating point EMOV s, d

(s+1, s) (d+1, d)


data transfer 6.4.2
(Single
precision) EMOVP s, d Floating point value

Floating point EDMOV s, d Real number data

data transfer (s+3, s+2, s+1, s) 2  6.4.3
(Double →
precision) EDMOVP s, d (d+3, d+2, d+1, d)

$MOV s, d
Character
Transfers character string 3  6.4.4
string data data in s to d.
transfer
$MOVP s, d

CML s, d
BIN 16-bit data  
inversion (s) (d)
CMLP s, d
6.4.5
DCML s, d
BIN 32-bit data  
inversion (s+1, s) (d1+1, d1)
DCMLP s, d

BMOV s, n, d (s) (d)

BIN block data 4  6.4.6
transfer n
BMOVP s, n, d

FMOV s, n, d
Identical BIN (d)
block data (s) 4  6.4.7
transfer n
FMOVP s, n, d

DFMOV s, n, d
Identical 32-bit (d+1, d)
block data (s+1, s) 4  6.4.8
transfer n
DFMOVP s, n, d

Programming MELSEC System Q and L series 2 – 23

Application instructions, Part 1 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

XCH d1, d2
BIN 16-bit data 3 
exchange (d1) (d2)

XCHP d1, d2

6.4.9
DXCH d1, d2
BIN 32-bit data 3 
((d1)+1, d1) ((d2)+1, d2)
exchange
DXCHP d1, d2

BXCH n, d1, d2
(d1) (d2)
BIN block data 4 6.4.10
exchange n
BXCHP n, d1, d2

SWAP s
Upper and
lower byte 3 6.4.11
exchanges
SWAPP s


The number of program steps depends on the devices used and the type of CPU.
 QCPU, LCPU
– Word device: internal word devices (except for file register ZR) :2
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification :2
– Constant; No limitations :2
Devices other than the above : 3 (NOTE 1)
NOTE 1: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

The number of program steps depends on the devices used and the type of CPU.
 High Performance model QCPU, Process CPU, Redundant CPU
– Word device: internal word devices (except for file register ZR) :3
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification :3
– Constant; No limitations :3
Devices other than the above : 3 (NOTE 1)
 Basic model QCPU
– Word device: internal word devices (except for file register ZR) :2
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification :2
– Constant; No limitations :2
Devices other than the above : 3 (NOTE 1)
 Universal model QCPU, LCPU
– All devices that can be used : 2 (NOTE 1)
NOTE 1: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

2 – 24
Instruction Tables Application instructions, Part 1

2.4.5 Program branch instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

Conditional jump
CJ p
(p = jump destination)
2  6.5.1
Conditional jump from
SCJ p next program scan
Jump (p = jump destination)
instructions
Jump instruction 2  6.5.1
JMP p (p = jump destination)

Jump to the end of a 1 6.5.2

GOEND —
program

2.4.6 Interrupt program execution control instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

Interrupt DI — Disables the execution of 1

disabled an interrupt program

Interrupt EI — Enables invoking an 1

enabled interrupt program
6.6.1
Bit pattern of In the bit pattern
execution designated by s a
conditions of IMASK s particular interrupt 2
interrupt address is allocated to
programs each bit.

Return from an
interrupt End of an interrupt 1 6.6.2
program to the IRET — program
main program

2.4.7 Data refresh instructions

of steps
Number

Subset

Category Instruction Variables Meaning Execution Reference

Condition Section

RFS s, n The RFS instruction

refreshes the inputs and
I/O partial refresh outputs of the designates 3 6.7.1
range of I/O devices
RFSP s, n during one program scan.

Programming MELSEC System Q and L series 2 – 25

Application instructions, Part 1 Instruction Tables

2.4.8 Other convenient instructions

of steps
Number

Subset
Category Instruction Variables Meaning Execution Reference
Condition Section

s+0
1-Phase Input s+1
count-up/-down UDCNT1 s, n, d Current
4 6.8.1
Counter count
0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 -1 -2 -3 -2 -1 0 1 1

Switching period
of counter contact

s+0
2-Phase Input s+1
count-up/-down UDCNT2 s, n, d 4 6.8.2
Current
Counter count
0 1 2 3 4 5 4 3 2 1 0 -1 -2 -1

Switching period
of counter contact

(Time, the timer is set)

x n → (d)
Programmable TTMR d, n 3 6.8.3
(teaching) Timer
n=0:1, n=1:10, n=2:100
The STMR instruction uses
outputs designated by d+0
through d+3 to perform four
Special Function different timer functions:
Timer d+0: OFF delay timer output
(Timer instruction STMR s, n, d 3 6.8.4
for low speed d+1: One shot timer output after
OFF (Set by trailing edge)
timers)
d+2: One shot timer output after
ON (Set by leading edge)
d+3: ON delay timer output
The ROTC instruction rotates a
sector designated by s+2 on a
Positioning
instruction for ROTC s, n1, n2, d table with a specified number of 5 6.8.5
sectors (divisions) designated by
rotary tables n1 to a specified position
designated by s+1.
A RAMP instruction changes the
content in (d1)+0 gradually from
Ramp Signal RAMP n1, n2, n3, the initial value designated by n1 6 6.8.6
d1, d2
to the final value designated by
n2.
The SPD instruction counts
pulses at the input designated by
Pulse density 4 6.8.7
measurement SPD s, n, d s for a period of time specified by
n. The result of the
measurement is stored in d.
The PLSY instruction outputs a
Pulse output with
adjustable PLSY s1, s2, d number of pulses specified by s2 4 6.8.8
at a frequency specified by s1 to
number of pulses an output designated by d.

Pulse width PWM n1, n2, d

n1
4 6.8.9
modulation n2

The MTR instruction reads the

information of 16 bits beginning
from the device designated by s.
Building an input The number of repetitions (rows) 5 6.8.10
MTR s, n, d1, d2
matrix is designated by n.
The conditions of read data are
stored in the device designated
by d2 onwards.

2 – 26
Instruction Tables Application instructions, Part 2

2.5 Application instructions, Part 2

2.5.1 Logical operation instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

WAND
s, d (d) ∧ (s) → (d) 3 

WANDP

WAND
s1, s2, d1 (s1) ∧ (s2) → (d1) 4 

WANDP
7.1.1
DAND
(d+1, d) ∧ (s+1, s)  
Logical product s, d
→ (d+1, d)
DANDP

DAND
((s1)+1, s1) ∧ ((s2)+1, s2)  
s1, s2, d → (d+1, d)
DANDP

BKAND (s1) (s2) (d)

s1, s2, n, d 5 7.1.2
∧ n
BKANDP

WOR
s, d (d) ∨ (s) → (d) 3 

WORP

WOR
s1, s2, d1 (s1) ∨ (s2) → (d1) 4 

WORP
7.1.3
DOR
(d+1, d) ∨ (s+1, s)  
Logical sum s, d
→ (d+1, d)
DORP

DOR
s1, s2, d ((s1)+1, s1) ∨ ((s2)+1, s2)  
→(d+1, d)
DORP

BKOR (s1) (s2) (d)

s1, s2, n, d 5 7.1.4
∨ n
BKORP

Programming MELSEC System Q and L series 2 – 27

Application instructions, Part 2 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

WXOR
s, d (d) ∨ (s) → (d) 3 

WXORP

WXOR
s1, s2, d1 (s1) ∨ (s2) → (d1) 4 

WXORP
7.1.5
DXOR
Logical (d+1, d) ∨ (s+1, s)  
s, d
exclusive OR → (d+1, d)
DXORP

DXOR
s1, s2, d ((s1)+1, s1) ∨ ((s2)+1, s2)  
→ (d+1, d)
DXORP

BKXOR (s1) (s2) (d)

s1, s2, n, d 5 7.1.6
∨ n
BKXORP

WXNR
s, d (d) ∨ (s)→ (d) 3 

WXNRP

WXNR (s1) ∨ (s2) 5 (d1)

s1, s2, d1 4 

WXNRP
7.1.7
DXNR (d+1, d) ∨ (s+1, s)
Logical s, d 5 (d+1, d)  
exclusive NOR
DXNRP

DXNR
((s1)+1, s1) ∨ ((s2)+1, s2)  
s1, s2, d
5 (d+1, d)
DXNRP

BKXNR
(s1) (s2) (d)
s1, s2, n, d 5 7.1.8
∨ n
BKXNRP

2 – 28
Instruction Tables Application instructions, Part 2

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section


The number of steps is three for the Universal model QCPU and LCPU only.

The number of program steps depends on the devices used and the type of CPU.
 High Performance model QCPU, Process CPU, Redundant CPU
– Word device: internal word devices (except for file register ZR) : 5 (NOTE 1)
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification : 5 (NOTE 1)
– Constant; No limitations : 5 (NOTE 1)
Devices other than the above : 3 (NOTE 2)
 Basic model QCPU, Universal model QCPU, LCPU
– All devices that can be used : 3 (NOTE 2)
NOTE 1: For these models the number of steps increases but processing speed becomes faster.
NOTE 2: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

The number of program steps depends on the devices used and the type of CPU.
 High Performance model QCPU, Process CPU, Redundant CPU
– Word device: internal word devices (except for file register ZR) : 6 (NOTE 1)
– Bit device: whose device numbers are multiplies of 16, whose digit designation is K8,
and which use no index qualification : 6 (NOTE 1)
– Constant; No limitations : 6 (NOTE 1)
Devices other than the above : 4 (NOTE 2)
 Basic model QCPU
– All devices that can be used : 4 (NOTE 2)
 Universal model QCPU, LCPU
– All devices that can be used : 3 (NOTE 2)
NOTE 1: For these models the number of steps increases but processing speed becomes faster.
NOTE 2: The number of steps may increase due to the conditions described in section 3.11 "Number of program steps".

Programming MELSEC System Q and L series 2 – 29

Application instructions, Part 2 Instruction Tables

2.5.2 Rotation instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

ROR b15 (d) b0 SM700

n, d 3 

RORP rotates by n bits to the

Data rotation to right
the right 7.2.1
(16-bit)
RCR b15 (d) b0 SM700

n, d 3 

RCRP rotates by n bits to the

right

ROL
SM700 b15 (d) b0
n, d 3 

ROLP rotates by n bits to the left

Data rotation to
the left 7.2.2
(16-bit)
RCL
SM700 b15 (d) b0
n, d 3 

RCLP rotates by n bits to the left

DROR (d+1) (d)

b31 to b16 b15 to b0 SM700
n, d 3 

DRORP rotates by n bits to the

Data rotation to right
the right 7.2.3
(32-bit)
DRCR (d+1) (d)
b31 to b16 b15 to b0 SM700
n, d 3 

DRCRP rotates by n bits to the

right

DROL (d+1) (d)

SM700 b31 to b16 b15 to b0
n, d 3 

DROLP rotates by n bits to the left

Data rotation to
the left 7.2.4
(32-bit)
DRCL (d+1) (d)
SM700 b31 to b16 b15 to b0
n, d 3 

DRCLP
rotates by n bits to the left

2 – 30
Instruction Tables Application instructions, Part 2

2.5.3 Shift instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

SFR b15 bn b0
n, d 3 

SFRP b15 b0 SM700

Shift a 16-bit 0 to 0
data word by 7.3.1
n bits
SFL b15 bn b0
n, d 3 

SFLP SM700 b15 b0

0 to 0

n
BSFR
(d)
n, d 3
BSFRP SM700
0
Shift n bit 7.3.2
devices by 1 bit
n
BSFL
(d)
n, d 3
BSFLP SM700
0

SFTBR n1
n2

n1, n2, d (d) 4

SFTBRP SM700
Shift n bit 0 0
devices by 7.3.3
n bits n1
SFTBL
n2

n1, n2, d (d) 4

SFTBLP SM700
0 0

n
DSFR
(d)
n, d 3 

DSFRP
Shift n word 0
devices by 7.3.4
one digit n
DSFL
(d)
n, d 3 

DSFLP
0

n1
SFTWR n2

n1, n2, d (d) 4

SFTWRP
Shift n word 0 0
devices by 7.3.5
n words
SFTWL n1
n2
n1, n2, d (d) 4
SFTWLP
0 0

Programming MELSEC System Q and L series 2 – 31

Application instructions, Part 2 Instruction Tables

2.5.4 Bit processing instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

BSET (d)
b15 bn b0 3 
n, d
BSETP 1
Set / reset 7.4.1
single bits
BRST (d)
b15 bn b0 3 
n, d
BRSTP 0

TEST (s1)
b15 to b0 (d)
s1, s2, d 4

Test condition TESTP Bit designated by s2

of single bits in 7.4.2

16-/32-bit data
words DTEST (s1)
b31 to b0 (d)
s1, s2, d 4
DTESTP Bit designated by s2

BKRST (s) ON (s) OFF

Reset sections OFF OFF
RESET
of bits s, n n 3 7.4.3
in a batch
BKRSTP ON OFF
ON OFF

2 – 32
Instruction Tables Application instructions, Part 2

2.5.5 Data processing instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

SER (s2)
(s1)
n
s1, s2, d, n 5
SERP (d) : identical No.
(d+1) : Number of
matches
Search 16-bit 7.5.1
data
DSER 32 bits (s2)
(s1)
n
s1, s2, d, n 5
DSERP (d) : identical No.
(d+1) : Number of
matches

SUM (s)
b15 b0
s, d 3 
(d): Binary coded
SUMP number of
Check data set bits
bits 7.5.2
(16-/32-bit)
DSUM (s+1) (s)

s, d 3 
(d): Binary coded
DSUMP number of
set bits

Decoding from 8 to 256 bits

DECO
(d)
Decoding data s, d, n (s) decode 4 7.5.3
n
2 Bit
n
DECOP

Encoding from 256 to 8 bits

ENCO
(d)
Encoding data s, d, n n
encode (s) 4 7.5.4
2 Bit
n
ENCOP

SEG
b3 to b0
7-segment (s) (d) 3  7.5.5
s, d
decoding
7SEG
SEGP

Programming MELSEC System Q and L series 2 – 33

Application instructions, Part 2 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

The DIS instruction disunites a

DIS 16-bit data value to groupings
of 4 bits. The data value to be
s, n, d disunited in s, the number of 4- 4 7.5.6
bit groupings in n, and the first
DISP number of destination device in
d must be specified.

UNI The UNI instruction separates

each 4 lowest bits of up to four
s, n, d 16-bit data values and unites 4 7.5.7
their conditions in one 16-bit
UNIP data value.

The NDIS instruction disunites

NDIS data in devices specified from
s1 on to bit groupings with a
s1, s2, d number of bits specified by s2.
The disunited bit groupings are
NDISP stored separately in the device
specified by d onwards.
Disunite/unite
16-bit data 4 7.5.8
words The NUNI instruction
NUNI separates bit groupings of a
size specified by s2 from
devices specified by s1 and
s1, s2, d unites these bit groupings in
one data value. The bit
NUNIP groupings are stored
successively from the device
specified by d onwards.

WTOB For this instruction the data

values in s to be disunited, the
s, n, d number of byte units in n, and
the first number of destination
WTOBP device in d must be specified.
4 7.5.9
BTOW The initial number of data
value in s to be united, the
s, n, d number of byte units n, and
destination device in d must be
BTOWP specified.

The MAX instruction searches

MAX for maximum values in 16-bit
data blocks. The number of
s, n, d data blocks to be searched
through is specified by n. The
MAXP greatest value found in s
Search through s+(n-1) is stored in d.
maximum 4 7.5.10
values in 16-/ The DMAX instruction
32-bit data DMAX searches for maximum values
in 32-bit data blocks. The
s, n, d number of data blocks to be
searched through is specified
DMAXP by n. The greatest value found
in s through s+(n-1) is stored in
d.

The MIN instruction searches

MIN for minimum values in 16-bit
data blocks. The number of
s, n, d data blocks to be searched
through is specified by n. The
MINP smallest value found in s
Searching
minimum through s+(n-1) is stored in d.
4 7.5.11
values in 16-/ The DMIN instruction searches
32-bit data DMIN for minimum values in 32-bit
data blocks. The number of
s, n, d data blocks to be searched
through is specified by n. The
DMINP smallest value found in s
through s+(n-1) is stored in d.

2 – 34
Instruction Tables Application instructions, Part 2

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

The SORT instruction sorts

16-bit data specified by s1 in
SORT ascending or descending
order. The number of data to
be sorted is specified by n.
Sorting 16-/ 6 7.5.12
32-bit data s1, n, s2, d1, d2
The DSORT instruction sorts
32-data specified by s1 in
DSORT ascending or descending
order. The number of data to
be sorted is specified by n.

The WSUM instruction

WSUM calculates the total of 16-bit
s, n, d data blocks in the device 4 7.5.13
specified by s. The result is
WSUMP stored in the device specified
Calculating
totals of 16-/ by d and d+1.
32-bit BIN data The DWSUM instruction
blocks DWSUM calculates the total of 32-bit
data blocks in the device 4 7.5.14
s, n, d specified by s and s+1. The
DWSUMP result is stored in d through
d+3.

Calculates the mean of n-point

MEAN devices (in 16-bit units)
s, n, d starting from the device 4
specified by (s), and then
MEANP stores the result into the
Calculation of device specified by (d).
7.5.15
averages Calculates the mean of n-point
DMEAN devices (in 32-bit units)
starting from the device 4
s, n, d specified by (s), and then
DMEANP stores the result into the
device specified by (d).

Programming MELSEC System Q and L series 2 – 35

Application instructions, Part 2 Instruction Tables

2.5.6 Structured program instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

The FOR/NEXT loop

FOR n repeats single program 2
sequences without
setting an input
condition. The program 7.6.1
sequence located
NEXT between the FOR and 1
Repetition the NEXT command is
instructions repeated for n times.

BREAK The BREAK instruction

terminates a FOR/NEXT
p, d loop execution and jumps 3 7.6.2
to the pointer specified
BREAKP by p.

The CALL instruction

CALL calls a subroutine
p program specified by a
pointer p. 2+n   7.6.3
p, s1 to sn 
s1 to sn are arguments
CALLP sent to subroutine
program (n <= 5).
The RET instruction
RET marks the end of a 1 7.6.4
subroutine program.
Subroutine On resetting the
program calls FCALL execution condition for
the FCALL instruction,
the contacts and coils in
the subroutine program
p specified in p (pointer/
label) are treated as if the 2+n 7.6.5
p, s1 to sn 
execution condition of the
FCALLP according instruction was
not set.
s1 to sn are arguments
sent to subroutine
program (n <= 5).
The ECALL instruction
ECALL calls a subroutine
Subroutine program specified by a
file name, p pointer address (label) in
program calls a program file specified 2+n 7.6.6
between file name, p, s1 to sn 
program files by a file name.
ECALLP s1 to sn are arguments
sent to subroutine
program (n <= 5).
On resetting the
EFCALL execution condition for
the EFCALL instruction,
the contacts and coils in
the subroutine program 3+n 7.6.7
file name, p specified in p (pointer/ 
EFCALLP label) are treated as if the
execution condition of the
according instruction was
not set.
Subroutine
program calls  Executes subroutine
between program p when input
program files condition is met.
 Performs non-
execution processing
XCALL p, s1 to sn of subroutine program 2+n 7.6.8
p if input conditions 
have not been met.
(s1 to sn are
arguments sent to
subroutine program.
n <= 5)

2 – 36
Instruction Tables Application instructions, Part 2

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

Performs auto refresh of

intelligent function
modules, link refresh,
COM auto refresh of CPU 1 7.6.9
shared memory, and
communications with
peripherals.
Select refresh
Performs auto refresh of
CCOM intelligent function 1 7.6.11
modules, auto refresh of
CPU shared memory,
and communications with
CCOMP peripherals after the 1 7.6.11
input conditions are met.
IX s The IX and IXEND 2
instructions perform
Index index qualification on
qualification of those devices in the 7.6.12
entire ladders IXEND program part located 1
between the IX and
IXEND instructions.
The IXDEV and IXSET
Designation of IXDEV instructions read the 1
addresses of the devices
qualification in the offset designation
values in index 7.6.13
qualification of area and write these
p, d offset numbers to an
entire ladders IXSET 3
index table in the device
designated by d.

n indicates number of arguments for subroutine program.

n indicates the total of the number of arguments used in the subroutine program and the number of program name
steps. The number of program name steps is calculated as "number of characters in the program/2" (decimal fraction
is rounded up).

The subset is effective only with the Universal model QCPU and LCPU.

Programming MELSEC System Q and L series 2 – 37

Application instructions, Part 2 Instruction Tables

2.5.7 Data table operation instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

FIFW (s) (d) Pointer Pointer + 1

Write data to a 3 7.7.1
data table s, d
Pointer + 1
FIFWP Device

FIFR (s) Pointer Pointer - 1 (d )

Read data
entered first s, d 3 7.7.2
from data table
FIFRP

FPOP (s) Pointer Pointer - 1 (d )

Read data
entered last s, d 3 7.7.3
from data table
FPOPP Pointer + 1
Device

FDEL
Delete
specified data
blocks from
data table FDELP
s, n, d 4 7.7.4

FINS (s) (d) Pointer Pointer + 1

Insert specified
data blocks in
data table
FINSP Designated by n

2 – 38
Instruction Tables Application instructions, Part 2

2.5.8 Buffer memory access instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

FROM The FROM instruction

reads 1-word data (16-
bit) from the buffer
memory of a special
Reading data FROMP function module.
from a special 5 7.8.1
n1, n2, n3, d
function
module DFRO The DFRO instruction
reads 2-word data (32-
bit) from the buffer
memory of a special
DFROP function module.

TO The TO instruction writes

1-word data (16-bit) from
the memory of the CPU
to the buffer memory of a
Writing data to TOP special function module.
a special 5 7.8.2
function s, n1, n2, n3
The DTO instruction
module DTO writes 2-word data (32-
bit) from the memory of
the CPU to the buffer
DTOP memory of a special
function module.

2.5.9 Display instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

SM701 set (1):

Output of an ASCII
character string of 16
characters to an output
module. The character
string, divided into twice 8
characters, is read from
the address area s and
PR s, d output to the outputs 3 7.9.1
specified by d.
SM701 not set (0):
ASCII Output of ASCII character
character string data up to the
output character code "00H" in
hexadecimal format from
the address area s to the
outputs specified by d.

The PRC instruction

outputs a comment of a
device (in ASCII code) to
an output module. 3 7.9.2
PRC s, d
If SM701 is set (1), 16
characters are output;
if SM701 is not set (0), 32
characters are output.

Clear display LEDR Resetting annunciators 1 7.9.3

and error displays

Programming MELSEC System Q and L series 2 – 39

Application instructions, Part 2 Instruction Tables

2.5.10 Debugging and failure diagnosis instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

The CHKST instruction

starts the execution of the
CHK instruction. If the
execution condition for
CHKST the CHKST instruction is
not set (0), the program
step following the CHK
instruction will be
executed.
1 7.10.1
The CHK instruction
supports failure check
operations for contact
circuits. Once an error
CHK occurs within such a
Failure check circuit, the device in d1 is
set and the
corresponding error code
is stored in d2.

The CHKCIR instruction

generates error check
circuits for the CHK
CHKCIR instruction and starts the
program section with the
generated error check 1 7.10.2
circuits.

End instructions for a

CHKEND program part with
generated check circuits.

2 – 40
Instruction Tables Application instructions, Part 2

2.5.11 Character string processing instructions

of steps
Number
Execution Reference

Subset
Category Instruction Variables Meaning Condition Section

The BINDA instruction

BINDA converts a 16-bit binary
value specified by s into a
5-digit decimal value in
Conversion of BINDAP ASCII code and stores it in
16-/32-bit binary the device specified in d.
data into s, d 3 7.11.1
decimal values in The DBINDA instruction
ASCII code DBINDA converts 32-bit binary data
specified by s into a 10-digit
decimal value in ASCII
DBINDAP code and stores it in the
device specified in d.
The BINHA instruction
BINHA converts 16-bit binary data
specified by s into a 4-digit
hexadecimal value in ASCII
Conversion of BINHAP code and stores it in the
16-/32-bit binary devices specified by d.
data into s, d 3 7.11.2
hexadecimal values The DBINHA instruction
in ASCII code DBINHA converts 32-bit binary data
specified by s into a 8-digit
hexadecimal value in ASCII
DBINHAP code and stores it in the
devices specified by d.
The BCDDA instruction
BCDDA converts 4-digit BCD data
specified by s into the
ASCII format and stores it
BCDDAP in the devices specified by
Conversion of 4-/8- d.
digit BCD data into s, d 3 7.11.3
ASCII code The DBCDDA instruction
DBCDDA converts 8-digit BCD data
specified by s into the
ASCII format and stores it
DBCDDAP in the devices specified by
d.
The DABIN instruction
DABIN converts the 5-digit decimal
ASCII data specified by s
into the BIN 16-bit format
DABINP and stores it in the devices
Conversion of specified by d.
decimal ASCII data 3 7.11.4
s, d The DDABIN instruction
into BIN 16-/32-bit
binary data DDABIN converts the 10-digit
decimal ASCII data
specified by s into the BIN
32-bit format and stores it
DDABINP in the devices specified by
d.
The HABIN instruction
HABIN converts the 4-digit
hexadecimal ASCII data in
the device specified by s
into the BIN 16-bit binary
HABINP format and stores it in the
Conversion of
hexadecimal ASCII devices specified by d.
s, d 3 7.11.5
data into 16-/32-bit The DHABIN instruction
binary data DHABIN converts the 8-digit
hexadecimal ASCII data
specified in the area s into
the BIN 32-bit format and
DHABINP stores it in the devices
specified by d.

Programming MELSEC System Q and L series 2 – 41

Application instructions, Part 2 Instruction Tables

of steps
Number
Execution Reference

Subset
Category Instruction Variables Meaning Condition Section

The DABCD instruction

DABCD converts the decimal ASCII
data in s into the 4-digit
BCD data format and
Conversion of DABCDP stores it in the devices
decimal ASCII data specified by d.
s, d 3 7.11.6
into 4-/8-digit BCD The DDABCD instruction
data DDABCD converts the decimal ASCII
data specified by s into the
8-digit BCD format and
DDABCDP stores it in the devices
specified in d.

COMRD The COMRD instruction

reads comment data from
Read-out of 3 7.11.7
comment data s, d the device specified by s
and stores it as ASCII code
COMRDP in the area d.

LEN The length instruction

Detection of detects the length of a
character string s, d character string specified in 3 7.11.8
length s and stores the result in
LENP the device specified by d.

Adds a decimal point to the

STR BIN 16-bit binary value in
the device specified by s2
to the digit specified by s1,
converts the data into a
STRP character string, and stores
Conversion of it in the area of the devices
BIN 16-/32-bit specified by d.
binary data into s1, s2, d 4 7.11.9
character string Adds a decimal point to the
data DSTR BIN 32-bit binary value in
the device specified by s2
to the digit specified by the
device s1, converts the
DSTRP data into a character string,
and stores it in the area of
the devices specified by d.
Converts the character
VAL strings stored in the area s
into BIN 16-bit data. The
number of digits and the
Conversion of VALP binary value are stored in
character string d1 and d2.
s, d1, d2 4 7.11.10
data into BIN 16-/
32-bit binary data DVAL Converts the character
strings stored in s into BIN
32-bit data. The number of
digits and the binary value
DVALP are stored in d1 and d2.

Converts the floating point

Conversion of ESTR data in s1 into character
floating point data string data. The data format 4 7.11.11
into character string s1, s2, d of the character string is
data ESTRP specified in s2. The result
is stored in d.

EVAL Converts the character

Conversion of
character string string in s into a decimal
s, d floating point number (real 3 7.11.12
data into decimal number). The result is
floating point data EVALP stored in d.

Converts the 16-bit binary

ASC data stored from s onwards
Conversion of 16-bit into the hexadecimal ASCII
data into ASCII s, n, d format and stores the result 4 7.11.13
code considering the number of
ASCP characters specified by n
from d onwards.

2 – 42
Instruction Tables Application instructions, Part 2

of steps
Number
Execution Reference

Subset
Category Instruction Variables Meaning Condition Section

Converts the hexadecimal

Conversion of HEX ASCII characters from s
onwards into binary values.
hexadecimal s, n, d The number of characters 4 7.11.14
ASCII values into
binary values to be converted is specified
HEXP by n. The result is stored
from d onwards.

Extraction of RIGHT Stores n characters from

character string the right side of the
data s, n, d character string (end of
(right part of character string) in s. The
character string) RIGHTP characters are stored in d.
4 7.11.15
Extraction of LEFT Stores n characters from
character string the left side of the character
data s, n, d string (beginning of
(left part of character string) in s. The
character string) LEFTP characters are stored in d.

MIDR Stores a specified part of

the character string stored
s1, s2, d in s. The first character of
Selecting and the part to be stored is
MIDRP specified in s2.
moving parts of
character strings 4 7.11.16
into a character Stores a part of specified
string MIDW length of the character
string stored in s1 in the
s1, s2, d
area specified in d. The first
MIDWP address of the storage area
in d is specified in s2.
Searches the character
INSTR string specified in s1 within
Search for the character string data 5 7.11.17
character strings s1, s2, n, d specified by s2. The search
INSTRP begins with the character
specified in n.
Inserts the character string
STRINS data specified by (S) to the
Insert character s, n, d (n)th character (insert 4 7.11.18
strings position) from the initial
STRINSP character string data
specified by (D).

STRDEL Deletes the (n2) characters

data specified by (d)
Delete character 4 7.11.19
strings d n1, n2 starting from the
device(insert position)
STRDELP specified by n1.

Calculates the BCD format

EMOD from the floating point
Floating point data number in s1 considering
conversion with s1, s2, d1 4 7.11.20
BCD representation the decimal point shift to
EMODP the right specified in s2.
The result is stored in d1.
Calculates the decimal for-
EREXP mat of the floating point
BCD data
data from the floating point
conversion with s1, s2, d1 data in BCD format in s1, 3 7.11.21
decimal floating
point format considering the decimal
EREXPP places specified in s2. The
result is stored in d1.

Programming MELSEC System Q and L series 2 – 43

Application instructions, Part 2 Instruction Tables

2.5.12 Special function instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

Sine SIN
calculation SIN(s+1, s)
(Floating point s, d → 3 7.12.1
single (d+1, d)
precision) SINP

Cosine COS
calculation COS(s+1, s)
(Floating point s, d → 3 7.12.3
single (d+1, d)
precision) COSP

Tangent TAN
calculation TAN(s+1, s)
(Floating point s, d → 3 7.12.5
single (d+1, d)
precision) TANP

Arcus sine ASIN

calculation ASIN(s+1, s)
(Floating point s, d → 3 7.12.7
single (d+1, d)
precision) ASINP

Arcus cosine ACOS

calculation ACOS(s+1, s)
(Floating point s, d → 3 7.12.9
single (d+1, d)
precision) ACOSP

Arcus tangent ATAN

calculation ATAN(s+1, s)
(Floating point s, d → 3 7.12.11
single (d+1, d)
precision) ATANP

Sine SIND
calculation SIN(s+3, s+2, s+1, s)
(Floating point s, d → 3 7.12.2
double (d+3, d+2, d+1, d)
precision) SINDP

Cosine COSD
calculation COS(s+3, s+2, s+1, s)
(Floating point s, d → 3 7.12.4
double (d+3, d+2, d+1, d)
precision) COSDP

Tangent TAND
calculation TAN(s+3, s+2, s+1, s)
(Floating point s, d → 3 7.12.6
double (d+3, d+2, d+1, d)
precision) TANDP

Arcus sine ASIND

calculation ASIN(s+3, s+2, s+1, s)
(Floating point s, d → 3 7.12.8
double (d+3, d+2, d+1, d)
precision) ASINDP

Arcus cosine ACOSD

calculation ACOS(s+3, s+2, s+1, s)
(Floating point s, d → 3 7.12.10
double (d+3, d+2, d+1, d)
precision) ACOSDP

2 – 44
Instruction Tables Application instructions, Part 2

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

Arcus tangent ATAND

calculation ATAN(s+3, s+2, s+1, s)
(Floating point s, d → 3 7.12.12
double (d+3, d+2, d+1, d)
precision) ATANDP

RAD (s+1, s)
→
s, d (d+1, d) 3 7.12.13
Conversion from degrees
RADP into radian
Conversion
from degrees
into radian (s+3, s+2, s+1, s)
RADD
→
s, d (d+3, d+2, d+1, d) 3 7.12.14
Conversion from degrees
RADDP into radian

DEG
(s+1, s) → (d+1, d)
s, d Conversion from radian 3 7.12.15
into degree
DEGP
Conversion
from radian
into degree (s+3, s+2, s+1, s)
DEGD
→
s, d (d+3, d+2, d+1, d) 3 7.12.16
Conversion from radian
DEGDP into degree

POW
(s1+1, s1)(s2+1, s2)
s1, s2, d → 4 7.12.17
(d+1, d)
POWP
Exponentiation
POWD (s1+3, s1+2, s1+1,
s1, s2, d s1)(s2+3, s2+2, s2+1, s2) 4 7.12.18
→
POWDP (d+3, d+2, d+1, d)

SQR
√(s+1, s)
s, d → 3 7.12.19
(d+1, d)
SQRP
Square root
calculation
SQRD
√(s+3, s+2, s+1, s)
s, d → 3 7.12.20
(d+3, d+2, d+1, d)
SQRDP

EXP
s, d e(s+1, s) → (d+1, d) 3 7.12.21
EXPP
Floating point
value as
exponent of e
EXPD
e(s+3, s+2, s+1, s)
s, d → 3 7.12.22
(d+3, d+2, d+1, d)
EXPDP

Programming MELSEC System Q and L series 2 – 45

Application instructions, Part 2 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

LOG
LOG e(s+1, s)
s, d → 3 7.12.23
(d+1, d)
LOGP
Logarithm
(natural)
calculation
LOGD
LOG e(s+3, s+2, s+1, s)
s, d → 3 7.12.24
(d+3, d+2, d+1, d)
LOGDP

LOG10
log10 (s+1, s)
s, d → 3 7.12.25
(d+1, d)
LOG10P
Common
logarithm
LOG10D
log10 (s+3, s+2, s+1, s)
s, d → 3 7.12.26
(d+3, d+2, d+1, d)
LOG10DP

RND
Randomize Stores the generated 2
d
value random value in d.
RNDP
7.12.27
SRND
Updates the series of
Update s random values stored 2
random values
in s.
SRNDP

Square root BSQR

calculation (s) (d) +0 Integer
from s, d 3
4-digit BCD +1 Decimal place
data BSQRP
7.12.28
Square root BDSQR
calculation
from s, d (d) +0 Integer 3
8-digit BCD +1 Decimal place
data BDSQRP

BSIN
Sine
calculation s, d 3 7.12.29
from BCD data
BSINP

BCOS
Cosine
calculation s, d 3 7.12.30
from BCD data
BCOSP

BTAN
Tangent
calculation s, d 3 7.12.31
from BCD data
BTANP

2 – 46
Instruction Tables Application instructions, Part 2

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

BASIN
Arcus sine
calculation s, d 3 7.12.32
from BCD data
BASINP

BACOS
Arcus cosine
calculation s, d 3 7.12.33
from BCD data
BACOSP

BATAN
Arcus tangent
calculation s, d 3 7.12.34
from BCD data
BATANP

Programming MELSEC System Q and L series 2 – 47

Application instructions, Part 2 Instruction Tables

2.5.13 Data control instructions

of steps
Number
Execution Reference

Subset
Category Instruction Variables Meaning Condition Section

If (s3)<(s1)
the data value
LIMIT in s1 is stored in d.
If (s1)≤(s3)≤(s2)
s1, s2, s3, d the data value in
s3 is stored in d.
LIMITP If (s2)<(s3)
the data value in
s2 is stored in d.

Upper and lower If

limit controls for ((s3)+1, s3)<((s1)+1, s1)
the data value in 5 7.13.1
BIN 16-/32-bit
data DLIMIT ((s1)+1, s1) is
stored in (d+1, d).
If ((s1)+1, s1)≤
((s3)+1, s3) <((s2)+1,s2)
s1, s2, s3, d the data value in
((s3)+1, s3) is
stored in (d+1, d).
If ((s2)+1, s2)<
DLIMITP ((s3)+1, s3)<((s2)+1, s2)
the data value in
((s2)+1, s2) is
stored in (d+1, d).
If (s1)≤(s3)≤(s2)
BAND 0 → (d)
If (s3)<(s1)
s1, s2, s3, d (s3)–(s1)→ (d)
BANDP If (s2)<(s3)
(s3)–(s2)→ (d)
If
Dead band DBAND ((s1)+1, s1)≤((s3)+1, s3)
controls for BIN ≤((s2)+1, s2) 5 7.13.2
16-/32-bit data 0 → (d+1, d)
If
s1, s2, s3, d ((s3)+1, s3)<(s1+1, s1)
((s3)+1, s3) – ((s1)+1, s1)
DBANDP →(d+1, d)
If
((s2)+1, s2)<((s3)+1, s3)
((s3)+1, s3) – ((s2)+1, s2)
→ (d+1, d)
If s3 = 0:
ZONE 0 → (d)
If s3 > 0:
s1, s2, s3, d s3 + s2 → (d)
ZONEP If s3 < 0:
s3 – s1 → (d)
Zone control for
BIN 16-/32-bit If ((s3)+1, s3) = 0 5 7.13.3
data DZONE 0 → (d+1, d)
If ((s3)+1, s3) > 0
s1, s2, s3, d ((s3)+1, s3) + ((s2)+1, s2)
→ (d+1, d)
DZONEP If ((s3)+1, s3) < 0
((s3)+1, s3) + ((s1)+1, s1)
→ (d+1, d)

2 – 48
Instruction Tables Application instructions, Part 2

of steps
Number
Execution Reference

Subset
Category Instruction Variables Meaning Condition Section

Executes scaling for the

scaling conversion data
SCL (16-bit data units) specified
by (s2) with the input value
specified by (s1), and then
stores the result into the 4
s1, s2, d device specified by (D).
The scaling conversion is
SCLP executed based on the
scaling conversion data
stored in the device
Point-by point specified by (s2) and up.
7.13.4
coordinate data Executes scaling for the
scaling conversion data
DSCL (32-bit data units) specified
by (s2) with the input value
specified by (s1), and then
s1, s2, d stores the result into the 4
device specified by (D).
The scaling conversion is
DSCLP executed based on the
scaling conversion data
stored in the device
specified by (s2) and up.
Executes scaling for the
scaling conversion data
SCL2 (16-bit data units) specified
by (s2) with the input value
specified by (s1), and then
s1, s2, d stores the result into the 4
device specified by (D).
The scaling conversion is
SCL2P executed based on the
scaling conversion data
stored in the device
X or Y specified by (s2) and up.
7.13.5
coordinate data Executes scaling for the
scaling conversion data
DSCL2 (32-bit data units) specified
by (s2) with the input value
specified by (s1), and then
stores the result into the 4
s1, s2, d
device specified by (D).
The scaling conversion is
DSCL2P executed based on the
scaling conversion data
stored in the device
specified by (s2) and up.

Programming MELSEC System Q and L series 2 – 49

Application instructions, Part 2 Instruction Tables

2.5.14 File register switching instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

The RSET instruction

Switch RSET switches from a file
instruction for register block being in 2 7.14.1
file register s use by a program to a file
blocks RSETP register block with the
number specified by s.
The QDRSET instruction
Switch QDRSET switches from a file
instruction for s register file being in use 2+n 7.14.2
file register by a program to a file 
files QDRSETP register file specified by
s.

QCDSET The QCDSET instruction

Switch switches from a comment
instruction for s file being in use by a 2+n 7.14.3

comment files program to a comment
QCDSETP file specified by s.

 n = (number of program name characters)/2 = Number of additional steps (Decimal fractions are rounded up)

2 – 50
Instruction Tables Application instructions, Part 2

2.5.15 Clock instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

DATERD (Clock →d+0 Year

element) d+1 Month
d+2 Day
Reading d 2 7.15.1
clock data d+3 Hour
DATERDP d+4 Minute
d+5 Sec.
d+6 Day of the week

DATEWR s+0 Year →(Clock

s+1 Month element)
s+2 Day
Writing s s+3 Hour 2 7.15.2
clock data
s+4 Minute
DATEWRP
s+5 Sec.
Day of the
s+6 week

DATE+ s1 s2 d
Adding Hour Hour Hour
4 7.15.3
s1, s2, d +
clock data Minute Minute Minute
Second Second Second
DATE+P

DATE-
s1 s2 d
Subtracting 4 7.15.4
s1, s2, d Hour Hour Hour
clock data Minute - Minute Minute
Second Second Second
DATE-P

Changing clock SECOND s d

data format Hour Second
from hh:mm:ss s, d Minute
Second
to seconds SECONDP
3 7.15.5
Changing clock HOUR
s d
data format s, d Second Hour
from seconds Minute
to hh:mm:ss HOURP Second

Programming MELSEC System Q and L series 2 – 51

Application instructions, Part 2 Instruction Tables

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

LDDT=
s1 Year s2 Year
→
ANDDT= s1, s2, n s1+1 Month = s2+1 Month Comparison 4
operation
ORDT= s1+2 Day s2+2 Day result

LDDT<>
s1 Year s2 Year
→
ANDDT<> s1, s2, n s1+1 Month <> s2+1 Month Comparison 4
operation
ORDT<> s1+2 Day s2+2 Day result

LDDT>
s1 Year s2 Year
→
ANDDT> s1, s2, n s1+1 Month < s2+1 Month Comparison 4
operation
ORDT> s1+2 Day s2+2 Day result
Date 7.15.6
comparison LDDT<=
s1 Year s2 Year
→
ANDDT<= s1, s2, n s1+1 Month <= s2+1 Month Comparison 4
operation
ORDT<= s1+2 Day s2+2 Day result

LDDT<
s1 Year s2 Year
→
ANDDT< s1, s2, n s1+1 Month > s2+1 Month Comparison 4
operation
ORDT< s1+2 Day s2+2 Day result

LDDT>=
s1 Year s2 Year
→
ANDDT>= s1, s2, n s1+1 Month >= s2+1 Month Comparison 4
operation
ORDT>= s1+2 Day s2+2 Day result

LDTM=
s1 Hour s2 Hour
→
ANDTM= s1, s2, n s1+1 Minute = s2+1 Minute Comparison 4
operation
ORTM= s1+2 Second s2+2 Second result

LDTM<>
s1 Hour s2 Hour
→
ANDTM<> s1, s2, n s1+1 Minute <> s2+1 Minute Comparison 4
operation
ORTM<> s1+2 Second s2+2 Second result

LDTM>
s1 Hour s2 Hour
→
ANDTM> s1, s2, n s1+1 Minute < s2+1 Minute Comparison 4
operation
ORTM> s1+2 Second s2+2 Second result
Clock 7.15.7
comparison LDTM<=
s1 Hour s2 Hour
→
ANDTM<= s1, s2, n s1+1 Minute <= s2+1 Minute Comparison 4
operation
ORTM<= s1+2 Second s2+2 Second result

LDTM<
s1 Hour s2 Hour
→
ANDTM< s1, s2, n s1+1 Minute > s2+1 Minute Comparison 4
operation
ORTM< s1+2 Second s2+2 Second result

LDTM>= s1 Hour s2 Hour

→
ANDTM>= s1, s2, n s1+1 Minute >= s2+1 Minute Comparison 4
operation
ORTM>= s1+2 Second s2+2 Second result

2 – 52
Instruction Tables Application instructions, Part 2

2.5.16 Expansion clock instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

(Clock →d+0 Year

element)
S.DATERD
d+1 Month
Reading clock d+2 Day
data of d+3 Hour 6 7.16.1
d
expansion d+4 Minute
block d+5 Sec.
SP.DATERD d+6 Dayweek
of the

d+7 1/1000 sec.

S.DATE+ (s1) (s2) (d)

Adding Hour Hour Hour
clock data of Minute Minute Minute
8 7.16.2
s1, s2, d
expansion Sec. + Sec. → Sec.
block — — —
SP.DATE+ 1/1000 1/1000 1/1000
sec. sec. sec.

(s1) (s2) (d)

S.DATE- Hour Hour Hour
Subtracting
clock data of Minute Minute Minute
s1, s2, d Sec. Sec. → Sec. 8 7.16.3
expansion –
block — — —
1/1000 1/1000 1/1000
SP.DATE- sec. sec. sec.

Programming MELSEC System Q and L series 2 – 53

Application instructions, Part 2 Instruction Tables

2.5.17 Program instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

PSTOP The PSTOP instruction

Switching
programs into s sets the program 2+n 7.17.1
specified by the device in 
stand-by mode s into the stand-by mode.
PSTOPP

The POFF instruction

Switching POFF sets the program
programs into specified by the device in
stand-by mode s s into the stand-by mode 2+n 7.17.2

and reset of and resets the outputs
outputs POFFP addressed by the
program.

The PSCAN instruction

PSCAN sets the program
Switching specified by the device in
programs into s into the scan execution 2+n 7.17.3
scan execution s mode. In this mode the 
mode PSCANP program is only executed
once during one program
scan.

PLOW The PLOW instruction

Switching sets the program
programs into 2+n 7.17.4
low-speed s specified by the device in 
s into the low-speed
execution mode PLOWP execution mode.

LDPCHK In conduction when

Checking the
program ANDPCHK s program specified by the 2+n 7.17.5
device in s is being 
execution status executed.
CRPCHK
 n = (number of program name characters)/2 = Number of additional steps (Decimal fractions are rounded up)

2 – 54
Instruction Tables Application instructions, Part 2

2.5.18 Other instructions

of steps
Number

Subset
Category Instruction Variables Meaning Execution Reference
Condition Section

WDT The WDT instruction

Reset resets the watchdog
watchdog timer (WDT) during 1 7.18.1
timer execution of a sequence
WDTP program.

Preset number (d)

of execution DUTY n1, n2, d 4 7.18.2
scans
SM420 to SM424, SM 430 to SM434

Turns ON device
specified by (d) if
measured ON time of 4 7.18.3
Time check TIMCHK s1, s2, d
input condition is longer
than preset time
continuously.

ZRRDB 0 ZR0
1 Higher 8 bits
Direct read of n, d 2 ZR1 3 7.18.4
one byte 3 Higher 8 bits
ZRRDBP
n 8 bits (d)

ZRWRB 0 ZR0
1 Higher 8 bits

Direct write of 2 ZR1

3 7.18.5
one byte n, s Higher 8 bits

ZRWRBP n 8 bits

Stores the indirect

ADRSET adress of the device
Storing of an designated by s at d and
s, d d+1. 3 7.18.6
indirect adress This adress is used
ADRSETP when a indirect device
read is performed.

The KEY instruction

supports the key input of
8 ASCII characters at the
Numerical key inputs specified by s (X).
input from KEY s, n, d1, d2 The values entered at 5 7.18.7
keyboard the inputs are encoded in
hexadecimal format and
stored in the devices
specified by d1.

ZPUSH The ZPUSH instruction

Batch save of saves the contents of the
index register d 2 7.18.8
index registers Z0
contents through Z15 in d.
ZPUSHP

Batch ZPOP The ZPOP instruction

recovery of recovers the contents of
index d 2 7.18.8
register the index registers Z0
ZPOPP through Z15 in d.
contents

Programming MELSEC System Q and L series 2 – 55

Application instructions, Part 2 Instruction Tables

of steps
Number

Subset
Category Instruction Variables Meaning Execution Reference
Condition Section

Reads the module

UNIRD information stored in the
area starting from the
Reading I/O No. designated by n1
module n1, d, n2 and stores it in the area 4 7.18.9
information starting from the device
UNIRDP designated by d. The
number of points is
designated by n2.

This instruction reads the

TYPERD module information
stored in the area
Reading
module model n, d starting from the I/O 3 7.18.10
number specified by "n",
name and stores it in the area
TYPERDP
starting from the device
specified by (D).

Stores trace data set at a

peripheral device to trace
file in IC memory card by 1
TRACE the designated number
Trace set/ when SM800, SM801, 7.18.11
reset and SM802 turns ON.

TRACER Resets the data set by 1

the TRACE instruction

Writing data to
a designated SP.FWRITE u0, s0, d0, s1, s2, d1 Writes data to a 11 7.18.12
designated file
file

Reading data
from a SP.FREAD u0, s0, d0, s1, d1, d2 Reads data from a 11 7.18.13
designated file
designated file

Writes data to the device

Writing data to S.DEVST n1, s, n2, d data storage file in the 9 7.18.14
standard ROM
standard ROM.

S.DEVLD
Reading data Reads data from the
from standard n1, d, n2 device data storage file 8 7.18.15
ROM in the standard ROM.
SP.DEVLD

Transfers the program

stored in a memory card
Loading or standard memory card
program from PLOADP s, d (other than drive 0) to 3 7.18.16
memory drive 0 and places the
program in standby
status.

Unloading Deletes the standby

program from program stored in 3 7.18.17
PUNLOADP s, d
program standard memory
memory (drive 0)

2 – 56
Instruction Tables Application instructions, Part 2

of steps
Number

Subset
Category Instruction Variables Meaning Execution Reference
Condition Section

Deletes standby program

stored in standard
memory (drive 0)
designated by s1.Then
Load and the program (s2) stored 4 7.18.18
unload PSWAPP s1, s2, d in a memory card or
standard memory (other
than drive 0) is
transfered to drive 0 and
placed in standby status.

RBMOV s, d, n
Highspeed (s) (d)
block transfer 4 7.18.19
of file register n
RBMOVP s, d, n

Displays the specified

character strings on the 2 7.18.20
User message UMSG s display unit as a user
message.

Programming MELSEC System Q and L series 2 – 57

Data link instructions Instruction Tables

2.6 Data link instructions

2.6.1 Instructions for network refresh

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

S.ZCOM
Jn

Link SP.ZCOM
instruction: Refreshes the 5 8.2.1
Network designated network.
refresh S.ZCOM
Un
SP.ZCOM

2.6.2 Read/write routing information

of steps
Number

Subset
Category Instruction Variables Meaning Execution Reference
Condition Section

S.RTREAD
Reads data set at routing 7 8.3.1
n, d parameters.
SP.RTREAD
Read/Write
routing
information
S.RTWRITE
Writes routing data to the
n, s area designated by 8 8.3.2
routing parameters.
SP.RTWRITE

2 – 58
Instruction Tables Multiple CPU dedicated instruction

2.7 Multiple CPU dedicated instruction

2.7.1 Instructions for writing to the CPU shared memory of host CPU

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

S.TO
Writes device data of the
n1, n2, n3, n4, d host station to the host 5 9.1.1
CPU shared memory.
SP.TO

TO
Write to CPU Writes device data of the
shared host station to the host 5
memory CPU shared memory.
TOP
n1, n2, s, n3 9.1.2
DTO Writes device data of the
host station to the host 5
CPU shared memory in
DTOP 32-bit units

2.7.2 Instructions for reading from the CPU shared memory of another CPU

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

Reads data from the

FROM shared memory of
another CPU and stores
the data in the device 5
memory of the CPU
Read from the FROMP performing the FROM
shared n1, n2, d, n3 instruction. 9.2.1
memory of
another CPU
DFRO Reads data from the
shared memory of
another CPU in 32-bit 5
units and stores the data
DFROP in the host station.

Programming MELSEC System Q and L series 2 – 59

Multiple CPU dedicated instruction Instruction Tables

2.7.3 Multiple CPU high-speed transmission dedicated instructions

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

In multiple CPU system,

D.DDWR data stored in a device
specified by host CPU
Writing (s2) or later is stored by
devices to the number of write 10 10.2.1
another CPU points specified by
DP.DDWR (d2+1) into a device
specified by another
CPU (n) (d1) or later.
n, s1, s2, d1, d2
In multiple CPU system,
D.DDRD data stored in a device
specified by another
Reading CPU (d1) or later is
devices from stored by the number of 10 10.2.2
another CPU read points specified by
DP.DDRD (s1+1) into a device
specified by host CPU
(s2) or later.

2 – 60
Instruction Tables System switching instruction for a redundant system

2.8 System switching instruction for a redundant system

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

Switches between the

control system and
System standby system at the 8 11.1.1
SP.CONTSW s, d
switching END processing of the
scan executed with the
SP.CONTSW instruction.

Programming MELSEC System Q and L series 2 – 61

Instructions for special function modules Instruction Tables

2.9 Instructions for special function modules

2.9.1 Instructions for serial communication modules

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning Condition Section

Reading of Reading of received data

data from a from a serial communi-
serial commu- BUFRCVS Un, n1, d1 cation module QJ71C24 12.1.1
nication to the PLC CPU in an
module interrupt program.

GETE
Reading of User registered frames
user regis- Un, s1, s2, d are read from a serial 12.1.2
tered frames communication module
GETEP

PUTE User frames are regis-

Registration or tered to or deleted from a
deletion of Un, s1, s2, d 12.1.3
user frames serial communication
module
PUTEP

PRR Sending of data via the

Transmission serial communication
Un, s, d 12.1.4
of data module using user
frames
PRRP

2.9.2 Instructions for PROFIBUS/DP interface modules

of steps
Number

Subset

Category Instruction Variables Meaning Execution Reference

Condition Section

Data is read from the

BBLKRD
buffer memory of a
Reading of Un, n1, n2, d PROFIBUS/DP interface 12.2.1
data
module and stored in the
BBLKRDP PLC CPU

Data stored in the PLC

BBLKWR
CPU is written to the
Writing of data Un, n1, n2, s buffer memory of a 12.2.2
PROFIBUS/DP interface
BBLKWR module

2 – 62
Instruction Tables Instructions for special function modules

2.9.3 Instructions for ETHERNET interface modules

of steps
Number

Subset
Execution Reference
Category Instruction Variables Meaning
Condition Section

BUFRCV Un, s1, s2, d1, d2 Data received during 12.3.1

fixed buffer communica-
Reading from tion is read from the
fixed buffer
ETHERNET interface
BUFRCVS Un, s1, d1 12.3.2
module

Data stored in the PLC

Writing to fixed CPU is moved to a fixed
buffer BUFSND Un, s1, s2, s3, d1 12.3.3
buffer of an ETHERNET
interface module

Open Open processing for a

OPEN Un, s1, s2, d1 12.3.4
connection connection

Close Close processing for a

connection CLOSE Un, s1, s2, d1 12.3.5
connection

Error codes stored in the

buffer memory of the
ETHERNET interface
Error clear ERRCLR Un, s1, d1 12.3.6
module are cleared and
the "ERR.“ LED is
switched off.

Error codes stored in the

buffer memory of the
Reading of an
ERRRD Un, s1, d1 ETHERNET interface 12.3.7
error code
module are read to the
PLC CPU

Re-initial processing of
Re-initializa-
UINI Un, s1, d1 an ETHERNET interface 12.3.8
tion
module

2.9.4 Instruction for MELSECNET/H

of steps
Number

Subset

Execution Reference
Category Instruction Variables Meaning Condition Section

Pairing setting PAIRSET Jn, s1 Setting of stations for 12.4.1

duplex network

Programming MELSEC System Q and L series 2 – 63

Instructions for special function modules Instruction Tables

2.9.5 Instructions for CC-Link

of steps
Number
Execution Reference
Category Instruction Variables Meaning
Condition Section

RLPASET
Transfer of the parameter
Parameter Un, s1 to s5, d1 settings to the master sta- 12.5.1
setting
tion of CC-Link
RLPASET_P

Reading from Data is read from the

the buffer RIRD buffer memory of another
memory or Un, s, d1, d2 stations CC-Link module 8 12.5.2
from the device or from the device mem-
memory of a ory of that stations PLC
CPU RIRD_P CPU

Writing to the Data is written to the

RIWT
buffer memory buffer memory of another
or to the device Un, s, d1, d2 stations CC-Link module 8 12.5.3
memory of a or to the device memory
CPU of that stations PLC CPU
RIWT_P

Data is read with hand-

RIRCV
Reading from shake from the buffer
an intelligent Un, s1, s2, d1, d2 memory of an intelligent 10 12.5.4
device station device station connected
RIRCV_P to CC-Link

Data is written with hand-

RISEND
Writing to an shake to the buffer mem-
intelligent Un, s1, s2, d1, d2 ory of an intelligent device 10 12.5.5
device station station connected to CC-
RISEND_P Link

Data is moved from the

RITO device memory of the PLC
Writing to CPU to the automatic
automatic updating buffer memory of
Un, n1, n2, n3, d 9 12.5.6
updating buffer the master station. This
memory data is then transferred to
RITO_P another station con-
nected to CC-Link.

Data transmitted from

Reading from RIFR another station to the
automatic automatic updating buffer
Un, n1, n2, n3, d 9 12.5.7
updating buffer memory of the master sta-
memory tion is moved to the device
RIFR_P memory of the PLC CPU.

2 – 64
Configuration of Instructions The structure of an instruction

3 Configuration of Instructions
3.1 The structure of an instruction
Most of the instructions consist of an instruction part and a device part. Other instructions do
not require a device part and thus only consist of the instruction part.

PLUS sd
{
{

Instruction Device
part part

Instruction part
The instruction part describes the functions of the instruction.
^ Addition
PLUS =

Device part
The device part describes the constants or variables to be specified. The device part can com-
prise three items: the source of data (s), the destination of data (d), and the number (n).

3.1.1 Source of data (s)

● The data source designates the devices to be processed by the instruction.

For 16-bit instructions the notation of the data source is s.
For 32-bit instructions its notation is s+1 and s.
● Within the data source constants or variables can be specified.

Constants
Constants specify a constant numerical value to be processed by the instruction. This value is
constantly set by the user written program and cannot be altered during program execution. It
is recommended to index qualify each variable to be used as constant.

Variables
Variables specify a device storing data to be processed by the instruction (also refer to section
3.4 "Programming of variables").
Before an instruction is executed, the data must be stored in the device. The data stored in vari-
ables can be altered during program execution.

Programming MELSEC System Q and L series 3–1

The structure of an instruction Configuration of Instructions

3.1.2 Destination of data (d)

● The data destination designates the devices to store the data after being processed by the
instruction.
For 16-bit instructions the notation of the data destination is d.
For 32-bit instructions its notation is d+1 and d. However, some instructions with 2 devices
require a value to be processed stored in the data destination d before the instruction is
executed. In this case, the result of the operation will be stored in the same device as well.
Example: The addition instruction for BIN 16-bit data.
Here, d first stores data for the operation and then the operation result:

s+d=d
s1 + s2 = d1

● A device for the storage of data has always to be set as data destination.

3.1.3 Number (n)

● The number n specifies how many devices are to be used or how often an instruction is to
be executed.
Example: The BMOV instruction for block data transfer:

Specifies the number of

transfers via the BMOV
instruction

● The value n may range from 0 to 32767. If n is specified 0, the instruction will not be executed.

3–2
Configuration of Instructions Notation of instructions

3.2 Notation of instructions

From the notation certain characteristics of the instructions can be derived.

3.2.1 16/32-bit and pulse

SORT 16-bit processing

SORTP 16-bit processing with pulse
DSORT 32-bit processing
DSORTP 32-bit processing with pulse

3.2.2 MELSEC and IEC

The GX IEC Developer includes several editors for the instructions:

Within these editors the instructions are represented in different notations.

For the selection of an instruction in the

GX IEC Developer this dialog box will
appear.
Depending on the selected library diffe-
rent instructions can be chosen:
ALL: MELSEC and IEC instructions
Project: Functions and Function Blocks
created by the user
Manufacturer: MELSEC instructions
Standard: IEC instructions

Programming MELSEC System Q and L series 3–3

Notation of instructions Configuration of Instructions

For example, this dialog box will appear

when the the manufacturer library is
selected. This listing contains the
"adapted" MELSEC instructions.

The functions of the "pure" and "adapted" instructions are identical. Only their notation differs.

Legend of the extensions within the IEC editor:

Extension in IEC Editor Meaning

_M MELSEC instruction

_P_M Pulse execution of an instruction

_MD Dedicated MELSEC instruction

(also refer to section 3.3 "Programming of dedicated instructions")

_P_MD Pulse execution of a dedicated instruction

_K_MD Use of a constant in a dedicated instruction

_K_P_MD Use of a constant and pulse execution in a dedicated instruction.

_S_MD Dedicated MELSEC instruction for CPUs of MELSEC System Q

_P_S_MD Pulse execution of a dedicated MELSEC instruction for CPUs of MELSEC

System Q

3–4
Configuration of Instructions Notation of instructions

3.2.3 Further characteristics of the instruction notation

The table below contains the symbols that represent several functions within the MELSEC
editor. The column on the right shows the according instruction names within the IEC editor.

Example: MELSEC editor IEC editor

LD$> LD_STRING_GT_M

MELSEC Editor IEC Editor

$ STRING
= EQ
<> NE
<= LE
< LT
>= GE
> GT
+ PLUS
- MINUS
x MULTI
/ DIVID

3.2.4 Specification of the notation

The chapters 5 through 12 that give a detailed description of the instructions contain illustra-
tions of both editors, i.e. both notations. The header line contains the "pure" MELSEC instruc-
tion as it occurs in the MELSEC instruction list.

NOTE The tabular overview at the beginning of each instruction category always represents both
notations.

Programming MELSEC System Q and L series 3–5

Programming of dedicated instructions Configuration of Instructions

3.3 Programming of dedicated instructions

The dedicated instructions are customised instructions that do not only differ in notation from
the pure MELSEC instructions. They also require a particular programming technique for the
different CPUs.
In the MELSEC editor the FLOAT_MD instruction has to be programmed in combination with
the LEDA, LEDC, LEDR instructions. In the IEC editors the dedicated instructions can be pro-
grammed as usual.
Example: Programming of the FLOAT_MD instruction (common execution 16-bit)

MELSEC Instruction List Ladder Diagram IEC Instruction List

Example: Programming of the FLOAT_P_MD instruction

(pulse execution 16-bit, use of a constant in device s)

MELSEC Instruction List Ladder Diagram IEC Instruction List

Refer to the following manuals for further information on the programming of dedicated instruc-
tions:
 GX IEC Developer Reference Manual
 Programming Manual (Dedicated Instructions)

3–6
Configuration of Instructions Programming of variables

3.4 Programming of variables

3.4.1 Programming with the GX IEC Developer

The majority of instructions besides the instruction part also require a device part with specified
variables. These variables contain the values for the execution of the instruction.
According to the selected editor in the GX IEC Developer a different method of programming
of the variables is required.

In the MELSEC editor:

The data registers D100 and D10 can be assigned directly to the variable designation D100
and D10.
The connected PLC automatically detects that the following devices are designated:
D100 = D100 and D101
D10 = D10, D11, D12, D13

In the IEC editor:

In the IEC editor direct devices can only be entered, if actually only this device is to be desig-
nated.
Example: AND D10
Before a DWSUMP_M instruction can be processed, the variables have to be defined in the
header of the program organisation unit (POU).

Example: Header of the IEC IL

var_D100 and var_D10 are entered here as identifiers. The PLC actually does not assign the devices D100 and D10 but inernally allocates free register areas for the variables.

Example: DWSUMP

DWSUMP var_D100, 4, var_D10

s n d
→

32-bit 16-bit array

or
constant

The variable var_D100 is of type DINT (32-bit). The variable var_D10 is of type ARRAY. The
array contains four 16-bit registers of type INT (also refer to section 3.5.2 "Addressing of arrays
and registers in the GX IEC Developer").

Programming MELSEC System Q and L series 3–7

Programming of variables Configuration of Instructions

Specification of the notation

The designation var_D100 or var_D10 in the screenshots indicate that not direct devices are
designated but identifiers. In these cases the variable definition is compulsory! If an instruction
can only be programmed over a variable definition this is explicitely noted.

NOTE As identifier any name can be entered (e.g. Motor1, Indicator). The names var_D100 or var_D10
were selected here for a clear comparison to the programming in the MELSEC editor.

The table of variables at the beginning of any instruction gives an overview of the data types
of the devices for each instruction (the example shows the DWSUM instruction in section
7.5.14).
Variables Data Type
Set Data Meaning
MELSEC IEC
s First number of device storing data to be added. BIN 32-bit ANY32
Array [1..4] of
d First number of device storing result. BIN 64-bit
ANY16
n Number of data blocks to be added. BIN 16-bit ANY16

In GX Works2
The data registers D100 and D10 can be assigned directly to the variable designation D100
and D10.
The connected PLC automatically detects that the following devices are designated:
D100 = D100 and D101
D10 = D10, D11, D12, D13

3–8
Configuration of Instructions Data types

3.5 Data types

The data type determines the number and processing of bits as well as the value range of the
variables.
The following data types exist:

Number of
Data Type Value Range bits

BOOL Boolean 0 (FALSE), 1 (TRUE) 1 bit

INT INTEGER -32768 through 32767 16 bits

DINT Double INTEGER -2147483648 through 2147483647 32 bits

WORD Bit string 16 0 through 65535 16 bits

DWORD Bit string 32 0 through 4294967295 32 bits

Single precision:
32 bits
-2128 < Value ≤ -2-126, 0, 2-126 ≤ Value < 2128
REAL Floating point number
Double precision:
64 bits
-21024 < Value ≤ -2-1022, 0, 2-1022 ≤ Value < 21024

T#-24d-0h31m23s648.00ms
TIME Time value through 32 bits
T#24d20h31m23s647.00ms

STRING Character string max. 50 characters

Hierarchy of data types ANY

ANY

ANY_SIMPLE ARRAY

ANY_NUM ANY_BIT TIME STRING

BOOL

WORD

DWORD

ANY_REAL ANY_INT
REAL INT

DINT

Programming MELSEC System Q and L series 3–9

Data types Configuration of Instructions

Hierarchy of data types ANY16 and ANY32

ANY_16 ANY_32

WORD INT DWORD DINT

Data type Meaning

ANY Any data type

ANY_SIMPLE Simple data type

ANY_NUM Numeric data type

ANY_REAL Floating point number

ANY_INT Integer data type

ANY_BIT Bit processing data type

ANY_16 Any 16-bit data type

ANY_32 Any 32-bit data type

TIME Time

STRING Character string

REAL Floating point number

INT Integer value

DINT Double integer value

BOOL Boolean value

WORD Word (16 bits)

DWORD Double word (32 bits)

ARRAY Array

3 – 10
Configuration of Instructions Data types

3.5.1 Processing of data

Processing of bit data

A bit device (X, Y, M, K, S, B or F) can obtain two states (ON = 1 or OFF = 0). Its status therefore
can be represented by one bit (1 or 0). Bit processing is always performed, if a specified bit
device is addressed by the program. For the processing of 16-bit or 32-bit instructions several
bit devices are grouped in blocks of 16 or 32 device numbers (i.e. 16 or 32 addresses).
● Usage of bit devices
A bit device (e.g. inputs, outputs, relays) consists of one bit.

Ladder Diagram Processing

M0 is a bit device

Y10 is a bit device

● Usage of word devices

The CPUs of the MELSEC System Q and L series support the addressing of each single
bit in a word device.

b15 to b0
Word device 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

Each single bit represents the

status OFF or ON by 0 or 1.

The bits have to be addressed in hexadecimal format. For example, the bit 5 (b5) in D0 is
addressed D0.5. Bit 10 in D0 is addressed D0.A.
Single bits of timers, counters, and retentive timers can not be addressed.

Ladder Diagram Processing

Bit addressing within a word

device.
(bit 5 (b5) in D0 is set)

Bit addressing within a word

device.
(The status of the contact
D0.5 depends on the I/O sta-
tus of bit 5 in word device D0)

 Usage of bit blocks

Single bits can be grouped in blocks of four and thus process word data. The detailed
description is given in the following sections, "Processing of word data (16/32 bits)".

Programming MELSEC System Q and L series 3 – 11

Data types Configuration of Instructions

Processing of word data (16 bits)

● Usage of bit devices
Bit devices are capable of processing word data provided that the number of bit devices
(addresses) is determined. Up to 16 bits can be processed in blocks of 4 bits each. The
length of each block (i.e. the digit designation) is determined by K1 to K4.
K1X0 4 addresses from X0 through X3
K2X0 8 addresses from X0 through X7
K3X0 12 addresses from X0 through XB
K4X0 16 addresses from X0 through XF

XF bis XC XB bis X8 X7 bis X4 X3 bis X0

K1
4 bits
K2
8 bits
K3
12 bits
K4
16 bits

– Designation of bit blocks for s

The table below shows the range of values processed as source data for the digit
designation of source data (s)

Digit Designation 16-bit instruction

K1 (4 digits) 0 to 15

K2 (8 digits) 0 to 255

K3 (12 digits) 0 to 4095

K4 (16 digits) -32768 to 32767

The bit addresses not used are set to 0.

Ladder Diagram Processing

16-bit instruction
K1X0 X3 X2 X1 X0

set to 0
b15 b4 b3 b2 b1 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0
→

Source data

NOTE For the block by block addressing of bit devices the number of the first bit device (initial device
number) can be designated at any random value.
Block by block addressing cannot be made for the direct access I/Os (DX, DY).

3 – 12
Configuration of Instructions Data types

– Designation of bit blocks for d

The digit designation for the destination data (d) determines the address range the data
is to be written to. The bit addresses exceeding the determined address range remain
ignored.

Ladder Diagram Processing

Numeric values as source data (s)

1 2 3 4
H1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

M15 M8 M7 M0
K2M0 0 0 1 1 0 1 0 0
Data destination (d) is not changed 3 4

Word device as source data (s)

b15 b8 b7 b0
D0 1 1 1 0 1 0 1 0 1 0 0 1 1 1 0 1

M115 M108M107 M100

K2M100 1 0 0 1 1 1 0 1
Data destination (d) is not changed

● Usage of word devices

Word devices are determined by an address. This address comprises 16 bits.

Programming MELSEC System Q and L series 3 – 13

Data types Configuration of Instructions

Processing of double word data (32 bits)

● Usage of bit devices
Bit devices are capable of processing word data provided that the number of bit devices
(addresses) is determined. Up to 32 bits can be processed in blocks of 4 bits each. The
length of each block (i.e. the digit designation) is determined by K1 to K8.
K1X0 4 addresses from X0 through X3
K2X0 8 addresses from X0 through X7
K3X0 12 addresses from X0 through XB
K4X0 16 addresses from X0 through XF
K5X0 20 addresses from X0 through X13
K6X0 24 addresses from X0 through X17
K7X0 28 addresses from X0 through X1B
K8X0 32 addresses from X0 through X1F

X1F X1C X1B X18 X17 X14 X13 X10 XF XC XB X8 X7 X4 X3 X0

K1
4 addresses
K2
8 addresses
K3
12 addresses
K4
16 addresses
K5
20 addresses
K6
24 addresses
K7
28 addresses
K8
32 addresses

– Designation of bit blocks for s

For a specification of the digit designation the range of the values processed as source
data is listed in the table below:

Digit Designation 32-bit Instruction

K1 (4 digits) 0 to 15

K2 (8 digits) 0 to 255

K3 (12 digits) 0 to 4095

K4 (16 digits) -32768 to 32767

K5 (20 digits) 0 to 1048575

K6 (24 digits) 0 to 16777215

K7 (28 digits) 0 to 268435455

K8 (32 digits) -2147483648 to 2147483647

The bit addresses not used are set to 0.

3 – 14
Configuration of Instructions Data types

Ladder Diagram Processing

32-bit instruction K1X0 X3 X2 X1 X0

set to 0
b15 b4 b3 b2 b1 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0
← Source data D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(s) b31 b16

set to 0

NOTE For the block by block addressing of bit devices the number of the first bit device (initial device
number) can be designated at any random value.
Block by block addressing cannot be made for the direct access I/Os (DX, DY).

– Designation of bit blocks for d

The digit designation for the destination data (d) determines the address range the data
is to be written to. The bit addresses exceeding the determined address range remain
ignored.

Ladder Diagram Processing

Numeric values as source data (s) H76123456

0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
3 4 5 6
0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0
7 8 1 2
K5M0
M15 M8 M7 M0
0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
Data destination (d) M31 M20 M19 M16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
is not changed

Word device as source data (s)

b15 b8 b7 b0
D0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0

b15 b8 b7 b0
D1 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0

M25 M18 M17 M10

1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1
M41 M30 M29 M26
Data destination (d)
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
is not changed

Programming MELSEC System Q and L series 3 – 15

Data types Configuration of Instructions

● Usage of word devices

Double word devices comprise two 16-bit devices.
According to the programming software and selected editor double word devices are
programmed differently.
– In the MELSEC editor of the GX IEC Developer

Ladder Diagram Explanation

D0 and D1 are used

Instruction for the 32-bit data transfer

– In the IEC editor of the GX IEC Developer

Before a 32-bit device can be programmed in the IEC editor of the GX IEC Developer, the
variables have to be defined in the header of the program organisation unit (POU).
The data types DWORD and DINT are of the 32-bit type.

Ladder Diagram Explanation

var_D0 must be declared as

DINT or DWORD

Instruction for the 32-bit data transfer

– In the editor of the GX Works2

Ladder Diagram Explanation

D0 and D1 are used

Instruction for the 32-bit data transfer

3 – 16
Configuration of Instructions Data types

Processing of data of the data type REAL

Data of the REAL type are floating-point numbers. Whether instructions processing floating-
point numbers should be performed with single precision (32-bit) or double precision (64-bit)
can be set in the PLC parameters. Only word devices are capable of storing floating-point num-
bers.
● Single precision floating-point data
Instructions which deal with single precision floating-point data designate devices which are
used for the lower 16 bits of data. The 32-bit floating-point number is stored in two successive
16-bit registers (designated device number) and (designated device number + 1).

M0
EMOV R100 D0

Designation of 2 points of word devices D0 and D1

Designation of 2 points of R100 and R101
32-bit floating-point data transfer instruction

NOTES Instructions processing floating-point numbers begin with an E (e.g. EMOV).

Two word devices are required for storing a single precision floating-point number. Therefore,
it is divided into the following components:
[Sign] 1.[Mantissa] x 2[Exponent]
The bit configuration of the registers and their contents are shown in the figure below:

>! >! to > ! > to >$ ># to >

b31 b30 to b23 b22 to b0
Sign Exponent Mantissa

– Sign of the floating-point number: The sign is stored in b31.

0 = Positive
1 = Negative
– Exponent: The n from 2n is binary stored from b23 through b30.
The meaning of the binary value n is shown in the following figure.

b23 to b30 FFH FEH FD H 81H 80H 7FH 7EH 02H 01H 00H
n free 127 126 2 1 0 -1 -125 -126 free

– Mantissa: The 23 bits from b0 to b22, represents the XXXXXX... at binary 1.XXXXXX....

Programming MELSEC System Q and L series 3 – 17

Data types Configuration of Instructions

Example: Representation of the value "10" as floating-point number.

The "x" in (nnn)X designates the base of the number system.
(10)10 → (1010)2 → (1.010000... x 23)2
Sign: Positive → 0
Exponent: 3 → 82H → (10000010)2
Mantissa: (010 00000 00000 00000 00000)2
The value "10" will be stored as 41200000H (see following figure).

Sign Exponent Mantissa

                               

"      

Example: Representation of the value "0.75" as floating-point number.

The "x" in (nnn)X designates the base of the number system.
(0.75)10 → (0.11)2 → (1.100... x 2-1)2
Sign: Positive → 0
Exponent: -1 → 7EH → (01111110)2
Mantissa: (100 00000 00000 00000 00000)2
The value "0.75" will be stored as 3F400000H (see following figure).

Sign Exponent Mantissa

                               

! . "     

NOTE Post decimal positions for binary data are represented as follows:
Example: (0.1101)2

0, 1 1 0 1

Bit significance: Bit significance: Bit significance: Bit significance:

2-1 2-2 2-3 2-4

(0.1101)2 = 2 -1+2 -2+2 -4= 0.5 + 0.25 + 0.0625 = (0.8125)10

3 – 18
Configuration of Instructions Data types

● Double precision floating-point data

Instructions which deal with double precision floating-point data designate devices which
are used for the lower 16 bits of data. The 64-bit floating-point number is stored in four
successive 16-bit registers (designated device number) to (designated device number + 3)

M0
EDMOV R100 D0

Designation of 4 points of word devices (D0, D1, D2, D3)

Designation of 4 points of R100, R101, R102 and R103

64-bit floating-point data transfer instruction

NOTE Instructions processing floating-point numbers begin with an E (e.g. EMOV).

Four word devices are required for storing a double precision floating-point number.
Therefore, it is divided into the following components:
[Sign] 1.[Mantissa] x 2[Exponent]
The bit configuration of the registers and their contents are shown in the figure below:.

>$! >$ to ># ># to >$ ># to >

b63 b62 to b52 b51 to b0
Sign Exponent Mantissa

– Sign of the floating-point number: The sign is stored in b63.

0 = Positive
1 = Negative
– Exponent: The n from 2n is binary stored from bits b52 through b62.
The meaning of the binary value n is shown in the following figure.

b52 – b62 7FFH 7FEH 7FDH 400H 3FFH 3FEH 3FDH 3FCH 02H 01H 00H
Free
n Free
1023 1022 2 1 0 1 2 1021 1022

– Mantissa: The 52 bits from b0 to b51, represents the XXXXXX... at binary 1.XXXXXX....

Programming MELSEC System Q and L series 3 – 19

Data types Configuration of Instructions

NOTES The CPU module floating decimal point data can be monitored using the monitoring function of
a peripheral device.
When floating-point data is used to express 0, the following bits are turned to 0:
Single precision floating-point data: bits b0 to b31
Double precision floating-point data: bits b0 to b63
The setting range of floating decimal point data is as follows:
Single precision floating-point data: -2128 < Value ≤ -2 -126, 0, 2 -126 ≤ Value < 2128
Double precision floating-point data: -21024 < Value ≤ -2 -1022, 0, 2 -1022 ≤ Value < 21024
For operations when a real number is out of range and operations when an invalid value is input,
an error occurs. For more informations refer to the QnUCPU User's Manual (Function Expla-
nation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Expla-
nation, Program Fundamentals).
Do not specify "-0" in floating-point data. (In this case the most significant bit of the floating-point
real number is "1"). An operation error will occur with the following CPU modules, if floating-point
operation is performed with "–0".
– Basic model QCPU (CPUs with first five digits of serial No. are "04122 or higher can perform
floating-point operation)
– High Performance model QCPU where internal operation is set to single precision (setting in
PLC parameter dialog box of the PLC system)
– Process CPU of the MELSEC System Q
– Redundant CPU of the MELSEC System Q
– Universal model QCPU of the MELSEC System Q
– L-series CPUs
The High Performance model QCPU with the internal processing set to "double precision" (dou-
ble precision is set by default for the floating-point operation processing) internally convert the
value "–0" to 0 to perform a floating-point operation. Therefore an operation error does not occur.

3 – 20
Configuration of Instructions Data types

● Floating-point data in the IEC Editor

Since the REAL IEC function uses the data type REAL as input/output but the MELSEC
instructions use the data type DINT, the following functions are provided to compensate this
difference:

The conversion from the IEC data type REAL into the MELSEC data type is performed by
the instruction REAL_TO_M_REAL (REAL_TO_M_REAL_E).
The conversion from the MELSEC data type into the IEC data type is performed by the
instruction M_REAL_TO_REAL (M_REAL_TO_REAL_E).
Example: For the application of dedicated instructions that process the data type REAL and
for IEC instructions the REAL to REAL conversion ist required.

32-bit 32-bit
MITSUBISHI-REAL IEC-REAL
(DINT) (REAL)
MLIB SLIB

When programming in in GX IEC Developer the BMOV_E instruction can be used to switch
off the variable check. No additional code is created.
Any type of data can be specified in s, even arrays are possible. n holds the number of 16-
bit data to copy.

Programming MELSEC System Q and L series 3 – 21

Data types Configuration of Instructions

3.5.2 Addressing of arrays and registers in the GX IEC Developer

Addressing of 32-bit registers

The addressing of 32-bit registers (data type DINT, DWORD) requires a variable definition in
the header of the program organisation unit (POU).
In the following example the DMOV instruction requires two 16-bit registers for moving one
32-bit data word. For the addressing in the MELSEC editor of the GX IEC Developer only the
initial registers (here D10, D20) are designated. Each required second 16-bit register (D11,
D21) is addressed automatically by the compiler.
In the IEC editor of the GX IEC Developer instead of the initial register a variable (here
var_D10, var_D20) with a specific data type (here DINT (32 bits)) has to be defined in the
header of the program organisation unit according to the header of the instruction. For these
variables the compiler assigns corresponding addresses internally.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Header of the DMOV instruction

Header of the program organisation unit (POU)

3 – 22
Configuration of Instructions Data types

Addressing of arrays
For the programming of instructions that use an array with array elements as input or output
devices (16-bit registers) the variables in the header of the program organisation unit have to
be defined according to the header of the instruction.
The individual array elements are addressed by specifying the array and the array element in
square parentheses (var_xx[x]).
The figures below show the addressing via arrays for the positioning instruction for rotary tables
(ROTC):

MELSEC Instruction List Ladder Diagram IEC Instruction List

Header of the ROTC instruction

Header of the program organisation unit (POU)

You can infer from the header of the ROTC instruction that the input device range s consists of
3 array elements of the type ANY16 and the output device range consists of 8 array elements
of the type BOOL.
In the GX Works2 and in the MELSEC editor of the GX IEC Developer for the input/output
device ranges s and d only each of the initial devices D200 and M0 is specified. The compiler
addresses the registers D200 through D202 for s and M0 through M7 for d.
In the IEC editors arrays must be defined for s and d. The input array s is defined as var_D200.
It consists of 3 array elements (var_D200[0] – var_D200[2]) of the type INT (16-bit integer). The
output array d is defined as var_M0. It consists of 8 array elements (var_M0[0] – var_M0[7]) of
the type BOOL (bit). For these variables the compiler assigns corresponding addresses inter-
nally.

Programming MELSEC System Q and L series 3 – 23

Data types Configuration of Instructions

NOTE Arrays can also be addressed variably. In this case instead of the array element number in
square brackets any identifier for example [Number] is entered. "Number" must be declared in
the header of the program organisation unit. Then a value corresponding to the according array
element can be moved to the register "Number".

Instructions for the array address/ initial address conversion

The instruction set for the conversion of an output array into an initial address of a device range
comprises three instructions.
The instruction GET_INT_ADDR converts an output array with array elements of the type INT
(16-bit integer) into an initial address of a device range.
The instruction GET_WORD_ADDR converts an output array with array elements of the type
WORD (16-bit word) into an initial address of a device range.
The instruction GET_BOOL_ADDR converts an output array with array elements of the type
BOOL (bit) into an initial address of a device range.

Ladder Diagram IEC Instruction List

After the conversion the array elements can be processed as individual devices. Therefore, the
variable definition in the header of the program organisation unit is not required.
In the program with the ROTC instruction shown above instead of the array elements
var_M0[0] – var_M0[7] the relays M0 through M7 can be used.
The methods of addressing devices in GX Works2 and the GX IEC Developer are identical.
These instructions only convert output arrays. Input arrays must be addressed and declared
as previously described.

3 – 24
Configuration of Instructions Data types

3.5.3 Usage of character string data (STRING)

The data string STRING ($) processes character strings.

Character strings are all entered characters (max. 50 characters) up to the NULL code (00H).

● If the entered character is the NULL code (00H)

For the storage of the NULL code a data word (register) is required.

Entered Instruction
D0 00H
NULL code for moving
(00H) character
strings

● If the number of characters contained in the string is even

The storage of character strings with an even number of characters requires a number of
data words calculated by the following formula:
(Number of characters / 2) + 1

If for example the character string "ABCD" is to be moved to D0, the registers D0 through
D1 are required for the string and the register D2 is required for the NULL code indicating
the end of string.

Entered Instruction
chracter string for moving D0 42H 41H
with 4 characters character D1 44H 43H
strings D2 00H

Programming MELSEC System Q and L series 3 – 25

Data types Configuration of Instructions

● If the number of characters contained in the character string is odd

The storage of character strings with an uneven number of characters requires a number of
data words calculated by the following formula:
(Number of characters +1) / 2

If for example the character string "ABCDE" is to be moved to D0, the registers D0 through
D2 are required for the character string. The NULL code indicating the end of string is written
to the upper byte of D2.

Entered Instruction D0 42H 41H

character string for moving
D1 44H 43H
with 5 characters character
strings D2 00H 45H

3 – 26
Configuration of Instructions Index qualification

3.6 Index qualification

Overview of indexing
● Index qualification is an indirect addressing method of a device through an index register.
For the index qualification within a program the device obtains the directly entered device
number plus the contents of the index register as adress.
● Indexing with 32-bit index registers in addition to 16-bit index registers is available with the
Universal model QCPU and LCPU.

Indexing with 16-bit index registers

● Example of indexing
Each index register can be set between –32768 and 32767.
The program shown below gives an example of the index qualification. In the first program
line the value –1 is assigned to the index register Z0. This register serves as index for D10
in the second program line. Therefore, D0 stores the value of D9 (D10Z = D(10-1) = D9).

Ladder diagram Explanation

X0
The constant -1 is stored in the index
MOV K 1 Z0
register Z0.
X0
MOV D10Z0 D0 The data from the index register
designated Z0 (D10+Z0(-1)=D9) are
stored under D0.

Indexing

● Devices that can be designated by index qualification

With the exception of the restrictions noted below, Indexing can be used with devices used
with contacts, coils, basic instructions, and application instructions.
– Devices that can not be designated by index qualification

Device Meaning
E Floating point number
$ Character string
. Bit addressing of word devices
FX, FY, FD Function devices
P Pointers used as label
I Interrupt pointers used as label
Z Index registers
S Step relays
TR SFC transfer devices 1)
BL SFC block devices 1)

1 SFC transfer devices and SFC block devices are devices for SFC use.
Refer to the following manual for how to use these devices: MELSEC-Q / L / QnA Programming Manual
(SFC)

Programming MELSEC System Q and L series 3 – 27

Index qualification Configuration of Instructions

– Devices with limits for use with index registers

Device Meaning Application Example

T Only the registers Z0 and Z1 can be used for
addressing timer contacts and coils. T0Z0 K100
T1Z1

C Only the registers Z0 and Z1 can be used for

addressing counter contacts and coils. C0Z1 K100
C1Z0

NOTES There are no restrictions on the addressing of current values of timers and counters.

Ladder Diagram Explanation

Setting value of timer.
X0 Index qualification not supported.
K100
T0

Current value of timer.

SM400 Index qualification supported.
BCD T0Z4 K4Y30
Setting value of counter.
X1 K10 Index qualification not supported.
C100
Current value of counter.
SM400 Index qualification supported.
BCD C100Z6 K2Y40

● A case where indexing has been performed, and the actual process device, would be as
follows:
(When Z0 = 20 and Z1 = 5)

Ladder example Actual Process Device

X0
MOV K20 Z0 X1
MOV K2X64 K1M33
Description
MOV K 5 Z1
K2X50Z0 K2X(50 + 14) = K2X64

X1 Converts K20 into a hexadecimal number.

MOV K2X50Z0 K1M38Z1 K1M38Z1 K1M(38 - 5) = K1M33

X0
MOV K20 Z0 X1
MOV D20 K3Y12A
Description
MOV K 5 Z1
D0Z0 D (0 + 20) = D20
K3Y12FZ1 K3Y(12F - 5) = K3Y12A
X1
MOV D0Z0 K3Y12FZ1
Hexadecimal number

3 – 28
Configuration of Instructions Index qualification

Indexing with 32-bit (Universal model QCPU (excluding Q00UJCPU) and LCPU)
A method of speciyfing index registers in indexing with 32-bit can be selected from the following
two methods.
● Specifing the index registers’ range used for indexing with 32-bit.
● Specifing the 32-bit indexing using “ZZ” specification.

NOTES 32-bit indexing with the "ZZ" specification is only available for the following CPU modules. See
the programming tool operating manual for the available programming tools:
 The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher (excluding
Q00UJCPU)
 QnUDE(H)CPU
 LCPU

● Example of specifying the range of index registers for use of 32-bit indexing.
Each index register can be set between -2147483648 and 2147483647.

Ladder diagram Explanation

X0
DMOV K40000 Z0 Stores 40000 at Z0.

X0
MOV ZR10Z0 D0 Stores the data of
ZR10Z0 = ZR{10+40000} = ZR40010 at D0.

Indexing

– Specification method
For indexing with a 32-bit index register, specify the head number of an index register to
be used on the Device tab of the Q parameter setting screen.

GX Works2

NOTES When the head number of the index register used is changed on the Device tab of the Q param-
eter setting screen, do not change the parameters only or do not write only the parameters into
the programmable controller. Be sure to write the parameter into the programmable controller
with the program.
When the parameter is forced to be written into the programmable controller, an error of CAN'T
EXE. PRG. occurs. (Error code: 2500)

Programming MELSEC System Q and L series 3 – 29

Index qualification Configuration of Instructions

– Device that indexing can be used

Indexing can be used only for the device shown below.

Device Meaning
ZR Serial number access format file register
D Extended data register (D)
W Extended link register (W)

– Usable range of index registers

The following table shows the usable range of index registers for indexing with 32-bit index
registers. For indexing with 32-bit index registers, the specified index register (Zn) and the
next index register of the specified register (Zn+1) are used. Be sure not to overlap index
registers to be used.

Setting Value Index Registers to be Setting Value Index Registers to be

used used
Z0 Z0, Z1 Z10 Z10, Z11
Z1 Z1, Z2 Z11 Z11, Z12
Z2 Z2, Z3 Z12 Z12, Z13
Z3 Z3, Z4 Z13 Z13, Z14
Z4 Z4, Z5 Z14 Z14, Z15
Z5 Z5, Z6 Z15 Z15, Z16
Z6 Z6, Z7 Z16 Z16, Z17
Z7 Z7, Z8 Z17 Z17, Z18
Z8 Z8, Z9 Z18 Z18, Z19
Z9 Z9, Z10 Z19 Cannot be specified

– An example of indexing and the actual process device are as follows.

(When Z0 (32-bit) = 100000 and Z2 (16-bit) = –20)

Ladder example Actual Process Device

X0 
DMOV K100000 Z0   
Description
MOV K-20 Z2
  
X1
  
MOV ZR1000Z0 D30Z2

3 – 30
Configuration of Instructions Index qualification

● Example of specifying 32-bit indexing with “ZZ” specification.

One index register can specify 32-bit indexing by using “ZZ” specification such as “ZR0ZZ4”.
Following figure shows an example.

Ladder diagram Explanation

M0
DMOVP K100000 Z4 Stores 100000 at Z4 and Z5.

M0
MOVP K100 ZR0ZZ4 Indexing ZR device with 32-bit index
registers (Z4 and Z5)
ZR (0+100000) =ZR100000

– Specification method
To perform 32-bit indexing by using “ZZ” specification, select “Use of ZZ” in “Indexing
Setting for ZR Device” in PC parameter.

– Device that indexing can be used

The following device is available for indexing.

Device Meaning
ZR Serial number access format file register
D Extended data register (D)
W Extended link register (W)

Programming MELSEC System Q and L series 3 – 31

Index qualification Configuration of Instructions

– Usable range of index registers

The following table shows the usable range of index registers in 32-bit indexing used “ZZ”
specification. The 32-bit indexing with “ZZ” specification is specified as the format ZRmZZn.
Specifying ZRmZZn enables Zn and Zn+1 of 32-bit values to index the device number.
Index Registers to be Index Registers to be
"ZZ" specification 1) "ZZ" specification 1)
used used
ZZ0 Z0, Z1 ZZ10 Z10, Z11
ZZ1 Z1, Z2 ZZ11 Z11, Z12
ZZ2 Z2, Z3 ZZ12 Z12, Z13
ZZ3 Z3, Z4 ZZ13 Z13, Z14
ZZ4 Z4, Z5 ZZ14 Z14, Z15
ZZ5 Z5, Z6 ZZ15 Z15, Z16
ZZ6 Z6, Z7 ZZ16 Z16, Z17
ZZ7 Z7, Z8 ZZ17 Z17, Z18
ZZ8 Z8, Z9 ZZ18 Z18, Z19
ZZ9 Z9, Z10 ZZ19 Cannot be specified
1refers to device name (ZR) for indexing target

– Following example shows the 32-bit indexing using the “ZZ” specification and the actual
processing device:
(When Z0 (32-bit) = 100000 and Z2 (16-bit) = –20)

Ladder example Actual Process Device

X1
X0 MOV ZR101000 D10
DMOV K100000 Z0

END
MOV K-20 Z2
Description
X1
MOV ZR1000ZZ0 D30Z2 ZR1000ZZ0 ZR(1000+100000)=ZR101000
D30Z2 D(30-20)=D10

– Available functions for “ZZ” specification

 Specifying devices in program instruction
 Monitoring device registrations
 Testing devices execution type
 Testing devices with conditions
 Setting monitor conditions
 Tracing sampling (Trace point (specifing devices), trace target device)
 Data logging function (Sampling interval (specifying devices), logging target data)

NOTES ZZn cannot be used alone as a device like “DMOV K100000 ZZ0”. When setting values of index
registers to specify 32-bit indexing with “ZZ” specification, set the value of Zn (Z0~Z19).
ZZn alone cannot be used as target for data transfer.

3 – 32
Configuration of Instructions Index qualification

Index modification using extended data register (D) and extended link register (W)
(Universal model QCPU (excluding Q00UJCPU) and LCPU)
Like index modification using data register (D) and link register (W) of internal user device, a
device can be specified by index modification within the range of the extended data register (D)
and extended link register (W).

Index modification in internal

Image of D device
User program user device

Z0=0
D100 IInternal user
device
MOV K1234

D1100
Z0=1000

Z1=0 Extended data

D20000
register
MOV K1234

D22000
Z1=2000

Index modification in
extended data register

● Index modification where the device number crosses over the boundary between the internal
user device and the extended data register (D) or extended link register (W)
The specification of index modification where the device number crosses over the boundary
between the internal user device and the extended data register (D) or extended link register
(W) cannot be made. If doing so, an error occurs when the device range check is enabled
at index modification (Error code 4101).

Index modification in internal

Image of D device
User program user device

Z0=0
D100 Internal user
device
MOV K1234

Extended data
D20100
Z0=20000 register

Index modification where the device number

crosses over the boundary between the
internal user device and the extended data
register is not possible.

Programming MELSEC System Q and L series 3 – 33

Index qualification Configuration of Instructions

● Index modification where the device number crosses over the boundary among the file
register (ZR), extended data register (D), and extended link register (W)
Index modification where the device number crosses over the boundary among the file
register (ZR), extended data register (D), and extended link register (W) will not cause an
error. However, an error occurs if the index modification result of file register (ZR), extended
data register (D), and extended link register exceeds the file register range (Error code 4101).

Index modification where the device

number crosses over the boundary
among the file register (ZR), extended
data register (D) will not cause an error.. File register files
User program

File register (8 k)
ZR100
Z0=0
MOV K1234
Z0=10000
D14196
Extended data
register (D)
D20000
Z1=0 (8 k)
D12288–
MOV K1234 Z20000Z1

Z1=4000 Extended link

W2DC0
register (W)
(8 k)
Index modification where the device number W2000–
crosses over the boundary between the
extended data register (D), and extended link
register (W) will not cause an error.

Extended link register exceeds

the file register range. .
Z1=10000

3 – 34
Configuration of Instructions Index qualification

Other index modifcations

● Bit data
Devices can as well be index qualified for the digit designation. The block length of the digit
designation can not be affected.

Ladder Diagram Explanation

BIN K4X0Z2 D0
Input of device numbers via index registers.
If Z2=3 then X(0+3) = X3.

BIN K4Z3X0 D0
This input would designate the block length of the digit
designation.
This designation is not supported.

● Both I/O numbers and buffer memory number can be performed indexing with intelligent
function module devices1)

Ladder Diagram Explanation

MOV U10Z1\G0Z2 D0

If Z1=2 and Z2=8, then

U(10+2)\G(0+8)=U12\G8

● Both network numbers and device numbers can be performed indexing with link direct
devices1)

Ladder Diagram Explanation

MOV J1Z1\K4X0Z2 D0

I If Z1=2 and Z2=8, then

J(1+2)\K4X(0+8)=J3\K4X8

● When indexing is used for multiple CPU shared devices, indexing for the head I/O numbers
of CPU modules and indexing for the CPU shared memory address are automatically
executed.

Ladder Diagram Explanation

MOV U3E0Z1\G0Z2 D0

If Z1= 2 and Z2 = 8, then

U3E(0+2)\G(0+8)= U3E2\G8

NOTE For the intellingent function module device, link direct device and the multiple CPU shared
device refer to the QnUCPU User’s Manual (Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User’s Manuall (Function Explanation, Program Fundamentals).

Programming MELSEC System Q and L series 3 – 35

Index qualification Configuration of Instructions

● Index modification using extended data register (D) and extended link register (W) by 32
bits (Universal model QCPU(except Q00UJCPU) and LCPU)
Like index modification using file register (ZR), index modification using extended data
register (D) and extended link register (W) by 32 bits can be performed by the following two
methods:
– Specifing the index registers’ range used for indexing with 32-bit.
– Specifing the 32-bit indexing using “ZZ” specification.

NOTES 32-bit indexing with the "ZZ" specification is only available for the following CPU modules
(also refer to the User’s manuals of the programming tool used):
 QnU(D)(H)CPU with first five digits of the serial No. is “10042” or higher (excluding
Q00UJCPU)
 QnUDE(H)CPU
 LCPU

3 – 36
Configuration of Instructions Index qualification

Precautions on performing indexing

● Performing indexing between the FOR and NEXT instructions
Pulses can be output between the FOR and NEXT instructions by use of the edge relay (V).
However, pulse output using the PLS/PLF/pulse (P) instruction is not allowed.

When edge relay is used When edge relay is not used

(M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.)

SM400 SM400
MOV K0 Z1 MOV K0 Z1

FOR K10 FOR K10

X0Z1 V0Z1 X0Z1
M0Z1 PLS M0Z1
SM400 SM400
INC Z1 INC Z1

NEXT NEXT

NOTES The ON/OFF data of X0Z1 is stored by the edge relay V0Z1. For example, the ON/OFF data of
X0 is stored by V0, and that of X1 by V1.

● Performing indexing with the CALL instruction

Pulses can be output with the CALL instruction by use of the edge relay (V). However, pulse
output using the PLS/PLF/pulse (P) instruction is not allowed.

When edge relay is used When edge relay is not used

(M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.)

SM400 SM400
MOV K0 Z1 MOV K0 Z1

CALL P0 CALL P0

SM400 SM400
MOV K1 Z1 MOV K1 Z1

CALL P0 CALL P0

FEND FEND
X0Z1 V0Z1 X0Z1
P0 M0Z1 P0 PLS M0Z1

RET RET

Programming MELSEC System Q and L series 3 – 37

Index qualification Configuration of Instructions

● Device range check during indexing

– Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU
Device range checks are not conducted during indexing.
Therefore, when the data after index modification exceed the user specified device range,
the data is written to another device without causing an error.
Note, however, that when the data after index modification is written to the device for
system use exceeding the user specified device range, an error occurs. (Error code: 1103)
Take extra precaution when using indexing in programming.

– Universal model QCPU and LCPU

The device range is checked for indexing.
With changing the settings of the PLC parameter, the device range is not checked.
● Changing indexing with 16-bit index register for indexing with 32-bit index register
For changing indexing with 16-bit index register for indexing with 32-bit index register, check
if the program has enough spaces for indexing. For indexing with 32-bit index registers, the
specified index register (Zn) and the next index register of the specified register (Zn+1) are
used. Be sure not to overlap index registers to be used.

3 – 38
Configuration of Instructions Indirect designation (GX Works2 only)

3.7 Indirect designation (GX Works2 only)

With indirect designation, a device address is stored in a word device. In the sequence program
the device address is not directly designated. For operations concerning this device address
the word device is used instead. This method can be used when the index register is insuffi-
cient.
The device which contains the device address for indirect designation has the prefix "@". For
example, designation of @D100 will make the contents of D100 and D101 the device address.
The address of the device performing indirect designation can be stored in the word device with
the ADRSET instruction.

NOTE The ADRSET instruction is not supported by the GX IEC Developer.

Ladder Diagram Description

W100 is stored in D100 and D101

The constant 1234 is

written to the adress which
is stored in D100 and D101.

D0
D1
Reads the contents of
D100 and D101

D100 W100
D101 W100 1234

A list of devices which are capable of indirect designation is shown below.

Device Type Indirect designation Example of indirect designation
Bit devices Incapable —
Internal devices
(System, user)  @D100
Word devices Capable
 @D100Z2 (Index qualification)
Bit devices Incapable —
Link direct device
Capable
 @J1\W10
Word devices
(The ADRSET instruction  @J1Z1\W10Z2 (Index qualification)
cannot be used to write  @U10\G0
Special function module the indirect adress)
 @U10Z1\G0Z2 (Index qualification)
Index register Zn Incapable —
 @R0, @ZR20000
File register Capable  @R0Z1, @ZR20000Z1
(Index qualification)
Extended data register (D)  @D1000
Capable
Extended link register (W)  @W1000
Nesting —
Pointer —
Incapable
Constants —
Other —

Programming MELSEC System Q and L series 3 – 39

Indirect designation (GX Works2 only) Configuration of Instructions

To store an address for indirect designation, two words are used. Therefore, to decrease or
increase a stored adress for indirect designation by arithmetic instructions, the addition or sub-
traction of 32-Bit data is required.
In the following program examples the device which stores the device for indirect designation
is incremented and decremented by 32-Bit instructions. By doing so, the address of the device
for indirect designation is increased resp. decreased by 1.

Ladder Diagram Description

Device which contains the address of the

device for indirect designation

32-bit instruction to increment D0

(Adds 1 to the data at D0 and D1)

Ladder Diagram Description

Device which contains the address of the

device for indirect designation

32-bit instruction to decrement D0

(Subtracts 1 from the data at D0 and D1)

3 – 40
Configuration of Instructions Indirect designation (GX Works2 only)

Indirect designation of extended data register (D) and extended link register (W)
Indirect designation can be performed in the extended data register (D) and extended link reg-
ister (W).
Note that when indirect designation is performed to the extended data register (D) and data
register (D) in internal device or to the extended link register (W) and link register (W) in internal
device, the areas of the internal user device and extended data register (D) or extended link
register (W) are not treated as a sequence.

Internal user device

ADRSET D12000 D100 Setting an address "D12000" D0

Data register
to D100 and D101.
D12000
"1000" is added to the D12287
address D12000 in D100 and
D+ K1000 D100 D102 D101. Result is stored in
D102 and D103.

MOV K1234 @D102

File register files

File register

D12288
Extended data
register (D)
D13000
Since the areas of the data register
and extended data register are not
D63487 Extended link
sequence, D13000 is inaccessible.
register (W)

Programming MELSEC System Q and L series 3 – 41

Reducing instruction processing time Configuration of Instructions

3.8 Reducing instruction processing time

3.8.1 Subset processing

Subset processing is used to place limits on bit devices used by basic instructions and appli-
cation instructions in order to increase processing speed. However, the instruction symbol
does not change.
To shorten scans, run instructions under the conditions indicated below.

Conditions which each device must meet for subset processing

● When using word data
Device Condition
 Drive number and file name of comment file to be switched to or first number of
device storing such data.
Bit device
 Only K4 can be designated for digit designation.
 Does not perform indexing.
 Internal user device.
 File register (R, ZR 4))
Word device
 Multiple CPU shared device 1, 2)
 Index register (Z) / Standard device register (Z) 3)
Constants No limitations

● When using double word data

Device Condition
 Designates a bit device number in a factor of 16.
Bit device  Only K8 can be designated for digit designation.
 Does not perform indexing.
 Internal user device.
 File register (R, ZR 4))
Word device
 Multiple CPU shared device 1, 2)
 Index register (Z) / Standard device register (Z) 3)
Constants No limitations

● When using bit data

Device Condition
Bit device  Internal user device (indexing possible)
 Bit specification of internal user device
Word device  Bit specification of file register (R, ZR 4))
 Bit specification of multiple CPU shared device 1, 2)
1
Only for Universal model QCPU
2 Valid only for the multiple CPU high speed transmission area (from U3En\G10000)
(Excluding the case that indexing is executed for the head I/O number of the CPU module (U3En\G10000))
3 Applies only to Universal model QCPU and LCPU.

4 Applies only to Universal model QCPU (excluding Q00UJCPU) and LCPU.

3 – 42
Configuration of Instructions Reducing instruction processing time

Instructions for which subset processing can be used

Types of Instructions Instruction Symbols

LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP, ANDF, ORP, ORF, LDPI,
Contact instructions
ANDPI, ANDFI, ORPI, ORFI
Output instructions OUT, SET, RST
Comparison operation instruction =, <>, <, <=, >, >=, D=, D<>, D<, D<=, D>, D>=
+, –, x, /, INC, DEC, D+, D–, Dx, D/, DINC, DDEC
Arithmetic operation
B+, B–, Bx, B/, E+, E–, Ex, E/
Data conversion instructions BCD, BIN, DBCD, DBIN, FLT, DFLT, INT, DINT
MOV, DMOV, CML, DCML, XCH, DXCH
Data transfer instruction
FMOV, BMOV, EMOV
Program branch instruction CJ, SCJ, JMP
Logic operations WAND, DAND, WOR, DOR, WXOR, DXOR, WXNR, DXNR
Rotation instruction RCL, DRCL, RCR, DRCR, ROL, DROL, ROR, DROR
Shift instruction SFL, DSFL, SFR, DSFR
Data processing instructions SUM, SEG
Structure creation instructions FOR, CALL

3.8.2 Operation processing with standard device registers (Z)

(Universal model QCPU and LCPU only)

Operation processing time can be reduced with standard device registers (Z).
The following figure shows an example program with standard device registers.

+ D0 D10 D20 Using data registers takes three steps and the
operation processing time of 28.5 ns.
(With the Q4/Q06/Q10/Q13/Q20/
Q26UD(E)HCPU or Q50/Q100UDEHCPU)

+ Z0 Z1 Z2 Using standard device registers instead of data

registers takes one step and the operation
processing time of 9.5 ns.
(With the Q4/Q06/Q10/Q13/Q20/Q26UD(E)HCPU
or Q50/Q100UDEHCPU)

Operation processing time is reduced with the instructions that the subset processing is pos-
sible.
For the number of steps, refer to section 3.11.
For the operation time for each instruction, refer to Appendix A.

NOTE Because standard device registers are the same devices as index registers, do not use device
numbers of the standard device registers for the index registers.

Programming MELSEC System Q and L series 3 – 43

Operation errors Configuration of Instructions

3.9 Operation errors

In the following cases operation errors occur:
● If the error conditions described under the topic "Operation Errors" for the individual
instructions match, an error code is returned.
● When an intelligent function module device is used, no intelligent function module is installed
at the specified I/O number position.
● When an intelligent function module device is used, the specified buffer memory address
does not exist.
● If a link device is used, but the corresponding network does not exist.
● If a link device is used, but there is no network module connected to the specified I/O number.
● When a multiple CPU shared device is used, a CPU module is not installed at the head I/O
number position of the specified CPU module.
● When a multiple CPU shared device is used, the specified shared memory address does
not exist.
● The setting of the device number crosses over the boundary between the internal user device
and the extended data register (D) or extended link register (W).
(Universal model QCPU (excluding Q00UJCPU) and LCPU)

NOTE When file register is set but a memory card is not installed or when file register is not set, writing/
reading to/from file register is as follows:
 For the High Performance model QCPU, Process CPU, and Redundant CPU
An error does not occur even when writing/reading to/from file register is performed. How-
ever, “0H” is stored when reading from file register is performed.
 For the Universal model QCPU and LCPU
The OPERATION ERROR (error code 4101) occurs when writing/reading to/from file register
is performed.

3 – 44
Configuration of Instructions Operation errors

3.9.1 Verification of the device range

Instructions for specified each device, including MOV and DMOV

● For the Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant
CPU
If instructions use devices with fixed length (MOV, DMOV, etc.), the device range will not be
verified. In those cases where the relevant address range is exceeded the data to be written
is written to a vacant device.
If for example, 12k addresses are designated, there will no error code be returned even if
the register address D12287 is exceeded.

Ladder Diagram Explanation

D12287 and D12288 are designated in

this example but D12288 does not
exist. A vacant register will be
overwritten with the contents of
D12288.

For an index qualification the device range is not verified either.

In cases where the corresponding device range is exceeded as the result of performing
indexing, data is written to other devices.
For the assignment order of internal user devices, refer to page 3-48 ("Character string data")
below.

● Universal model QCPU and LCPU

The device range is checked. When the device number is outside the device range, an
operation error occurs.
For example, when12 k points are assigned to a data register, an error occurs if the device
number of the data register exceeds D12287.

Ladder Diagram Explanation

When D12287 is specified with the

DMOV instruction, the target devices
are D12287 and D12288.
However, an operation error occurs
because D12288 does not exist.

The device range is checked even though indexing is executed. With changing the settings
of the PLC parameter, the device range is not checked.
For changing the settings of the PLC parameter of the programming tool, refer to the User’s
Manual of the corresponding programming tool.

Programming MELSEC System Q and L series 3 – 45

Operation errors Configuration of Instructions

Instructions for a block of devices, including BMOV and FMOV

● For the Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant
CPU
If instructions use devices with variable length, the device range is verified (BMOV, FMOV,
and other instructions that designate initial addresses). In those cases where the relevant
address range is exceeded an error code is returned.
If for example, 12k addresses are designated, the error code is returned after the register
address D12287 is exceeded.

Ladder Diagram Explanation

D12287 and D12288 are designated in

this example.
However, D12288 does not exist and
an error code is returned.

The device range is verified for an index qualification too.

There is no error code returned, if the initial device number exceeds the address range.

Ladder Diagram Explanation

D12287 and D12288 are designated in

this example.
However, D12288 does not exist and
an error code is returned.
The initial device number D12289
exceeds the relevant range. The data
are stored from the register W0
onwards without returning an error
code.

● Universal model QCPU and LCPU

The device range is checked. In those cases where the relevant address range is exceeded
an error code is returned.
If for example, 12k addresses are designated, the error code is only returned after the
register address D12287 is exceeded.

Ladder Diagram Explanation

D12287 and D12288 are designated in

this example.
However, D12288 does not exist and
an error code is returned.

3 – 46
Configuration of Instructions Operation errors

The device range is verified for an index qualification too. An error occurs when the head
device number of the devices with indexing exceeds the device range.

Ladder Diagram Explanation

D12287 and D12288 are designated in

this example.
However, D12288 does not exist and
an error code is returned.

The initial device number D12289

exceeds the relevant range. An
operation error occurs.

With changing the settings of the PLC parameter, the device range is not checked.
For changing the settings of the PLC parameter of the programming tool, refer to the User’s
Manual of the corresponding programming tool.

Programming MELSEC System Q and L series 3 – 47

Operation errors Configuration of Instructions

Character string data

Since character strings are of variable lengths the device range is verified. In cases where the
corresponding device range is exceeded, an error code is returned.
If for example, 12k addresses are designated, there will no error code be returned until the reg-
ister address D12287 is exceeded.

Ladder Diagram Explanation

D12287 and D12288 are designated in

this example.
However, D12288 does not exist and
an error code is returned.

However, with the Basic Model QCPU, High Performance model QCPU, Process CPU, and
Redundant CPU, when indexing is executed and the head device number is outside the device
range, no error occurs and the other devices are accessed.
When performing the following access in Universal model QCPU or LCPU, an error (error code
4101) occurs.
 Access crossing the boundary of devices caused by indexing (range of A area)

The allocation order of individual devices is shown below:

SM
SD
X
Y
M
L
B
F
SB
V Area A
S
Contact and coil of T
Contact and coil of ST
Contact and coil of C
Present value of T
Present value of ST
Present value of C
D
W
SW
Empty area Boundary B
File register (32k points)

 Access crossing the boundary of file registers caused by indexing

 Access to file registers (R, ZR) without setting file register files
 Access to file registers (R, ZR) exceeded the range of file register files

3 – 48
Configuration of Instructions Operation errors

Presetting PLC parameter not to check indexing device range enables the Universal model
QCPU not to detect an error in the above accesses from  to . Detecting an error in the
above accesses however, depends on the serial No. of Universal model QCPU.

Setting device range First 5 digits of serial No. for Universal model QCPU
in indexing "10021" or lower "10022" or higher
Set Detected errors in accesses  to 
Not set Detected errors in accesses  to  Not detected

For changing the settings of the PLC parameter, refer to the User’s Manual of the programming
tool.

NOTE When indexing is executed only with Universal model QCPU or LCPU, devices between internal
user devices (SW) and file registers (R) cannot be skipped. (Error code 4101)

Index qualification of the direct output (DY)

The device range is verified for an index qualification of the direct output (DY).

Programming MELSEC System Q and L series 3 – 49

Operation errors Configuration of Instructions

Precautions for using the extended data register (D) or extended link register (W) (for
the Universal model QCPU (except Q00UJCPU), and LCPU)
With the following specification methods, data cannot be specified crossing over the boundary
of the internal user device and extended data register (D) or extended link register (W). Doing
so causes an "OPERATION ERROR" (Error code 4101).
● Index modification
● Indirect designation
● Specification with the instructions that handle data blocks
Data block indicates the following data:
– Data used in the instructions, such as FMOV, BMOV, BK+, where multiple words are
targeted for operation
– Control data, composed of two or more words, specified in the instructions, such as
SP.FWRITE, SP.FREAD
– Data whose data type is 32-bit or more (BIN 32-bit, real number, indirect address of the
device)

Data block where the device number

crosses over the boundary between the
internal user device and the extended data
register (D) cannot be handled. Image of D device

D100 Internal user

FMOV K0 D100 K200 device

D199

FMOV K0 D12200 K200

D12200

FMOV K0 D20000 K200 D12299 Extended data

register (D)

D20100

D20299

3 – 50
Configuration of Instructions Operation errors

3.9.2 Verification of the device data

Verification of binary data

● If the operation result exceeds the value range, no error code is returned.
The carry flag in this case is not set.

Verification of BCD data

● Each digit of the BCD values (0 to 9) is verified.
If one individual digit exceeds the range of 0 to 9 (A to F), an error code is returned.
● If the operation result exceeds the value range, no error code is returned.
The carry flag in this case is not set.

Verification of floating-point numbers (with single precision floating-point operation

instruction)
Operation errors occur in the following cases:
● The absolute value of the floating-point number is 1.0 x 2-127 or lower.
● The absolute valuse of the floating-point number is 1.0 x 2128 or higher.

Verification of floating-point numbers (with double precision floating-point operation

instruction)
Operation errors occur in the following cases:
● The absolute value of the floating-point number is 1.0 x 2-1023 or lower.
● The absolute value of the floating-point number is 1.0 x 21024 or higher.

Verification of character strings

The device data are not verified.

3.9.3 Buffer memory access

For accessing buffer memories, using instructions with intelligent function module devices
(from Un\G0) is recommended.

3.9.4 Multiple CPU shared memory access

For accessing multiple CPU shared memories, using instructions with multiple CPU shared
devices (from U3En\G10000) is recommended.

Programming MELSEC System Q and L series 3 – 51

Execution conditions of the instructions Configuration of Instructions

3.10 Execution conditions of the instructions

3.10.1 Execution condition

There are 4 different types of execution conditions for the instructions:

● Non-conditional execution
The instructions are executed regardless of the signal status of the devices.
Example: LD X0, OUT Y10
● Execution at ON
The instructions are executed as long as the execution instruction is set.
Example: MOV, FROM
● Execution at leading edge
The instructions are executed at leading edge (signal status changes from 0 to 1) from the
execution condition.
Example: PLS, MOVP
● Execution at trailing edge
The instructions are executed at trailing edge (signal status changes from 1 to 0) from the
execution condition.
Example: PLF

The vast majority of instructions are of the following two types:

– Execution condition set ON
– Execution at leading edge from the execution condition

Execution condition set ON:

The instruction is executed as long as the execution instruction is set. Such instructions are not
particularly indicated.
Example: MOV_M/ MOV

Ladder Diagram MELSEC Instruction List

Execution at leading edge from the execution condition:

When judging the leading edge from the execution condition the instruction is executed only if
the signal state changes from 0 to 1.
Example: MOVP_M/ MOVP

Ladder Diagram MELSEC Instruction List

3 – 52
Configuration of Instructions Execution conditions of the instructions

The following example shows the execution of the MOV instruction with the execution condition
set ON and the execution at leading edge from the execution condition:

Ladder Diagram Explanation

Execution at
execution condition set ON

Execution at leading edge from

the execution condition

3.10.2 EN input and ENO output

All instructions described in this manual are provided in the manufacturer library of the GX IEC
Developer. These instructions in addition to the input and output variables provide an EN input
and an ENO output.
The figure below shows several MELSEC instructions from the GX IEC Developer manufac-
turer library:

In the IEC standard library nearly all instructions appear twice. They just differ in the suffix "_E".
These instructions provide an EN input and an ENO output.
The figure below shows two IEC instructions from the standard library of the GX IEC Devel-
oper:

The following examples show the differing execution of the instruction with and without EN
inputs and ENO outputs.

Example 1: Without additional connection

Without additional connection the execution condition of the instruction is permanently set.

Programming MELSEC System Q and L series 3 – 53

Execution conditions of the instructions Configuration of Instructions

Example 2: Connection with a contact

If the EN input is connected with a contact, the instruction is executed if the condition is
matched.

Example 3: Connection with an operation result

If the boolean result of an arithmetic operation is connected to the EN input, the instruction is
only executed, if the result of the arithmetic operation is TRUE.

Example 4: Connection with the preceding instruction

If the EN input is connected to the ENO output of the preceding instruction, the instructions are
only executed, if the condition is matched.

NOTE The ENO output must not compulsorily be connected. The signal at the EN input is looped-
through to the ENO output. If the EN input is "TRUE", the ENO output is "TRUE" as well.

3 – 54
Configuration of Instructions Number of program steps

3.11 Number of program steps

In order not to exceed the required memory capacity in the internal memory and ROM or RAM
memory of the memory cards a calculation of the total number of steps in a program is
required. In the following sections the calculation of steps for the instructions is described.

Counting the number of basic steps

The number of steps for an instruction depends on the number of basic steps. Most of the
instructions for their execution only require a number of basic steps. The number of basic steps
depends on the number of used devices plus 1.
The example below shows the calculation of the number of basic steps for the PLUS instruc-
tion:

Ladder Diagram Explanation

3 Program steps
The numbers in brackets specify the
cumulative number of program steps for the
devices.
4 Program steps

The numbers in brackets specify the

cumulative number of program steps for the
devices.

Conditions for increasing the number of steps

The number of steps is increased over the number of basic steps in cases where a device is
used that is designated indirectly or for which the number of steps is increased.
● When device is designated indirectly
In cases where indirect designation is done by @, the number of steps is increased 1 step
over the number of basic steps.
For example, when a 3-step MOV instruction is designated indirectly (example: MOV K4X0
@D0), one step is added and the instruction becomes 4 steps.
● Devices with additional steps (Basic Model QCPU, High Performance model QCPU, Process
CPU, and Redundant CPU):

Devices increasing the Added Steps Example

Number of Steps

Devices of special function modules MOV U4\G10 D0

Multiple CPU shared device MOV U3E1\G0 D0

Link devices MOV J3\B20 D0

Index register 1 MOV Z0 D0

File registers addressed in series MOV ZR123 D0

32-bit constants DMOV K123 D0

Floating point number as constants EMOV E0.1 D0

For an odd number:

(number of characters + 1)/2
Character strings $MOV „123“ D0
For an even number:
Number of characters/2

Programming MELSEC System Q and L series 3 – 55

Number of program steps Configuration of Instructions

● Devices with additional steps (Universal model QCPU(except Q00UJCPU) and LCPU)
– Instructions applicable to subset processing
The following table shows steps depending on the devices.

Added Steps
(Number of Basic Number
Instruction Symbols Devices With Additional Steps
Instruction of Steps
Steps)

Serial number access format file register,

LD, LDI, AND, ANI, OR, ORI, Extended data register (D),
LDP, LDF, ANDP, ANDF, ORP, Extended link register (W) 1(2) 1
ORF
Multiple CPU shared device 3)

Serial number access format file register,

Extended data register (D),
LDPI, LDFI Extended link register (W) 1(4) 3

Multiple CPU shared device 3)

Serial number access format file register,

Extended data register (D),
ANDPI, ANDFI, ORPI, ORFI Extended link register (W) 1(5) 4

Multiple CPU shared device 3)

Serial number access format file register

Extended data register (D),
SET Extended link register (W) 1(2) 1

Multiple CPU shared device 3)

Timer/Counter 3(4)

Serial number access format file register

OUT Extended data register (D), 1
Extended link register (W) 1(2)

Multiple CPU shared device 3)

Serial number access format file register,

Extended data register (D),
RST (bit device) Extended link register (W) 1(2) 1

Multiple CPU shared device 3)

Timer/Counter (Bit/word device) 2(4)

Serial number access format file register,

RST (word device) Extended data register (D), 1(3) 2
Extended link register (W)

Multiple CPU shared device 3) 1(3)

Standard device register 2) -1

LD=, LD<>, LD<, LD<=, LD>,
LD>=, AND=, AND<>, AND<, Serial number access format file register,
AND<=, AND>, AND>=, Extended data register (D), 3
OR=, OR<>, OR<, OR<=, Extended link register (W) 1
OR>, OR>=
Multiple CPU shared device 3)

3 – 56
Configuration of Instructions Number of program steps

Added Steps
Instruction Symbols Devices With Additional Steps (Number of Basic Number
Instruction of Steps
Steps)

Standard device register 2) -1

LDD=, LDD<>, LDD<, LDD<=, Serial number access format file register,
LDD>, LDD>=, Extended data register (D),
ANDD=, ANDD<>, ANDD<, Extended link register (W)
3
ANDD<=, ANDD>, AND>=,
1
ORD=, ORD<>, ORD<, Multiple CPU shared device 3)
ORD<=, ORD>, ORD>=
Decimal constant, hexadecimal constant,
real constant

Standard device register 2) d: -1

+, -, +P, -P,
Serial number access format file register
WAND, WOR, WXOR, WXNR,
Extended data register (D), Extended link 3
WANDP, WORP, WXORP,
register (W) s1: 1, d: 3
WXNRP (2 devices)
Multiple CPU shared device 3)

Standard device register 2) d: -1

Serial number access format file register,

Extended data register (D),
D+, D-, D+P, D-P, DAND, DOR,
Extended link register (W) s1: 1, d: 3
DXOR, DXNR, DANDP, DORP, 3
DXORP, DXNRP (2 devices) 3)
Multiple CPU shared device

Decimal constant, hexadecimal constant,

s1: 1
real constant

Serial number access format file register,

+, -, +P, -P,
Extended data register (D),
WAND, WOR, WXOR, WXNR,
Extended link register (W) s1, s2: 1, d: 2 3
WANDP, WORP, WXORP,
WXNRP (3 devices) 1)
Multiple CPU shared device 3)

Serial number access format file register,

Extended data register (D),
Extended link register (W) s1, s2:1, d: 2
D+, D-, D+P, D-P, DAND, DOR,
DXOR, DXNR, DANDP, DORP, 3
Multiple CPU shared device 3)
DXORP, DXNRP (3 devices)1)
Decimal constant, hexadecimal constant,
s1, s2: 1
real constant

Serial number access format file register,

Extended data register (D),
x, xP, /, /P Extended link register (W) s1, s2:1, d: 2 3

Multiple CPU shared device 3)

Serial number access format file register,

Extended data register (D),
Extended link register (W) s1, s2:1, d: 2
Dx, DxP, D/, D/P, Ex, ExP 3
Multiple CPU shared device 3)

Decimal constant, hexadecimal constant,

s1, s2: 1
real constant

Index register/Standard device register 2) -1

Serial number access format file register,

INC, INCP, DEC, DECP, DINC,
Extended data register (D), 3 2
DINCP, DDEC, DDECP
Extended link register (W)

Multiple CPU shared device 3) 1

Programming MELSEC System Q and L series 3 – 57

Number of program steps Configuration of Instructions

Added Steps
Instruction Symbols Devices With Additional Steps (Number of Basic Number
Instruction of Steps
Steps)

Serial number access format file register,

Extended data register (D),
MOV, MOVP Extended link register (W) 1 2

Multiple CPU shared device 3)

Serial number access format file register,

Extended data register (D),
Extended link register (W)
DMOV, DMOVP, EMOV,
1 2
EMOVP Multiple CPU shared device 3)

Decimal constant, hexadecimal constant,

real constant

Serial number access format file register,

Extended data register (D),
BCD, BCDP, BIN, BINP, FLT,
Extended link register (W) s1: 1, s2: 2 2
FLTP, CML, CMLP
Multiple CPU shared device 3)

Serial number access format file register,

Extended data register (D),
Extended link register (W) s1: 1, s2: 2
DBCD, DBCDP, DBIN, DBINP,
INT, INTP, DINT, DINTP, DFLT, 2
Multiple CPU shared device 3)
DFLTP, DCML, DCMLP
Decimal constant, hexadecimal constant,
s1: 1
real constant

1 If the same device is used for s1 and s2, the number of basic steps increases by one.
2
The number of steps decreases with a standard device register.
3
Not available with LCPU.

3 – 58
Configuration of Instructions Number of program steps

When multiple standard device registers are used in an instruction applicable to subset
processing, the number of steps decreases.
The following table shows the number of steps for each instruction.

Added Steps Basic

Locations Where Standard Device (Number of
Instruction Symbols Register Is Used Instruction Number of
Steps
Steps)

LD=, LD<>, LD<, LD<=, LD>, LD>=,

AND=, AND<>, AND<, AND<=,
AND>, AND>=,
OR=, OR<>, OR<, OR<=, OR>,
OR>=,
LDD=, LDD<>, LDD<, LDD<=, LDD>, s1 and s2 –2(1) 3
LDD>=,
ANDD=, ANDD<>, ANDD<,
ANDD<=, ANDD>, AND>=,
ORD=, ORD<>, ORD<, ORD<=,
ORD>, ORD>=

+, -, +P, -P, D+, D-, D+P, D-P,

WAND, WOR, WXOR, WXNR,
DAND, DOR, DXOR, DXNR, WANDP,
s1 and d –2(1) 3
WORP, WXORP, WXNRP, DANDP,
DORP, DXORP, DXNRP
(2 devices)

s1, s2 and d –2(1)

s1, or s2 and d –1(2)

+, -, +P, -P, D+, D-, D+P, D-P, WAND,
WOR, WXOR, WXNR, DAND, DOR, s1 and s2
DXOR, DXNR, WANDP, WORP, (only when that device that the
±0(3) 3
WXORP, WXNRP, DANDP, DORP, number of steps does not increase is
DXORP, DXNRP specified for d)
(3 devices) 1)
s1 and s2
(only when a serial number access +2(5)
format file register is specified for d)

s1, s2 and d –2(1)

x, xP, /, /P 3
s1, or s2 and d –1(2)

s1, s2 and d –2(1)

s1, or s2 and d –1(2)

s1 and s2
(only when that device that the
Dx, DxP, D/, D/P, Ex, ExP ±0(3) 3
number of steps does not increase is
specified for d)

s1 and s2
(only when a serial number access +2(5)
format file register is specified for d)

MOV, MOVP, DMOV, DMOVP, EMOV,

s1 and d –1(1) 2
EMOVP

BCD, BCDP, BIN, BINP, DBCD,

DBCDP, DBIN, DBINP, FLT, FLTP,
s1 and d –1(1) 2
DFLT, DFLTP, INT, INTP, DINT,
DINTP, CML, CMLP, DCML, DCMLP

1 If the same device is used for s1 and d, the number of basic steps increases by one.

Programming MELSEC System Q and L series 3 – 59

Number of program steps Configuration of Instructions

– Except Instructions applicable to subset processing

The following table shows steps depending on the devices.

Devices with Additional Steps Added Steps Example

Devices of special function modules MOV U4\G10 D0

Multiple CPU shared device MOV U3E1\G10000 D0

Link direct device MOV J3\B20 D0

Index register / standard device register MOV Z0 D0

File registers addressed in series 1 MOV ZR123 D0

Extended data register (D) MOV D123

Extended link register (W) MOV W123

32-bit constants DMOV K123 D0

Floating point number as constants EMOV E0.1 D0

For an odd number:

(number of characters + 1/2)
Character strings $MOV „123“ D0
For an even number:
Number of characters/2

In cases where several of these factors apply the number of steps sums up.
If for example, MOV U1\G10 ZR123 is programmed, 1 step is added for the buffer memory and
1 step for the file register addressed in series, resulting in a total of 2 steps (see the following
figure):

Example: MOV
If U1\G10 ZR123 has been designated, a total of 2 steps is added.

U1\
MOV G10 ZR123

Serial number access format file registers : 1 step

+
: 1 step
Intelligent function module devices
=
Increased by 2 steps

3 – 60
Configuration of Instructions Multiple Instructions using the same device

3.12 Multiple Instructions using the same device

This section describes the operation for executing multiple instructions of the OUT, SET/RST,
or PLS/PLF that use the same device in one scan.

3.12.1 OUT instructions using the same device

Do not program more than one OUT instruction using the same device in one scan. If the OUT
instructions using the same device are programmed in one scan, the specified device will turn
ON or OFF every time the OUT instruction is executed, depending on the operation result of
the program up to the relevant OUT instruction. Since turning ON or OFF of the device is deter-
mined when each OUT instruction is executed, the device may turn ON and OFF repeatedly
during one scan.
The following diagrams show an example of a ladder that turns the same internal relay (M0)
with inputs X0 and X1 ON and OFF.

Ladder diagram

X0
M0

X1
M0

Timing chart
X0 X0
M0 M0
X1 X1
M0 M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns ON because
M0 turns OFF because X1 is OFF. X1 is ON.

M0 turns ON because X0 is ON M0 remains OFF

because X0 is OFF.

With the refresh type CPU module, when the output (Y) is specified by the OUT instruction, the
ON/OFF status of the last OUT instruction of the scan will be output.

Programming MELSEC System Q and L series 3 – 61

Multiple Instructions using the same device Configuration of Instructions

3.12.2 SET/RST instructions using the same device

The SET instruction turns ON the specified device when the execution command is ON and
performs nothing when the execution command is OFF. For this reason, when the SET instruc-
tions using the same device are executed two or more times in one scan, the specified device
will be ON if any one of the execution commands is ON.
The RST instruction turns OFF the specified device when the execution command is ON and
performs nothing when the execution command is OFF. For this reason, when the RST instruc-
tions using the same device are executed two or more times in one scan, the specified device
will be OFF if any one of the execution commands is ON.
When the SET instruction and RST instruction using the same device are programmed in one
scan, the SET instruction turns ON the specified device when the SET execution command is
ON and the RST instruction turns OFF the specified device when the RST execution command
is ON. When both the SET and RST execution commands are OFF, the ON/OFF status of the
specified device will not be changed.

Ladder diagram

X0
SET M0

X1
RST M0

Timing chart X0 X0
SET M0 SET M0
X1 X1
RST M0 RST M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns OFF because

RST M0 is not executed X1 is ON.
because X1is OFF.
(M0 remains ON) SET M0 is not executed because
X0 is OFF. (M0 remains ON)
M0 turns ON because X0 is ON

When using a refresh type CPU module and specifying output (Y) in the SET/RST instruction,
the ON/OFF status of the device at the execution of the last instruction in the scan is returned
as the output (Y).

3 – 62
Configuration of Instructions Multiple Instructions using the same device

3.12.3 PLS instructions using the same device

The PLS instruction turns ON the specified device when the execution command is turned ON
from OFF. It turns OFF the device at any other time (OFF to OFF, ON to ON, or ON to OFF).

If two or more PLS instructions using the same device are executed in one scan, each instruc-
tion turns ON the device when the corresponding execution command is turned ON from OFF
and turns OFF the device in other cases. For this reason, if multiple PLS instructions using the
same device are executed in a single scan, a device that has been turned ON by the PLS
instruction may not be turned ON during one scan.

Ladder diagram

X0
PLS M0

X1
PLS M0

Timing chart

The ON/OFF timing of the X0 and X1 is different.

(The specified device does not turn ON throughout the scan.)
X0 X0
The ON/OFF timing of the X0 and X1 is different.
PLS M0 PLS M0
(The specified device does not turn ON throughout the scan.)
X1 X1
PLS M0 PLS M0
END END END

ON
X0 OFF
ON
X1 OFF

ON ON
M0 OFF M0 turns ON because X1 goes
M0 turns OFF be- ON (OFF → ON).
M0 turns ON because X0 goes cause X1 status is oth- M0 turns OFF because X0 status is other
ON (OFF → ON). er than OFF → ON. than OFF → ON. (M0 remains OFF.)

X0 and X1 turn ON from OFF at the same time.

1
X0 X0
PLS M0 PLS M0
X1 X1
PLS M0 PLS M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns OFF because X1 status is

M0 turns ON because X1 other than OFF → ON.
goes ON (OFF → ON). (M0 remains OFF)
(M0 remains ON)
M0 turns OFF because X0 status
M0 turns ON because X0 goes ON (OFF → ON). is other than OFF → ON

Programming MELSEC System Q and L series 3 – 63

Multiple Instructions using the same device Configuration of Instructions

When using a refresh type CPU module and specifying output (Y) in the PLS instructions, the
ON/OFF status of the device at the execution of the last PLS instruction in the scan is returned
as the output (Y).

3.12.4 PLF instructions using the same device

The PLF instruction turns ON the specified device when the execution command is turned OFF
from ON. It turns OFF the device at any other time (OFF to OFF, OFF to ON, or ON to ON).
If two or more PLF instructions using the same device are executed in one scan, each instruc-
tion turns ON the device when the corresponding execution command is turned OFF from ON
and turns OFF the device in other cases. For this reason, if multiple PLF instructions using the
same device are executed in a single scan, a device that has been turned ON by the PLF
instruction may not be turn ON during one scan.

3 – 64
Configuration of Instructions Multiple Instructions using the same device

Ladder diagram

X0
PLF M0

X1
PLF M0

Timing chart
The ON/OFF timing of the X0 and X1 is different.
(The specified device does not turn ON throughout the scan.)

X0 X0
PLF M0 PLF M0
X1 X1
PLF M0 PLF M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF
M0 turns OFF because M0 turns OFF because X1
X1 status is other than status is other than ON →
ON → OFF OFF. (M0 remains OFF.)
M0 turns ON because X0
goes OFF (ON → OFF). M0 turns OFF because X0 status is other
than ON → OFF. (M0 remains OFF.)

X0 and X1 turn OFF from ON at the same time.

X0 X0
PLF M0 PLF M0
X1 X1
PLF M0 PLF M0
END END END

ON

X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns ON because X1 M0 turns OFF because X1

goes OFF (ON → OFF) status is other than ON → OFF.
(M0 remains ON) (M0 remains OFF.)
M0 turns ON because X0 M0 turns OFF because X0 status is other
goes OFF (ON → OFF). than ON → OFF.

When using a refresh type CPU module and specifying output (Y) in the PLF instructions, the
ON/OFF status of the device at the execution of the last PLF instruction in the scan is returned
as the output (Y).

Programming MELSEC System Q and L series 3 – 65

Precautions for use of file registers Configuration of Instructions

3.13 Precautions for use of file registers

This section explains the precautions for use of the file registers in the QCPU and LCPU.

CPU modules that cannot use file registers

The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers, use
the CPU module of other than the Q00JCPU and Q00UJCPU.

Setting of file registers to be used

When using the file registers, the file registers to be used must be set with the PLC parameter
or QDRSET instruction. (The PLC parameters of the Q00CPU, Q01CPU and LCPU need not
be set since they are preset to "Use file register". QDRSET instructions are not available with
LCPU.)
If the file registers to be used have not been set, normal operation cannot be performed with
the instructions that use the file registers.

NOTE Even when file registers to be used are not set in the PLC parameter, a program that uses file
registers can be created.
For the CPU module other than the Universal model QCPU and LCPU, an error does not occur
when that program is written to the CPU module.
However, note that the correct data cannot be written/read to/from the file register.
For the Universal model QCPU and LCPU, an error occurs if the program where file registers are
used is executed.

Securing of file register area

● High Performance model QCPU, Process CPU, Redundant CPU, Universal model QCPU
When using file registers, register the file registers to the standard RAM/memory card to
secure the file register area.
● Basic Model QCPU (except Q00JCPU)
The file register area has been secured in the standard RAM beforehand. The user need
not secure the file register area.
● LCPU
To use the file register, secure a file register area by registering the file register in standard
RAM.

The following table indicates the memories that can use the file registers in each CPU module.

High Performance model QCPU /

Process CPU / Redundant CPU / Basic Model QCPU (except Q00JCPU) /
Memory Universal model QCPU (except LCPU
Q00UJCPU)

Standard RAM  

1) 2) 
Memory card 

Can be registered

Cannot be registered
1 When the flash memory is used, only read from the file registers can be performed. (Write to the flash
ROM cannot be performed.)
2 Unusable for the Q00UCPU and Q01UCPU.

3 – 66
Configuration of Instructions Precautions for use of file registers

NOTE For the file register setting method and file register area securing method, refer to User’s Manual
(Functions Explanation, Program Fundamentals) for the CPU module used.

Designation of file register number in excess of the registered number of points

● Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU
An error will not occur if data are written or read to or from the file registers that have numbers
greater than the registered number of points. However, note that the read/write of correct
data to/from the file registers cannot be performed.
● Universal model QCPU and LCPU
When data are written to or read from the file registers that are not registered, an error
occurs. (Error code: 4101)

File register specifying method

There are the block switching method and serial number access method to specify the file reg-
isters.
● Block switching method
In the block switching method, specify the number of used file register points in units of 32k
points (one block). For file registers of 32k points or more, specify the file registers by
switching the block No. to be used with the RSET instruction. Specify each block as R0 to
R32767.

Standard RAM/
Memory card
RSET K1 Specifying
R0 for block 1 R0

to Block 0
MOV D0 R0

R32767

RSET K2 Specifying R0
R0 for block 2 Block 1
to

MOV D0 R0 R32767
R0 Block 2
to

Programming MELSEC System Q and L series 3 – 67

Precautions for use of file registers Configuration of Instructions

● Serial number access method

In the serial number access method, specify the file registers beyond 32k points with
consecutive device numbers. The file registers of multiple blocks can be used as consecutive
file registers. Use "ZR" as the device name.

Standard RAM/
Memory card
MOV D0 ZR32768
ZR0
Block 0
to

ZR32767
MOV D0 ZR65536 ZR32768

Block 1
to

ZR65535
ZR65536
Block 2
to

Settings and restrictions when refreshing file registers

● Settings
The settings of refresh devices are as follows.
– Refresh settings for CC-Link IE controller network (Cannot be set on LCPU.)
– Refresh settings for MELSECNET/H (Cannot be set on LCPU.)
– Refresh settings for CC-Link
– Auto refresh settings for the intelligent function module
– Auto refresh settings for the multiple CPU system (Cannot be set on LCPU.)

● Restrictions
The restrictions when specifying file registers to refresh devices are as follows.
– On QCPU, Refresh cannot be performed correctly if the use of file register which has the
same name as the program is specified by the PLC parameter. When the file register which
has the same name as the program is used, refresh is performed to the data of the file
register having the same name as the program that is set at the last number in the
[Program] tab page of PLC parameter.
To read/write the refresh data, specify the file register to the refresh device after switching
the file register to the corresponding one with the QDRSET instruction.
– Refresh cannot be performed correctly if the file name of file register or the drive number
is changed by the QDRSET instruction. (QDRSET instructions are not available with
LCPU.)
If the file name of file register or the drive number is changed by the QDRSET instruction,
link refresh is performed to the data of the setting file at the time of the END instruction
execution.
To read/write the refresh data, specify the file register of the setting file at the time of the
END instruction execution.

3 – 68
Configuration of Instructions Precautions for use of file registers

If the drive number is changed by the QDRSET instruction when "ZR" is specified for the
device in the CPU modules other than the Universal model QCPU, an error (LINK PARA
ERROR (3101)) occurs. (Note that an error does not occur when "R" is specified for the
device.)
– When a block number is switched by the RSET instruction, refresh is performed to the
data of the file register (R) in the switched block number.
When a block number is switched by the RSET instruction, refresh is performed to the
data of the file register (R) in the block number at the time of the END instruction execution.
To read/write the refresh data, specify the file register of the block number at the time of
the END instruction execution.

Precautions when file registers in the flash memory are used

File registers in the flash memory can be only read in a sequence program.
(Write to the flash memory cannot be performed in a sequence program.)

Sequence program Flash memory

Write
BMOV D100 R0 K10
File
register
BMOV R100 D0 K10
Read

When using the flash memory for the file registers, write data in advance. Using GX Works2,
write data to the flash card.

Programming MELSEC System Q and L series 3 – 69

Precautions for use of file registers Configuration of Instructions

3 – 70
Layout and Structure of the Chapters

4 Layout and Structure of the Chapters

This chapter gives an introduction to the chapters 5 through 12 and describes the layout and
structure of the explanations to the instructions for the MELSEC Sstem Q and L series.
The figure below shows that each of the these chapters starts with a table that lists and com-
ments the structure and subdivision of the instructions described in that chapter.

Each subdivided topic is described in the following according chapter and illustrated by pro-
gram examples.

Programming MELSEC System Q and L series 4–1

Overview of the instructions Layout and Structure of the Chapters

4.1 Overview of the instructions

Each subdivided topic starts with a table that lists all individual instructions described in this
section. As the figure below shows, all variations of the instructions are represented in
MELSEC and IEC editor notation.

When using the GX IEC Developer, always choose the IEC instruction when different notations
are offered.

4.2 The CPU table

The sections describing the instructions start with a table that indicates each CPU (Basic
model QCPU, High Performance model QCPU, Process CPU, Redundant CPU, Universal
model QCPU, LCPU) capable of processing the respective instruction. The capable CPUs are
indicated by a black spot.

Data conversion instructions ENEG, ENEGP

6.3.12 ENEG, ENEGP

CPU High
Basic Process Redundant Universal LCPU
Performance
1)

1
Basic model QCPU: The serial number (upper five digits) is "04122" or higher.

Any particular processing details of a certain CPU are commented in a footnote (e.g. extended
instructions, refer to section 3.3 "Programming of dedicated instructions".

4–2
Layout and Structure of the Chapters Devices

4.3 Devices
The table "Devices" lists all usable devices that can be used for the internal variables (e.g. s1,
s2, d).
The devices are not listed separately; only a distinction is drawn whether the instruction is
capable of designating bit and/or word devices.

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Constant
Register Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d       — — —
n         —

Whether the instruction supports file register access is indicated in the column "File Register".
The column "MELSECNET/H Direct J\“ specifies whether the instruction supports read/
write operations of bit and/or word data from/to stations connected to the MELSECNET/H.
"J\" specifies the station number and "“ the device number.
The column "Special Function Module U\G“ specifies whether the instruction supports read/
write operations of data from/to the buffer memory of an installed special function module.
"U\“ specifies the head address of the special function module and "G“ the buffer memory
address.
Whether the instruction can apply an index qualification is indicated in the column "Index
Register Zn".
Whether decimal (K) or hexadecimal (H, 16#) constants can be processed by the instruction is
indicated in the column "Constant K, H (16#)".
The column "Other" specifies whether the instruction uses any other devices and constants.
Any particular details are commented in footnotes below the table.

Programming MELSEC System Q and L series 4–3

Representation format of the instruction Layout and Structure of the Chapters

4.4 Representation format of the instruction

4.4.1 Representation in the GX IEC Developer

The device tables are followed by the representation format of the instruction in the GX IEC
Developer.
The figure below from the left to the right shows the representation of the instruction LD_EQ_M
in the MELSEC editor (MELSEC instruction list) and in the IEC editor (ladder diagram and IEC
instruction list).

4.4.2 Representation in GX Works2

The representation format for the instruction in the GX IEC Developer is followed by the repre-
sentation format of the instruction in GX Works2.

4–4
Layout and Structure of the Chapters Variables

4.5 Variables
The table of variables lists all internal variables of the instruction.

The column "Meaning" describes the functions of the devices and device elements.
The column "Data Type" lists the data types of the devices. Provided that there are differences
between the data types of the MELSEC and the IEC editor, these are listed as well. Refer to
the sections 3.4 "Programming of variables" and 3.5 "Data types" for further details on
variables.

4.6 Functions
The section "Functions" describes the functions of the instruction in detail.
The figure below shows the description of the functions of the LDF/LDP instruction.

Programming MELSEC System Q and L series 4–5

Notes Layout and Structure of the Chapters

4.7 Notes
The section "NOTE" points out particular details, errors, and sources of malfunction in the pro-
gramming of the instruction.

NOTE The MEP and MEF instructions will occasionally not function when pulse conversion is ap-
plied to contacts that are indexed by a subroutine or by a FOR/NEXT instruction. In this ca-
se, the EPG/EGF instruction has to be applied.

The MEP/MEF instruction operates with the ooperation results immediately prior to the
MEP and MEF instructions. For this reason, an AND instruction should be used at the
same position. The MEP and MEF instructions cannot be used at the LD or OR position.

4.8 Operation errors

The description of the operation errors mainly refer to the error code list, see section 13.1 "Error
code list".
The figure below shows the operation errors of the DELTA-/DELTAP instruction.

Operation In the following cases an operation error occurs, the error flag (SM0) turns
Errors ON, and an error code is stored into SD0.
 The number of output designated by d exceeds the output range.
(Error code: 4101)

4–6
Layout and Structure of the Chapters Program examples

4.9 Program examples

The program examples given at the end of each section primarily contain programs for the
MELSEC System Q.
The program examples are programmed in the representation format of the ladder diagram.
For a clearer description in many cases graphical illustrations were added.
The figure below shows a program example of the instructions LD, AND, OR, and ORI.

In the following figure a program example for the RBMOVP instruction is shown. The represen-
tation of the instructions is that of the GX Works2.

Programming MELSEC System Q and L series 4–7

Program examples Layout and Structure of the Chapters

4–8
5 Sequence Instructions
Sequence instructions, besides conventional instructions to program input and output con-
tacts, also include program jump commands, block connection instructions and bit shift instruc-
tions, master control, program termination and other instructions. These are the fundamental
instructions for programming the MELSEC series.
The following table shows the division of the fundamental instruction set:

Instruction Meaning
Input instruction Operation start,
series and parallel connection of contacts.
Connection instruction Series and parallel block connection,
storage and processing of operation results,
inversion of operation results,
conversion of operation results into pulses,
setting of edge relays.
Output instruction Bit devices, counter and timer contacts,
output, setting, and resetting of annunciators,
setting and resetting of devices,
leading edge and trailing edge output,
bit device output inversion,
generating pulses.
Shift instruction Shifting bit devices.
Master control instruction Setting and resetting single parts of a program.
Termination instruction End of a part of program,
end of sequence and routine programs.
Miscellaneous instructions Sequence program stop,
no operation.

NOTE The following table, besides the MELSEC instructions in the different editors, also contains the
according IEC instructions:

MELSEC Instruction
in IEC Editor IEC Instruction in
in MELSEC Editor IEC Editor
Instruction List Ladder Diagram

LD — — LD

LDI — — LDN

AND — AND

ANI — ANDN

OR — — OR

ORI — — ORN

LDP LDP_M — — —
LDF LDF_M — — —

ANDP ANDP_M — —

ANDF ANDF_M — —

Programming MELSEC System Q and L series 5–1

 MELSEC Instruction
IEC Instruction in
in IEC Editor IEC Editor
in MELSEC Editor
Instruction List Ladder Diagram

ORP ORP_M — —

ORF ORF_M — —

LDPI
LDFI
ANDPI
ANDFI
ORPI
ORFI

AND (
ANB — — ...
)

OR (
ORB — — ...
)

MPS MPS_M —

MRD MRD_M —

MPP MPP_M —

INV INV_M NOT

MEP MEP_M — —

MEF MEF_M — —

EGP EGP_M — —

EGF EGF_M — —

OUT OUT_M ST

OUT T TIMER_M — —

OUTH T TIMER_H_M — —

OUT C COUNTER_M — —

5–2
 MELSEC Instruction
IEC Instruction in
in IEC Editor IEC Editor
in MELSEC Editor
Instruction List Ladder Diagram
OUT F

SET SET_M S

RST RST_M R

SET F
RST F

PLS PLS_M — R_TRIG 1)

PLF PLF_M — R_TRIG 1)

FF FF_M — —

DELTA DELTA_M — —

DELTAP

SFT SFT_M — SHL/SHR

SFTP

MC MC_M — —

MCR MCR_M — —

FEND FEND_M — 2)

END END_M — 2)

STOP STOP_M — —

NOP — — —
NOPLF
PAGE
1
These are IEC function blocks.
2
FEND and END are set automatically by GX Works2 and the GX IEC Developer.

Programming MELSEC System Q and L series 5–3

LD, LDI, AND, ANI, OR, ORI Input instructions

5.1 Input instructions

5.1.1 LD, LDI, AND, ANI, OR, ORI

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G DX, BL
s       — — 

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List
(IEC Instruction)

GX Works2

Variables Set Data Meaning Data Type

s Devices used as connections bit

5–4
Input instructions LD, LDI, AND, ANI, OR, ORI

Functions Operation start

LD Load (normally open contact)
LDI Load inverse (normally closed contact)
Every operation starts with an LD (LoaD) or an LDI ((LoaD Inverse) instruction.
The LD instruction specifies an NO contact (normally open) and the LDI instruction specifies
an NC contact (normally closed). The device designated by the instruction is the input condition
(operation result) for the following instruction.

Series connection
AND of NO contacts
ANI of NC contacts
Contacts are connected in series via an AND instruction as NO contact or via an ANI instruc-
tion as NC contact.
The device designated by the instruction sets the operation condition for the following instruc-
tion.
Both commands are logical connections and must not be programmed at the beginning of an
operation.

Parallel connection
OR of NO contacts
ORI of NC contacts
Parallel connection of contacts is established via an OR instruction as NO contact or via an
ORI instruction as NC contact.
The device designated by the instruction sets the operation condition for the following instruc-
tion.
Both commands are logical connections and must not be programmed at the beginning of an
operation.

NOTE The devices designated by the instructions can also be word devices. In this case, the condition
of a specified bit is read as contact.
Word devices are designated in hexadecimal code. Bit b11 in D0 for example is designated as
D0.0B.
For further information on addressing bits in word devices refer to chapter 3 "Configuration of In-
structions".

Programming MELSEC System Q and L series 5–5

LD, LDI, AND, ANI, OR, ORI Input instructions

Program LD, AND, OR, ORI

Example 1
The following program shows series and parallel connections of contacts. Bit 5 (b5) in D0 is
also read as contact.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Program LD, LDI, AND, ANI, OR

Example 2
The following program shows combined connections. Some contact points are connected via
ORB and ANB instructions. Bits (b1 and b4) in D6 are read as contacts.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Program LD, AND, ANI

Example 3
The following program outputs operation results of devices at Y35 through Y37.

MELSEC Instruction List Ladder Diagram IEC Instruction List

5–6
Input instructions LDP, LDF, ANDP, ANDF, ORP, ORF

5.1.2 LDP, LDF, ANDP, ANDF, ORP, ORF

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G DX
s       — — 

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

s Devices used as connections bit

Programming MELSEC System Q and L series 5–7

LDP, LDF, ANDP, ANDF, ORP, ORF Input instructions

Functions Pulse operation start

LDP leading edge
LDF trailing edge
Similar to the LD and LDI instructions, these instructions designate contacts specified by bit or
word devices.
The result of the LDP instruction is 1, if the addressed bit of the device changes from 0 to 1 (lead-
ing edge).
The result of the LDF instruction is 1, if the addressed bit of the device changes from 1 to 0 (trail-
ing edge). As single instruction the LDP instruction executes the same function as a PLS instruc-
tion and with the input condition at leading edge generates a pulse output.
The program example on the left shows a ladder diagram applying an LDP instruction. The
example on the right does not apply an LDP instruction.

Pulse series connection

ANDP leading edge
ANDF trailing edge
The ANDP instruction connects a contact in series with a contact specified by a bit or word
device. This contact has the condition 1, if the addressed bit of a device changes from 0 to 1.
Using an ANDF instruction the specified contact has the condition 1, if the addressed bit of a
device changes from 1 to 0.

Pulse parallel connection

ORP leading edge
ORF trailing edge
The ORP instruction connects a contact in parallel to a contact specified by a bit or word
device. This contact has the condition 1, if the addressed bit of a device changes from 0 to 1.
Using an ORF instruction the specified contact has the condition 1, if the addressed bit of a
device changes from 1 to 0.

The following table shows the results of an LDP, LDF, ANDP, ORP, ANDF and ORF instruction:

Device specified by Result of Result of

LDP/LDF/ANDP/ORP/ANDF/ORF Instruction LDP/ANDP/ORP LDF/ANDF/ORF
Bit Device/Word Device Bit Designation Instruction Instruction

0→1 1
0 0
1 0
1→0 1

5–8
Input instructions LDP, LDF, ANDP, ANDF, ORP, ORF

NOTE Word devices are designated in hexadecimal code. Bit b11 in D0 for example is designated as
D0.0B.

Program ORP
Example
With leading edge from X0 or by setting (leading edge) bit 10 (b10) in data register D0, the fol-
lowing program executes a MOV instruction.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 5–9

LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI Input instructions

5.1.3 LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI

CPU High
Basic Process Redundant Universal LCPU
Performance
1) 

1
Availability depending on serial number:
 QnU(D)(H)CPU: The serial number (first five digits) is "10102" or higher.
 QnUDE(H)CPU: The serial number (first five digits) is "10102" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G DX
s       — — 

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2
Bit device number / Word device bit designation (s)
X1/D0.1
LDP

X1/D0.1
LDF

X2/D0.2
ANDP

X2/D0.2
ANDF

ORP

X3/D0.3

ORF

X3/D0.3

Variables Set Data Meaning Data Type

s Devices used as connections bit

5 – 10
Input instructions LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI

Functions Pulse NOT operation start

LDPI leading edge
LDFI trailing edge
LDPI is the leading edge pulse NOT operation start instruction that is on only at the leading
edge of the specified bit device (when the bit device goes from on to off) or when the bit device
is on or off. If a word device has been specified, LDPI is on only when the specified bit is 0, 1,
or changes from 1 to 0.
LDFI is the trailing edge pulse NOT operation start instruction that is on only at the trailing edge
of the specified bit device (when the bit device goes from off to on) or when the bit device is on
or off. If a word device has been specified, LDFI is on only when the specified bit is 0, 1, or
changes from 0 to 1.

Pulse NOT series connection

ANDPI leading edge
ANDFI trailing edge
ANDPI is a leading edge pulse NOT series connection, and ANDFI is a trailing edge pulse NOT
series connection.
ANDPI and ANDFI execute an AND operation with the previous operation result, and take the
resulting value as the operation result.

Pulse NOT parallel connection

ORPI leading edge
ORFI trailing edge
ORPI is a leading edge pulse NOT parallel connection, and ORFI is a trailing edge pulse NOT
parallel connection. ORPI and ORFI execute an OR operation with the previous operation
result, and take the resulting value as the operation result.

The on or off data used by LDPI/LDFI/ANDPI/ANDFI/ORPI/ORFI are indicated in the table

below.
Device specified by Result of Result of
LDPI/LDFI/ANDPI/ANDFI/ORPI/ORFI Instruction LDPI/ANDPI/ORPI LDFI/ANDFI/ORFI
Bit Device/Word Device Instruction Instruction

0→1 1
0 0
1 0
1→0 1

Programming MELSEC System Q and L series 5 – 11

LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI Input instructions

Program LDPI, ORFI

Example 1
The following program stores 0 into D0 when X0 is on, off, or turns from on to off, or M0 is on,
off, or turns from off to on.

Ladder Diagram

Program ANDPI
Example 2
The following program stores 0 into D0 when X0 is on and b10 (bit 11) of D0 is on, off, or turns
from on to off.

Ladder Diagram

5 – 12
Connection instructions ANB, ORB

5.2 Connection instructions

5.2.1 ANB, ORB

CPU High
Basic Performance Process Redundant Universal LCPU

     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
— — — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List
(IEC Instruction)

GX Works2

ANB

Variables Set Data Meaning Data Type

— — —

Programming MELSEC System Q and L series 5 – 13

ANB, ORB Connection instructions

Functions Ladder block series connection

ANB Block series connection
The ANB instruction (AND block) connects two or more parallel connection blocks in series and
supplies an operation result for the following operations.
If more than two blocks are connected in series, after each parallel block an ANB instruction
has to be programmed.
The ANB connection is an independent instruction and does not require any device.
Within one program the ANB instruction can be applied any number of times.
If more than two blocks are connected consecutively, the number of ANB instructions is limited
to 15 (= 16 blocks). Exceeding this limit results in malfunction.

Ladder block parallel connection

ORB Block parallel connection
The ORB instruction (OR block) connects two or more series connection blocks in parallel and
supplies an operation result for the following operations.
If more than two blocks are connected in parallel, after each series block an ORB instruction
has to be programmed.
For block parallel connections designating one contact only an OR or ORI instruction has to be
set.

The ORB connection is an independent instruction and does not require any device.
Within one program the ORB instruction can be applied any number of times.
If more than two blocks are connected consecutively, the number of ORB instructions is limited
to 15 (= 16 blocks). Exceeding these limits results in malfunction.

Program ANB, ORB

Example
The following program connects the parallel connection block of X0 and X2 in series with the
parallel connection block of X1 and X3. The result is connected in parallel with the series con-
nection of X4 an X5.

MELSEC Instruction List Ladder Diagram IEC Instruction List

5 – 14
Connection instructions MPS, MRD, MPP

5.2.2 MPS, MRD, MPP

NOTE These instructions should not be used within the IEC editors.

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
— — — — — — — — — —

GX IEC
Developer
MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

— — —

Programming MELSEC System Q and L series 5 – 15

MPS, MRD, MPP Connection instructions

Functions Operation result processing

MPS Store operation result (memory push)
The MPS instruction stores the operation result preceding the MPS instruction.
Up to 16 consecutive MPS instructions per network can be programmed.
If the MPP instruction is used during this process, the number of uses calculated for the MPS
instruction will be decremented by one.
MRD Read operation result (memory read)
The MRD instruction reads stored operation results via an MPS instruction. The following oper-
ation executed depends on the reading result.
MPP Read and clear operation result (memory pop)
The MRD instruction reads stored operation results via an MPS instruction. The following oper-
ation executed depends on the reading result. Then the result is cleared.
Subtracts 1 from the number of MPS instruction times of use.

The MPS, MRP and MPP instructions are independent instructions and do not require any
device.
In ladder programming mode the MPS, MRD and MPP instructions are not displayed explicitly.
Whether connections are of the MPS, MRD or MPP type depends on the structure of the ladder
diagram.
The example on the left shows a ladder diagram applying MPS, MRD or MPP instructions. The
example on the right shows a ladder diagram without MPS, MRD or MPP instructions.

The number of MPS instructions in a program must equal the number of MPP instructions. Fail-
ure to observe this will not correctly display the ladder in the ladder mode of the peripheral
device.

5 – 16
Connection instructions MPS, MRD, MPP

Program MPS, MRD, MPP

Example 1
The following program illustrates the use of instructions for programming combined connec-
tions.

MELSEC Instruction List Ladder Diagram

Program MPS, MRD, MPP

Example 2
The following program illustrates the programming of instructions that output interim results in
a series connection.

MELSEC Instruction List Ladder Diagram

Programming MELSEC System Q and L series 5 – 17

INV Connection instructions

5.2.3 INV

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
— — — — — — — — — —

GX IEC
Developer
MELSEC Instruction List Ladder Diagram IEC Instruction List
(IEC Instruction)

GX Works2

Variables Set Data Meaning Data Type

— — —

5 – 18
Connection instructions INV

Functions Operation result inversion

INV Inversion instruction
The INV instruction inverts the operation result preceding the INV instruction.
 If the result is 1 before the operation it will be 0 afterwards.
 If the result is 0 before the operation it will be 1 afterwards.

Program The following program inverts the status of X0 and outputs the inverted signal at Y10.
Example

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 5 – 19

MEP, MEF Connection instructions

5.2.4 MEP, MEF

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
— — — — — — — — — —

GX IEC
Developer
MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

— — —

5 – 20
Connection instructions MEP, MEF

Functions Operation result into pulse conversion

MEP Pulse generation at leading edge of operation result
The MEP instruction is used in cases where the applied instructions cannot output operation
results as specified pulse output.
The MEP instruction is set after the according instruction and generates one output pulse,
when the input signal changes from 0 to 1 (at leading edge). The next pulse is generated when
the input is at leading edge once again.

MEF Pulse generation at trailing edge of operation result

The MEF instruction is used in cases where the applied instructions cannot output operation
results as specified pulse output. The MEF instruction is set after the according instruction and
generates one output pulse, when the input signal changes from 1 to 0 (at trailing edge). The
next pulse is generated when the input is at trailing edge once again.
These two instructions are especially suitable for multiple contacts connections. For example,
multiple NO contacts (normally open contacts) connected in series would maintain the opera-
tion result 1 if they were all closed. If a relay was set by this operation result, it could not be
reset. With a MEP instruction connected in series with these NO contacts the relay could be
reset because the instruction outputs one pulse only, if the series connection result of all con-
tacts changes from 0 to 1.

NOTE The MEP and MEF instructions will occasionally not function properly when pulse conversion is
applied to contacts that are indexed by a subroutine or by a FOR/NEXT instruction. In this case,
the EGP/EGF instruction has to be applied.
The MEP/MEF instruction operates with the operation results immediately prior to the MEP and
MEF instructions. For this reason, an AND instruction should be used at the same position. The
MEP and MEF instructions cannot be used at the LD or OR position.

Program MEP
Example
With leading edge from the series connection result at X0 and X1, the following program sets
the relay M0.

MELSEC Instruction List IEC Instruction List

Ladder Diagram

Programming MELSEC System Q and L series 5 – 21

EGP, EGF Connection instructions

5.2.5 EGP, EGF

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G V
d — — — — — — — — 

GX IEC
Developer
MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

d Edge relay, storing the operation result. bit (V only)

Functions Pulse conversions of edge relay operation results

EGP Switching an edge relay with leading edge of an operation result
Operation results up to the EGP instruction are stored in memory by the edge relay (V). Goes
ON (continuity status) at the leading edge (OFF to ON) of the operation result up to the EGP
instruction. If the operation result up to the EGP instruction is other than a leading edge (i.e.,
from ON to ON, ON to OFF, or OFF to OFF), it goes OFF (non-continuity status).

EGF Switching an edge relay with trailing edge of an operation result

Operation results up to the EGF instruction are stored in memory by the edge relay (V). Goes
ON at the trailing edge (from ON to OFF) of the operation result up to the EGF instruction. If
the operation result up to the EGF instruction is other than a trailing edge (i.e., from OFF to
ON, ON to ON, or OFF to OFF), it goes OFF (non-continuity status).
The EGP and EGF instructions are used for subroutine programs, and for conducting pulse
operations for programs designated by indexing between the FOR and NEXT instructions.
The EGP and EGF instructions can be used like an AND instruction.

5 – 22
Connection instructions EGP, EGF

Program EGP
Example
The following program first resets the index register Z0 to 0 and then calls the subroutine UP1 (1).
With leading edge X0Z0 is set to X0 and V0Z0 is set to V0. Further, D0Z0 is set to D0 and incre-
mented by 1.
After returning, the index register Z0 stores 1, and the subroutine is called again (2). With leading
edge from X1, V1 is set and D1 is incremented.

MELSEC Instruction List IEC Instruction List

Ladder Diagram

Programming MELSEC System Q and L series 5 – 23

OUT Output instructions

5.3 Output instructions

5.3.1 OUT

CPU High
Basic Performance Process Redundant Universal LCPU

     

Devices Usable Devices

Internal Devices MELSECNET/H Special
Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G DY
d 1)      — — 

1
Except T, C, F

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List
(IEC Instruction)

GX Works2

Variables Set Data Meaning Data Type

d Number of device to be set (1) or reset (0). bit

5 – 24
Output instructions OUT

Functions Output instruction

OUT Out instruction (excluding timers, counters, and annunciators)
An output is set depending on the preceding input condition.
Several OUT instructions can be programmed in parallel following an input condition.
The operation result of an OUT contact can be used as input condition for the following pro-
gram steps as NO contact (normally open) or NC contact (normally closed).
.

OUT Instruction
Bit Device or Word Contact Type
Input Condition Output Contact Device Bit Designa-
tion NO Contact NC Contact
0 OFF 0 Non-continuity Continuity
1 ON 1 Continuity Non-continuity

NOTE See section 3.12.1 for the operation to be performed when the OUT instruction for the same
device is executed more than once during one scan.

Program OUT
Example 1
The following program shows the programming of an OUT instruction using bit devices as out-
puts (Y33 through Y35).

MELSEC Instruction List Ladder Diagram IEC Instruction List

Program OUT
Example 2
The following program shows the programming of an OUT instruction using bits of the word
device D0 (bits b5 through b7).

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 5 – 25

OUT T, OUTH T Output instructions

5.3.2 OUT T, OUTH T

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K Other
Bit Word Bit Word U\G
d 1) — — — — — — — —
3) 4)
2) —   —   —  —
1
T only
2
Time setting
3
Except T, C
4
Specification of time settings by decimal constants (K) only. Hexadecimal constants cannot be read.

GX IEC
MELSEC Instruction List Ladder Diagram
Developer

IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

d Number of timer bit
Set value Timer setting value BIN 16-bit

5 – 26
Output instructions OUT T, OUTH T

Functions Setting timers

OUT T Low speed timer (100 ms)
OUTH T High speed timer (10 ms)
When the operation results up to the OUT(H) T instruction are ON, the timer coil goes ON and
the timer counts up to the value that has been set. This time is designated directly by a constant
or variably by the value in a data register.
After the specified time has passed (setting value  actual value ) the succeeding input contact
is set.
The operation result of the OUT(H) T contact is programmed as input condition in one (or sev-
eral) following program step(s) like a common NO (normally open) or NC (normally closed)
contact.
Several OUT(H) T instructions can be programmed succeeding one single input condition.
The contact responds as follows when the operation result up to the OUT instruction is a
change from ON to OFF:

Timer Timer as Input Condition

Actual Prior to Time Up After Time Up

Type Timer Coil
Value NO contact NC contact NO contact NC contact
Low speed
(100 ms)
OFF 0 Non-continuity Continuity Non-continuity Continuity
High speed
(10 ms)
Low speed
(100 ms),
retentive Actual value
OFF maintained Non-continuity Continuity Continuity Non-continuity
High speed
(10 ms),
retentive

To clear the present value of a retentive timer and turn the contact OFF after time up, use the
RST instruction.
A negative number (–32768 to –1) cannot be set as the setting value for the timer. If the setting
value is 0, the timer will time out when the OUT(H) T instruction is executed. Please note: When
specifying a setting value for the timer using a word device the value is not checked whether it is
in the setting range. Check the value in the user program so that a negative number is not set.
The execution of the OUT(H) T instruction performs as follows:
– The timer coil designated by d is set or reset.
– The according timer contact is set or reset.
– The time settings are refreshed.
If a program jumps to an OUT(H) T instruction while it is executed, the contact conditions and
timer settings are maintained.
If one instruction is executed repeatedly within one cycle, the value of the repetitions is
refreshed.
Indexing for timer coils or contacts can be conducted only by Z0 or Z1. Timer setting value has
no limitation for indexing.

Programming MELSEC System Q and L series 5 – 27

OUT T, OUTH T Output instructions

NOTE Timer’s time limit

Time limit of the timer is set in the PLC system of the PLC parameter dialog box.

Basic Model QCPU, High Perform-

ance model QCPU, Process CPU, Universal model QCPU, LCPU
Type of Timer Redundant CPU
Setting Range Setting Unit Setting Range Setting Unit
Low speed timer 1 ms to 1000 ms 1 ms to 1000 ms
1 ms 1 ms
Low speed retentive timer (Default: 100 ms) (Default: 100 ms)
High speed timer 0.1 ms to 100.0 ms 0.01 ms to 100.0 ms
0.1 ms 0.01 ms
High speed retentive timer (Default: 10.0 ms) (Default: 10.0 ms)

Please refer to section A.5.4 for more information about timers.

Program OUT T
Example 1
10 seconds after setting X0, the following program sets the outputs Y10 and Y14. A low speed
timer (T1, 100 ms) is used.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Program OUT T
Example 2
The following program reads the time setting via the inputs X10 to X1F in BCD data format.
With leading edge from X0 BCD data is converted into BIN data first and stored in D10. After
setting X2 the time setting is read. After the set time has passed Y15 is set. A low speed timer
(T2, 100 ms) is used.

MELSEC Instruction List Ladder Diagram IEC Instruction List

5 – 28
Output instructions OUT T, OUTH T

Program OUTH T
Example 3
250 ms after setting X10 the following program sets the output Y10. A high speed timer (10 ms)
is used.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 5 – 29

OUT C Output instructions

5.3.3 OUT C

CPU High
Basic Performance Process Redundant Universal LCPU

     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant Other
Register Module Zn K
Bit Word Bit Word U\G
d 1) — — — — — — — —
2) — 3)  —   — 4) —
1
C only
2 Count setting
3
Except T, C
4
Specification of count settings by decimal constants (K) only. Hexadecimal constants cannot be read.

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

d Number of counter bit
Set value Counter setting value BIN 16-bit

5 – 30
Output instructions OUT C

Functions Setting counters

OUT C Counter
When the operation results up to the OUT instruction change from OFF to ON, 1 is added to
the present value (count value).
The count up status (present value set value), and the contacts respond as follows:
No count is conducted with the operation results at ON. There is no need to perform pulse con-
version on count input.
After the count up status is reached, there is no change in the count value or the contacts until
the RST instruction is executed.
A negative number ( –32768 to –1) cannot be set as the setting value for the timer. If the set
value is 0, the processing is identical to that which takes place for 1.
Indexing for the counter coil and contact can use only Z0 and Z1. Counter setting value has no
limitation for indexing.

NOTE Please refer to section A.5.5 of this manual for more information about counters.

Program OUT C
Example 1
After X0 has been set for 10 times, the following program sets Y30 and if X1 is set resets Y30.

MELSEC Instruction List Ladder Diagram

IEC Instruction List

Programming MELSEC System Q and L series 5 – 31

OUT C Output instructions

Program OUT C
Example 2
The following program sets the setting value in C10 to 10 (D0 =10) with leading edge from X0,
and to 20 (D0 =20) with leading edge from X1.
If X3 is set, the counter starts counting and sets Y30 when it reaches the setting value in D0.

MELSEC Instruction List Ladder Diagram

IEC Instruction List

5 – 32
Output instructions OUT F

5.3.4 OUT F

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
d 1) — — — — — — — —
1
F only

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List
(IEC Instruction)

GX Works2

Variables Set Data Meaning Data Type

d Number of annunciator to be set bit (F only)

Programming MELSEC System Q and L series 5 – 33

OUT F Output instructions

Functions Output of annunciators

OUT F Annunciator
If the input condition of an OUT F instruction is set, the annunciator is set and the following
operations are performed:
● The "USER" LED ("ERR." LED for Basic model QCPU) lights up.
● The numbers of set annunciators are stored in the special registers SD64 through SD79.
● The value in SD63 is incremented by 1.
If special register SD63 stores the value 16, i.e. 16 annunciators are already ON, no further
numbers are stored in the range of SD64 through SD79.
If an annunciator is reset via an OUT instruction, the condition of the "USER" LED ("ERR." LED
for Basic model QCPU), and the content of the special registers SD63 through SD79 are main-
tained.
Annunciators, registers, and displays are cleared via the RST F instruction.

Program OUT F
Example
If X0 is set, the following program sets the annunciator F7. The number 7 is stored in the reg-
isters SD64 through SD79. The value in register SD63 is incremented by 1 (i.e. 1 number of
annunciator stored).

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
X0 is set

5 – 34
Output instructions SET

5.3.5 SET

CPU High
Basic Performance Process Redundant Universal LCPU

     

Devices Usable Devices

Internal Devices MELSECNET/H Special
Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G BL DY
 1) 1)     
d  — —
1
Except T, C

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction

GX Works2

Variables Set Data Meaning Data Type

d Number of bit device (output contact) to be set / word device bit designation. bit

Programming MELSEC System Q and L series 5 – 35

SET Output instructions

Functions Setting of devices

SET Set instruction
The SET instruction consists of a SET command followed by a number (address) of device d
to be set.
When the execution command is turned ON, the status of the designated device (bit device or
designated bit of word device) is set to 1.
If the input condition is reset once again, the set device remains set. A device can be reset via
the RST instruction.

:#
5-6 ;
:%
456 ;

NOTE See section 3.12.2 for the operation to be performed when the SET instruction for the same
device is executed more than once during one scan.

Program SET
Example 1
If X8 is set, the following program sets the output Y8B. If X9 is set, Y8B is reset.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Program SET
Example 2
If X8 is set, the following program sets bit 5 (b5) in D0 from 0 to 1. If X9 is set, this bit is reset.

MELSEC Instruction List Ladder Diagram IEC Instruction List

5 – 36
Output instructions RST

5.3.6 RST

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G DY
d        — 

GX IEC
IEC Instruction List
Developer MELSEC Instruction List Ladder Diagram (IEC Instruction)

GX Works2

Variables Set Data Meaning Data Type

d Device to be reset bit, BIN 16-bit

Programming MELSEC System Q and L series 5 – 37

RST Output instructions

Functions Resetting devices

RST Reset instruction
The RST instruction consists of an RST command followed by a number (address) of device d
to be reset.
After execution of the RST instruction input and output contacts of bit devices are switched off
(0), actual values of timers and counters (T, C) are reset to 0 and the according contacts are
switched off, the designated bit of a word device is reset to 0, and the content of word devices
is reset to 0.
The functions of the word devices designated by the RST instruction are identical to that of the
MOV instruction in the following diagram on the right.

NOTE See section 3.12.2 for the operation to be performed when the RST instruction for the same de-
vice is executed more than once during one scan.

Program RST
Example 1
With leading edge from X0, the following program stores the content at X10 through X1F in the
data register D8. If X5 is set, the content of D8 is reset to 0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

5 – 38
Output instructions RST

Program RST T, C
Example 2
The following program illustrates resetting of retentive timers and counters.
In the first program step T225 is set, if X4 has been set for 30 minutes (18000 seconds).
In the second program step C23 counts the number of times T225 is set.
If this timer is set for 16 times (setting value of C23 = 16) the output Y55 is set.
If X5 is set, the counter will be reset to 0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 5 – 39

SET F, RST F Output instructions

5.3.7 SET F, RST F

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
d 1) — — — — — — — —
1
F only

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List
(IEC Instruction)

GX Works2

Variables Set Data Meaning Data Type

d (SET) Number of annunciator to be set bit (F only)
d (RST) Number of annunciator to be reset bit (F only)

5 – 40
Output instructions SET F, RST F

Functions Setting and resetting of annunciators

SET F Set instruction
The SET F instruction consists of a SET command followed by an annunciator number desig-
nated by d to be set.
After execution of the input condition, the designated device number d is set. The SET instruc-
tion outputs a pulse to set an annunciator.
The following procedures are executed:
 The "USER" LED lights up. ("ERR." LED for Basic model QCPUs)
 The numbers (addresses) of set annunciators are stored in the registers SD64 through
SD79.
 The value in SD63 is incremented by 1.
If special register SD63 stores the value 16, i.e. 16 annunciators are already ON, no further
numbers are stored in the range of SD64 through SD79.

RST F Reset instruction

The RST F instruction consists of an RST command followed by an annunciator number des-
ignated by d to be reset.
After execution of the input condition the designated device number is reset. The output signal
resetting an annunciator is a pulse.
The number of a reset annunciator is cleared from the registers SD64 through SD79 and the
value in register SD63 is decremented by 1. If the value in the register SD63 was 16 and annun-
ciators are cleared from this register via an RST F instruction then those annunciator numbers
are stored that could not be stored before. These annunciator numbers are stored in the
cleared registers within SD64 through SD79.
If the value in special register SD63 is decremented to 0 and all annunciators are reset, the
"USER" LED turns off ("ERR." LED for Basic model QCPUs).
In the diagram below F30 is set in a first step (1) but cannot be registered because there are
16 numbers already stored. In a second step (2) F90 is reset. Thus, in a third step (3) F30 can
be stored in SD79 because the other stored annunciators are shifted up by one cleared register
(SD65).

Programming MELSEC System Q and L series 5 – 41

SET F, RST F Output instructions

Program SET F/ RST F

Example
If X1 is set, the following program sets the annunciator F11. The number 11 is stored in the
registers SD64 through SD79 and the value in SD63 is incremented by 1 (1). Then, if X2 is set,
the annunciator F11 is reset. The number 11 is cleared from the special registers SD64 through
SD79 and the value in SD63 is decremented by 1 (2).

MELSEC Instruction List Ladder Diagram IEC Instruction List

5 – 42
Output instructions PLS, PLF

5.3.8 PLS, PLF

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G DY
d       — — 

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

d Device of which the output signal is converted into a pulse bit

Programming MELSEC System Q and L series 5 – 43

PLS, PLF Output instructions

Functions Leading edge and trailing edge output

PLS Output at leading edge
The PLS instruction consists of the PLS command followed by the number of device d to be set.
The PLS instruction (pulse) with leading edge from the input condition sets a device for one
program scan.

X5
PLS M0

1
One scan

NOTE See section 3.12.3 for the operation to be performed when the PLS instruction for the same de-
vice is executed more than once during one scan.

If the RUN/STOP key switch on the CPU unit is set to STOP while a PLS instruction is
executed, the PLS instruction will not be executed further on after the switch is set back to RUN
even if the input condition is still set.


 

2 2

1
   
1
 
    

  

 



One scan of PLS M0

2
RUN/STOP switch of the CPU switched from RUN to STOP
3 RUN/STOP switch of the CPU switched from STOP to RUN
If a latch relay is designated by a PLS instruction, and the power is turned OFF while a latch
relay is set, after turning ON the power again the designated latch relay is set for one scan.

5 – 44
Output instructions PLS, PLF

PLF Output at trailing edge

The PLF instruction consists of the PLF command followed by the number of device d to be set.
The PLF instruction with trailing edge from the input condition sets a device for one program
scan.

X5
PLF M0

1
One scan

NOTE See section 3.12.4 for the operation to be performed when the PLF instruction for the same
device is executed more than once during one scan.

If the RUN/STOP switch of the CPU unit is set to STOP while a PLS instruction is executed,
the PLS instruction will not be executed further on after the switch is set back to RUN even if
the input condition is still set.

NOTE The device d designated by a PLS or PLF instruction remains set for more than one program
scan if a CJ or similar instruction was applied to jump to the PLS or PLF instruction and the part
of program was not executed.

Program PLS
Example 1
With leading edge from X9, the following program sets the internal relay M9 for one program
scan.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
One scan

Programming MELSEC System Q and L series 5 – 45

PLS, PLF Output instructions

Program PLF
Example2
With trailing edge from X9, the following program sets the internal relay M9 for one program scan.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
One scan

5 – 46
Output instructions FF

5.3.9 FF

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G DY
d       — — 

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

d Number of bit device or designated bit of word device to be inverted. bit

Programming MELSEC System Q and L series 5 – 47

FF Output instructions

Functions Bit device output inversion

FF Inversion of bit output device
The FF instruction inverts the operation condition of the device designated by d with leading
edge at the input of the FF instruction. The device can be a bit device or a specified bit of a
word device. If the condition of the output device is set (1) it will be reset (0) after inversion. If
the condition of the output device is reset (0), it will be set (1) after inversion.

Program FF
Example 1
With leading edge from X9, the following program inverts the output condition of Y10.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Program FF
Example 2
With leading edge from X9, the following program inverts bit 10 (b10) of D10.

MELSEC Instruction List Ladder Diagram IEC Instruction List

5 – 48
Output instructions DELTA, DELTAP

5.3.10 DELTA, DELTAP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G DY
d — — — — — — — — 

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

d Number of direct access output to generate pulse at. bit 1)

1
direct access outputs only

Programming MELSEC System Q and L series 5 – 49

DELTA, DELTAP Output instructions

Functions Generating pulses at direct access outputs

DELTA Pulse conversion of contacts
The DELTA instruction generates a pulse at a direct access output (DY) designated by d, i.e.
the output is set for a certain time only.
If the output designated by the DELTA instruction is DY0, the executed function is identical to
that of the SET/RST instruction (see diagram).
The DELTA(P) instruction is used by commands for leading edge execution in special function
units.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The number of output designated by d exceeds the output range.
(Error code 4101)

Program DELTAP
Example
With leading edge from X20, the following program presets CH1 of the AD61 output unit
mounted at slot 0 of the main base unit. The preset value 0 is stored at addresses 1 and 2 of
the AD61 buffer memory. The DELTAP instruction outputs the preset instruction at DY11.

MELSEC Instruction List Ladder Diagram IEC Instruction List

5 – 50
Shift instructions SFT, SFTP

5.4 Shift instructions

5.4.1 SFT, SFTP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Other
Constant
Register Module Zn
Bit Word Bit Word U\G DY
d 1) 1) 1) 1) 1) 1) — — 

1 Except T and C

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

d Number of device to be shifted. bit

Programming MELSEC System Q and L series 5 – 51

SFT, SFTP Shift instructions

Functions Shift instruction

SFT Shifting bit devices
The SFT instruction shifts devices by one bit. Devices are only shifted via the SFTP instruction,
if the input condition is set (leading edge).
The instruction shifts the condition of a device (specified by d-1) to the destination address d.
The condition of the device with the lower address d-1 is reset. Turn the first device to be shifted
ON with the SET instruction.
If several SFT instructions are applied consecutively, the program starts from the device with
the higher number.
The program below sets the internal relay M10 if X2 is set (2,3). The condition of M10 (1) is
shifted via the SFT P instruction within the shift range (1).

If bits in word devices are shifted, the condition (0/1) of the bit d-1 is shifted to d. The bit d-1 is
reset after the SFT instruction. In the following illustration bit 5 (b5) in D0 is shifted. Bit 4 (b4)
is reset after execution of the instruction.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by d exceeds the range of the corresponding device.
(For the Universal model QCPU and LCPU only.)
(Error code 4101)

5 – 52
Shift instructions SFT, SFTP

Program SFT
Example
With leading edge from X8, the following program shifts the condition of Y57 to Y5B. With lead-
ing edge from X7, Y57 is set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 5 – 53

MC, MCR Master control instructions

5.5 Master control instructions

5.5.1 MC, MCR

NOTE These instructions should not be used within the IEC editors.

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G N DY
n — — — — — — — — 

d       — — 

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

n Level of nesting (N0 – N14). Nesting
d Number of device to set nesting. bit

5 – 54
Master control instructions MC, MCR

Functions Setting and resetting master control

General notes
The MC instruction is applied to create highly efficient ladder switching sequence programs.
After setting the input condition, the program part between the destination d and the MCR
instruction is executed. The master control regions are distinguished by nesting (N). Nesting
can be performed from N0 through N14.
Since the GX IEC Developer Software does not allow a vivid programming of the MC/MCR
instruction, here the ladder diagrams of the GX Works2 Software are shown as an illustration.
The ladder diagram illustrates the function of the MC instruction. If the input X0 is reset, the
program part in level 1 (designated by N1) is skipped (1). If X0 is set, the program part from N1
to the MCR instruction is executed (2).
When programming in the ladder mode, it is not necessary to input MC contacts on the vertical
bus. These are displayed automatically.

MC Activating indicated program parts

The MC instruction is the start instruction for master control to process a specified program
part. If the input condition of the MC instruction is set, the devices between the MC and the
MCR instruction are processed regularly.
The devices between the MC and the MCR instruction are even processed after the input con-
dition of the MC instruction is reset. Therefore, the program scan time in this case is not
decreased. When the input condition is reset, the devices between the MC and the MCR
instruction are processed as follows:

Devices Processing
10 ms timer Count value setting is reset to 0.
100 ms timer Input and output contacts are reset (0).
Retentive 10 ms timer
Retentive 100 ms timer Count value setting and condition of input contacts remai-
ned. Output contact is reset (0).
Counter
Devices in the OUT instruction All outputs are reset.
Devices in the SET, RST, and SFT instruction Actual status remained.

Programming MELSEC System Q and L series 5 – 55

MC, MCR Master control instructions

NOTE If an instruction that does not require any input condition (e.g. FOR/NEXT, EI, DI) is placed bet-
ween the MC and MCR instructions, this instruction is executed by the PLC without regard to the
input condition of the MC instruction.

For one MC instruction, identical nesting levels n are allowed, provided that different numbers
(addresses) of devices are set.
After setting the MC instruction the device designated by d is set. If this device is designated
as input condition elsewhere in the program, the contacts are processed as double contacts
and set or reset in parallel. Therefore, the device designated by d should not be used within
other instructions.

MCR Deactivating indicated program parts

The MCR instruction resets the MC instruction and indicates the end of the program part for
master control.
The MCR instruction must not be set via an input contact.

Notes on programming nesting numbers (addresses):

Nesting can be performed from N0 to N14. The first master control region designated by the
MC instruction has to start with the lowest nesting address and the first MCR instruction has
to start with the highest nesting address. If nesting addresses are designated in a different
order, the nesting levels (1, 2) are not processed accurately by the PLC. The following diagram
illustrates this case.

5 – 56
Master control instructions MC, MCR

If several MCR instructions are progammed consecutively, the program can be shortened by
placing one MCR instruction only with the lowest nesting address to finish all MC program
parts.

Programming MELSEC System Q and L series 5 – 57

MC, MCR Master control instructions

Program MC, MCR

Example
The MC instruction designates a nesting address N to specify the nesting level. Nesting
addresses can be designated within N0 to N14.
The nesting addresses determine the execution sequence of MC program parts. The following
program illustrates designation of different execution levels by nesting addresses. For better
comprehensibility the GX Works2 ladder diagram is shown:

5 – 58
Master control instructions MC, MCR

In addition the GX IEC Developer ladder diagram is shown:

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 5 – 59

FEND Termination instructions

5.6 Termination instructions

5.6.1 FEND

NOTE This instruction should not be used within the IEC editors.

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant
Other
Register Module Zn
Bit Word Bit Word U\G
— — — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

— — —

5 – 60
Termination instructions FEND

Functions End of main routine program

FEND End of program branches
The FEND instruction specifies the end of a program branch. This branch can either be a main
routine program or a subroutine program.
After execution of the FEND instruction the program jumps to the END instruction. The execu-
tion of internal processes like timer/counter processing or CPU self-diagnostics check begin at
program step 1 again.
The program example on the left shows the termination of program branches invoked via the
CJ (conditional jump) instruction.
After execution of the CJ instruction the invoked program part is executed up to the next FEND
instruction. Without execution of the CJ instruction the program jumps back to program step 0
after the next FEND instruction.
The program example on the right shows the execution of the FEND instruction in order to split
a main routine program from a sub-routine or interrupt program.

1
Main routine program
2
Subroutine program
3 Interrupt program

NOTE In the instruction list of the GX Works2 the FEND instruction has to be programmed by the user.
After this program organization unit has been processed no further one will be executed be-
cause it would follow the FEND instruction.
Alternatively to this programming the IEC editor can be used. In that case the FEND instruction
would be set by the GX IEC Developer compiler automatically.

Programming MELSEC System Q and L series 5 – 61

FEND Termination instructions

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The FEND instruction is executed after a CALL, FCALL, ECALL, or EFCALL instruction and
before a RET instruction. (Error code 4211)
● The FEND instruction is executed after a FOR instruction and before a NEXT instruction.
(Error code 4200)
● The FEND instruction is executed during an interrupt program and before an IRET instruction.
(Error code 4221)
● The FEND instruction is executed after a CHKCIR instruction and before a CHKEND instruc-
tion. (Error code 4230)
● The FEND instruction is executed after an IX instruction and before an IXEND instruction.
(Error code 4231)

5 – 62
Termination instructions END

5.6.2 END

NOTE This instruction should not be used within the IEC editors.

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special Other
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G U
— — — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

— — —

Programming MELSEC System Q and L series 5 – 63

END Termination instructions

Functions End of sequence program

END End of sequence program
The END instruction specifies the end of a program. Executing the END instruction the pro-
gram jumps back to program step 0.

1
Sequence program

The END instruction cannot be applied in a program routine. A program routine is terminated
by the FEND instruction.
If the END instruction is missing in a program an error message is returned when starting the
program, and the program execution is terminated by the PLC. Without the END instruction
operation errors even occur, if the capacity of a subprogram is set by parameters.
The following diagram illustrates appropriate programming of the END and FEND instruction:

1
Main routine program
2
Subroutine program
3 Interrupt program

4 Sequence program

NOTE The FEND instruction will be set by both the GX IEC Developer and GX Works2 automatically.

5 – 64
Termination instructions END

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The jump destination of a CJ, SCJ, or JMP instruction is allocated after the END instruction.
● A subprogram or interrupt routine allocated after the END instruction is called.
● The END instruction is executed after a CALL, FCALL, ECALL, or EFCALL instruction and before
a RET instruction. (Error code 4211)
● The END instruction is executed after a FOR instruction and before a NEXT instruction.
(Error code 4200)
● The END instruction is executed during an interrupt program and before an IRET instruction.
(Error code 4221)
● The END instruction is executed after a CHKCIR instruction and before a CHKEND instruction.
(Error code 4230)
● The END instruction is executed after an IX instruction and before an IXEND instruction.
(Error code 4231)

Programming MELSEC System Q and L series 5 – 65

STOP Miscellaneous instructions

5.7 Miscellaneous instructions

5.7.1 STOP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G U
— — — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2

Variables Set Data Meaning Data Type

— — —

5 – 66
Miscellaneous instructions STOP

Functions Sequence program stop

STOP Stop instruction
If the input condition of the STOP instruction is set, all outputs (Y) are reset and all operations
of the PLC are terminated. The STOP instruction has the same function as the STOP position
of the RUN/STOP key switch on the CPU.
On execution of the STOP instruction the bit b4 through bit b7 in special register SD203 store
the binary value 3.

1 Binary value 3

In order to restart the operation of the PLC the RUN/STOP switch has to be switched to STOP
and then to RUN again.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The STOP instruction is executed after a CALL, FCALL, ECALL, EFCALL or XCALL instruction
and before a RET instruction. (Error code 4211)
● The STOP instruction is executed after a FOR instruction and before a NEXT instruction.
(Error code 4200)
● The STOP instruction is executed during an interrupt program and before an IRET instruction.
(Error code 4221)
● The STOP instruction is executed after a CHKCIR instruction and before a CHKEND instruc-
tion.
(Error code 4230)
● The STOP instruction is executed after an IX instruction and before an IXEND instruction.
(Error code 4231)
● The STOP instruction was executed during the fixed scan execution type program.
(For the Universal model QCPU and LCPU only) (Error code 4223)

Program STOP
Example
If X8 is set the following program terminates operation. All following program steps are
executed after switching the RUN/STOP switch to STOP and to RUN again.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 5 – 67

NOP, NOPLF, PAGE n Miscellaneous instructions

5.7.2 NOP, NOPLF, PAGE n

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File- Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
— — — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

NOTE The NOP instruction does not work with the IEC editors. The only way to program this instruc-
tions is by using the MELSEC instruction list.

GX Works2
In the ladder display, NOP is not displayed.

 




   

Variables Set Data Meaning Data Type

— — —

5 – 68
Miscellaneous instructions NOP, NOPLF, PAGE n

Functions No operation program step

NOP No operation program step
The NOP instruction is a no-operation instruction that does not affect any other operations or
program parts. The NOP instruction creates an empty logical program step that can be
replaced by other program instructions during the development of a new program.
The NOP instruction is especially suitable for the following cases:
 To provide space for debugging sequence programs.
 To delete an instruction (over write it) without changing the number of steps.
 To delete an instruction temporarily for later editing.

NOTE After finishing program editing the NOP instructions should be deleted where possible in order
to shorten program scan time.

NOPLF To change pages during printouts

The NOPLF instruction is a no-operation instruction that does not affect any other operations
or program parts. The NOPLF is used when printing from a peripheral device to force a page
change at any desired location.
When printing ladders:
 A page break will be inserted between ladder blocks with the presence of the NOPLF
instruction.
 The ladder cannot be displayed correctly if an NOPLF instruction is inserted in the midst of
a ladder block.
Do not insert an NOPLF instruction in the midst of a ladder block.
When printing instruction lists:
 The page will be changed after the printing of the NOPLF instruction.
Refer to the Operating Manual for the peripheral device in use for details of printouts from
peripheral devices.

PAGE n Subsequent programs will be controlled from step 0 of page n

This is a no operation instruction that has no impact on any operations up to that point.
No processing is performed at peripheral devices with this instruction.

Programming MELSEC System Q and L series 5 – 69

NOP, NOPLF, PAGE n Miscellaneous instructions

Program NOP
Example 1
The following program contains a NOP instruction to replace the contact connection AND for
debugging purposes.

Program NOP
Example 2
The following program example contains a NOP instruction to replace an LD instruction.

Program NOP
Example 3
The following program example contains a NOP instruction to replace an LD instruction.

NOTE Input contacts (LD, LDI) should be replaced by a NOP instruction carefully, because the logical
structure of the program is changed considerably.

5 – 70
Miscellaneous instructions NOP, NOPLF, PAGE n

Program NOPLF
Example 4
The following program example shows the results of a NOPLF instruction.

Printing the ladder will result in the following:

X0
0 MOV K1 D30

MOV K2 D40

5 NOPLF NOPLF instruction,

inserted as a delimiter
of ladder blocks,
causes print out page
to be changed forcibly.
X1
6 Y40

8 END

Printing an instruction list with the NOPLF instruction will result in the following:

0 LD X0

1 MOV K1 D30

3 MOV K2 D40

5 NOPLF Changes print output

page after printing
NOPLF.

6 LD X1

7 OUT Y40

8 END

Programming MELSEC System Q and L series 5 – 71

NOP, NOPLF, PAGE n Miscellaneous instructions

Program PAGE n
Example 5

NOP

5 – 72
6 Application Instructions, Part 1
The application instructions, part 1 comprise instructions that process numerical 16-bit and
32-bit data, floating point data, and character string data. Commonly, these basic instructions
perform comparison and arithmetic operations.

Instruction Meaning
Comparison operation instruction Compares data to data (e.g. =, >, ≥)
Arithmetic operation instruction Adds, subtracts, multiplies, divides, increments, and
decrements BIN and BCD data, floating point data, and
BIN block data
Links character strings
Data conversion instruction Converts data types (e.g. BCD → BIN, BIN → BCD)
Data transfer instruction Transmits designated data
Program branch instruction Program jump commands
Program execution control instruction Enables and disables program interrupts
Refresh instruction Refreshes bit devices, links, and I/O interfaces
Other convenient instructions Count 1- or 2-phase input up or down,
teaching timer, special function timer,
rotary table near path rotation control, ramp signal,
pulse density measurement, fixed cycle pulse output,
pulse width modulation, matrix input

Programming MELSEC System Q and L series 6–1

 Comparison operation instructions

6.1 Comparison operation instructions

Comparison operation instructions compare data values (e.g. equal to =, greater than >, less
than <). Programming the comparison operation instructions is similar to the corresponding
basic instructions:
LD, LDI ⇒ LD=, LDD=
AND, ANI ⇒ AND=, ANDD=
OR, ORI ⇒ OR=, ORD=

MELSEC MELSEC MELSEC MELSEC

Instruction Instruction Instruction Instruction
Function in in Function in in
MELSEC Editor IEC Editor MELSEC Editor IEC Editor
LD= LD_EQ_M LD<= LD_LE_M
AND= AND_EQ_M AND<= AND_LE_M
OR= OR_EQ_M OR<= OR_LE_M
LDD= LDD_EQ_M LDD<= LDD_LE_M
ANDD= ANDD_EQ_M ANDD<= ANDD_LE_M
ORD= ORD_EQ_M ORD<= ORD_LE_M
LDE= LD_EEQ_M LDE<= LD_ELE_M
ANDE= AND_EEQ_M ANDE<= AND_ELE_M
ORE= OR_EEQ_M ORE<= OR_ELE_M

= LDED= ≤ LDED<=
ANDED= ANDED<=
equal less equal
ORED= ORED<=

LD$= LD_STRING LD$<= LD_STRING

_EQ_M _LE_M
AND_STRING AND_STRING
AND$= _EQ_M AND$<= _LE_M
OR_STRING OR_STRING
OR$= OR$<=
_EQ_M _LE_M
BKCMP= BKCMP_EQ_M BKCMP<= BKCMP_LE_M
BKCMP=P BKCMP_EQP_M BKCMP<=P BKCMP_LEP_M
DBKCMP= DBKCMP<=
DBKCMP=P DBKCMP<=P

6–2
Comparison operation instructions

MELSEC MELSEC MELSEC MELSEC

Instruction Instruction Instruction Instruction
Function Function
in in in in
MELSEC Editor IEC Editor MELSEC Editor IEC Editor
LD<> LD_NE_M LD< LD_LT_M
AND<> AND_NE_M AND< AND_LT_M
OR<> OR_NE_M OR< OR_LT_M
LDD<> LDD_NE_M LDD< LDD_LT_M
ANDD<> ANDD_NE_M ANDD< ANDD_LT_M
ORD<> ORD_NE_M ORD< ORD_LT_M
LDE<> LD_ENE_M LDE< LD_ELT_M
ANDE<> AND_ENE_M ANDE< AND_ELT_M
ORE<> OR_ENE_M ORE< OR_ELT_M

≠ LDED<>
< LDED<
ANDED<> ANDED<
not equal less than
ORED<> ORED<
LD_STRING LD_STRING
LD$<> _NE_M LD$< _LT_M
AND_STRING AND_STRING
AND$<> AND$<
_NE_M _LT_M

OR$<> OR_STRING OR$< OR_STRING

_NE_M _LT_M
BKCMP<> BKCMP_NE_M BKCMP< BKCMP_LT_M
BKCMP<>P BKCMP_NEP_M BKCMP<P BKCMP_LTP_M
DBKCMP<> DBKCMP<
DBKCMP<>P DBKCMP<P
LD> LD_GT_M LD>= LD_GE_M
AND> AND_GT_M AND>= AND_GE_M
OR> OR_GT_M OR>= OR_GE_M
LDD> LDD_GT_M LDD>= LDD_GE_M
ANDD> ANDD_GT_M ANDD>= ANDD_GE_M
ORD> ORD_GT_M ORD>= ORD_GE_M
LDE> LD_EGT_M LDE>= LD_EGE_M
ANDE> AND_EGT_M ANDE>= AND_EGE_M
ORE> OR_EGT_M ORE>= OR_EGE_M

> LDED>
≥ LDED>=
ANDED> ANDED>=
greater greater equal
ORED> ORED>=
LD_STRING LD_STRING
LD$> LD$>=
_GT_M _GE_M

AND$> AND_STRING AND$>= AND_STRING

_GT_M _GE_M
OR_STRING OR_STRING
OR$> _GT_M OR$>= _GE_M
BKCMP> BKCMP_GT_M BKCMP>= BKCMP_GE_M
BKCMP>P BKCMP_GTP_M BKCMP>=P BKCMP_GEP_M
DBKCMP> DBKCMP>=
DBKCMP>P DBKCMP>=P

Programming MELSEC System Q and L series 6–3

 Comparison operation instructions

NOTE Within the IEC editors please use the IEC commands.
IEC Commands
Function IEC Command Meaning
= EQ Equal
<> NE Not equal
<= LE Less equal
< LT Less than
>= GE Greater equal
> GT Greater than

Execution Conditions
The following illustration shows the execution conditions for the various comparison operation
instructions.

„ = 1 = ON
… = 0 = OFF

LDORI0B1
NOTE When s1 and s2 are assigned by a hexadecimal constant and the numerical value (8 to F) whose
most significant bit (b15) is "1" is designated as a constant, the value is considered as a negative
BIN value in comparison operation.
The result of the comparison operation 16#8000 > 16#7999 is FALSE (0), although TRUE (1)
would be expected. The values are converted to BIN data and therefore bit 15 (b15) is set. If bit
15 is set, the value becomes negative.

Program Comparison of two-digit BCD values:

Example 1

EINLAB1

8731H is processed as -30927 and 568H as 1384. The comparison operation then is
-30927 > 1384 and Y10 is not set.

6–4
Comparison operation instructions

NOTE For comparison operation instructions with 32-bit data, the numerical input value has to be
determined by a 32-bit instruction like DMOV. The instruction will not be carried out correctly, if
the value was determined by a 16-bit instruction like MOV, because a 32-bit instruction always
applies the n and (n+1) data value.

Program Comparison instruction with 32-bit data:

Example 2

EINLAB2, EINLAB3, LDORI0B2

The example shows two comparison operations with 32-bit data. The first program sets M5,
because both values are determined by the 32-bit instruction DMOV.
The second program has no definite result, because the value in the upper bytes is not defined
definitely.

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6–5

=, < >, >, < =, <, > = Comparison operation instructions

6.1.1 =, < >, >, < =, <, > =

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s1         —
s2         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

V
_
___ME1, V____KE1, V____IE1

GX Works2

VVVV__

Variables Set Data Meaning Data Type

s1
Comparative data, or device storing comparative data BIN 16-bit
s2

6–6
Comparison operation instructions =, < >, >, < =, <, > =

Functions BIN 16-bit data comparison

=, <>, >, <=, <, >= Comparison operation instructions
A 16-bit comparison operation instruction consists of the instruction itself and two designated
devices s1 and s2 to be compared.
The result of the comparison operation is binary ("1" if the comparison is true, "0" if the com-
parison is false). The binary result can be processed as a logical connection result.
The results of the comparison operations for the individual instructions are as follows:
Comparison Operation Results
Instruction Symbol
1 0
= s1 = s2 s1 ≠ s2
<> s1 ≠ s2 s1 = s2
> s1 > s2 s1 ≤ s2
<= s1 ≤ s2 s1 > s2
< s1 < s2 s1 ≥ s2
>= s1 ≥ s2 s1 < s2

NOTE When s1 and s2 are assigned by a hexadecimal constant and the numerical value (8 to F) whose
most significant bit (b15) is "1" is designated as a constant, the value is considered as a negative
BIN value in comparison operation.

Program Comparison operation instruction =

Example 1
The following program compares the data at X0 to XF with the data in D3. It turns ON Y33, if
the data are equal.

MELSEC Instruction List Ladder Diagram IEC Instruction List

V____MB1, V____KB1, V____IB1

Program Comparison operation instruction <>

Example 2
The following program compares BIN value 100 to the data in D3. It turns ON Y33, if the data
in D3 is not equal to 100.

MELSEC Instruction List Ladder Diagram IEC Instruction List

V____MB2, V____KB2, V____IB2

Programming MELSEC System Q and L series 6–7

=, < >, >, < =, <, > = Comparison operation instructions

Program Comparison operation instruction >

Example 3
The following program compares BIN value 100 to the data in D3. It turns ON Y33, if the data
in D3 is less than 100 and M3 is set. Y33 is also switched ON, if M8 and M3 are set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

V____MB3, V____KB3, V____IB3

Program Comparison operation instruction <=

Example 4
The following program compares the data in D0 to the data in D3. It turns ON Y33, if the data
in D0 is less than or equal to D3. Y33 is also switched ON, if M8 and M3 are set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

V____MB4, V____KB4, V____IB4

6–8
Comparison operation instructions D=, D<>, D>, D<=, D<, D>=

6.1.2 D=, D<>, D>, D<=, D<, D>=

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
s1         —
s2         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

D
_
___ME1, D____KE1, D____IE1

GX Works2

D___KE1

Variables Set Data Meaning Data Type

s1
Comparative data, or device storing comparative data. BIN 32-bit
s2

Programming MELSEC System Q and L series 6–9

D=, D<>, D>, D<=, D<, D>= Comparison operation instructions

Functions BIN 32-bit data comparison

D=, D<>, D>, D<=, D<, D>= Comparison operation instructions
A 32-bit comparison operation instruction consists of the instruction itself and two designated
devices s1 and s2 to be compared.
The result of the comparison operation is binary ("1" if the comparison is true, "0" if the com-
parison is false). The binary result can be processed as a logical connection result.
The results of the comparison operations for the individual instructions are as follows:
Comparison Operation Results
Instruction Symbol
1 0
D= s1 = s2 s1 ≠ s2
D<> s1 ≠ s2 s1 = s2
D> s1 > s2 s1 ≤ s2
D<= s1 ≤ s2 s1 > s2
D< s1 < s2 s1 ≥ s2
D>= s1 ≥ s2 s1 < s2

NOTE When s1 and s2 are assigned by a hexadecimal constant and the numerical value (8 to F) whose
most significant bit (b15) is "1" is designated as a constant, the value is considered as a negative
BIN value in comparison operation.

Program Comparison operation instruction D=

Example 1
The following program compares the data at X0 to X1F with the data in D3 and D4. It turns ON
Y33 if the data are equal.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D____MB1, D____KB1, D____IB1

Program Comparison operation instruction D<>

Example 2
The following program compares BIN value 38000 to the data in D3 and D4. It turns ON Y33,
if M3 is set and the data in D3 and D4 are not equal to 38000.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D____MB2, D____KB2, D____IB2

6 – 10
Comparison operation instructions D=, D<>, D>, D<=, D<, D>=

Program Comparison operation instruction D>

Example 3
The following program compares BIN value -80000 to the data in D3 and D4. It turns ON Y33,
if M3 is set and the data in D3 and D4 are less than -80000. Y33 is also switched ON, if M3
and M8 are set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D____MB3, D____KB3, D____IB3

Program Comparison operation instruction D<=

Example 4
The following program compares the data in D0 and D1 to the data in D3 and D4. Y33 is set,
if the data in D3 and D4 are greater than or equal to D0 and D1. Y33 is also switched ON if M3
and M8 are set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D____MB4, D____KB4, D____IB4

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 11

E=, E<>, E>, E< =, E<, E>= Comparison operation instructions

6.1.3 E=, E<>, E>, E< =, E<, E>=

CPU High
Basic Process Redundant Universal LCPU
Performance
1)     

1 Basic model QCPU: The upper five digits of the serial No. are "04122" or higher.

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Register Module Zn E Other
Bit Word Bit Word U\G
s1 —   —   1)  —
1)
s2 —   —     —
1
Available only in multiple Universal model QCPU and LCPU

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

E
_
___ME1, E____KE1, E____IE1

GX Works2

E___KE1

Variables Set Data Meaning Data Type

s1
Comparative data, or device storing comparative data. Real number
s2

6 – 12
Comparison operation instructions E=, E<>, E>, E< =, E<, E>=

Functions Floating point data comparisons (Single precision)

E=, E<>, E>, E<=, E<, E>= Comparison operation instructions
A comparison operation instruction for floating point data consists of the instruction itself and
two designated devices s1 and s2 to be compared.
The result of the comparison operation is binary ("1" if the comparison is true, "0" if the com-
parison is false). The binary result can be processed as a logical connection result.
The results of the comparison operations for the individual instructions are as follows:

Comparison Operation Results

Instruction Symbol
1 0
E= s1 = s2 s1 ≠ s2
E<> s1 ≠ s2 s1 = s2
E> s1 > s2 s1 ≤ s2
E<= s1 ≤ s2 s1 > s2
E< s1 < s2 s1 ≥ s2
E>= s1 ≥ s2 s1 < s2

NOTE In some cases, rounding errors appear and floating point values that were equal before the com-
parison operation are not equal afterwards. In the following example M0 is not switched ON:

E___
NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The value of the designated device is –0. (For the Basic model QCPU, High Performance
model QCPU, Process CPU, Redundant CPU) (Error code 4100)
NOTE: There are CPU modules that will not result in an operation error if –0 is specified.
Refer to section 3.5.1 for details.
● The value of the specified device is outside the following range:
0, ±2–126 ≤ (Value) < ±2128
(For the Universal model QCPU, LCPU)
(Error code 4141)
● The value of the specified device is –0, unnormalized number, nonnumeric, or ± ∞.
(For the Universal model QCPU, LCPU)
(Error code 4140)

Programming MELSEC System Q and L series 6 – 13

E=, E<>, E>, E< =, E<, E>= Comparison operation instructions

Program Comparison operation instruction E=

Example 1
The following program compares floating point data in D0 and D1 to floating point data in D3
and D4. It turns ON Y33, if the data are equal.

MELSEC Instruction List Ladder Diagram IEC Instruction List

E____MB1, E____KB1, E____IB1

Program Comparison operation instruction E<>

Example 2
The following program compares the floating point real number 1.23 to a floating point real
number in D3 and D4. It turns ON Y33, if M3 is set and the data in D3 and D4 are not equal to
1.23.

MELSEC Instruction List Ladder Diagram IEC Instruction List

E____MB2, E____KB2, E____IB2

Program Comparison operation instruction E>

Example 3
The following program compares floating point data in D0 and D1 to floating point data in D3
and D4. It turns ON Y3, if M3 is set and the data in D3 and D4 are less than the data in D0 and
D1.
Y3 is also switched ON, if M3 and M8 are set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

E____MB3, E____KB3, E____IB3

6 – 14
Comparison operation instructions E=, E<>, E>, E< =, E<, E>=

Program Comparison operation instruction E<=

Example 4
The following example compares a floating point number in D0 and D1 to the floating point
number 1.23. It turns ON Y33, if the data in D0 and D1 are less than or equal to 1.23. Y33 is
also switched ON, if M3 and M8 are set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

E____MB4, E____KB4, E____IB4

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 15

ED=, ED<>, ED>, ED< =, ED<, ED>= Comparison operation instructions

6.1.4 ED=, ED<>, ED>, ED< =, ED<, ED>=

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn E
Bit Word Bit Word U\G
s1 —   — — — —  —
s2 —   — — — —  —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2
ED /ED /ED /E /E /E

LD s1 s2

AND s1 s2

OR
s1 s2

E___KE1

Variables Set Data Meaning Data Type

s1
Comparative data, or device storing comparative data. Real number
s2

6 – 16
Comparison operation instructions ED=, ED<>, ED>, ED< =, ED<, ED>=

Functions Floating decimal point data comparisons (Double precision)

ED=, ED<>, ED>, ED< =, ED<, ED>= Comparison operation instructions
A comparison operation instruction for 64-bit floating point data consists of the instruction itself
and two designated devices s1 and s2 to be compared.
The result of the comparison operation is binary ("1" if the comparison is true, "0" if the com-
parison is false). The binary result can be processed as a logical connection result.
The results of the comparison operations for the individual instructions are as follows:

Comparison Operation Results

Instruction Symbol
1 0
ED= s1 = s2 s1 ≠ s2
ED<> s1 ≠ s2 s1 = s2
ED> s1 > s2 s1 ≤ s2
ED<= s1 ≤ s2 s1 > s2
ED< s1 < s2 s1 ≥ s2
ED>= s1 ≥ s2 s1 < s2

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The value of the specified device is not within the following range:
0, ±2 -1022 ≤ (Value of specified device) < ±21024
(Error code 4140)
● The value of the designated device is –0.
(Error code 4140)

Program Comparison operation instruction ED=

Example 1
The following program compares 64-bit floating decimal point real number data at D0 to D3 with
64-bit floating decimal point real number data at D4 to D7.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Programming MELSEC System Q and L series 6 – 17

ED=, ED<>, ED>, ED< =, ED<, ED>= Comparison operation instructions

Program Comparison operation instruction ED<>

Example 2
The following program compares the floating decimal point real number 1.23 with the 64-bit
floating decimal point real number data at D4 to D7.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Program Comparison operation instruction ED>

Example 3
The following program compares 64-bit floating decimal point real number data at D0 to D3 with
64-bit floating decimal point real number data at D4 to D7.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Program Comparison operation instruction ED<=

Example 4
The following program compares the 64-bit floating decimal point data at D0 to D3 with the
floating decimal point real number 1.23.

MELSEC Instruction List Ladder Diagram IEC Instruction List

E____MB4, E____KB4, E____IB4

6 – 18
Comparison operation instructions ED=, ED<>, ED>, ED< =, ED<, ED>=

NOTE Since the number of digits of the real number that can be input by a programing tool is up to 15
digits, the comparison with the real number whose number of significant digits is 16 or more can-
not be made by the instruction shown in this section.
When judging match/mismatch with the real number whose significant digits is 16 or more by the
instruction in this section, compare it with the approximate values of the real number to be com-
pared and judge by the sizes.

EXAMPLE 1 When judging the match of E1.234567890123456+10 (number of significant digits is 16) and the
double-precision floating-point data:

E1.23456789012345+10 E1.234567890123456+10 E1.23456789012346+10

Whether D0 to D3 is within this range is checked.(Values on boundaries are excluded.)

EXAMPLE 2 When judging the mismatch of E1.234567890123456+10 (Number of significant digits is 16)
and the double-precision floating-point data:

E1.23456789012345+10 E1.234567890123456+10 E1.23456789012346+10

Whether D0 to D3 is within this range is checked.(Values on boundaries are included.)

Programming MELSEC System Q and L series 6 – 19

$ =, $ < >, $ >, $ < =, $ <, $ > = Comparison operation instructions

6.1.5 $ =, $ < >, $ >, $ < =, $ <, $ > =

CPU High
Basic Process Redundant Universal LCPU
Performance
    

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Register Module Zn $ Other
Bit Word Bit Word U\G
s1 —   — — — —  —
s2 —   — — — —  —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

S___ME1, S____KE1, S____IE1S

_

GX Works2

S___KE1

Variables Set Data Meaning Data Type

s1
Comparative data, or first number of the device storing comparative data Character string
s2

6 – 20
Comparison operation instructions $ =, $ < >, $ >, $ < =, $ <, $ > =

Functions Character string data comparison

$=, $<>, $>, $<=, $<, $>= Comparison operation instructions
A comparison operation instruction for character string data consists of the instruction itself and
two designated devices s1 and s2 to be compared.
The result of the comparison operation is binary ("1" if the comparison is true, "0" if the com-
parison is false). The binary result can be processed as a logical connection result. The com-
parison is performed with character string data in ASCII code character by character, beginning
with the first character in the string.
The s1 and s2 character strings include all characters from the designated device number up
to the next device storing the code "00H".
If all character strings match, the comparison result for the operations $=, $<=, $>= is 1.

SSSS_0E1

If the character strings are different, the character string with the larger character code will be
the larger one.
Below, the comparison result for the operations $<>, $>, $>= is 1.

SSSS_0E2

If the character strings are different, the first different sized character code determines whether
the character string is larger or smaller.
Below, the comparison result for the operations $<>, $>, $>= is 1.

SSSS_0E3

Programming MELSEC System Q and L series 6 – 21

$ =, $ < >, $ >, $ < =, $ <, $ > = Comparison operation instructions

If the character strings are of different lengths, the data with the longer character string will be
larger.
Below, the comparison result for the operations $<>, $>, $>=, is 1.

SSSS_0E4

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The code "00H" does not exist within the relevant device range of s1 and s2.
(Error code 4101)
● The character string of s1 and s2 exceeds 16383 characters.
(Error code 4101)

NOTE The character string data comparison instruction also checks the device range.
Even though, in cases where one character string exceeds the device range, character string
data is being compared and non-matching characters within the device range are detected. The
comparison operation results are output without returning an error code.

S____AB1, SSSS_0E5
In the example shown above, the s1 character string exceeds the device range, and the most sig-
nificant 16 bits (D12288) were renamed W0. Nevertheless, the comparison result is 0, because
the second character in s1 is detected as different from that in s2. In this case no error code
regarding the device range is returned.
This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 22
Comparison operation instructions $ =, $ < >, $ >, $ < =, $ <, $ > =

Program Comparison operation instruction $=

Example 1
The following program compares character string data in D0 to character string data in D3. It
turns ON Y33, if the data are equal.

MELSEC Instruction List IEC Instruction List

Ladder Diagram

S____MB1, S____KB1, S____IB1

Program Comparison operation instruction $<>

Example 2
The following program compares the character string "ABCDEF" to character string data in
D10. It turns ON Y33, if the data are not equal.

MELSEC Instruction List IEC Instruction List

Ladder Diagram

S____MB2, S____KB2, S____IB2

Programming MELSEC System Q and L series 6 – 23

$ =, $ < >, $ >, $ < =, $ <, $ > = Comparison operation instructions

Program Comparison operation instruction $>

Example 3
The following program compares character string data in D10 to character string data in D100.
It turns ON Y33, if character string data in D10 is greater.

MELSEC Instruction List IEC Instruction List

Ladder Diagram

S____MB3, S____KB3, S____IB3

Program Comparison operation instruction $<=

Example 4
The following program compares character string data in D0 to the character string "12345".
Y33 is set, if character string data in D0 is less than or equal to "12345".

MELSEC Instruction List IEC Instruction List

Ladder diagram

S____MB4, S____KB4, S____IB4

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 24
Comparison operation instructions BKCMP, BKCMPP

6.1.6 BKCMP, BKCMPP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
s1 —   — — — —  —
s2 —   — — — — — —
d    — — — — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

CMPME1, BKCMPKE1, BKCMPIE1B

K

GX Works2

BKCMPGE1

Variables Set Data Meaning Data Type

s1 Comparative data, or first number of the device storing comparative data BIN 16-bit
s2 First number of devices storing comparative data BIN 16-bit
d First number of device storing results of comparison operation Bit
n Number of data blocks compared BIN 16-bit

Programming MELSEC System Q and L series 6 – 25

BKCMP, BKCMPP Comparison operation instructions

Functions BIN block data comparisons

BKCMP Comparison operation instructions
A comparison operation instruction for BIN block data consists of the instruction itself, two des-
ignated devices s1 and s2 to be compared, a device d to store the result, and the number of
datablocks to be compared.
It compares the nth BIN 16-bit block in s1 to the nth BIN 16-bit block in s2, beginning with the
first number of device. The result of each block comparison is stored in d.
If the block comparison result is 1, then 1 is stored in d.
If the block comparison result is 0, then 0 is stored in d.

BKCMP0E1

The comparison operation is conducted in 16-bit units.

The constant designated by s1 must be BIN 16-bit data ranging from -32768 to 32767.

BKCMP0E2

The results of the comparison operations for the individual instructions are as follows:

Comparison Operation Results for nth 16-bit Block

Instruction Symbol
1 0
BKCMP= s1 = s2 s1 ≠ s2
BKCMP<> s1 ≠ s2 s1 = s2
BKCMP> s1 > s2 s1 ≤ s2
BKCMP<= s1 ≤ s2 s1 > s2
BKCMP< s1 < s2 s1 ≥ s2
BKCMP>= s1 ≥ s2 s1 < s2

If all comparison results stored in d are 1, the block comparison signal SM704 is set.
If the device designated by d is already set (1), that device will not change. If the conditions
designated by s1 and s2 are changed and the BKCMP_P instruction is executed, the device
designated by d should be reset (0) before.

6 – 26
Comparison operation instructions BKCMP, BKCMPP

Operation In following case an operation error occurs, the error flag (SM0) turns ON, and an error code
Errors is stored into SD0.
● The BIN block data at s1, s2, or d exceeds the relevant device range.
(Error code 4101)
● The device range from [s1 to (s1) + (n-1)] overlaps with the device range [d to (d) + (n-1)].
(Error code 4101)
● The device range from [s2 to (s2) + (n-1)] overlaps with the device range [d to (d) + (n-1)].
(Error code 4101)
● The device range from [s1 to (s1) + (n-1)] overlaps with the device range [s2 to (s2) + (n-1)].
(Error code 4101)

Program Comparison operation instruction BKCMP=P

Example 1
With leading edge from X20, the following program compares BIN block data in D100 to BIN
block data in R0. The results of the comparison are stored from M10 onward. The number of
blocks (4) to be compared is stored in D0

MELSEC Instruction List Ladder Diagram IEC Instruction List

BKCMPMB1, BKCMPKB1, BKCMPIB1, BKCMP0B1

Programming MELSEC System Q and L series 6 – 27

BKCMP, BKCMPP Comparison operation instructions

Program Comparison operation instruction BKCMP<>P

Example 2
With leading edge from X1C, the following program compares the constant K1000 to the block
data beginning from D10. The number of blocks (4) to be compared is determined by the con-
stant K4. The results of the comparison are stored in b4 through b7 of D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Bits already in this state do not change (see function).
BKCMPMB2, BKCMPKB2, BKCMPIB2, BKCMP0B2

6 – 28
Comparison operation instructions BKCMP, BKCMPP

Program Comparison operation instruction BKCMP<=

Example 3
The following program compares, when X20 is turned ON, block data beginning from D10 to
block data beginning from D30. The number of blocks (3) to be compared is determined by the
constant K3. The results of the comparison are stored from M100 onward.
When all comparison results stored from M100 onward are 1, the block comparison signal
SM704 is set and the character string "ALL ON" is transferred to D100.

MELSEC Instruction List IEC Instruction List

Ladder Diagram

BKCMPMB3, BKCMPKB3, BKCMPIB3, BKCMP0B3

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 29

DBKCMP, DBKCMPP Comparison operation instructions

6.1.7 DBKCMP, DBKCMPP

CPU High
Basic Process Redundant Universal LCPU
Performance
1) 

1 QnU(D)(H)CPU: The serial number (first five digits) is "10102" or higher.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or higher.

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
s1 —   — — — —  —
s2 —   — — — — — —
d  —  — — — — — —
n —        —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2
=, <>, >, <=, <, >=

DBKCMP DBKCMP s1 s2 d n

DBKCMP P DBKCMP P s1 s2 d n

Variables Set Data Meaning Data Type

s1 Comparative data, or first number of the device storing comparative data BIN 32-bit
s2 First number of devices storing comparative data BIN 32-bit
d First number of device storing results of comparison operation Bit
n Number of data blocks compared BIN 16-bit

6 – 30
Comparison operation instructions DBKCMP, DBKCMPP

Functions BIN 32-bit block data comparisons

DBKCMP Comparison operation instructions
A comparison operation instruction for BIN 32-bit block data consists of the instruction itself,
two designated devices s1 and s2 to be compared, a device d to store the result, and the
number of datablocks to be compared.
It compares the nth BIN 32-bit block in s1 to the nth BIN 32-bit block in s2, beginning with the
first number of device. The result of each block comparison is stored in d.
If the block comparison result is 1, then 1 is stored in d.
If the block comparison result is 0, then 0 is stored in d.

b31 b0 b31 b0
(s1)+1, (s1) 1090 (BIN) (s2)+1, (s2) 1000 (BIN) (d) OFF (0)
(s1)+3, (s1)+2 2080 (BIN) (s2)+3, (s2)+2 2000 (BIN) (d)+1 OFF (0)
(s1)+5, (s1)+4 5060 (BIN) n (s2)+5, (s2)+4 5060 (BIN) n (d)+2 ON (1) n

(s1)+n–1, (s1)+n–2 1106 (BIN) (s2)+n–1, (s2)+n–2 1106 (BIN) (d)+n–1 ON (1)

The comparison operation is conducted in 32-bit units.

The constant designated by s1 must be BIN 32-bit data ranging from -2147483648 to
2147483647.

b31 b0
(s2)+1, s2 32700 (BIN) d ON (1)
b31 b0 (s2)+3, (s2)+2 40000 (BIN) d +1 OFF (0)
(s1)+1, s1 32800 (BIN) (s2)+5, (s2)+4 32800 (BIN) n d +2 ON (1) n

(s2)+n 1, (s2)+n 2 2147400 (BIN) d +n 1 OFF (0)

The results of the comparison operations for the individual instructions are as follows:
Comparison operation results for nth 32-bit Block
Instruction Symbol
1 0
DBKCMP= s1 = s2 s1 ≠ s2
DBKCMP<> s1 ≠ s2 s1 = s2
DBKCMP> s1 > s2 s1 ≤ s2
DBKCMP<= s1 ≤ s2 s1 > s2
DBKCMP< s1 < s2 s1 ≥ s2
DBKCMP>= s1 ≥ s2 s1 < s2

If all comparison results stored into the devices starting from the device specified by d to nth
device are ON (1), or one of the results is OFF (0), the special relays will be ON or OFF in
accordance with the conditions as follows.
All results of comparison operation are on (1) All results of comparison operation are off (0)
Interrupt Interrupt
Relay (other than (other than
Initial executi- Initial executi-
on/scan I45)/ Interrupt (I45) on/scan I45)/ Interrupt (I45)
Fixed scan Fixed scan
execution execution
SM704 ON ON ON OFF OFF OFF
SM716 ON — — OFF — —
SM717 — ON — — OFF —
SM718 — — ON — — OFF

In a standby program, a special relay depending on the caller program turns on or off.
If the value specified by n is 0, the instruction will be not processed.

Programming MELSEC System Q and L series 6 – 31

DBKCMP, DBKCMPP Comparison operation instructions

Operation In following case an operation error occurs, the error flag (SM0) turns ON, and an error code
Errors is stored into SD0.
● A negative value is specified for n.
(Error code 4100)
● The BIN block data at s1, s2, or d exceeds the relevant device range.
(Error code 4101)
● The device range of the n-point devices starting from the device specified by s1 overlaps
with the range of the n-point devices starting from the device specified by d.
(Error code 4101)
● The device range of the n-point devices starting from the device specified by s2 overlaps
with the range of the n-point devices starting from the device specified by d.
(Error code 4101)

Program Comparison operation instruction DBKCMP<>

Example 1
The following program compares the value data stored at R0 to R5 with the value data stored
at D20 to D25, and then stores the operation result into Y0 to Y2, when M0 is turned on.

MELSEC Instruction List Ladder Diagram IEC Instruction List

b31 b0 b31 b0
R1,R0 -2147483000 D21,D20 -2147483000 Y0 OFF (0)
R3,R2 0 D23,D22 1 Y1 ON (1)
R5,R4 2147483000 D25,D24 2147482999 Y2 ON (1)

6 – 32
Comparison operation instructions DBKCMP, DBKCMPP

Program Comparison operation instruction DBKCMP>=

Example 2
The following program compares the constant with the value data stored at D0 to D9, and then
stores the operation result into D10.5 to D10.9, when M0 is turned ON.

MELSEC Instruction List Ladder Diagram IEC Instruction List

b31 b0
D1,D0 -70000 D10.5 ON (1)
b31 b0 D3,D2 50000 D10.6 OFF (0)
-60000 D5,D4 -32768 D10.7 OFF (0)
D7,D6 32767 D10.8 OFF (0)
D9,D8 0 D10.9 OFF (0)

NOTE When certain bits are specified in a word device, bits other than the certain bits that store the
operation result do not change.

D10.F D10.0
Before execution 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0

D10.F D10.0
After execution
0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0

No change No change

Programming MELSEC System Q and L series 6 – 33

DBKCMP, DBKCMPP Comparison operation instructions

Program Comparison operation instruction DBKCMP<=

Example 3
The following program compares the value data stored at D0 to D5 with the value data stored
at D10 to D15, and then stores the operation result into M20 to M22, when M0 is turned ON.
Also, the program transfers the character string "ALL ON" to D100 and up when all devices
from M20 to M22 have reached the ON status.

MELSEC Instruction List Ladder Diagram IEC Instruction List

b31 b0 b31 b0
D1,D0 -2147483000 D11,D10 -2147483000 M20 ON (1)
D3,D2 60000 D13,D12 60001 M21 ON (1)
D5,D4 -900000 D15,D14 -899999 M22 ON (1)

When all operation results are on (1), the special relays (1)
SM704 ON
corresponding to each program turn on (1).
(Since this program examples refer to scan programs, SM716 ON (1)
SM704 and SM716 turn on (1), SM717 and SM718 do SM717 OFF (0)
not change in the scan program)
SM718 OFF (0)

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 34
Arithmetic operation Instructions

6.2 Arithmetic operation Instructions

Arithmetic operation instructions perform simple calculations like addition, subtraction, multipli-
cation, and division.
BIN BCD
Function MELSEC Instruction MELSEC Instruction MELSEC Instruction MELSEC Instruction
in in in in
MELSEC Editor IEC Editor MELSEC Editor IEC Editor
PLUS_M, BPLUS_M,
+ PLUS_3_M B+ BPLUS_3_M

+
PLUSP_M, BPLUSP_M,
+P B+P
PLUSP_3_M BPLUSP_3_M
Addition D+ DPLUS_M, DB+ DBPLUS_M,
DPLUS_3_M DBPLUS_3_M
DPLUSP_M, DBPLUSP_M,
D+P DB+P
DPLUSP_3_M DBPLUSP_3_M

- MINUS_M, B- BMINUS_M,
MINUS_3_M BMINUS_3_M

−
MINUSP_M, BMINUSP_M,
-P MINUSP_3_M B-P BMINUSP_3_M
Subtraction DMINUS_M, DBMINUS_M,
D- DB-
DMINUS_3_M DBMINUS_3_M

D-P DMINUSP_M, DB-P DBMINUSP_M,

DMINUSP_3_M DBMINUSP_3_M
× MULTI_3_M B× BMULTI_M
× ×P MULTIP_3_M B×P BMULTIP_M
Multiplication D× DMULTI_3_M DB× DBMULTI_M
D×P DMULTIP_3_M DB×P DBMULTIP_M
/ DIVID_3_M B/ BDIVID_M
/ /P DIVIDP_3_M B/P BDIVIDP_M
Division D/ DDIVID_3_M DB/ DBDIVID_M
D/P DDIVIDP_3_M DB/P DBDIVIDP_M
INC INC_M
+1 INCP INCP_M
Increment DINC DINC_M
DINCP DINCP_M
DEC DEC_M
−1 DECP DECP_M
Decrement DDEC DDEC_M
DDECP DDECP_M

NOTE Within the IEC editors please use the IEC commands.

Programming MELSEC System Q and L series 6 – 35

 Arithmetic operation Instructions

Floating Point Data BIN Block Data

Function MELSEC Instruction MELSEC Instruction MELSEC Instruction MELSEC Instruction

in in in in
MELSEC Editor IEC Editor MELSEC Editor IEC Editor

E+ EPLUS_M, BK+ BKPLUS_M

EPLUS_3_M

+ E+P
EPLUSP_M,
BK+P BKPLUSP_M
EPLUSP_3_M
Addition
ED+ DBK+

ED+P DBK+P

E- EMINUS_M, BK- BKMINUS_M

EMINUS_3_M

− E-P
EMINUSP_M,
BK-P BKMINUSP_M
EMINUSP_3_M
Subtraction
ED- DBK-

ED-P DBK-P

E× EMUL_M

× E×P EMULP_M

Multiplication EDx

EDxP

E/ EDIV_M

/ E/P EDIVP_M

Division ED/

ED/P

Character String Data

Function MELSEC Instruction MELSEC Instruction
in in
MELSEC Editor IEC Editor

+
STRING_PLUS_M,
$+
STRING_PLUS_3_M
Addition $+P STRING_PLUSP_M,
STRING_PLUSP_3_M

NOTE Within the IEC editors please use the IEC commands.

6 – 36
Arithmetic operation Instructions

BIN data arithmetic operation instructions

If the result of the addition exceeds a BIN value 32767 (2147483647 for a 32-bit instruction), a
negative value is generated (overflow).
If the result of the subtraction falls below a BIN value -32768 (-2147483647 for a 32-bit instruc-
tion), a positive value is generated (underflow).
The calculation of positive and negative values appears as follows:
5 + 8 = 13
5 - 8 = -3
5 × 3 = 15
-5 × 3 = -15
-5 × (-3) = 15
5 / 3 = 1 remainder 2
-5 / 3 = -1 remainder -2
5 / (-3) = -1 remainder 2
-5 / (-3) = 1 remainder -2

BCD data arithmetic operation instructions

If the result of the addition exceeds 9999 (99999999 for a 32-bit instruction), the higher bits are
ignored (overflow). The carry flag in this case is not set.

1 Carry ignored
BCD_0E1

If the result of the subtraction falls below 0000 (underflow), the carry is processed as shown:

2
Carry
BCD_0E2

Programming MELSEC System Q and L series 6 – 37

+, +P, -, -P Arithmetic operation Instructions

6.2.1 +, +P, -, -P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —
s1         —
s2         —
d1        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

PLUS_ME1, PLUS_KE1, PLUS_IE1P

L

GX Works2

PLUS_GE1

Variables Set Data Meaning Data Type

Addition or subtraction data, or first number of device storing addition or
s
subtraction data
Data to be added to or subtracted from, or first number of device storing such
d
data
Data to be added to or subtracted from, or first number of device storing such BIN 16-bit
s1
data
Addition or subtraction data, or first number of device storing addition or
s2
subtraction data
d1 First number of device storing addition or subtraction data

6 – 38
Arithmetic operation Instructions +, +P, -, -P

Functions BIN 16-bit addition and subtraction operations

+ BIN addition (16-bit)
● Variation 1:
BIN 16-bit data in d is added to BIN 16-bit data in s. The result of the addition is stored in d.

PLUSP0E1

● Varation 2:
BIN 16-bit data in s1 is added to BIN 16-bit data in s2. The result of the addition is stored in d1.

PLUSP0E2
BIN 16-bit data designated by s, d, s1, s2, and d1 have to range within -32768 and 32767.
The most significant bit (b15) determines, whether data in s, d, s1, or d1 are positive (bit = 0)
or negative (bit = 1).
If the least significant bit (b0) is fallen below or the most significant bit (b15) is exceeded, the
carry flag is not set.

Programming MELSEC System Q and L series 6 – 39

+, +P, -, -P Arithmetic operation Instructions

- BIN subtraction (16-bit)

● Variation 1:
BIN 16-bit data in s is subtracted from BIN 16-bit data in d. The result of the subtraction is
stored in d.

MINUP0E1

● Variation 2:
BIN 16-bit data in s2 is subtracted from BIN 16-bit data in s1. The result is stored in d1.

MINUP0E2
BIN 16-bit data designated by s, d, s1, s2, and d1 have to range within -32768 and 32767.
The most significant bit (b15) determines, whether data in s, d, s1, or d1 are positive (bit = 0)
or negative (bit = 1).
If the least significant bit (b0) is fallen below or the most significant bit (b15) is exceeded, the
carry flag is not set.

6 – 40
Arithmetic operation Instructions +, +P, -, -P

Program +P
Example 1
WIth leading edge from X5, the following program adds data in D3 to data in D0. The result is
stored from Y38 to Y3F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

PLUS_MB1, PLUS_KB1, PLUS_IB1

Program -
Example 2
The following program outputs the difference between the nominal and the actual value of timer
T3 to Y40 through Y53 in BCD.

MELSEC Instruction List Ladder Diagram IEC Instruction List

PLUS_MB2, PLUS_KB2, PLUS_IB2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 41

D+, D+P, D-, D-P Arithmetic operation Instructions

6.2.2 D+, D+P, D-, D-P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
s         —
d        — —
s1         —
s2         —
d1        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

D
P
DPLUSME1, DPLUSKE1, DPLUSIE1

GX Works2

DPLUSGE1

Variables Set Data Meaning Data Type

Addition or subtraction data, or first number of device storing addition or
s
subtraction data
Data to be added to or subtracted from, or first number of device storing such
d
data
Data to be added to or subtracted from, or first number of device storing such BIN 32-bit
s1
data
Addition or subtraction data, or first number of device storing addition or
s2
subtraction data
d1 First number of device storing addition or subtraction data

6 – 42
Arithmetic operation Instructions D+, D+P, D-, D-P

Functions BIN 32-bit addition and subtraction operations

D+ BIN addition (32-bit)
● Variation 1:
BIN 32-bit data in d is added to BIN 32-bit data in s. The result of the addition is stored in d.

DPLUS0E1

● Variation 2:
BIN 32-bit data in s1 is added to BIN 32-bit data in s2. The result of the addition is stored in d1.

DPLUS0E2
BIN 32-bit data designated by s, d, s1, s2, and d1 have to range within -2147483648 and
2147483647.
The most significant bit (b31) determines, whether data in s, d, s1, or d1 are positive (bit = 0)
or negative (bit = 1).
If the least significant bit (b0) is fallen below or the most significant bit (b31) is exceeded, the
carry flag is not set.

D- BIN subtraction (32-bit)

● Varation 1:
BIN 32-bit data in s is subtracted from BIN 32-bit data in d. The result of the subtraction is
stored in d.

DMINU0E1

Programming MELSEC System Q and L series 6 – 43

D+, D+P, D-, D-P Arithmetic operation Instructions

● Variation 2:
BIN 32-bit data in s2 is subtracted from BIN 32-bit data in s1. The result is stored in d1.

DMINU0E2
BIN 32-bit data designated by s, d, s1, s2, and d1 have to range within -2147483648 and
2147483647.
The most significant bit (b31) determines, whether data in s, d, s1, or d1 are positive (bit = 0)
or negative (bit = 1).
If the least significant bit (b0) is fallen below or the most significant bit (b31) is exceeded, the
carry flag is not set.

Program D+P
Example 1
With leading edge from X0, the following program adds data in X10 through X2B to D9 and
D10. The result is stored in Y30 through Y4B.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DPLUSMB1, DPLUSKB1, DPLUSIB1

Program D-P
Example 2
With leading edge from XB, the following program subtracts data in M0 through M23 from data
in D0 and D1. The result is stored in D10 and D11.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DPLUSMB2, DPLUSKB2, DPLUSIB2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 44
Arithmetic operation Instructions x, xP, /, /P

6.2.3 x, xP, /, /P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) Direct J\ Function
File Module Index Register Constant Other
Register Zn K, H (16#)
Bit Word Bit Word Index Register
U\G
s1         —
s2         —
d1        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

LTIME1, MULTIKE1, MULTIIE1M

U

GX Works2

MULTIGE1

Variables Set Data Meaning Data Type

Data that will be multiplied or divided, or first number of device storing data that
s1 BIN 16-bit
will be multiplied or divided
s2 Data to multiply or divide by, or first number of device storing such data BIN 16-bit
First number of device storing the operation results of multiplication or division
d1 BIN 32-bit
operation

Programming MELSEC System Q and L series 6 – 45

x, xP, /, /P Arithmetic operation Instructions

Functions BIN 16-bit multiplication and division

x BIN multiplication (16-bit)
BIN 16-bit data in s1 is multiplied with BIN 16-bit data in s2. The result is stored in d1.

XXPP0E1
If the result in d1 is a bit device, designation is made from the lower bits.
Example:
K1: lower 4 bits (b0 to b3)
K4: lower 16 bits (b0 to b15)
K8: 32 bits (b0 to b31)
BIN 16-bit data designated by s1 and s2 have to range within -32768 and 32767.
The most significant bit (b15 or b31) in d1 determines, whether data in s1, s2 or d1 are positive
(bit = 0) or negative (bit = 1).

/ BIN division (16-bit)

BIN 16-bit data in s1 is divided by BIN 16-bit data in s2. The result is stored in d1.

XXPP0E2
If a word device is used, the result of the operation is stored as 32-bits, and both, the quotient
and remainder are stored. The quotient is stored in the least significant 16-bits. The remainder
is stored in the most significant 16-bits.
If a bit device is used, 16-bits are used and only the quotient is stored.
BIN 16-bit data designated by s1 and s2 have to range within -32768 and 32767.
The most signigicant bit (b15) in d1 determines, whether data in s1, s2, d1 or (d1)+1 is positive
(bit = 0) or negative (bit = 1).

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● Division by 0 (Error code 4100)

6 – 46
Arithmetic operation Instructions x, xP, /, /P

Program xP
Example 1
With leading edge from X5, the following program multiplies 5678 and 1234. The result is
stored in D3 and D4.

MELSEC Instruction List Ladder Diagram IEC Instruction List

MULTIMB1, MULTIKB1, MULTIIB1

Program x
Example 2
The following program multiplies BIN data at X8 through XF and BIN data at X10 through X1B.
The result is output at Y30 through Y3F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

MULTIMB2, MULTIKB2, MULTIIB2

Programming MELSEC System Q and L series 6 – 47

x, xP, /, /P Arithmetic operation Instructions

Program /P
Example 3
With leading edge from X3, the following program divides data at X8 through XF by 3.14. The
result is output at Y30 through Y3F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

MULTIMB3, MULTIKB3, MULTIIB3

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 48
Arithmetic operation Instructions Dx, DxP, D/, D/P

6.2.4 Dx, DxP, D/, D/P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Devices
Internal Devices MELSECNET/H Special
(System, User) Direct J\ Function Index
File ModuleSpecia RegisterIndex ConstantConst
ant Other
Register l Function Register K, H (16#)
Bit Word Bit Word Module Zn
U\G
s1         —
s2         —
d1    — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

D
M
DMULTME1, DMULTKE1, DMULTIE1

GX Works2

DMULTGE1

Variables Data Type

Set Data Meaning
MELSEC IEC
Data that will be multiplied or divided, or first number of device
s1 BIN 32-bit ANY32
storing data that will be multiplied or divided
Data to multiply or divide by, or first number of device storing
s2 BIN 32-bit ANY32
such data
First number of device storing the operation results of Array [1..2] of
d1 BIN 64-bit
multiplication or division operation ANY32

Programming MELSEC System Q and L series 6 – 49

Dx, DxP, D/, D/P Arithmetic operation Instructions

Functions BIN 32-bit multiplication and division

Dx BIN multiplication (32-bit)
BIN 32-bit data in s1 is multiplied with BIN 32-bit data in s2. The result is stored in d1.

DXP_0E1

If the result in d1 is a bit device, designation is made from the lower bits.
Example:
K1: lower 4 bits (b0 to b3)
K4: lower 16 bits (b0 to b15)
K8: 32 bits (b0 to b31)
If the upper 32 bits of the bit device are required for the result of the multiplication operation,
first temporarily store the data in a word device, then transfer the word device data to the bit
device designated by (d1)+2 and (d1)+3.
BIN 32-bit data designated by s1 and s2 has to range within -2147483648 and 2147483647.
The most significant bit (b31 or b63) in d1 determines, whether data in s1, s2 or d1 is positive
(bit = 0) or negative (bit = 1).

D/ BIN division (32-bit)

BIN 32-bit data in s1 is divided by BIN 32-bit data in s2. The result is stored in d1.

DXP_0E2
If a word device is used, the result of the division operation is stored as array of DINT (64-bit),
and both the quotient and remainder are stored. The quotient is stored in the lower array ele-
ments (32-bit). The remainder is stored in the upper array elements (32-bit).
If a bit device is used, 32 bits are used and only the quotient is stored.
BIN 32-bit data designated by s1 and s2 has to range within -2147483648 and 2147483647.
The most significant bit (b31) in d1 determines, whether data in s1, s2, d1 or (d1)+2 is positive
(bit = 0) or negative (bit = 1).

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● Division by 0 (Error code 4100)

6 – 50
Arithmetic operation Instructions Dx, DxP, D/, D/P

Program DxP
Example 1
With leading edge from X5, the following program multiplies BIN data in D7 and D8 with BIN
data in D18 and D19. The result is stored in D1 through D4.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DMULTMB1, DMULTKB1, DMULTIB1

Program xP
Example 2
With leading edge from X3, the following program multiplies data at X8 through XF and 3.14.
The result is output at Y30 through Y3F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DMULTMB2, DMULTKB2, DMULTIB2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 51

B+, B+P, B-, B-P Arithmetic operation Instructions

6.2.5 B+, B+P, B-, B-P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —
s1         —
s2         —
d1        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BPLUSME1, BPLUSKE1, BPLUSIE1B

P
GX Works2

Variables Set Data Meaning Data Type

Addition or subtraction data, or first number of device storing addition or
s
subtraction data
Data to be added to or subtracted from, or first number of device storing such
d
data
Data to be added to or subtracted from, or first number of device storing such BCD 4-digit
s1
data
Addition or subtraction data, or first number of device storing addition or
s2
subtraction data
d1 First number of device storing addition or subtraction data

6 – 52
Arithmetic operation Instructions B+, B+P, B-, B-P

Functions BCD 4-digit addition and subtraction operations

B+ BCD addition (4-digit)
● Variation 1:
BCD 4-digit data in d is added to BCD 4-digit data in s. The result of the addition is stored in d.

BBP_0E1

● Variation 2:
BCD 4-digit data in s1 is added to BCD 4-digit data in s2. The result is stored in d1.

BBP_0E2

BCD 4-digit data designated by s, d, s1, s2, and d1 have to range within 0 and 9999. Undesig-
nated digits are read as 0 (e.g. 12 = 0012).
If the result of the addition exceeds 9999, the higher bits are ignored (overflow). The carry flag
in this case is not set.

BBP_0E3

B- BCD subtraction (4-digit)

● Variation 1:
BCD 4-digit data in s is subtracted from BCD 4-digit data in d. The result is stored in d.

1
Undesignated digits are read as 0.
BBP_0E4

Programming MELSEC System Q and L series 6 – 53

B+, B+P, B-, B-P Arithmetic operation Instructions

● Variation 2:
BCD 4-digit data in s2 is subtracted from BCD 4-digit data in s1. The result is stored in d1.

1 Undesignated digits are read as 0.

BBP_0E5
BCD 4-digit data designated by s, d, s1, s2, and d1 have to range within 0 and 9999.
If the result of the subtraction operation is negative, the minuend is reduced by the number of
steps determined by the subtrahend. The carry flag in this case is not set.

BBP_0E6
In the further course of a program, make sure that either positive or negative results are treated
adequately.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The BCD 4-digit data designated by s, d, s1, s2, or d1 exceed the relevant device range of
0 to 9999. (Error code 4100)

Program B+P (s, d)

Example 1
The following program adds BCD data 5678 to BCD data 1234. The result is stored in D993
and output at Y30 through Y3F.
The first line of the program stores the value 5678 in D993.
The following program step adds BCD data 1234 to BCD data in D993.
The MOV instruction in the last program step outputs the result in D993 at Y30 through Y3F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BPLUSMB1, BPLUSKB1, BPLUSIB1

6 – 54
Arithmetic operation Instructions B+, B+P, B-, B-P

Program B-P (s, d)

Example 2
The following program subtracts BCD data 4321 from BCD data 7654. The result is stored in
D10 and output at Y30 through Y3F.
The first line of the program stores the value 7654 in D10.
The following program step subtracts BCD data 4321 from BCD data in D10.
The MOV instruction in the last program step outputs the result in D10 at Y30 through Y3F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BPLUSMB2, BPLUSKB2, BPLUSIB2

Program B+P (s1, s2, d1)

Example 3
With leading edge from X20, the following program adds BCD data in D3 to BCD data in Z1.
The result is output at Y8 through Y17.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BPLUSMB3, BPLUSKB3, BPLUSIB3

Program B-P (s1, s2, d1)

Example 4
With leading edge from X20, the following program subtracts BCD data in D20 from BCD data
in D10. The result is stored in R10.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BPLUSMB4, BPLUSKB4, BPLUSIB4

Programming MELSEC System Q and L series 6 – 55

DB+, DB+P, DB-, DB-P Arithmetic operation Instructions

6.2.6 DB+, DB+P, DB-, DB-P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —
s1         —
s2         —
d1        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

DBPLUME1, DBPLUKE1, DBPLUIE1

GX Works2

G
E
1

Variables Set Data Meaning Data Type

s Addition or subtraction data, or first number of device storing addition or
subtraction data
d Data to be added to or subtracted from, or first number of device storing such
data
s1 Data to be added to or subtracted from, or first number of device storing such BCD 8-digit
data
s2 Addition or subtraction data, or first number of device storing addition or
subtraction data
d1 First number of device storing addition or subtraction data

6 – 56
Arithmetic operation Instructions DB+, DB+P, DB-, DB-P

Functions BCD 8-digit addition and subtraction operations

DB+ BCD addition (8-digit)
● Variation 1:
BCD 8-digit data in d is added to BCD 8-digit data in s. The result is stored in d.

1
Undesignated digits are read as 0.
DBP_0E1

● Variation 2:
BCD 8-digit data in s1 is added to BCD 8-digit data in s2. The result is stored in d1.

1 Undesignated digits are read as 0.

DBP_0E2

BCD 8-digit data designated by s, d, s1, and d1 have to range within 0 and 99999999. Undesig-
nated digits are read as 0 (e.g. 12345 = 00012345).
If the result of the addition exceeds 99999999, the higher bits are ignored (overflow). The carry
flag in this case is not set.

DBP_0E3

DB- BCD subtraction (8-digit)

● Variation 1:
BCD 8-digit data in s is subtracted from BCD 8-digit data in d. The result is stored in d.

1
Undesignated digits are read as 0
DBP_0E4

Programming MELSEC System Q and L series 6 – 57

DB+, DB+P, DB-, DB-P Arithmetic operation Instructions

● Variation 2:
BCD 8-digit data in s2 is subtracted from BCD 8-digit data in s1. The result is stored in d1.

1
Undesignated digits are read as 0
DBP_0E5

BCD 8-digit data designated by s, d, s1, and d1 have to range within 0 and 99999999. Undesig-
nated digits are read as 0 (e.g. 12345 = 00012345).
If the result of the subtraction operation is negative, the minuend is reduced by the number of
steps determined by the subtrahend. The carry flag in this case is not set.

DBP_0E6
In the further course of a program, make sure that either positive or negative results are treated
adequately.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The BCD 8-digit data designated by s, d, s1, s2, or d1 exceed the relevant device range of
0 to 99999999. (Error code 4100)

Program DB+P (s, d)

Example 1
The following program adds BCD data 12345600 to BCD data 34567000. The result is stored
in D887 and D888 and output at Y30 through Y4F.
The first line of the program stores the value 12345600 in D887 and D888.
The following program step adds BCD data 34567000 to BCD data in D887 and D888.
The DMOVP instruction in the last program step outputs the result in D887 and D888 at Y30
through Y4F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DBPLUMB1, DBPLUKB1, DBPLUIB1

6 – 58
Arithmetic operation Instructions DB+, DB+P, DB-, DB-P

Program DB-P (s, d)

Example 2
The following program subtracts BCD data 12345678 from BCD data 98765432. The result is
stored in D100 and D101 and output at Y30 through Y4F.
The first line of the program stores the value 98765432 in D100 and D101.
The following program step subtracts BCD data 12345678 from BCD data in D100 and D101.
The DMOVP instruction in the last program step outputs the result in D100 and D101 at Y30
through Y4F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DBPLUMB2, DBPLUKB2, DBPLUIB2

Program DB+P (s1, s2, d1)

Example 3
With leading edge from X20, the following program adds BCD data in D3 and D4 to BCD data
in Z and V. The result is stored in R10 and R11.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DBPLUMB3, DBPLUKB3, DBPLUIB3

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 59

Bx, BxP, B/, B/P Arithmetic operation Instructions

6.2.7 Bx, BxP, B/, B/P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s1         —
s2         —
d1        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

ULTME1, BMULTKE1, BMULTIE1B

M

GX Works2

BMULTGE1

Variables Data Type

Set Data Meaning
MELSEC IEC
Data that will be multiplied or divided, or first number of
s1 BCD 4-digit WORD
device storing data that will be multiplied or divided
Data to multiply or divide by, or first number of device
s2 BCD 4-digit WORD
storing such data
First number of device storing the operation results of
d1 BCD 8-digit 2 Arrays of WORD
multiplication or division operation

6 – 60
Arithmetic operation Instructions Bx, BxP, B/, B/P

Functions BCD 4-digit multiplication and division operations

Bx BCD multiplication (4-digit)
BCD 4-digit data in s1 is multiplied with BCD 4-digit data in s2. The result is stored in d1.

BXP_0E1
BCD 4-digit data designated by s1 and s2 have to range within 0 and 9999.

B/ BCD division (4-digit)

BCD 4-digit data in s1 is divided by BCD 4-digit data in s2. The result is stored in d1.

BXP_0E2
The result of the division is stored in two 16-bit WORD arrays. The lower array stores the quo-
tient (BCD 4-digit) and the upper array stores the remainder (BCD 4-digit).
If d is a bit device, the remainder of the division is not stored.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The s1 or s2 BCD data is outside the 0 to 9999 range. (Error code 4101)
● Division by 0 (Error code 4100)

Programming MELSEC System Q and L series 6 – 61

Bx, BxP, B/, B/P Arithmetic operation Instructions

Program BxP
Example 1
With leading edge from XB, the following program multiplies BCD data at X0 through XF with
BCD data in D8. The result is stored in D0 and D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Multiplicand
2 Multiplier
3 Result of multiplication

BMULTMB1, BMULTKB1, BMULTIB1, BXP_0B1

Program B/P
Example 2
The following program divides BCD data 5678 by BCD data 1234. The result is stored in D502
and the remainder is stored in D503. The last program step outputs the quotient in D502 at Y30
through Y3F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1 Dividend
2
Divisor
3 Quotient

4 Remainder

BMULTMB2, BMULTKB2, BMULTIB2, BXP_0B2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 62
Arithmetic operation Instructions DBx, DBxP, DB/, DB/P

6.2.8 DBx, DBxP, DB/, DB/P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s1         —
s2         —
d1    — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

D
B
MULME1, DBMULKE1, DBMULIE1

GX Works2

DBMULGE1

Variables Set DataSet Meaning Data Type

Data
Data that will be multiplied or divided, or first number of device storing data that
s1 BCD 8-digit
will be multiplied or divided
s2 Data to multiply or divide by, or first number of device storing such data BCD 8-digit
First number of device storing the operation results of multiplication or division
d1 BCD 16-digit
operation

Programming MELSEC System Q and L series 6 – 63

DBx, DBxP, DB/, DB/P Arithmetic operation Instructions

Functions BCD 8-digit multiplication and division operations

DBx BCD multiplication (8-digit)
BCD 8-digit data in s1 is multiplied with BCD 8-digit data in s2. The result is stored in d1.

DBXP_0E1

If the result in d1 is a bit device, designation is made from the lower bits.
Example:
K1: lower 4 bits (b0 to b3)
K4: lower 16 bits (b0 to b15)
K8: 32 bits (b0 to b31)
BCD 8-digit data designated by s1 and s2 have to range within 0 and 99999999. Undesignated
digits are read as 0 (e.g. 12345 = 00012345).

DB/ BCD division (8-digit)

BCD 8-digit data in s1 is divided by BCD 8-digit data in s2. The result is stored in d1.

DBXP_0E2
The result of the division is stored in two 32-bit WORD arrays. The lower array stores the quo-
tient (BCD 8-digit) and the upper array stores the remainder (BCD 8-digit).
If d is a bit device, the remainder of the division is not stored.

6 – 64
Arithmetic operation Instructions DBx, DBxP, DB/, DB/P

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The s1 or s2 BCD data is outside the 0 to 99999999 range. (Error code 4101)
● Division by 0 (Error code 4100)

Program DBxP
Example 1
The following program multiplies BCD data 68347125 with BCD data 576682. The result is
stored in D502 through D505. The following program step outputs the upper eight digits (D504,
D505) at Y30 through Y4F.

MELSEC Instruction List IEC Instruction List

Ladder Diagram

DBMULMB1, DBMULKB1, DBMULIB1, DBXP0B1

Programming MELSEC System Q and L series 6 – 65

DBx, DBxP, DB/, DB/P Arithmetic operation Instructions

Program DB/P
Example 2
With leading edge from XB, the following program divides BCD data at X20 through X3F by
BCD data in D8 and D9. The result is stored in D765 through D768.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Dividend
2 Divisor
3
Quotient
4 Remainder

DBMULMB2, DBMULKB2, DBMULIB2, DBXP0B2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 66
Arithmetic operation Instructions E+, E+P, E-, E-P

6.2.9 E+, E+P, E-, E-P

CPU High
Basic Process Redundant Universal LCPU
Performance
1)     
1
Basic model QCPU: The upper five digits of the serial No. are "04122" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants
Register Module Zn E Other
Bit Word Bit Word U\G
s —   —   1)  —
d —   —   1) — —
s1 —   —   1)  —
s2 —   —   1)  —
d1 —   —   1) — —
1
Available only in multiple Universal model QCPU and LCPU

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

LUSME1, EPLUSKE1, EPLUSIE1E

P

GX Works2

EPLUSGE1

Variables Set Data Meaning Data Type

Addition or subtraction data, or first number of device storing addition or
s
subtraction data
Data to be added to or subtracted from, or first number of device storing such
d
data
Data to be added to or subtracted from, or first number of device storing such Real number
s1
data
Addition or subtraction data, or first number of device storing addition or
s2
subtraction data
d1 First number of device storing addition or subtraction data

NOTE Within the IEC editors please use the IEC commands.

Programming MELSEC System Q and L series 6 – 67

E+, E+P, E-, E-P Arithmetic operation Instructions

Functions Floating point data addition and subtraction operations (single precision)
E+ 32-bit floating point data addition
● Variation 1:
Floating point data in d is added to floating point data in s. The result is stored in d.

1
32-bit floating point data, data type real number
EP_0E1

● Variation 2:
Floating point data in s1 is added to floating point data in s2. The result is stored in d1.

1 32-bit floating point data, data type real number

EP_0E3

Floating point data designated by s, d, s1, s2, and d1 have to range within:
0, ±2-126 ≤ (s, d, s1, s2, d1) < ±2128

E- 32-bit floating point data subtraction

● Variation 1:
Floating point data in s is subtracted from floating point data in d. The result is stored in d.

1
32-bit floating point data, data type real number
EP_0E2

6 – 68
Arithmetic operation Instructions E+, E+P, E-, E-P

● Variation 2:
Floating point data in s2 is subtracted from floating point data in s1. The result is stored in d1.

1 32-bit floating point data, data type real number

EP_0E4

Floating point data designated by s, d, s1, s2, and d1 have to range within:
0, ±2-126 ≤ (s, d, s1, s2, d1) < ±2128

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The contents of the designated device or the result of the addition are not zero and not within
the following range (Error code 4100):
±2-126 ≤ (Contents of designated device) < ±2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
● The value of the designated device is –0.
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code 4100)
NOTE: There are CPU modules that will not result in an operation error if –0 is specified.
Refer to section 3.5.1 for details.
● The result of addition and subtraction exceeds the following range (overflow occurs):
(For the Universal model QCPU, LCPU)
–2128 ≤ (Result of addition and subtraction) ≤ 2128
(Error code 4141)
● The value of the specified device is –0, unnormalized number, nonnumeric, or ± ∞.
(For the Universal model QCPU, LCPU)
(Error code 4140)

Programming MELSEC System Q and L series 6 – 69

E+, E+P, E-, E-P Arithmetic operation Instructions

Program E+P (s, d)

Example 1
With leading edge from X20, the following program adds floating point data in D3 and D4 to
floating point data in D10 and D11. The result is stored in D3 and D4.

MELSEC Instruction List Ladder Diagram IEC Instruction List

EPLUSMB1, EPLUSKB1, EPLUSIB1, EP_0B1

Program E-P (s, d)

Example 2
The following program subtracts floating point data in D10 and D11 from floating point data in
D20 and D21. The result is stored in D20 and D21.

MELSEC Instruction List Ladder Diagram IEC Instruction List

EPLUSMB2, EPLUSKB2, EPLUSIB2, EP_0B2

6 – 70
Arithmetic operation Instructions E+, E+P, E-, E-P

Program E+P (s1, s2, d)

Example 3
With leading edge from X20, the following program adds floating point data in D3 and D4 to
floating point data in D10 and D11. The result is stored in R0 and R1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

EPLUSMB3, EPLUSKB3, EPLUSIB3, EP_0B3

Program E-P (s1, s2, d)

Example 4
The following program subtracts floating point data in D20 and D21 from floating point data in D10
and D11. The result is stored in D30 and D31.

MELSEC Instruction List Ladder Diagram IEC Instruction List

EPLUSMB4, EPLUSKB4, EPLUSIB4, EP_0B4

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 71

ED+, ED+P, ED-, ED-P Arithmetic operation Instructions

6.2.10 ED+, ED+P, ED-, ED-P

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants Other
Register Module Zn E
Bit Word Bit Word U\G
s —   — — — —  —
d —   — — — — — —
s1 —   — — — —  —
s2 —   — — — —  —
d1 —   — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GX Works2
ED+/ED-

s d

E
P
P s d
L
U
S
G
E
1

ED+/ED-

s1 s2 d

P s1 s2 d

Variables Set Data Meaning Data Type

Addition or subtraction data, or first number of device storing addition or
s
subtraction data
Data to be added to or subtracted from, or first number of device storing such
d
data
Data to be added to or subtracted from, or first number of device storing such Real number
s1
data
Addition or subtraction data, or first number of device storing addition or
s2
subtraction data
d1 First number of device storing addition or subtraction data

NOTE Within the IEC editors please use the IEC commands.

6 – 72
Arithmetic operation Instructions ED+, ED+P, ED-, ED-P

Functions Floating point data addition and subtraction operations (double precision)
ED+ 64-bit floating point data addition
● Variation 1:
Floating point data in d is added to floating point data in s. The result is stored in d.

d +3 d +2 d +1 d s +3 s +2 s +1 s d +3 d +2 d +1 d

1 1 1

1
64-bit floating point data, data type real number
EP_0E1

● Variation 2:
64-bit floating point data in s1 is added to floating point data in s2. The result is stored in d1.

s1+3 s1+2 s1+1 s1 s2+3 s2+2 s2+1 s2 d1+3 d1+2 d1+1 d1

1 1 1

1
64-bit floating point data, data type real number
EP_0E3

Floating point data designated by s, d, s1, s2, and d1 have to range within:
0, ±2-1022 ≤ (s, d, s1, s2, d1) < ±21024

ED- 64-bit floating point data subtraction

● Variation 1:
Floating point data in s is subtracted from floating point data in d. The result is stored in d.

d +3 d +2 d +1 d s +3 s +2 s +1 s d +3 d +2 d +1 d
–
1 1 1

1
64-bit floating point data, data type real number

● Variation 2: EP_0E2

Floating point data in s2 is subtracted from floating point data in s1. The result is stored in d1.

s1+3 s1+2 s1+1 s1 s2+3 s2+2 s2+1 s2 d1+3 d1+2 d1+1 d1

–
1 1 1

1 64-bit floating point data, data type real number

EP_0E4
Floating point data designated by s, d, s1, s2, and d1 have to range within:
0, ±2-1022 ≤ (s, d, s1, s2, d1) < ±21024

Programming MELSEC System Q and L series 6 – 73

ED+, ED+P, ED-, ED-P Arithmetic operation Instructions

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The contents of the designated device or the result of the addition are not zero and not within
the following range:
±2-1022 ≤ (Contents of designated device) < ±21024
(Error code 4140)
● The value of the designated device is –0.
(Error code 4140)
● The result of addition and subtraction exceeds the following range (overflow occurs):
–21024 ≤ (Result of addition and subtraction) ≤ 21024
(Error code 4141)

6 – 74
Arithmetic operation Instructions ED+, ED+P, ED-, ED-P

Program ED+P (s, d)

Example 1
With leading edge from X20, the following program adds 64-bit floating point data in D3 to D6
to 64-bit floating point data in D10 to D13. The result is stored in D3 to D6.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D6 D5 D4 D3 D13 D12 D11 D10 D6 D5 D4 D3

5961.437 12003.200 17964.637

EPLUSMB1, EPLUSKB1, EPLUSIB1, EP_0B1

Program ED-P (s, d)

Example 2
The following program subtracts 64-bit floating point data in D10 to D13 from 64-bit floating
point data in D20 to D23. The result is stored in D20 to D23.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D23 D22 D21 D20 D13 D12 D11 D10 D23 D22 D21 D20
97365.203 76059.797 21305.406

EPLUSMB2, EPLUSKB2, EPLUSIB2, EP_0B2

Programming MELSEC System Q and L series 6 – 75

ED+, ED+P, ED-, ED-P Arithmetic operation Instructions

Program ED+P (s1, s2, d)

Example 3
With leading edge from X20, the following program adds 64-bit floating point data in D3 to D6
to 64-bit floating point data in D10 to D13. The result is stored in R0 to R3.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D6 D5 D4 D3 D13 D12 D11 D10 R3 R2 R1 R0

5961.437 12003.200 17964.637

EPLUSMB3, EPLUSKB3, EPLUSIB3, EP_0B3

Program ED-P (s1, s2, d)

Example 4
The following program subtracts 64-bit floating point data in D20 to D23 from 64-bit floating point
data in D10 to D13. The result is stored in D30 to D33.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D13 D12 D11 D10 D23 D22 D21 D20 D33 D32 D31 D30
97365.203 76059.797 21305.406

EPLUSMB4, EPLUSKB4, EPLUSIB4, EP_0B4

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 76
Arithmetic operation Instructions Ex, ExP, E/, E/P

6.2.11 Ex, ExP, E/, E/P

CPU High
Basic Process Redundant Universal LCPU
Performance
1)     
1
Basic model QCPU: The upper five digits of the serial No. are "04122" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special Other
(System, User) File Direct J\ Function Index Register Constants
Register Module Zn E
Bit Word Bit Word U\G
s1 —   —   1)  —
s2 —   —   1)  —
d1 —   —    1) — —
1
Available only in multiple Universal model QCPU and LCPU

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

ULTME1, EMULTKE1, EMULTIE1E

M

GX Works2

EMULTGE1

Variables Set Data Meaning Data Type

Data that will be multiplied or divided, or first number of device storing data that
s1
will be multiplied or divided
s2 Data to multiply or divide by, or first number of device storing such data Real number
First number of device storing the operation results of multiplication or division
d1
operation

Programming MELSEC System Q and L series 6 – 77

Ex, ExP, E/, E/P Arithmetic operation Instructions

Functions Floating point data multiplication and division operations (single precision)
Ex 32-bit floating point data multiplication
Floating point data in s1 is multiplied with floating point data in s2. The result is stored in d1.

1
32-bit floating point data, data type real number
EXP_0E1

Floating point data designated by s1, s2, and d1 have to range within:
0, ±2-126 ≤ (s1, s2, d1) < ±2128

E/ 64-bit floating point data division

Floating point data in s1 is divided by floating point data in s2. The result is stored in d1.

1
32-bit floating point data, data type real number
EXP_0E2
Floating point data designated by s1, s2, and d1 have to range within:
0, ±2-126 ≤ (s1, s2, d1) < ±2128

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The contents of the designated device or the result of the operation is not zero and not within
the following range:
±2-126 ≤ (Contents of designated device or operation result) < ±2128
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code 4100)
● The value of the specified device is –0.
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU) (Error code 4100)
NOTE: There are CPU modules that will not result in an operation error if –0 is specified.
Refer to page 3-17 for details.
● Division by 0 (Error code 4100)
● The result of multiplication and division exceeds the following range (overflow occurs):
(For the Universal model QCPU, LCPU)
–2128 ≤ (Result of multiplication and division) ≤ 2128
(Error code 4141)
● The value of the specified device is –0, unnormalized number, nonnumeric, or ± ∞.
(For the Universal model QCPU, LCPU)
(Error code 4140)

6 – 78
Arithmetic operation Instructions Ex, ExP, E/, E/P

Program ExP
Example 1
With leading edge from X20, the following program multiplies floating point data in D3 and D4
with floating point data in D10 and D11. The result is stored in R0 and R1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

EMULTMB1, EMULTKB1, EMULTIB1, EXP_0B1

Program E/P
Example 2
The following program divides floating point data in D10 an D11 by floating point data in D20
and D21. The result is stored in D30 and D31.

MELSEC Instruction List Ladder Diagram IEC Instruction List

EMULTMB2, EMULTKB2, EMULTIB2, EXP_0B2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 79

EDx, EDxP, ED/, ED/P Arithmetic operation Instructions

6.2.12 EDx, EDxP, ED/, ED/P

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Usable Devices

Internal Devices MELSECNET/H Special
Other
(System, User) File Direct J\ Function Index Register Constants
Register Module Zn E
Bit Word Bit Word U\G U
s1 —   — — — —  —
s2 —   — — — —  —
d1 —   — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

ULTME1, EMULTKE1, EMULTIE1E

M

GX Works2
ED*, ED/

s1 s2 d

E
M
U P s1 s2 d
L
T
G
E
1

Variables Set Data Meaning Data Type

Data that will be multiplied or divided, or first number of device storing data that
s1
will be multiplied or divided
s2 Data to multiply or divide by, or first number of device storing such data Real number
First number of device storing the operation results of multiplication or division
d1
operation

NOTE Within the IEC editors please use the IEC commands.

6 – 80
Arithmetic operation Instructions EDx, EDxP, ED/, ED/P

Functions Floating point data multiplication and division operations (double precision)
EDx 64-bit floating point data multiplication
Floating point data in s1 is multiplied with floating point data in s2. The result is stored in d1.

s1+3 s1+2 s1+1 s1 s2+3 s2+2 s2+1 s2 d1+3 d1+2 d1+1 d1

x
1 1 1

1
64-bit floating point data, data type real number
EXP_0E1
Floating point data designated by s1, s2, and d1 have to range within:
0, ±2-1022 ≤ (s1, s2, d1) < ±21024

ED/ 64-bit floating point data division

Floating point data in s1 is divided by floating point data in s2. The result is stored in d1.

s1+3 s1+2 s1+1 s1 s2+3 s2+2 s2+1 s2 d1+3 d1+2 d1+1 d1

/
1 1 1

1
64-bit floating point data, data type real number
EXP_0E2
Floating point data designated by s1, s2, and d1 have to range within:
0, ±2-1022 ≤ (s1, s2, d1) < ±21024

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The contents of the designated device or the result of the operation is not zero and not within
the following range:
±2-1022 ≤ (Contents of designated device or result of operation) < ±21024
(For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU)
(Error code 4140)
● The value of the designated device is –0.
(Error code 4140)
● Division by 0
(Error code 4100)
● The result of multiplication or division exceeds the following range. (The overflow occurs.)
(For the Universal model QCPU, LCPU)
–21024 ≤ (Result of multiplication or division) ≤ 21024
(Error code 4141)

Programming MELSEC System Q and L series 6 – 81

EDx, EDxP, ED/, ED/P Arithmetic operation Instructions

Program EDxP
Example 1
With leading edge from X20, the following program multiplies 64-bit floating point data in D3 to
D6 with 64-bit floating point data in D10 to D13. The result is stored in R0 to R3.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D6 D5 D4 D3 D13 D12 D11 D10 R3 R2 R1 R0

36.7896 11.9278 438.8190

EMULTMB1, EMULTKB1, EMULTIB1, EXP_0B1

Program ED/P
Example 2
The following program divides 64-bit floating point data in D10 to D13 by 64-bit floating point
data in D20 to D23. The result is stored in D30 to D33.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D13 D12 D11 D10 D23 D22 D21 D20 D33 D32 D31 D30
52171.39 9.73521 5359.041

EMULTMB2, EMULTKB2, EMULTIB2, EXP_0B2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 82
Arithmetic operation Instructions BK+, BK+P, BK-, BK-P

6.2.13 BK+, BK+P, BK-, BK-P

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s1 —   — — — — — —
s2 —   — — — —  —
d —   — — — — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

PLUME1, BKPLUKE1, BKPLUIE1B

K

GX Works2

BKPLUGE1

Variables Set Data Meaning Data Type

Data to be added to or subtracted from, or first number of device storing such
s1
data
Addition or subtraction data, or first number of device storing addition or
s2 BIN 16-bit
subtraction data
d First number of device storing results of operation
n Number of data blocks

Programming MELSEC System Q and L series 6 – 83

BK+, BK+P, BK-, BK-P Arithmetic operation Instructions

Functions BIN 16-bit data addition and subtraction operations

BK+ BIN 16-bit data block addition
An addition operation instruction for BIN 16-bit data block data consists of the instruction itself,
two designated devices s1 and s2 to be added, a device d to store the result, and the number
of data blocks to be added.
It adds the nth 16-bit block in s1 to the nth 16-bit block in s2, beginning with the first number of
device. The result of each block addition is stored in d.

BKP_0E1
The addition operation is conducted in 16-bit units.
The constant designated by s2 must be BIN 16-bit data ranging from -32768 to 32767.

BKP_0E2
The most significant bit of each block determines, whether data in s1, s2 or d are positive
(bit = 0) or negative (bit = 1).
If the least significant bit of a block is fallen below or the most significant bit of a block is
exceeded, the carry flag is not set.

6 – 84
Arithmetic operation Instructions BK+, BK+P, BK-, BK-P

BK- BIN 16-bit data block subtraction

A subtraction operation instruction for BIN 16-bit data block data consists of the instruction
itself, two designated devices s1 and s2 to be added, a device d to store the result, and the
number of data blocks to be subtracted.
It subtracts the nth 16-bit block in s2 from the nth 16-bit block in s1, beginning with the first
number of device. The result of each block addition is stored in d.

BKP_0E3
The subtraction operation is conducted in 16-bit units.
The constant designated by s2 must be BIN 16-bit data ranging from -32768 to 32767.

BKP_0E4
The most significant bit of each block determines, whether data in s1, s2 or d are positive
(bit = 0) or negative (bit = 1).
If the least significant bit of a block is fallen below or the most significant bit of a block is
exceeded, the carry flag is not set.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The number of data blocks in s1, s2 or d exceeds the relevant device range.
(Error code 4101)
● The device ranges of s1 and s2 overlap.
(Except when the same device is assigned to s1 and d)
(Error code: 4101)
● The device ranges of s2 and d overlap.
(Except when the same device is assigned to s2 and d)
(Error code: 4101)

Programming MELSEC System Q and L series 6 – 85

BK+, BK+P, BK-, BK-P Arithmetic operation Instructions

Program BK+P
Example 1
With leading edge from X20, the following program adds BIN block data beginning from D100
to BIN block data beginning from R0. The result of the operation is stored beginning from D200.
The number of blocks (4) added is stored in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BKPLUMB1, BKPLUKB1, BKPLUIB1, BKP_0B1

Program BK-P
Example 2
With leading edge from X1C, the following program subtracts a constant 8765 from BIN block
data beginning from D100. The result of the operation is stored beginning from R0. The number
of data blocks (3) subtracted is designated by a constant K3.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BKPLUMB2, BKPLUKB2, BKPLUIB2, BKP_0B2

6 – 86
Arithmetic operation Instructions DBK+, DBK+P, DBK-, DBK-P

6.2.14 DBK+, DBK+P, DBK-, DBK-P

CPU High
Basic Process Redundant Universal LCPU
Performance
1) 
1
QnU(D)(H)CPU: The serial number (first five digits) is "10102" or higher.
QnUDE(H)CPU: The serial number (first five digits) is "10102" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s1 —   — — — — — —
s2 —   — — — —  —
d —   — — — — — —
n —        —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

PLUME1, BKPLUKE1, BKPLUIE1B

K

GX Works2
BK+, BK-

s1 s2 d n

B
K
P P s2 s2 d n
L
U
G
E
1

Variables Set Data Meaning Data Type

Data to be added to or subtracted from, or first number of device storing such
s1
data
Addition or subtraction data, or first number of device storing addition or
s2 BIN 16-bit
subtraction data
d First number of device storing results of operation
n Number of data blocks

NOTE Within the IEC editors please use the IEC commands.

Programming MELSEC System Q and L series 6 – 87

DBK+, DBK+P, DBK-, DBK-P Arithmetic operation Instructions

Functions BIN 32-bit data block addition and subtraction operations

DBK+ BIN 32-bit data block addition
An addition operation instruction for BIN 32-bit data block data consists of the instruction itself,
two designated devices s1 and s2 to be added, a device d to store the result, and the number
of data blocks to be added.
It adds the nth 32-bit block in s1 to the nth 32-bit block in s2, beginning with the first number of
device. The result of each block addition is stored in d.

b31 b0 b31 b0 b31 b0

(s1)+1, s1 -30000 (BIN) (s2)+1, s2 50000 (BIN) d +1, d 20000 (BIN)
(s1)+3, (s1)+2 40000 (BIN) (s2)+3, (s2)+2 20000 (BIN) d +3, d +2 60000 (BIN)
(s1)+5, (s1)+4 -50000 (BIN) n + (s2)+5, (s2)+4 -10000 (BIN) n d +5, d +4 -60000 (BIN) n

(s1)+n 1, (s1)+n 2 60000 (BIN) (s2)+n 1, (s2)+n 2 -20000 (BIN) d +n 1, d +n 2 40000 (BIN)

BKP_0E1
The addition operation is conducted in 32-bit units.
The constant designated by s1 must be BIN 32-bit data ranging from -2147483648 to
2147483647.

b31 b0 b31 b0
(s1) +1, s1 -30000 (BIN) d +1, d 20000 (BIN)
(s1) +3, (s1) +2 40000 (BIN) b31 b0 d +3, d +2 90000 (BIN)
(s1) +5, (s1) +4 -50000 (BIN) n + (s2)+1, s2 50000 (BIN) d +5, d +4 0 (BIN) n

(s1) +n 1, (s1)+n 2 60000 (BIN) d +n 1, d +n 2 110000 (BIN)

BKP_0E2
If the value specified by n is 0, the instruction will be not processed.
The most significant bit of each block determines, whether data in s1, s2 or d are positive
(bit = 0) or negative (bit = 1).
If the least significant bit of a block is fallen below or the most significant bit of a block is
exceeded, the carry flag is not set.

6 – 88
Arithmetic operation Instructions DBK+, DBK+P, DBK-, DBK-P

DBK- BIN 32-bit data block subtraction

A subtraction operation instruction for BIN 32-bit data block data consists of the instruction
itself, two designated devices s1 and s2 to be subtracted, a device d to store the result, and
the number of data blocks to be subtracted.
It subtracts the nth 32-bit block in s2 from the nth 32-bit block in s1, beginning with the first
number of device. The result of each block addition is stored in d.

b31 b0 b31 b0 b31 b0

(s1)+1, S1 -55555 (BIN) (s2)+1, S2 44445 (BIN) d +1, d -1000000 (BIN)
(s1)+3, (s1)+2 33333 (BIN) (s2)+3, (s2)+2 3333 (BIN) d +3, d +2 30000 (BIN)
(s1)+5, (s1)+4 44444 (BIN) n (s2)+5, (s2)+4 -10000 (BIN) n d +5, d +4 54444 (BIN) n

(s1)+n 1, (s1)+n 2 13579 (BIN) (s2)+n 1, (s2)+n 2 12345 (BIN) d +n 1, d +n 2 1234 (BIN)

BKP_0E3
The subtraction operation is conducted in 32-bit units.
The constant designated by s2 must be BIN 32-bit data ranging from –2147483648 to
2147483647.

b31 b0 b31 b0
(s1) +1, s1 -99999 (BIN) d +1, d -109998 (BIN)
(s1) +3, (s1) +2 99999 (BIN) b31 b0 d +3, d +2 90000 (BIN)
(s1) +5, (s1) +4 -59999 (BIN) n (s2)+1, s2 9999 (BIN) d +5, d +4 69998 (BIN) n

(s1) +n 1, (s1)+n 2 79999 (BIN) d +n 1, d +n 2 70000 (BIN)

BKP_0E4
If the value specified by n is 0, the instruction will be not processed.
The most significant bit of each block determines, whether data in s1, s2 or d are positive
(bit = 0) or negative (bit = 1).
If the least significant bit of a block is fallen below or the most significant bit of a block is
exceeded, the carry flag is not set.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● A negative value is specified for n. (Error code 4100)
● The range of the n-point devices starting from the device specified by s1, s2, or d exceeds
the specified device range.
(Error code: 4101)
● The range of the n-point devices starting from the device specified by s1 overlaps with the
range of the n-point devices starting from the device specified by d.
(Except when s1 and d specify the same device.)
(Error code: 4101)
● The range of the n-point devices starting from the device specified by s2 overlaps with the
range of the n-point devices starting from the device specified by d.
(Except when s2 and d specify the same device.)
(Error code: 4101)

Programming MELSEC System Q and L series 6 – 89

DBK+, DBK+P, DBK-, DBK-P Arithmetic operation Instructions

Program DBK+P
Example 1
The following program adds the value data stored at R0 to R5 to the constant, and then stores
the operation result into D30 to D35, when M0 is turned on.

MELSEC Instruction List Ladder Diagram IEC Instruction List

b31 b0 b31 b0
R1,R0 600000 D31,D30 723456
R3,R2 -800000 + 123456 D33,D32 -676544
R5,R4 -123456 D35,D34 0

BKPLUMB1, BKPLUKB1, BKPLUIB1, BKP_0B1

Program DBK-P
Example 2
The following program subtracts the value data stored at D50 to D59 from the value data stored
at D100 to D109, and then stores the operation result into R100 to R109, when M0 is turned on.

MELSEC Instruction List Ladder Diagram IEC Instruction List

b31 b0 b31 b0 b31 b0

D101,D100 12345 D51,D50 11111 R101,R100 1234
D103,D102 54321 D53,D52 -11111 R103,R102 65432
D105,D104 -12345 D55,D54 22222 R105,R104 -34567
D107,D106 -54321 D57,D56 -22222 R107,R106 -32099
D109,D108 99999 D58,D58 33333 R109,R108 66666

BKPLUMB2, BKPLUKB2, BKPLUIB2, BKP_0B2

6 – 90
Arithmetic operation Instructions $+, $+P

6.2.15 $+, $+P

CPU High
Basic Process Redundant Universal LCPU
Performance
    

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants Other
Register Module Zn $
Bit Word Bit Word U\G
s —   — — — —  —
d —   — — — — — —
s1 —   — — — —  —
s2 —   — — — —  —
d1 —   — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

LUSME1, SPLUSKE1, SPLUSIE1S

P

GX Works2

SPLUSGE1

Variables Set Data Meaning Data Type

s Data to be linked, or first number of device storing such data
d First number of device storing results of operation
s1 Data to be linked, or first number of device storing such data Character string
s2 Data to be linked, or first number of device storing such data
d1 First number of device storing results of operation

Programming MELSEC System Q and L series 6 – 91

$+, $+P Arithmetic operation Instructions

Functions Character string linking operations

$+ Character string linking
● Variation 1:
Character string data in s is appended to character data in d. The linked character string is
stored in d.
The linked character string begins with the character at the least significant byte in d and ends
with the code "00H" in s.

SSP_0E1
The code "00H" indicates the end of a character string. When two strings are linked, in the first
string this code is ignored and the "00H" of the second string marks the end of the linked string.

● Variation 2:
Character string data in s2 is appended to character string data in s1. The linked character
string is stored in d1.
The linked character string begins with the character at the least significant byte in s1 and ends
with the code "00H" in s2.

SSP_0E2
The code "00H" indicates the end of a character string. When two strings are linked, in the first
string this code is ignored and the "00H" of the second string marks the end of the linked string.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The linked character string cannot be stored.
(Error code 4100)
● The storage device numbers designated by s, d, s1, s2, and d1 overlap.
(Error code 4101)
● The character string of s, d, s1, s2, and d1 exceeds 16383 characters.
(Error code 4101)

6 – 92
Arithmetic operation Instructions $+, $+P

Program $+P
Example 1
With leading edge from X0, the following program links character string data in D10 through
D12 to the character string "ABCD". The linked character string is stored in D10 through D14.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
"00H" indicates the end of character strings and is stored automatically.
SPLUSMB1, SPLUSKB1, SPLUSIB1, SSP_0B1

Program $+
Example 2
While X0 is set (1), the following program links character string data in D10 through D12 to a
character string "ABCD". The linked character string is stored from D101 through D104.

MELSEC Instruction List IEC Instruction List

Ladder Diagram

1
"00H" indicates the end of character strings and is stored automatically.
SPLUSMB2, SPLUSKB2, SPLUSIB2, SSP_0B2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 93

INC, INCP, DEC, DECP Arithmetic operation Instructions

6.2.16 INC, INCP, DEC, DECP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constants Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

I
N
C__ME1, INC__KE1, INC__IE1

GX Works2

INC_GE1

Variables Set Data Meaning Data Type

d First number of device conducted by INC (add 1) or DEC (subtract 1) operation. BIN 16-bit

6 – 94
Arithmetic operation Instructions INC, INCP, DEC, DECP

Functions BIN 16-bit increment and decrement operations

INC BIN 16-bit increment
Adds 1 to device designated by d (16-bit).

DEC_0E1
If the content of d is 32767, the result after incrementing is -32768.

DEC BIN 16-bit decrement

Subtracts 1 from device designated by d (16-bit).

DEC_0E2
If the content of d is 0, the result after decrementing is -1.
If the content of d is -32768, the result after decrementing is 32767.

Program INCP
Example 1
With leading edge from X8, the following program outputs the actual value of the counter (nom-
inal value = 9999) C0 through C20 (C0 plus Z1) at Y30 through Y3F as BCD data. Z1 is reset
(RST Z1), if Z1 is equal to 21 (LD = K21 Z1) or if the reset input X7 is set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

INC__MB1, INC__KB1, INC__IB1

Programming MELSEC System Q and L series 6 – 95

INC, INCP, DEC, DECP Arithmetic operation Instructions

Program DECP
Example 2
The following example shows a down counter program. With leading edge from X7, this pro-
gram stores a value 100 in D8. While M38 is not set, data in D8 is decremented by 1 with lead-
ing edge from X8. At D8 = 0, M38 is set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

INC__MB2, INC__KB2, INC__IB2

6 – 96
Arithmetic operation Instructions DINC, DINCP, DDEC, DDECP

6.2.17 DINC, DINCP, DDEC, DDECP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
Other
(System, User) File Direct J\ Function Index Register Constants
Register Module Zn K, H (16#)
Bit Word Bit Word U\G U
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

DINC_ME1, DINC_KE1, DINC_IE1

GX Works2

DINC_GE1

Variables Set Data Meaning Data Type

First number of device conducted by DINC (add 1) or DDEC (subtract 1)
d BIN 32-bit
operation.

Programming MELSEC System Q and L series 6 – 97

DINC, DINCP, DDEC, DDECP Arithmetic operation Instructions

Functions BIN 32-bit increment and decrement operations

DINC BIN 32-bit increment
Adds 1 to device designated by d (32-bit).

DDEC0E1
If the content of d is 2147483647, the result after incrementing is -2147483648.

DDEC BIN 32-bit decrement

Subtracts 1 from device designated by d (16-bit).

DDEC0E2
If the content of d is 0, the result after decrementing is -1.
If the content of d is -2147483647, the result after decrementing is 2147483647.

Program DINCP
Example 1
With leading edge from X0, the following program adds 1 to data in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DINC_MB1, DINC_KB1, DINC_IB1

Program DINCP
Example 2
With leading edge from X0, the following program adds 1 to data at X10 through X27. The
result is stored in D3 and D4.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DINC_MB2, DINC_KB2, DINC_IB2

6 – 98
Arithmetic operation Instructions DINC, DINCP, DDEC, DDECP

Program DDECP
Example 3
With leading edge from X0, the following program subtracts 1 from data in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DINC_MB3, DINC_KB3, DINC_IB3

Program DDECP
Example 4
With leading edge from X0, the following program subtracts 1 from data in X10 through X27.
The result is stored in D3 and D4.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DINC_MB4, DINC_KB4, DINC_IB4

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 99

DINC, DINCP, DDEC, DDECP Arithmetic operation Instructions

6 – 100
Data conversion instructions

6.3 Data conversion instructions

The instructions described in the following section convert different data types.
NOTE Within the IEC editors the IEC commands should be used.

MELSEC Instruction MELSEC Instruction

Conversion in in
MELSEC Editor IEC Editor
BCD BCD_M
BIN (16-/32-bit) BCDP BCDP_M
⇓
BCD (4-/8-digit) DBCD DBCD_M
DBCDP DBCDP_M
BIN BIN_M
BCD (4-/8-digit) BINP BINP_M
⇓
BIN (16-/32-bit) DBIN DBIN_M
DBINP DBINP_M
FLT FLT_M
BIN (16-/32-bit)
FLTP FLTP_M
⇓
Floating point data DFLT DFLT_M
(Single precision)
DFLTP DFLTP_M
FLTD
BIN (16-/32-bit)
FLTPD
⇓
Floating point data DFLTD
(Double precision)
DFLTPD
INT_MD
INT
INT_E_MD
INT_P_MD
Floating point data INTP
(Single precision INT_P_E_MD
⇓ DINT_MD
BIN (16-/32-bit) DINT
DINT_E_MD
DINT_P_MD
DINTP
DINT_P_E_MD
INTD
Floating point data
(Double precision) INTPD
⇓ DINTD
BIN (16-/32-bit)
DINTPD
BIN 16-bit DBL DBL_M
⇓
BIN 32-bit DBLP DBLP_M

BIN 32-bit WORD WORD_M

⇓
BIN 16-bit WORDP WORDP_M

GRY GRY_M
BIN (16-/32-bit) GRYP GRYP_M
⇓
GRAY CODE Data DGRY DGRY_M
DGRYP DGRYP_M
GBIN GBIN_M
GRAY CODE Data GBINP GBINP_M
⇓
BIN (16-/32-bit) DGBIN DGBIN_M
DGBINP DGBINP_M

Programming MELSEC System Q and L series 6 – 101

 Data conversion instructions

MELSEC Instruction MELSEC Instruction

Conversion in in
MELSEC Editor IEC Editor
NEG NEG_M
Sign Reversal NEGP NEGP_M
BIN (16-/32-bit)
(Complement of 2) DNEG DNEG_M
DNEGP DNEGP_M
ENEG ENEG_M

Sign Reversal ENEGP ENEGP_M

Floating point data EDNEG
EDNEGP
BIN Block (16-bit) BKBCD BKBCD_M
⇓
BCD Block (4-digit) BKBCDP BKBCDP_M

BCD Block (4-digit) BKBIN BKBIN_M

⇓
BIN Block (16-bit) BKBINP BKBINP_M

Floating point data ECON

(Single precision)
⇓
Floating point data ECONP
(Double precision)
Floating point data EDCON
(Double precision)
⇓
Floating point data EDCONP
(Single precision)

6 – 102
Data conversion instructions BCD, BCDP, DBCD, DBCDP

6.3.1 BCD, BCDP, DBCD, DBCDP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BCD__ME1, BCD__KE1, BCD__IE1

GX Works2

BCD__GE1

Variables Set Data Meaning Data Type

s BIN data, or first number of device storing BIN data. BIN 16-/32-bit
d First number of device storing BCD data. BCD 4-/8-digit

Programming MELSEC System Q and L series 6 – 103

BCD, BCDP, DBCD, DBCDP Data conversion instructions

Functions Conversion from BIN data into BCD data

BCD Conversion from BIN 16-bit data into BCD 4-digit data
BIN data in s (0 to 9999) is converted into BCD data. The result is stored in d.
The most significant two bits of BIN data in s must be reset (0) when converted into BCD 4-digit
data.

BCD_0E3

DBCD Conversion from BIN 32-bit data into BCD 8-digit data
BIN data in s (0 to 99999999) is converted into BCD data. The result is stored in d. The most
significant five bits of BIN data in s must be reset (0) when converted to BCD 8-digit data.

DBCD0E1

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● BIN 16-bit data in s exceeds the relevant device range of 0 to 9999.
(Error code 4100)
● BIN 32-bit data in s+1 or s exceed the relevant device range of 0 to 99999999.
(Error code 4100)

6 – 104
Data conversion instructions BCD, BCDP, DBCD, DBCDP

Program BCDP
Example
The following program outputs the current value in C4 (5678) to Y20 through Y2F. The output
module displays the value on the display unit.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Output power supply
2 Output module
BCD__MB1, BCD__KB1, BCD__IB1, BCD_0B1

Programming MELSEC System Q and L series 6 – 105

BIN, BINP, DBIN, DBINP Data conversion instructions

6.3.2 BIN, BINP, DBIN, DBINP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G U
s         —
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BIN__ME1, BIN__KE1, BIN__IE1

GX Works2

BIN__GE1

Variables Set Data Meaning Data Type

s BCD data, or first number of device storing BCD data. BCD 4-/8-digit
d First number of device storing BIN data. BIN 16-/32-bit

6 – 106
Data conversion instructions BIN, BINP, DBIN, DBINP

Functions Conversion from BCD data into BIN data

BIN Conversion from BCD 4-digit data into BIN 16-bit data
BCD data in s (0 to 9999) is converted into BIN data. The result is stored in d.
The most significant two bits of BIN data in d must be reset (0) when converted from BCD
4-digit it data.

BIN_0E1

DBIN Conversion from BCD 8-digit data into BIN 32-bit data
BCD data in s (0 to 99999999) is converted to BIN data. The result is stored in d.
The most significant five bits of BIN data in d must be reset (0) when converting from BCD
8-digit data.

BIN_0E2

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The individual digits in s do not range within 0 to 9. (Error code 4100)
This error can be suppressed by turning SM722 ON. However, the instruction is not executed
regardless of the status of SM722 if the specified value in s is out of range.
For the BINP/DBINP instruction, the next operation will not be performed until the command
(execution condition) is turned from OFF to ON regardless of the presence/absence of an
error.
BIN_AB1, BIN_AB2

Programming MELSEC System Q and L series 6 – 107

BIN, BINP, DBIN, DBINP Data conversion instructions

Program BINP
Example 1
The following program converts BCD data in X10 through X1B into BIN data. The result is
stored in D8.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Input power supply
2
Input module
3 Available inputs

BIN__MB1, BIN__KB1, BIN__IB1, BIN_0B1

6 – 108
Data conversion instructions BIN, BINP, DBIN, DBINP

Program DBINP
Example 2
With leading edge from X8, the following program converts BCD data at X10 through X37 into
BIN data. The result is stored in D0 through D1.

MELSEC Instruction List Ladder Diagram

IEC Instruction List

1 Input power supply

2 Input module
BIN__MB2, BIN__KB2, BIN__IB2, BIN_0B2

NOTE BCD data at X10 through X37 exceeding the relevant device range of 2147483647 cannot be
processed by 32-bit devices! In this case the values in D0 and D1 become negative. For further
datails see section 3.4 "Programming of variables" in the Programming Manual.
This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 109

FLT, FLTP, DFLT, DFLTP Data conversion instructions

6.3.3 FLT, FLTP, DFLT, DFLTP

CPU High
Basic Process Redundant Universal LCPU
Performance
1)     

1 Basic model QCPU: The upper five digits of the serial No. are "04122" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
1)
d —   —    — —
1
Available only in multiple Universal model QCPU and LCPU

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

FLT__ME1, FLT__KE1, FLT__IE1

GX Works2

FLT__GE1

Variables Set Data Meaning Data Type

s BIN data, or first number of device storing BIN data. BIN 16-/32-bit
d First number of device storing floating point data. Real number

6 – 110
Data conversion instructions FLT, FLTP, DFLT, DFLTP

Functions Conversion from BIN 16-bit/32-bit data into floating point data (Single precision)
FLT Conversion from BIN 16-bit data into floating point data
BIN 16-bit data in s is converted into 32-bit floating point data. The result is stored in d.

1 32-bit floating point data, data type real number

FLT_0E1

BIN 16-bit data designated by s has to range within -32768 and 32767.

DFLT Conversion from BIN 32-bit data into floating point data
BIN 32-bit data in s is converted into 32-bit floating point data. The result is stored in d.

1
32-bit floating point data, data type real number
FLT_0E2

BIN 32-bit data designated by s and s+1 have to range within -2147483648 and 2147483647.
Due to the fact that floating point data (data type real number) is processed by simple 32-bit
procedures, the number of significant bits is 24 for a binary display, or approx. 7 digits for a dec-
imal display.
The result of the conversion is rounded off at the 25th bit. All higher bits are eliminated. For this
reason, if the resulting integer exceeds a range of -16777216 to 16777215 (BIN 24-bit value),
errors may occur in the conversion.

1 Rounded off
2 Eliminated
FLT_0E3

Programming MELSEC System Q and L series 6 – 111

FLT, FLTP, DFLT, DFLTP Data conversion instructions

Program FLTP
Example 1
The following program converts BIN 16-bit data in D20 into 32-bit floating point data. The result
is stored in D0 and D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
BIN 16-bit data
2
32-bit floating point data, data type real number
FLT__MB1, FLT__KB1, FLT__IB1, FLT_0B1

Program DFLTP
Example 2
The following program converts BIN 32-bit data in D20 and D21 into 32-bit floating point data.
The result is stored in D0 and D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1 BIN 32-bit data

2
32-bit floating point data, data type real number
3 Conversion error, because there are 7 significant digits

FLT__MB2, FLT__KB2, FLT__IB2, FLT_0B2

NOTE These programs will not run without variable definition in the header of the program organization
unit (POU). They would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 112
Data conversion instructions FLTD, FLTPD, DFLTD, DFLTPD

6.3.4 FLTD, FLTPD, DFLTD, DFLTPD

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s —   — — —   —
d —   — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

FLT__ME1, FLT__KE1, FLT__IE1

GX Works2
FLTD/DFLTD

s d

F
L
T
_
G
E
1
P s d

Variables Set Data Meaning Data Type

s BIN data, or first number of device storing BIN data. BIN 16-/32-bit
d First number of device storing floating point data. Real number

Programming MELSEC System Q and L series 6 – 113

FLTD, FLTPD, DFLTD, DFLTPD Data conversion instructions

Functions Conversion from BIN 16-bit/32-bit data into floating point data (Double precision)
FLTD Conversion from BIN 16-bit data into floating point data
BIN 16-bit data in s is converted into 64-bit floating point data. The result is stored in d.

s d+3 d+2 d+1 d

BIN 16-bit

1
64-bit floating point data, data type real number
BIN 16-bit data designated by s has to range within -32768 and 32767.

DFLTD Conversion from BIN 32-bit data into floating point data
BIN 32-bit data in s is converted into 64-bit floating point data. The result is stored in d.

s+1 s d+3 d+2 d+1 d

BIN 32-bit 1

1
64-bit floating point data, data type real number

FLT_0E2
FLT_0E3
Program FLTDP
Example 1
The following program converts BIN 16-bit data in D20 into 64-bit floating point data. The result
is stored in D0 to D3.

MELSEC Instruction List Ladder Diagram

D20 D3 D2 D1 D0
15923 15923

1
BIN 16-bit data
2
64-bit floating point data, data type real number
FLT__MB1, FLT__KB1, FLT__IB1, FLT_0B1

6 – 114
Data conversion instructions FLTD, FLTPD, DFLTD, DFLTPD

Program DFLTDP
Example 2
The following program converts BIN 32-bit data in D20 and D21 into 64-bit floating point data.
The result is stored in D0 to D3.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D21 D20 D3 D2 D1 D0
16543521 16543521

1
BIN 32-bit data
2 64-bit floating point data, data type real number
FLT__MB2, FLT__KB2, FLT__IB2, FLT_0B2

NOTE These programs will not run without variable definition in the header of the program organiza-
tion unit (POU). They would cause compiler or checker error messages. For details see section
3.5.2 "Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 115

INT, INTP, DINT, DINTP Data conversion instructions

6.3.5 INT, INTP, DINT, DINTP

CPU High
Basic Process Redundant Universal LCPU
Performance
1)     

1 Basic model QCPU: The upper five digits of the serial No. are "04122" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant Other
Register Module Zn E
Bit Word Bit Word U\G
s —   —   1)  —
d        — —
1
Available only in multiple Universal model QCPU and LCPU

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

INT__ME1, INT__KE1, INT__IE1

GX Works2

INT__GE1

Variables Set Data Meaning Data Type

s Floating point data, or first number of device storing floating point data. Real number
d First number of device storing BIN data. BIN 16-/32-bit

6 – 116
Data conversion instructions INT, INTP, DINT, DINTP

Functions Conversion from floating point data into BIN 16-bit/32-bit data (Single precision)
INT Conversion from 32-bit floating point data into BIN 16-bit data
32-bit floating point data in s is converted into BIN 16-bit data. The result is stored in d.

1
32-bit floating point data, data type real number
INT_0E1
Floating point data in s and s+1 have to range within -32768 and 32767.
The converted integer value is stored as BIN 16-bit data.
The converted integer value is rounded off at the first digit after the decimal point.

DINT Conversion from 32-bit floating point data into BIN 32-bit data
32-bit floating point data in s is converted to BIN 32-bit data. The result is stored in d.

1 32-bit floating point data, data type real number

INT_0E2
Floating point data in s and s+1 have to range within -2147483648 and 2147483647.
The converted integer value is stored as BIN 32-bit data.
The converted integer value is rounded off at the first digit after the decimal point.

Programming MELSEC System Q and L series 6 – 117

INT, INTP, DINT, DINTP Data conversion instructions

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The contents of the designated device or the result of the addition are not zero and not within
the following range:
2-126 ≤ (Contents of designated device) < 2128
(For the Universal model QCPU, LCPU) (Error code 4140)
● The value of the specified device is –0, unnormalized number, nonnumeric, and ∞.
(For the Universal model QCPU, LCPU) (Error code 4140)
● Performing an INT instruction, floating point data designated by s exceeds the relevant
device range of -32768 to 32767.
● Performing a DINT instruction, floating point data designated by s exceeds the relevant
device range of -2147483648 to 2147483647.

Program INTP
Example 1
The following program converts 32-bit floating point data in D20 and D21 into BIN 16-bit data.
The result is stored in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
32-bit floating point data, data type real number
2 BIN 16-bit data
3
No result. Value exceeds relevant device range of INT instruction. Error code is returned.

6 – 118
Data conversion instructions INT, INTP, DINT, DINTP

INT__MB1, INT__KB1, INT__IB1, INT_0B1

Program DINTP
Example 2
The following program converts 32-bit floating point data in D20 and D21 into BIN 32-bit data.
The result is stored in D0 and D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
32-bit floating point data, data type real number
2
BIN 32-bit data
3 No result. Value exceeds relevant device range of DINT instruction. Error code is returned.

INT__MB2, INT__KB2, INT__IB2, INT_0B2

NOTE These programs will not run without variable definition in the header of the program organization
unit (POU). They would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 119

INTD, INTPD, DINTD, DINTPD Data conversion instructions

6.3.6 INTD, INTPD, DINTD, DINTPD

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn E
Bit Word Bit Word U\G
s —   — — — —  —
d —   — — —  — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

INT__ME1, INT__KE1, INT__IE1

GX Works2
INTD/DINTD

s d

IN
T
_
G
E
1
P s d

Variables Set Data Meaning Data Type

s Floating point data, or first number of device storing floating point data. Real number
d First number of device storing BIN data. BIN 16-/32-bit

6 – 120
Data conversion instructions INTD, INTPD, DINTD, DINTPD

Functions Conversion from floating point data into BIN data (Double precision)
INTD Conversion from 64-bit floating point data into BIN 16-bit data
64-bit floating point data in s is converted into BIN 16-bit data. The result is stored in d.

s+3 s+2 s+1 s d

BIN 16-bit

1
64-bit floating point data, data type real number
INT_0E1
Floating point data in s+3, s+2, s+1 and s have to range within -32768 and 32767.
The converted integer value is stored as BIN 16-bit data.
The converted integer value is rounded off at the first digit after the decimal point.

DINTD Conversion from 64-bit floating point data into BIN 32-bit data
64-bit floating point data in s is converted to BIN 32-bit data. The result is stored in d.

s+3 s+2 s+1 s d+1 d

1 BIN 32-bit

1 64-bit floating point data, data type real number

INT_0E2
Floating point data in s+3, s+2, s+1 and s have to range within -2147483648 and 2147483647.
The converted integer value is stored as BIN 32-bit data.
The converted integer value is rounded off at the first digit after the decimal point.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The value of the designated device is not zero and not within the following range:
2-1022 ≤ (Contents of designated device) < 21024
(Error code 4140)
● The value of the specified device is –0. (Error code 4140)
● Performing an INTD instruction, floating point data designated by s exceeds the relevant
device range of -32768 to 32767. (Error code 4100)
● Performing a DINTD instruction, floating point data designated by s exceeds the relevant
device range of -2147483648 to 2147483647. (Error code 4100)

Programming MELSEC System Q and L series 6 – 121

INTD, INTPD, DINTD, DINTPD Data conversion instructions

Program INTDP
Example 1
The following program converts 64-bit floating point data in D20 to D23 into BIN 16-bit data.
The result is stored in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D23 D22 D21 D20 D0

25915.6796 25916

1 2
D23 D22 D21 D20
33562.3211
1 3

1
64-bit floating point data, data type real number
2
BIN 16-bit data
3 No result. Value exceeds relevant device range of INTD instruction. Error code is returned.

INT__MB1, INT__KB1, INT__IB1, INT_0B1

Program DINTDP
Example 2
The following program converts 64-bit floating point data in D20 to D23 into BIN 32-bit data.
The result is stored in D0 and D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D23 D22 D21 D20 D1 D0

574968.321 574968
1 2
D23 D22 D21 D20
2147483649.22
1 3

1 64-bit floating point data, data type real number

2 BIN 32-bit data
3
No result. Value exceeds relevant device range of DINTD instruction. Error code is returned.

INT__MB2, INT__KB2, INT__IB2, INT_0B2

NOTE These programs will not run without variable definition in the header of the program organiza-
tion unit (POU). They would cause compiler or checker error messages. For details see section
3.5.2 "Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 122
Data conversion instructions DBL, DBLP

6.3.7 DBL, DBLP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

DBL__ME1, DBL__KE1, DBL__IE1

GX Works2

DBL__GE1

Variables Set Data Meaning Data Type

s First number of device storing data to be converted. BIN 16-bit
d First number of device storing converted data. BIN 32-bit

Programming MELSEC System Q and L series 6 – 123

DBL, DBLP Data conversion instructions

Functions Conversion from BIN 16-bit data into BIN 32-bit data
DBL Conversion from BIN 16-bit data into BIN 32-bit data
BIN 16-bit data in s is converted into BIN 32-bit data with sign. The result is stored in d.

DBL_0E1

Program DBLP
Example
With leading edge from X20, the following program converts BIN 16-bit data in D100 into BIN
32-bit data. The result ist stored in R0 and R1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

DBL__MB1, DBL__KB1, DBL__IB1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 124
Data conversion instructions WORD, WORDP

6.3.8 WORD, WORDP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

WORD_ME1, WORD_KE1, WORD_IE1

GX Works2

WORD_GE1

Variables Set Data Meaning Data Type

s First number of device storing data to be converted. BIN 32-bit
d First number of device storing converted data. BIN 16-bit

Programming MELSEC System Q and L series 6 – 125

WORD, WORDP Data conversion instructions

Functions Conversion from BIN 32-bit data into BIN 16-bit data
WORD Conversion from BIN 32-bit data into BIN 16-bit data
BIN 32-bit data in s is converted into BIN 16-bit data. The result is stored in d.

WORD0E1

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The BIN data designated by s and s+1 exceed the relevant device range of -32768 to 32767.
(Error code 4100)

Program WORDP
Example
With leading edge from X20, the following program converts BIN 32-bit data in D100 and D101
into BIN 16-bit data. The result is stored in R0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

WORD_MB1, WORD_KB1, WORD_IB1, WORD0B1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 126
Data conversion instructions GRY, GRYP, DGRY, DGRYP

6.3.9 GRY, GRYP, DGRY, DGRYP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GRY__ME1, GRY__KE1, GRY__IE1

GX Works2

GRY__GE1

Variables Set Data Meaning Data Type

s BIN data, or first number of device storing BIN data. BIN 16-/32-bit
Gray code data
d First number of device storing converted Gray code data.
16-/32-bit

Programming MELSEC System Q and L series 6 – 127

GRY, GRYP, DGRY, DGRYP Data conversion instructions

Functions Conversion from BIN data into Gray code data

GRY Conversion from BIN 16-bit data into Gray code data
BIN 16-bit data in s is converted into Gray code data. The result is stored in d.

GRY_0E1

DGRY Conversion from BIN 32-bit data into Gray code data
BIN 32-bit data in s is converted into Gray code data. The result is stored in d.

GRY_0E2

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● Data in s is negative. (Error code 4100)

6 – 128
Data conversion instructions GRY, GRYP, DGRY, DGRYP

Program GRYP
Example 1
With leading edge from X10, the following program converts BIN 16-bit data in D100 into Gray
code data. The result is stored in D200.

MELSEC Instruction List Ladder Diagram IEC Instruction List

GRY__MB1, GRY__KB1, GRY__IB1

Program DGRYP
Example 2
With leading edge from X1C, the following program converts BIN 32-bit data in D10 and D11
into Gray code data. The result is stored in D100 and D101.

MELSEC Instruction List Ladder Diagram IEC Instruction List

GRY__MB2, GRY__KB2, GRY__IB2

NOTE The program example 2 will not run without variable definition in the header of the program
organization unit (POU). It would cause compiler or checker error messages. For details see
section 3.5.2 "Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 129

GBIN, GBINP, DGBIN, DGBINP Data conversion instructions

6.3.10 GBIN, GBINP, DGBIN, DGBINP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

GBIN_ME1, GBIN_KE1, GBIN_IE1

GX Works2

GBIN_GE1

Variables Set Data Meaning Data Type

s Gray code data, or first number of device storing Gray code data. Gray code data
16-/32-bit
d First number of device storing converted BIN data. BIN 16-/32-bit

6 – 130
Data conversion instructions GBIN, GBINP, DGBIN, DGBINP

Functions Conversion from Gray code data into BIN data

GBIN Conversion from Gray code data into BIN 16-bit data
Gray code data in s is converted into BIN 16-bit data. The result is stored in d.

GBIN0E1

DGBIN Conversion from Gray code data into BIN 32-bit data
Gray code data in s is converted into BIN 32-bit data. The result is stored in d.

GBIN0E2

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● Performing a GBIN instruction, data in s exceeds the relevant device range of 0 to 32767.
(Error code 4100)
● Performing a DGBIN instruction, data in s exceeds the relevant device range of 0 to
2147483647. (Error code 4100)

Programming MELSEC System Q and L series 6 – 131

GBIN, GBINP, DGBIN, DGBINP Data conversion instructions

Program GBINP
Example 1
With leading edge from X10, the following program converts Gray code data in D100 into BIN
16-bit data. The result is stored in D200.

MELSEC Instruction List Ladder Diagram IEC Instruction List

GBIN_MB1, GBIN_KB1, GBIN_IB1

Program DGBINP
Example 2
With leading edge from X1C, the following program converts Gray code data in D10 and D11
into BIN 32-bit data. The result is stored in D0 and D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

GBIN_MB2, GBIN_KB2, GBIN_IB2

NOTE The program example 2 will not run without variable definition in the header of the program
organization unit (POU). It would cause compiler or checker error messages. For details see
section 3.5.2 "Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 132
Data conversion instructions NEG, NEGP, DNEG, DNEGP

6.3.11 NEG, NEGP, DNEG, DNEGP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

NEG__ME1, NEG__KE1, NEG__IE1

GX Works2

NEG__GE1

Variables Set Data Meaning Data Type

d First number of device storing data for the sign reversal. BIN 16-/32-bit

Programming MELSEC System Q and L series 6 – 133

NEG, NEGP, DNEG, DNEGP Data conversion instructions

Functions Complement of 2 of BIN 16- and 32-bit data (sign reversal)

NEG Negation of BIN 16-bit data
The NEG instruction (complement of 2) reverses the sign of BIN 16-bit data. BIN 16-bit data in
d is inverted first and then the value "1" is added. The result is stored in d.

1
Inversion with following addition
NEG_0E1

The function of this instruction is to change a negative sign into a positive one, or to change a
positive sign into a negative one.

DNEG Negation of BIN 32-bit data

The DNEG instruction (complement of 2) reverses the sign of BIN 32-bit data. BIN 32-bit data
in d is inverted first and then the value "1" is added. The result is stored in d.

1 Inversion with following addition

NEG_0E2

6 – 134
Data conversion instructions NEG, NEGP, DNEG, DNEGP

Program NEGP
Example
With leading edge from XA, the following program subtracts data in D10 from data in D20. M3
is set, if D10 is less than D20. If M3 is set, the result in D10 is the absolute value (complement
of 2) and becomes positive.

MELSEC Instruction List Ladder Diagram IEC Instruction List

NEG__MB1, NEG__KB1, NEG__IB1

Programming MELSEC System Q and L series 6 – 135

ENEG, ENEGP Data conversion instructions

6.3.12 ENEG, ENEGP

CPU High
Basic Process Redundant Universal LCPU
Performance
1)     

1 Basic model QCPU: The serial number (upper five digits) is "04122" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
d —   —   1) — —
1
Available only in multiple Universal model QCPU and LCPU

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

ENEG_ME1, ENEG_KE1, ENEG_IE1

GX Works2

ENEG_GE1

Variables Set Data Meaning Data Type

d First number of device storing floating point data for the sign reversal. Real number

6 – 136
Data conversion instructions ENEG, ENEGP

Functions Sign reversal for floating point data (Single precision)

ENEG Negation of 32-bit floating point data
These instructions negate 32-bit floating point data in d. The result is stored in d.
The function of these instructions is to change a negative sign into a positive one, or a positive
sign into a negative one.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The contents of the designated device or the result of the addition are not zero and not within
the following range:
2-126 ≤ (Contents of designated device) < 2128
(For the Universal model QCPU, LCPU) (Error code 4140)
● The value of the specified device is –0, unnormalized number, nonnumeric, or ∞.
(For the Universal model QCPU, LCPU) (Error code 4140)

Program ENEGP
Example
With leading edge from X20, the following program negates floating point data in D100 and
D101. The result is stored in D100 and D101.

MELSEC Instruction List Ladder Diagram IEC Instruction List

ENEG_MB1, ENEG_KB1, ENEG_IB1, ENEG0B1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 137

EDNEG, EDNEGP Data conversion instructions

6.3.13 EDNEG, EDNEGP

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
d —   — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

ENEG_ME1, ENEG_KE1, ENEG_IE1

GX Works2

EDNEG d
4
EDNEGP d
E
N
E
G
_
G
E
1

Variables Set Data Meaning Data Type

d First number of device storing floating point data for the sign reversal. Real number

6 – 138
Data conversion instructions EDNEG, EDNEGP

Functions Sign reversal for floating point data (Double precision)

EDNEG Negation of 64-bit floating point data
These instructions negate 64-bit floating point data in d. The result is stored in d.
The function of these instructions is to change a negative sign into a positive one, or a positive
sign into a negative one.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The contents of the designated device or the result of the addition are not zero and not within
the following range:
2-1022 ≤ (Contents of designated device) < 21024
(Error code 4140)
● The value of the specified device is –0.
(Error code 4140)

Program EDNEGP
Example
With leading edge from X20, the following program negates 64-bit floating point data in D0 to
D3. The result is stored in D0 to D3.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D3 D2 D1 D0 D3 D2 D1 D0
1.2345

ENEG_MB1, ENEG_KB1, ENEG_IB1, ENEG0B1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 139

BKBCD, BKBCDP Data conversion instructions

6.3.14 BKBCD, BKBCDP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s —   — — — — — —
d —   — — — — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BKBCDME1, BKBCDKE1, BKBCDIE1

GX Works2

BKBCDGE1

Variables Set Data Meaning Data Type

s First number of device storing BIN data to be converted. BIN 16-bit
d First number of device storing converted BCD data. BCD 4-digit
n Number of data blocks to be converted. BIN 16-bit

6 – 140
Data conversion instructions BKBCD, BKBCDP

Functions Conversion from BIN block data into BCD block data
BKBCD Conversion from BIN 16-bit block data into BCD 4-digit block data
This instruction converts each nth BIN 16-bit block in s into the nth BCD 4-digit block. Con-
verted data is stored in d.
BIN 16-bit block data in s has to range within 0 and 9999.
The most significant two bits of the BIN 16-bit data blocks in s must be reset (0).

BKBCD0E1

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The number of data blocks determined by n exceeds the storage device numbers designated
by s and d. (Error code 4101)
● BIN block data in s exceeds the relevant device range of 0 to 9999.
(Error code 4100)
● The storage device numbers designated by s and d overlap.
(Error code 4101)
For details on index qualification refer to section 3.6 of this manual.

Programming MELSEC System Q and L series 6 – 141

BKBCD, BKBCDP Data conversion instructions

Program BKBCDP
Example
With leading edge from X20, the following program converts BIN 16-bit block data in D100 into
BCD 4-digit block data. Converted data is stored in D200. The number of data blocks (3) con-
verted is stored in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BKBCDMB1, BKBCDKB1, BKBCDIB1, BKBCD0B1

6 – 142
Data conversion instructions BKBIN, BKBINP

6.3.15 BKBIN, BKBINP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s —   — — — — — —
d —   — — — — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BKBINME1, BKBINKE1, BKBINIE1

GX Works2

BKBINGE1

Variables Set Data Meaning Data Type

s First number of device storing BCD data to be converted. BCD 4-digit
d First number of device storing converted BIN data. BIN 16-bit
n Number of data blocks to be converted. BIN 16-bit

Programming MELSEC System Q and L series 6 – 143

BKBIN, BKBINP Data conversion instructions

Functions Conversion from BCD block data into BIN block data
BKBIN, BKBINP Conversion from BCD 4-digit block data into BIN 16-bit block data
This instruction converts each nth BCD 4-digit block in s into the nth BIN 16-bit block. Con-
verted data is stored in d.
BIN 16-bit block data in s has to range within 0 to 9999.

BKBIN0E1

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The number of data blocks determined by n exceeds the storage device numbers designated
by s and d. (Error code 4101)
● BCD block data in s exceeds the relevant device range of 0 to 9999.
(Error code 4100)
● The storage device numbers designated by s and d overlap.
(Error code 4101)
For details on index qualification refer to section 3.6 of this manual.

6 – 144
Data conversion instructions BKBIN, BKBINP

Program BKBINP
Example
With leading edge from X20, the following program converts BCD 4-digit block data in D100
into BIN 16-bit block data. Converted data is stored in D200. The number of data blocks (3)
converted is stored in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BKBINMB1, BKBINKB1, BKBINIB1, BKBIN0B1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 145

ECON, ECONP Data conversion instructions

6.3.16 ECON, ECONP

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn E
Bit Word Bit Word U\G
s —   — — —   —
d —   — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BKBINME1, BKBINKE1, BKBINIE1

GX Works2

ECON s d

ECONP s d
B
K
B
IN
G
E
1

Variables Set Data Meaning Data Type

Conversion source data, or head number of the device where
s (Real number (single precision)
conversion source data is stored
d Head number of the device where the converted data is stored (Real number (double precision))

6 – 146
Data conversion instructions ECON, ECONP

Functions Conversion from Single precision to Double precision

ECON Conversion from 32-bit into 64-bit floating point real number
This instruction converts 32-bit floating-point real number specified for s into 64-bit floating-
point real number, and stores the conversion result to the device specified for d.

S +1 S d +3 d +2 d +1 d

1 2

BKBIN0E1
1 32-bit floating-point real number
2
64-bit floating-point real number

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The value of the designated device is not zero and not within the following range:
2-126 ≤ (Value of designated device) < 2128
(Error code 4140)
● The value of the specified device is –0, unnormalized number, nonnumeric, or ∞.
(Error code 4140)

Program ECON
Example
With leading edge from X0, the following program converts 32-bit floating-point real number of
the devices D10 to D11, into 64-bit floating-point real number. Converted data is stored to the
devices D0 to D3.

Ladder Diagram

BKBINMB1, BKBINKB1, BKBINIB1, BKBIN0B1

Programming MELSEC System Q and L series 6 – 147

EDCON, EDCONP Data conversion instructions

6.3.17 EDCON, EDCONP

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn E
Bit Word Bit Word U\G
s —   — — — —  —
d —   — — —  — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BKBINME1, BKBINKE1, BKBINIE1

GX Works2

EDCON s d

EDCONP s d
B
K
B
IN
G
E
1

Variables Set Data Meaning Data Type

Conversion source data, or head number of the device where
s Real number (double precision)
conversion source data is stored
d Head number of the device where the converted data is stored Real number (single precision))

6 – 148
Data conversion instructions EDCON, EDCONP

Functions Conversion from Double precision to Single precision

EDCON Conversion from 64-bit into 32-bit floating point real number
This instruction converts 64-bit floating-point real number specified for s into 32-bit floating-
point real number, and stores the conversion result to the device specified for d.

s+3 s+2 s+1 s d+1 d

1 2

BKBIN0E1
1
64-bit floating-point real number
2
32-bit floating-point real number

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The value of the designated device is not zero and not within the following range:
2-1022 ≤ (Value of designated device) < 21024
(Error code 4140)
● The value of the specified device is –0.
(Error code 4140)
● The conversion result is not within the following range:
–2128 ≤ (Conversion result) ≤ 2128
(Error code 4141)

Program EDCON
Example
With leading edge from X0, the following program converts 64-bit floating-point real number of
the devices D10 to D13, into 32-bit floating-point real number. Converted data is stored to the
devices D0 and D1.

Ladder Diagram

Programming MELSEC System Q and L series 6 – 149

EDCON, EDCONP Data transfer instructions

6.4 Data transfer instructions

These instructions transfer, invert, or exchange data. Refer to the following table for an over-
view of the instructions.

NOTE Transferred data remain stored until they are replaced. Therefore, data even remain stored if the
input condition of the transfer instruction is reset.

MELSEC Instruction MELSEC Instruction

Function in in
MELSEC Editor IEC Editor
MOV MOV_M

BIN Data Transfer MOVP MOVP_M

(16-/32-bit) DMOV DMOV_M
DMOVP DMOVP_M
EMOV EMOV_M
Transfer of EMOVP EMOVP_M
Floating Point Data
(16-/32-bit) EDMOV EDMOV_M
EDMOVP EDMOVP_M

Transfer of $MOV STRING_MOV_M

Character String Data $MOVP STRING_MOVP_M
CML CML_M

Inverted BIN Data Transfer CMLP CMLP_M

(16-/32-bit) DCML DCML_M
DCMLP DCMLP_M
BMOV BMOV_M
Block Data Transfer
BMOVP BMOVP_M
FMOV FMOV_M
Block Transfer of FMOVP FMOVP_M
identical Data
(16-/32-bit) DFMOV DFMOV_M
DFMOVP DFMOVP_M
XCH XCH_M

BIN Data Exchange XCHP XCHP_M

(16-/32-bit) DXCH DXCH_M
DXCHP DXCHP_M

BIN Data Exchange BXCH BXCH_M

(16-bit blocks) BXCHP BXCHP_M

Byte Exchange SWAP SWAP_MD

(upper and lower byte) SWAPP SWAP_P_MD

NOTE Within the IEC editors please use the IEC commands.

6 – 150
Data transfer instructions MOV, MOVP, DMOV, DMOVP

6.4.1 MOV, MOVP, DMOV, DMOVP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

MOV__ME1, MOV__KE1, MOV__IE1

GX Works2

MOV__GE1

Variables Set Data Meaning Data Type

s Source data, or first number of device storing data to be transferred.
BIN 16-/32-bit
d First number of destination device to store transferred data.

Programming MELSEC System Q and L series 6 – 151

MOV, MOVP, DMOV, DMOVP Data transfer instructions

Functions BIN 16-bit/32-bit data transfer

MOV BIN 16-bit data transfer
The MOV instruction transfers BIN 16-bit data in s to the device designated by d.

MOV_0E1

DMOV BIN 32-bit data transfer

The DMOV instruction transfers BIN 32-bit data in s to the device designated by d.

MOV_0E2

Program MOVP
Example 1
The following program transfers data at X0 through XB to D8.

MELSEC Instruction List Ladder Diagram IEC Instruction List

MOV__MB1, MOV__KB1, MOV__IB1

Program MOVP
Example 2
With leading edge from X8, the following program transfers the constant 155 as BIN value to
D8.

MELSEC Instruction List Ladder Diagram IEC Instruction List

MOV__MB2, MOV__KB2, MOV__IB2, MOV_0B1

6 – 152
Data transfer instructions MOV, MOVP, DMOV, DMOVP

Program DMOVP
Example 3
The following program transfers data in D0 and D1 to D7 and D8.

MELSEC Instruction List Ladder Diagram IEC Instruction List

MOV__MB3, MOV__KB3, MOV__IB3

Program DMOVP
Example 4
The following program transfers data at X0 through X1F to D0 and D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

MOV__MB4, MOV__KB4, MOV__IB4

NOTE The program examples 3 and 4 will not run without variable definition in the header of the pro-
gram organization unit (POU). They would cause compiler or checker error messages. For
details see section 3.5.2 "Addressing of arrays and registers in the GX IEC Developer" of this
manual.

Programming MELSEC System Q and L series 6 – 153

EMOV, EMOVP Data transfer instructions

6.4.2 EMOV, EMOVP

CPU High
Basic Process Redundant Universal LCPU
Performance
1)     

1 Basic model QCPU: The upper five digits of the serial No. are "04122" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant Other
Register Module Zn E
Bit Word Bit Word U\G
s —   —   1)  —
1)
d —   —    — —
1
Available only in multiple Universal model QCPU, LCPU

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

EMOVME1, EMOVKE1, EMOVIE1

GX Works2

EMOVGE1

Variables Set Data Meaning Data Type

s Floating point data, or first number of device storing data to be transferred.
Real number
d First number of device storing transferred floating point data.

6 – 154
Data transfer instructions EMOV, EMOVP

Functions Floating point data transfer (Single precision)

EMOV 32-bit floating point data transfer
The EMOV instruction transfers 32-bit floating point data in s to the device designated by d.

1
32-bit floating point number, data type real number
EMOV0E1

Program EMOVP
Example 1
The following program transfers 32-bit floating point data in D10 and D11 to D0 and D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

EMOVMB1, EMOVKB1, EMOVIB1, EMOV0B1

Program EMOVP
Example 2
With leading edge from X8, the following program transfers the real number –1.23 to D10 and
D11.

MELSEC Instruction List Ladder Diagram IEC Instruction List

EMOVMB2, EMOVKB2, EMOVIB2, EMOV0B2

NOTE These programs will not run without variable definition in the header of the program organization
unit (POU). They would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 155

EDMOV, EDMOVP Data transfer instructions

6.4.3 EDMOV, EDMOVP

CPU High
Basic Process Redundant Universal LCPU
Performance
 

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn E
Bit Word Bit Word U\G
s —   — — — —  —
d —   — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

EMOVME1, EMOVKE1, EMOVIE1

GX Works2
MOV/DMOV.

s d

E
M
O
V
G
E
1
P s d

Variables Set Data Meaning Data Type

s Floating point data, or first number of device storing data to be transferred.
Real number
d First number of device storing transferred floating point data.

6 – 156
Data transfer instructions EDMOV, EDMOVP

Functions Floating point data transfer (Double precision)

EDMOV 64-bit floating point data transfer
The EDMOV instruction transfers 64-bit floating point data in s to the device designated by d.

s+3 s+2 s+1 s d+3 d+2 d+1 d

4.23542 4.23542
1 1

1
64-bit floating point number, data type real number
EMOV0E1

Program EDMOVP
Example 1
The following program transfers 64-bit floating point data in D10 to D13 to D0 to D3.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D13 D12 D11 D10 D3 D2 D1 D0

36.475 36.475

EMOVMB1, EMOVKB1, EMOVIB1, EMOV0B1

Program EDMOVP
Example 2
With leading edge from X8, the following program transfers the real number –1.23 to D10 to
D13.

MELSEC Instruction List Ladder Diagram IEC Instruction List

D13 D12 D11 D10

EMOVMB2, EMOVKB2, EMOVIB2, EMOV0B2

NOTE These programs will not run without variable definition in the header of the program organization
unit (POU). They would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 157

$MOV, $MOVP Data transfer instructions

6.4.4 $MOV, $MOVP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn $
Bit Word Bit Word U\G
s —   — — — —  —
d —   — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

SMOV_ME1, SMOV_KE1, SMOV_IE1

GX Works2

SMOV_ME1

Variables Set Data Meaning Data Type

s Character string data, or first number of device storing data to be transferred.
Character string
d First number of device storing transferred character string data.

6 – 158
Data transfer instructions $MOV, $MOVP

Functions Character string data transfer

$MOV Character string data transfer
The $MOV instruction transfers character string data in s to d. The instruction transfers char-
acter string data from the first number of device designated by s up to the number of device
storing the code "00H" (end of string) in one operation.

1
Indicates end of character string
2
1st character
3
nth character
SMOV0E1
The $MOV instruction is even performed without error messages, if the range of devices stor-
ing character string data to be transferred (s through s+n) overlaps with the range of devices
storing transferred data (d through d+n). The $MOV instruction performs as follows, if character
string data in D10 through D13 is transferred to D11 through D14:

SMOV0E2
If the code "00H" is stored at lower bytes of s+n, the characters following at the higher bytes are
omitted. In d+n, the transferred code "00H" will be stored at both, the higher bytes and the lower
bytes:

1 Character is not transferred.

2
"00H" is stored automatically.
SMOV0E3

Programming MELSEC System Q and L series 6 – 159

$MOV, $MOVP Data transfer instructions

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The code "00H" does not exist in character string data designated by s. (Error code 4101)
● Character string data in s cannot be transferred completely to d. (Error code 4101)
● The character string of s exceeds 16383 characters. (Error code 4101)

Program With leading edge from X0, the following program transfers character string data at D10
Example through D12 to D20 through D22.

Ladder Diagram
MELSEC Instruction List

IEC Instruction List

SMOV_MB1, SMOV_KB1, SMOV_IB1, SMOV0B1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 160
Data transfer instructions CML, CMLP, DCML, DCMLP

6.4.5 CML, CMLP, DCML, DCMLP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

CML__ME1, CML__KE1, CML__IE1

GX Works2

Variables Set Data Meaning Data Type

s BIN data, or first number of device storing data to be inverted.
BIN 16-/32-bit
d First number of device storing inverted data.

Programming MELSEC System Q and L series 6 – 161

CML, CMLP, DCML, DCMLP Data transfer instructions

Functions BIN 16-bit/32-bit data inversion

CML BIN 16-bit data inversion
BIN 16-bit data in s is inverted bit by bit. The result is stored in d.

DCML BIN 32-bit data inversion

BIN 32-bit data in s is inverted bit by bit. The result is stored in d.

Program CML
Example 1
While SM402 is set, the following program transfers data at X0 through X7 inverted to D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Undesignated bits are read as 0.
CML__MB1, CML__KB1, CML__IB1, CML_0B1
In this example the number of bits in s is smaller than the number of bits in d.

6 – 162
Data transfer instructions CML, CMLP, DCML, DCMLP

Program CML
Example 2
While SM402 is set, the following program transfers data in M16 through M23 inverted to K3
Y40 (Y40 through Y4F). Y48 through Y4B are all set (1), because they were read as 0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Undesignated bits are read as 0.
In this example the number of bits in s is smaller than the number of bits in d.

Program CMLP
Example 3
With leading edge from X3, the following program transfers data in D0 inverted to D16.

MELSEC Instruction List Ladder Diagram IEC Instruction List

CML__MB3, CML__KB3, CML__IB3, CML_0B3

Programming MELSEC System Q and L series 6 – 163

CML, CMLP, DCML, DCMLP Data transfer instructions

Program DCML
Example 4
While SM402 is set, the following program transfers data at X0 through X1F inverted to D0 and
D1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Undesignated bits are read as 0.
CML__MB4, CML__KB4, CML__IB4, CML_0B4
In this example the number of bits in s is smaller than the number of bits in d.

Program DCML
Example 5
While SM402 is set, the following program transfers data in M16 through M35 inverted to Y40
and Y57.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1 Undesignated bits are read as 0.

In this example the number of bits in s is smaller than the number of bits in d.
CML__MB5, CML__KB5, CML__IB5, CML_0E4

6 – 164
Data transfer instructions CML, CMLP, DCML, DCMLP

Program DCMLP
Example 6
With leading edge from X3, the following program transfers data in D0 and D1 inverted to D16
and D17.

MELSEC Instruction List Ladder Diagram IEC Instruction List

CML__MB6, CML__KB6, CML__IB6, CML_0B6

NOTE The program examples 4 and 6 will not run without variable definition in the header of the pro-
gram organization unit (POU). They would cause compiler or checker error messages. For
details see section 3.5.2 "Addressing of arrays and registers in the GX IEC Developer" of this
manual.

Programming MELSEC System Q and L series 6 – 165

BMOV, BMOVP Data transfer instructions

6.4.6 BMOV, BMOVP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s       — — —
d       — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BMOV_ME1, BMOV_KE1, BMOV_IE1

GX Works2

BMOV_GE1

Variables Set Data Meaning Data Type

s First number of device storing data to be transferred.
d First number of device storing transferred data. BIN 16-bit
n Number of data blocks to be transferred.

6 – 166
Data transfer instructions BMOV, BMOVP

Functions BIN block data transfer

BMOV BIN 16-bit block data transfer
The BMOV instruction transfers successive data blocks in a batch. The first number of device
storing block data is designated by s. The number of successive data blocks to be transferred
is determined by n. The data are transferred to the device designated by d onwards.

V0E1B
M
O
A transfer can even be performed without operation errors, if the source and the destination
devices overlap. Transfer to the smaller device number begins from s. Transfer to the larger
device number begins from s+(n-1).
However, as shown in the example below, when transferring data from R to ZR, or from ZR to
R, the range to be transferred (source) and the range of destination must not overlap. Transfer
from R to R, or from ZR to ZR can be performed without any problem.
– ZR transfer range
(specified head No. of ZR) to
(specified head No. of ZR + the number of transfers -1)
– R transfer range
((specified head No. of R + file register block No. 32768) to
(specified head No. of R + file register block No. 32768 + the number of transfers -1))

Example Transfer ranges of ZR and R overlap when transferring 10000 blocks of data from ZR30000
to R10 (block no. 1 of destination).
Die Übertragungsbereiche von ZR und R überlappen sich, wenn 10000 Datenblöcke von
ZR30000 nach R10 (Block-Nr. 1 des Datenziels) übertragen werden.
– ZR transfer range: (30000) to (30000 + 10000 -1) = (30000) to (39999)
– R transfer range: (10 + (1 x 32768)) to (10 + (1 x 32768) + 10000 -1)
= (32778) to (42777)
Therefore the range 32778 to 39999 overlaps and the data is not transferred correctly.

Source Destination
ZR0 R0

Overlapped Block No. 0

ZR30000 R32767
ZR39999 R10
R10009 Block No. 1

Programming MELSEC System Q and L series 6 – 167

BMOV, BMOVP Data transfer instructions

If s is a word device and d is a bit device, the number of bits designated by digit designation for
the bit device will be the object bits for the word device. If K1Y30 is designated by d, the object
bits for the word device s are the lower 4 bits.

V0E2B
M
O
If s and d are bit devices, the number of bits in s and d must equal.
When using a link direct device and an intelligent function module device for s and d, only either
of s or d can be used.
Whether to check a device range during execution of the BMOV instruction can be selected
with the device range check inhibit flag (SM237) (only when the conditions for subset process-
ing are established). While SM237 is ON, whether s to s + (n) -1 and d to d + (n) - 1 are within
the device range or not are not checked.

NOTES SM237 can be used only for the Universal model QCPU whose first 5 digits of serial number is
10012 or higher and for LCPU.
While SM237 is on, do not make the following access.
– The indexing target exceeds the device range.
– The value obtained from "d to d+(n)- 1" is over the boundaries of the device ranges.
– Accessing the file register with file register not set.
– Accessing the area where the multiple CPU high speed transmission area device is not avail-
able (only for the QCPU).

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The number of data blocks determined by n exceeds the storage device numbers designated
by s and d.
(Error code 4101)

6 – 168
Data transfer instructions BMOV, BMOVP

Program BMOVP
Example 1
With leading edge from SM402, the following program transfers the lower 4 bits of data (b0
through b3) in D66 through D69 to the outputs Y30 through Y3F. The number of blocks (4) to
be transferred is determined by the constant K4.
The bit patterns show the structure of bits before and after the transfer.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
These bits are ignored.
BMOV_MB1, BMOV_KB1, BMOV_IB1, BMOV0B1

Program BMOVP
Example 2
With leading edge from SM402, the following program transfers data at X20 through X2F to
D100 through 103. The number of blocks (4) to be transferred is determined by the constant
K4.
The bit patterns show the structure of bits before and after the transfer.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BMOV_MB2, BMOV_KB2, BMOV_IB2, BMOV0B2

Programming MELSEC System Q and L series 6 – 169

FMOV, FMOVP Data transfer instructions

6.4.7 FMOV, FMOVP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s         —
d       — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

FMOV_ME1, FMOV_KE1, FMOV_IE1

GX Works2

FMOV_ME1

Variables Set Data Meaning Data Type

s First number of device storing data to be transferred.
d First number of device storing transferred data. BIN 16-bit
n Number of data blocks to be transferred.

6 – 170
Data transfer instructions FMOV, FMOVP

Functions Identical BIN block data transfer

FMOV Identical BIN 16-bit block data transfer
The FMOV instruction transfers 16-bit block data in s to d through d+(n-1). Each device of the
data block from d through d+(n-1) stores the value from s.

FMOV0E1
If s is a word device and d is a bit device, the number of bits designated by digit designation for
the bit device will be the object bits for the word device.

1
These bits are ignored.
FMOV0E2
If s and d are bit devices, the number of bits in s and d must equal.
Whether to check a device range during execution of the FMOV instruction can be selected
with the device range check inhibit flag (SM237) (only when the conditions for subset process-
ing are established). While SM237 is ON, whether d to d + (n) - 1 is within the device range or
not is not checked.
NOTES SM237 can be used only for the Universal model QCPU whose first 5 digits of serial number is
10012 or higher and for LCPU.
While SM237 is on, do not make the following access.
– The indexing target exceeds the device range.
– The value obtained from "d to d+(n–1)" is over the boundaries of the device ranges.
– Accessing the file register with file register not set.
– Accessing the area where the multiple CPU high speed transmission area device is not avail-
able (only for the QCPU).

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The number of data blocks determined by n exceeds the storage device numbers designated
by d. (Error code 4101)

Programming MELSEC System Q and L series 6 – 171

FMOV, FMOVP Data transfer instructions

Program FMOVP
Example 1
With leading edge from XA, the following program transfers the lower 4 bits of data (b0 through
b3) in D0 to the outputs Y10 through Y23. The number of blocks (5) is determined by the con-
stant K5.
The bit patterns show the structure of bits before and after the transfer.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
These bits are ignored.
FMOV_MB1, FMOV_KB1, FMOV_IB1, FMOV0B3

Program FMOVP
Example 2
With leading edge from XA, the following program transfers data at X20 through X23 to D100
through D103. The number of blocks (4) to be transferred is determined by the constant K4.
The bit patterns show the structure of bits before and after the transfer.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
These bits are ignored.

6 – 172
Data transfer instructions DFMOV, DFMOVP

6.4.8 DFMOV, DFMOVP

CPU High
Basic Process Redundant Universal LCPU
Performance
1) 

1 QnU(D)(H)CPU: The serial number (first five digits) is "10102" or higher.

QnUDE(H)CPU: The serial number (first five digits) is "10102" or higher.

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Register Module Zn K, H (16#) Other
Bit Word Bit Word U\G
s         —
d       — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

FMOV_ME1, FMOV_KE1, FMOV_IE1

GX Works2

DFMOV s d n

DFMOVP s d n
F
M
O
V
_
M
E
1

Variables Set Data Meaning Data Type

s First number of device storing data to be transferred.
d First number of device storing transferred data. BIN 32-bit
n Number of data blocks to be transferred.

Programming MELSEC System Q and L series 6 – 173

DFMOV, DFMOVP Data transfer instructions

Functions Identical BIN 32-bit block data transfer

DFMOV Identical BIN 32-bit block data transfer
The DFMOV instruction transfers 32-bit data in s to d through d+(n-2). Each device of the data
block from d through d+(n-2) stores the value from s.

b31 b0
Transfer 1234567H
b31 b0 d+1 , d
s+1, s 1234567H d+3 , d+2 1234567H
d+5 , d+4 1234567H n

d+n–1 , d+n–2 1234567H

FMOV0E1
If s is a word device and d is a bit device, the number of bits designated by digit designation for
the bit device will be the object bits for the word device.
If K5Y0 is specified by s, the lower 20 bits (five digits) of the word device specified by s will be
the object.

Y1F Y14 Y13 Y0

s+1, s

Ignored 20 bits (five digits) data

b31 b20 b19 b0
0 d+1, d

0 d+3 d+2

Transfer b31 b20 b19 b0

0 d+(2n–1), d+(2n–2)

Filled with 0s 20 bits (five digits) data

FMOV0E2
If d specifies data of a device with digit specification, the amount of data stored in the device
specified by d will be transferred.
If K5Y0 is specified by d, the lower 20 bits of the word device specified by s will be the object.
If both s and d specify data of a device with digit specification, the amount of data specified by
d will be transferred regardless of the number of digits.

b31 b20 b19 b0

s+1, s 3
Amount of data specified digits by d

Transfer 4
d+n d+1 d

Y14n+19 Y14n Y27 Y14 Y13 Y0

4

If the value specified by n is 0, the instruction will be not processed.

Whether to check a device range during the execution of the DFMOV instruction can be
selected with the device range check inhibit flag (SM237). (Only when the conditions of the
subset processing are established).

6 – 174
Data transfer instructions DFMOV, DFMOVP

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The value specified by n is negative.
(Error code 4100)
● The number of data blocks determined by n exceeds the storage device numbers designated
by d.
(Error code 4101)

Program DFMOVP
Example
With leading edge from M0, the following program transfers the value of data (Y0 to Y13 (20
bits) into D10 to D17.

MELSEC Instruction List Ladder Diagram IEC Instruction List

Y1F Y14 Y13 Y0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Ignored 20 bits (five digits) data

b31 b20 b19 b0

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D11,D1

Transfer 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D13,D1

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D15,D1

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D17,D1

Filled with 0s 20 bits (five digits) data

FMOV_MB1, FMOV_KB1, FMOV_IB1, FMOV0B3

FMOV_MB2, FMOV_KB2, FMOV_IB2, FMOV0B2

Programming MELSEC System Q and L series 6 – 175

XCH, XCHP, DXCH, DXCHP Data transfer instructions

6.4.9 XCH, XCHP, DXCH, DXCHP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
d1        — —
d2        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

XCH__ME1, XCH__KE1, XCH__IE1

GX Works2

XCH__GE1

Variables Set Data Meaning Data Type

d1
First number of device storing data to be exchanged. BIN 16-/32-bit
d2

6 – 176
Data transfer instructions XCH, XCHP, DXCH, DXCHP

Functions BIN data exchange

XCH BIN 16-bit data exchange
The XCH instruction exchanges BIN 16-bit data in d1 and BIN 16-bit data in d2.

XCH_0E1

DXCH BIN 32-bit data exchange

The DXCH instruction exchanges BIN 32-bit data in (d1)+1, d1 and BIN 32-bit data in(d2)+1,
d2.

XCH_0E2

Program XCHP
Example 1
With leading edge from X8, the following program exchanges data in D0 and the actual value
in T0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

XCH__MB1, XCH__KB1, XCH__IB1

Programming MELSEC System Q and L series 6 – 177

XCH, XCHP, DXCH, DXCHP Data transfer instructions

Program XCHP
Example 2
With leading edge from X10, the following program exchanges data in D0 and data in M16
through M31.

MELSEC Instruction List Ladder Diagram IEC Instruction List

XCH__MB2, XCH__KB2, XCH__IB2

Program DXCHP
Example 3
With leading edge from X10, the following program exchanges data in D0 and D1 and data in
M16 through M47.

MELSEC Instruction List Ladder Diagram IEC Instruction List

XCH__MB3, XCH__KB3, XCH__IB3

Program DXCHP
Example 4
With leading edge from M0, the following program exchanges data in D0 and D1 and data in
D9 and D10.

MELSEC Instruction List Ladder Diagram IEC Instruction List

XCH__MB4, XCH__KB4, XCH__IB4

NOTE The program examples 3 and 4 will not run without variable definition in the header of the pro-
gram organization unit (POU). They would cause compiler or checker error messages. For
details see section 3.5.2 "Addressing of arrays and registers in the GX IEC Developer" of this
manual.

6 – 178
Data transfer instructions BXCH, BXCHP

6.4.10 BXCH, BXCHP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
d1 —   — — — — — —
d2 —   — — — — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

BXCH_ME1, BXCH_KE1, BXCH_IE1

GX Works2

BXCH_GE1

Variables Set Data Meaning Data Type

d1
First number of device storing data to be exchanged
d2 BIN 16-bit
n Number of exchanges

Programming MELSEC System Q and L series 6 – 179

BXCH, BXCHP Data transfer instructions

Functions BIN block data exchange

BXCH BIN 16-bit block data exchange
The BXCH instruction exchanges BIN 16-bit block data in d1 and BIN 16-bit block data in d2.

BXCH0E1

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The number of data blocks determined by n exceeds the storage device numbers designated
by d1 and d2. (Error code 4101)
● The storage device numbers designated by d1and d2 overlap. (Error code 4101)

6 – 180
Data transfer instructions BXCH, BXCHP

Program BXCHP
Example
With leading edge from X1C, the following program exchanges data blocks beginning from
D200 and data blocks beginning from R0. The number of blocks (3) to be exchanged is deter-
mined by the constant K3.
The bit patterns show the structure of bits before and after the transfer.

MELSEC Instruction List Ladder Diagram IEC Instruction List

BXCH_MB1, BXCH_KB1, BXCH_IB1, BXCH0B1

Programming MELSEC System Q and L series 6 – 181

SWAP, SWAPP Data transfer instructions

6.4.11 SWAP, SWAPP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s        — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

SWAP_ME1, SWAP_KE1, SWAP_IE1

GX Works2

BXCH_GE1

Variables Set Data Meaning Data Type

s First number of device storing data to be swapped. BIN 16-bit

6 – 182
Data transfer instructions SWAP, SWAPP

Functions Upper and lower byte exchanges

SWAP Upper and lower byte exchanges
The swap instruction exchanges the upper and lower 8 bits (upper and lower byte) of BIN 16-bit
data in s.

SWAP0E1

Program SWAPP
Example
With leading edge from X10, the following program exchanges the upper and lower 8 bits in
R10.

MELSEC Instruction List Ladder Diagram IEC Instruction List

SWAP_MB1, SWAP_KB1, SWAP_IB1, SWAP0B1

Programming MELSEC System Q and L series 6 – 183

SWAP, SWAPP Data transfer instructions

6 – 184
Program branch instructions

6.5 Program branch instructions

Program branch instructions include a jump destination.

MELSEC Instruction MELSEC Instruction

Function in in
MELSEC Editor IEC Editor
Conditional Jump CJ CJ_M
Conditional Jump
from next Scan SCJ SCJ_M

Jump JMP JMP_M

Jump to End of Program GOEND GOEND_M

A jump destination is designated by a pointer P (GX Works2) or a label (GX IEC Developer).
For details on programming a label in GX IEC Developer see the Programming Manual for the
GX IEC Developer.

GX IEC Developer

CJ___IB3, CJ___IB1

GX Works2

CJ___GB1

Programming MELSEC System Q and L series 6 – 185

CJ, SCJ, JMP Program branch instructions

6.5.1 CJ, SCJ, JMP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
Other
(System, User) File Direct J\ Function Index Register Constant
Register Module Zn K, H (16#)
Bit Word Bit Word U\G P
p — — — — — — — — 

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

J___ME1, CJ___KE1, CJ___IE1C

GX Works2

CJ___GE1

Variables Set Data Meaning Data Type

p Jump destination Pointer/Label

6 – 186
Program branch instructions CJ, SCJ, JMP

Functions Jump instructions

A jump instruction consists of a jump command CJ, SCJ, or JMP (Conditional Jump, JuMP)
and a pointer (or label) P, designating the jump destination.
The pointer (label) number has to range within P(Label)0 and P(Label)4095. A jump destina-
tion P(Label)xx can be freely placed in a program.

CJ Conditional jump
Executes the program specified by the pointer number within the same program file, when the
execution command is ON.
When the execution command is OFF, the program at the next step is executed.

1
Input condition
2
CJ instruction
3 Executed each scan

CJ__0E1

SCJ Conditional jump from next program scan

Executes the program specified by the pointer number within the same program file starting
with the scan immediately after turning from OFF to ON of the execution command.
When the execution command is OFF or turned from ON to OFF, the program at the next step
is executed.

1
Input condition
2 SCJ instruction
3 One scan

4
Executed each scan
CJ__0E2

JMP Jump instruction

The jump instruction executes the part of a program designated by the jump destination within
the same program file without any input condition (unconditional jump).

Programming MELSEC System Q and L series 6 – 187

CJ, SCJ, JMP Program branch instructions

NOTE If a set timer is skipped by a CJ, SCJ, or JMC instruction it will nevertheless keep its timing
accurately.
If an OUT instruction is skipped by a jump instruction, the condition of the output remains un-
changed.
Executing a jump instruction shortens the scan time of a program in relation to the skipped pro-
gram steps (see tables in appendices).
The CJ, SCJ, and JMP instruction can even jump back to a lower jump destination. However, a
program must exit the program loop before the watchdog timer times out (the following program
example exits the loop, when X7 is set).

CJ___AB1
The condition of a device skipped by a jump instruction remains unchanged. This is illustrated
by the following program example:

CJ___AB2
After XB is set, this program jumps to the jump destination Label19. The conditions of the out-
puts Y43 and Y49 even remain unchanged, if XC or XD are set or reset.
The jump destination (e.g. Label9) occupies one program step.

CJ___AB3
The CJ, SCJ, or JMP instruction only jumps to destinations within one single program.
If a jump destination is located within the skip range during a skip operation (operation skipping
parts of a program), program execution proceeds from the first available address following the
jump destination.

6 – 188
Program branch instructions CJ, SCJ, JMP

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● A common pointer has been designated. (Error code 4210)
● The jump destination of the jump instruction is not defined in a program (jump destination
or pointer is missing). (Error code 4210)
● The jump destination is located after an END instruction.
(Error code 4210)

Program CJ
Example 1
The following program jumps to the destination Label_3 when X9 is set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

CJ___MB1, CJ___KB1, CJ___IB1

Program SCJ
Example 2
The following program jumps to the destination Label_3 from the next scan when XC is set.

MELSEC Instruction List Ladder Diagram IEC Instruction List

CJ___MB2, CJ___KB2, CJ___IB2

Programming MELSEC System Q and L series 6 – 189

GOEND Program branch instructions

6.5.2 GOEND

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
— — — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

G
OENDME1, GOENDKE1, GOENDIE1

GX Works2

GOENDGE1

Variables Set Data Meaning Data Type

— — —

6 – 190
Program branch instructions GOEND

Functions GOEND Jump to the end of a program

The jump destination of the GOEND instruction is the FEND or END instruction of the program.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● A GOEND instruction was executed after a CALL or ECALL instruction and before a RET
instruction. (Error code 4211)
● A GOEND instruction was executed after a FOR instruction and before a NEXT instruction.
(Error code 4200)
● A GOEND instruction was executed during an interrupt program but before an IRET
instruction. (Error code 4221)
● A GOEND instruction was executed between a CHKCIR and a CHKEND instruction.
(Error code 4230)
● A GOEND instruction was executed between an IX and an IXEND instruction.
(Error code 4231)

Program GOEND
Example
The following program jumps to the END instruction when data in D0 is negative.

MELSEC Instruction List Ladder Diagram IEC Instruction List

GOENDMB1, GOENDKB1, GOENDIB1

Programming MELSEC System Q and L series 6 – 191

 Program execution control instructions

6.6 Program execution control instructions

Program execution control instructions invoke interrupt routines. The interrupts can be enabled
or disabled individually or via bit patterns.
The following table gives an overview of these instructions:

MELSEC Instruction MELSEC Instruction

Function in in
MELSEC Editor IEC Editor
Interrupt disabled DI DI_M
Interrupt enabled EI EI_M
Bit pattern of execution conditions of
IMASK IMASK_M
interrupt programs
End of interrupt program IRET IRET_M

6 – 192
Program execution control instructions DI, EI, IMASK

6.6.1 DI, EI, IMASK

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s — 1) 1) — 1) 1) — — —
— — — — — — — — — —
1 IMASK instruction only

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

DI__ME1, DI__KE1, DI__IE1

GX Works2

DI___GE1

Variables Set Data Meaning Data Type

s Bit pattern storing execution conditions of interrupts or first number of device BIN 16-bit
storing bit pattern.

Programming MELSEC System Q and L series 6 – 193

DI, EI, IMASK Program execution control instructions

Functions Interrupt instructions

An interrupt program is an inserted part of program (designated by an interrupt address Ixx)
that can be invoked by an external interrupt signal. The interrupt program is executed depend-
ing on the EI/DI instruction.
DI Disable interrupt
The DI instruction disables the execution of an interrupt program until an EI instruction is exe-
cuted. The DI state is actice when power is turned ON or when the CPU module is reset.

EI Enable interrupt
The EI instruction enables invoking an interrupt program designated by an interrupt address
Ixx, or enables the execution of an IMASK instruction.
Even though an interrupt condition might be generated between the DI and EI instructions, the
interrupt program is suspended until the entire cycle from DI to EI has been processed. The fol-
lowing diagram illustrates such an execution:

1
Sequence program
2
Interrupt program
DI__0E1

NOTE The GX IEC Developer inserts the FEND instruction automatically. The event Ixx has to be allo-
cated to a task.

6 – 194
Program execution control instructions DI, EI, IMASK

IMASK Bit pattern of execution conditions of interrupt programs

In the bit pattern designated by s a particular interrupt address is allocated to each bit. The
condition of each bit determines whether the allocated interrupt can be executed. If the bit is
reset (0), the interrupt program cannot be executed. If the bit is set (1), the interrupt program
will be executed.

System Q The allocation of bits in s through s+7 to the corresponding interrupt addresses is shown
CPU (Basic below:
Model
QCPU)
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
s I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

s +1 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16

s+2 I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32

s+3 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48

s+4 I79 I78 I77 I76 I75 I74 I73 I72 I71 I70 I69 I68 I67 I66 I65 I64

s+5 I95 I94 I93 I92 I91 I90 I89 I88 I87 I86 I85 I84 I83 I82 I81 I80

s+6 I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96

s+7 I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112

IMASK0E3
When the power supply of the CPU is switched on or when the CPU has been reset, the exe-
cution of interrupt programs I0 through I31, I48 to I127 is enabled.
The bit patterns designated by s through s+2 are stored in the special registers SD715 through
SD717. The bit patterns designated by s+3 through s+7 are stored in the special registers
SD781 through SD785.
The bit patterns are designated as s through s+7 successively although the special registers
are separated (SD715 through SD717 and SD781 through SD785).

Programming MELSEC System Q and L series 6 – 195

DI, EI, IMASK Program execution control instructions

System Q The allocation of bits in s through s+15 to the corresponding interrupt addresses is shown
CPU (other below:
than Basic
Model b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
QCPU) and s I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

L-series s +1 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16
CPU
s+2 I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32

s+3 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48

s+4 I79 I78 I77 I76 I75 I74 I73 I72 I71 I70 I69 I68 I67 I66 I65 I64

s+5 I95 I94 I93 I92 I91 I90 I89 I88 I87 I86 I85 I84 I83 I82 I81 I80

s+6 I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96

s+7 I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112

s+8 I143 I142 I141 I140 I139 I138 I137 I136 I135 I134 I133 I132 I131 I130 I129 I128

s+9 I159 I158 I157 I156 I155 I154 I153 I152 I151 I150 I149 I148 I147 I146 I145 I144

s +10 I175 I174 I173 I172 I171 I170 I169 I168 I167 I166 I165 I164 I163 I162 I161 I160

s + 11 I191 I190 I189 I188 I187 I186 I185 I184 I183 I182 I181 I130 I129 I128 I127 I126

s + 12 I207 I206 I205 I204 I203 I202 I201 I200 I199 I198 I197 I196 I195 I194 I193 I192

s + 13 I223 I222 I221 I220 I219 I218 I217 I216 I215 I214 I213 I212 I211 I210 I209 I208

s + 14 I239 I238 I237 I236 I235 I234 I233 I232 I231 I230 I229 I228 I227 I226 I225 I224

s + 15 I255 I254 I253 I252 I251 I250 I249 I248 I247 I246 I245 I244 I243 I242 I241 I240

IMASK0E2
When the power supply of the CPU is switched on or when the CPU has been reset with the
RUN/STOP switch, the execution of interrupt programs are as follows:
● High Performance model QCPU, Process CPU, and Redundant CPU
Execution of interrupt programs I0 to I31 and I48 to I255 is enabled, and execution of interrupt
programs I32 to I47 is disabled.
● Universal model QCPU and LCPU
Execution of interrupt programs I0 to I31 and I45 to I255 is enabled, and execution of interrupt
programs I32 to I44 is disabled.
The bit patterns designated by s through s+2 are stored in the special registers SD715 through
SD717. The bit patterns designated by s+3 through s+15 are stored in the special registers
SD781 through SD793.
Although the special registers are separated (SD715 through SD717 and SD781 through
SD793), the bit patterns are designated as s through s+15 successively.

6 – 196
Program execution control instructions DI, EI, IMASK

NOTES The interrupt address (interrupt pointer) designating the interrupt program occupies one pro-
gram step.

DI___AB1

With the GX Works2 or with the GX IEC Developer in MELSEC mode the instructions FEND and
IRET have to be programmed by the user.
Alternatively to the MELSEC editor the IEC editor can be used. The interrupt is allocated to a
task and the FEND and IRET instructions are placed automatically by the compiler of the GX IEC
Developer MEDOC (see program example).
For the information on interrupt conditions, link direct devices, refer to the QnUCPU User’s Ma-
nual(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Ma-
nuall(Function Explanation, Program Fundamentals).
During the execution of an interrupt program the DI status is internally set, so that no other in-
terrupt program can be executed simultaneously. Another interrupt program can only be invoked
after setting an EI instruction.
If an EI or DI instruction is placed within an MC instruction, the EI or DI instruction is executed
without regard to the MC instruction.
DI___AB2

Programming MELSEC System Q and L series 6 – 197

DI, EI, IMASK Program execution control instructions

Program EI, DI, IMASK (GX IEC Developer)

Example
The following program enables the execution of an interrupt program, if X0 is set (1). If X0 is
reset (0), the execution of the interrupt program is disabled.
The lower diagram shows the tasks to be programmed in the IEC mode. These tasks invoke
the interrupt programs I1 and I2.
Interrupt_1 (I1) and Interrupt_2 (I2) are interrupt programs. The IRET instruction does not need
to be programmed because it is placed automatically by the compiler of the GX IEC Developer.

MELSEC Instruction List Ladder Diagram

IEC Instruction List

DI___MB1, DI___KB1, DI___IB1, DI___AB3

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 198
Program execution control instructions DI, EI, IMASK

Program EI, DI, IMASK (GX Works2)

Example
In the following program, the execution of an interrupt program is enabled if X0 is set (1). When
X0 is reset (0), the execution of the interrupt program is disabled.
I1 and I3 are interrupt programs.

Ladder Diagram

Instruction List

Programming MELSEC System Q and L series 6 – 199

IRET Program execution control instructions

6.6.2 IRET

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
— — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

RET_ME1, IRET_KE1, IRET_IE1I

GX Works2

IRET_GE1

Variables Set Data Meaning Data Type

— — —

NOTE Within the IEC editors the IRET instruction is placed automatically in the program.

6 – 200
Program execution control instructions IRET

Functions Return from an interrupt program to the main program

IRET End of an interrupt program
The end of an interrupt program is indicated by an IRET instruction.
The main program is returned to after execution of the IRET instruction.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● There is no corresponding interrupt address for the interrupt call.
(Error code 4220)
● If the IRET instruction is placed prior to an interrupt program, the CPU quits processing at
that point. (Error code 4223)
● An END, FEND, GOEND, or STOP instruction was placed between an interrupt call and an
IRET instruction.
● The IRET instruction was executed during the fixed scan execution type program.
(For the Universal model QCPU, LCPU) (Error code 4223)

NOTE The following example shows a programming error!

1
Sequence program
2
Interrupt program
DI__0E2

Program For the application of an IRET instruction in a program refer to the program examples for the
Example EI, DI, and IMASK instructions (refer to section 6.6.1).

Programming MELSEC System Q and L series 6 – 201

 Link refresh instructions

6.7 Link refresh instructions

Link refresh instructions refresh data at input/output interfaces. The following table gives an
overview of these instructions:

MELSEC Instruction MELSEC Instruction

Function in in
MELSEC Editor IEC Editor
RFS RFS_M
I/O partial refresh
RFSP RFSP_M

6 – 202
Link refresh instructions RFS, RFSP

6.7.1 RFS, RFSP

CPU High
Basic Process Redundant Universal LCPU
Performance
     

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s 1) — — — — — — — —
n         —
1 X and Y only

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

FS_ME1, RFS_KE1, RFS_IE1R

GX Works2

RFS__GE1

Variables Set Data Meaning Data Type

s First number of I/O device to be refreshed Bit
n Number of I/O bits to be refreshed BIN 16-bit

Programming MELSEC System Q and L series 6 – 203

RFS, RFSP Link refresh instructions

Functions I/O partial refresh

RFS Refresh instruction
The RFS instruction refreshes the inputs and outputs of the designated range of I/O devices
during one program scan. It reads data from an external source or writes data to an output
module.
Data is read from an external source or written to an external output module in a batch after
executing an END instruction. Therefore, a pulse signal cannot be output during one program
scan. When the I/O refresh instruction is executed, the inputs (X) or outputs (Y) of the corre-
sponding device numbers are refreshed forcibly midway through program execution. Thus,
even pulse signals can be output.
If direct access inputs/outputs (DX/DY) are used, the inputs (X) and outputs (Y) are refreshed
bit by bit.

RFS__AB1, RFS__AB2
The program example on the left refreshes the input X0 and the output Y20 via an RFS instruc-
tion.
The program example on the right performs the same functions via DX and DY without a
refresh instruction.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The number of points determined by n exceeds the input/output device range.
(Error code 4101)

Program RFSP
Example
With leading edge from M0, the following program refreshes the inputs X100 through X11F and
the outputs Y200 through Y23F.

MELSEC Instruction List Ladder Diagram IEC Instruction List

RFS__MB1, RFS__KB1, RFS__IB1

6 – 204
Other convenient instructions

6.8 Other convenient instructions

The instructions in the following table support programming of special timers and special
counters, pulse counters and pulse outputs. Also included are instructions for positioning rotary
tables and for building input matrices.
The following table gives an overview of these instructions:

MELSEC Instruction MELSEC Instruction

Function in in
MELSEC Editor IEC Editor
1-Phase Input
UDCNT1 UDCNT1_M
count-up/-down Counter
2-Phase Input UDCNT2 UDCNT2_M
count-up/-down Counter
Programmable (teaching) Timer TTMR TTMR_M
Special Function Timer STMR STMR_M
Positioning of Rotary Tables ROTC ROTC_M
Ramp Signal RAMP RAMP_M
Pulse Counter SPD SPD_M
Pulse Output with
PLSY PLSY_M
set Number of Outputs
Pulse Width Modulation PWM PWM_M
Building of Input Matrices MTR MTR_M

Programming MELSEC System Q and L series 6 – 205

UDCNT1 Other convenient instructions

6.8.1 UDCNT1

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s 1) — — — — — — — —
d — 2,3) — — — — — — —
n 3) 3) 3)      —
1
X only
2
C only
3
Local devices and the file registers set for individual programs cannot be used

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

UDCN1ME1, UDCN1KE1, UDCN1IE1

GX Works2

UDCN1GE1

Variables Data Type

Set Data Meaning
MELSEC IEC
s+0: Input device number for count input (pulse signal, phase).
Array [1..2] of
s s+1: Set count up or down bit
0 = count up BOOL
1 = count down
d Number of counter performing the UDCNT1 instruction. BIN 16-bit
ANY16
(counter only)
n Setting BIN 16-bit ANY16

6 – 206
Other convenient instructions UDCNT1

Functions 1-phase count-up/-down counter

UDCNT1 Counter instruction
When the input designated by s+0 (array_s [0]) changes from 0 to 1 the current count of the
counter designated by d is updated. Consequently, only leading edges are counted.
The counting direction is determined by the status of the input designated by s+1 (array_s [1]):
– If the input condition is 0, the pulses of the input designated by s+0 (Array_s [0]) are added
to the current count value.
– If the input condition is 1, the pulses of the input designated by s+0 (Array_s [0]) are
subtracted from the current count value.
The count processing performs as follows:
– When counting up, the counter contact designated by d is set (1), if the current count value
is identical to the setting value in n. The counting process continues while the counter contact
is set (see program example).
– When counting down, the counter contact is reset (0), if the current count value is identical
to n-1 (see program example).
– The counter designated by d is a ring counter. If the count reads 32767 and is increased by
1, the counter jumps to -32768. If the count reads -32768 and is decreased by 1, the counter
jumps to 32767. The following diagram illustrates ring counting:

1
Counting up
2
Counting down
UDCNT0E1
The UDCNT1 instruction is started when the execution condition is set and stopped when the
execution condition is reset. If the counter is started once again, it counts on from the value
before it was stopped.
An RST instruction resets the counter designated by d and the according counter contact.

NOTE The counting process of a UDCNT1 instruction is performed during a CPU interrupt (1 ms). For
this reason only pulses with set/reset times over 1 ms can be counted accurately.
The setting value cannot be changed during the counting process (in this case the input desi-
gnated by s+0 (Array_s [0]) is set). In order to change the setting, the input designated by s+0
(Array_s [0]) has to be reset.
Counters designated by a UDCNT1 instruction cannot be used by other instructions at the same
time. In this case they would not return an accurate count.
The UDCNT1 instruction can be used as many as 6 times within all the programs being exe-
cuted. The seventh and the subsequent UDCNT1 instructions are not processed.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by s exceeds the range of the corresponding device.
(Error code 4101)

Programming MELSEC System Q and L series 6 – 207

UDCNT1 Other convenient instructions

Program UDCNT1
Example
If X20 is set, the following program designates counter C0 (up/down counter) to count the
number of leading edges from X0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Count
2
Counter contact of counter C0
UDCN1MB1, UDCN1KB1, UDCN1IB1, UDCNT0B1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 208
Other convenient instructions UDCNT2

6.8.2 UDCNT2

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s 1) — — — — — — — —
d — 2,3) — — — — — — —
n 3) 3) 3)      —
1
X only
2
C only
3
Local devices and the file registers set for individual programs cannot be used

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

UDCN2ME1, UDCN2KE1, UDCN2IE1

GX Works2

UDCN2GE1

Variables Data Type

Set Data Meaning
MELSEC IEC
s+0: Input device number for count input (pulse signal, phase A) Array [1..2] of
s Bit
s+1: Input device number of count input (pulse signal, phase B) BOOL

d Number of counter performing the UDCNT1 instruction BIN 16-bit

ANY16
(counter only)
n Setting BIN 16-bit ANY16

Programming MELSEC System Q and L series 6 – 209

UDCNT2 Other convenient instructions

Functions 2-phase count-up/-down counter

UDCNT2 Counter instruction
The count of the counter designated by d is changed depending on the condition of the two
inputs s+0 (array_s [0]) and s+1 (array_s [1]).
The direction of the count is determined as follows:
– If the input s+0 (array_s[0]) is set (1) and the input s+1 (array_s[1]) changes from 0 to 1 the
current count is increased by 1.
– If the input s+0 (array_s[0]) is set (1) and the input s+1 (array_s[1]) changes from 1 to 0 the
current count is decreased by 1.
– If the input s+0 (array_s[0]) is reset (0) no counting operation is executed.
The count processing performs as follows:
– When counting up, the counter contact designated by d is set (1), if the current count value
is identical to the setting value in n. The counting process continues while the counter contact
is set (see program example).
– When counting down, the counter contact is reset (0), if the current count value is identical
to n-1 (see program example).
– The counter designated by d is a ring counter. If the count reads 32767 and is increased by
1, the counter jumps to -32768. If the count reads -32768 and is decreased by 1, the counter
jumps to 32767. The following diagram illustrates ring counting:

1
Counting up
2
Counting down
UDCNT0E2
The UDCNT2 instruction is started when the execution condition is set and stopped when the
execution condition is reset. If the counter is started once again, it counts on from the value
before it was stopped.
An RST instruction resets the counter designated by d and the according counter contact.

NOTE The counting process of a UDCNT2 instruction is performed during a CPU interrupt (1 ms). For
this reason only pulses with set/reset times over 1 ms can be counted accurately.
The setting value cannot be changed during the counting process (-> the input designated by
s+0 (Array_s [0]) is set). In order to change the setting, the input designated by s+0 (Array_s [0])
has to be reset.
Counters designated by a UDCNT2 instruction cannot be used by other instructions at the same
time. In this case they would not return an accurate count.
The UDCNT2 instruction can be used as many as 5 times within all the programs being exe-
cuted. The sixth and the subsequent UDCNT2 instructions are not processed.

6 – 210
Other convenient instructions UDCNT2

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by s exceeds the range of the corresponding device.
(Error code 4101)

Program UDCNT2
Example
If X20 is set, the following program designates counter C0. The count and the count direction
(up/down) depend on the conditions of X0 and X1.

MELSEC Instruction List Ladder Diagram IEC Instruction List

UDCN2MB1, UDCN2KB1, UDCN2IB1, UDCNT0B2

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 211

TTMR Other convenient instructions

6.8.3 TTMR

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
d —   — — — — — —
n —        —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

TTMR_ME1, TTMR_KE1, TTMR_IE1

GX Works2

TTMR_GE1

Variables Data Type

Set Data Meaning
MELSEC IEC
d+0: Device storing measurement value. Array [1..2] of
d
d+1: For internal use by the CPU. BIN 16-bit ANY16

n Measurement value multiplier ANY16

6 – 212
Other convenient instructions TTMR

Functions Programmable (teaching) Timer

TTMR Timer instruction
A timer programmed via the TTMR instruction measures the time of an input signal in seconds.
The measurement value is multiplied with n and stored in d (array_d [0]+[1]).
With leading edge from the input the devices d+0 (array_d [0]) and d+1 (array_d [1]) are
cleared.
The multipliers designated by n are as follows:
n = 0, multiplier 1
n = 1, multiplier 10
n = 2, multiplier 100
No processing is performed when the value specified by "n" is other than 0 to 2.

NOTE Time measurement is performed during the execution of a TTMR instruction. Applying a JMP in-
struction or a similar instruction to the TTMR instruction causes inaccurate time measurement.
The multiplier n must not be changed during the execution of a TTMR instruction. A change
would cause inaccurate measurement.
The TTMR instruction can also be used in low speed type programs.
The device designated by d+1 (array_d [1]) is used by the CPU. A change would cause inac-
curate measurement.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by d exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU) (Error code 4101)

Program TTMR
Example
If X0 is set, the following program measures the time in seconds (n = 0, multiplier = 1). The
result is stored in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

TTMR_MB1, TTMR_KB1, TTMR_IB1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 213

STMR Other convenient instructions

6.8.4 STMR

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H
Bit Word Bit Word U\G
s — 1) — — — — — — —
n         —
d — — — — — — — — —
1 Can only be used by timer (T) data.

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

STMR_ME1, STMR_KE1, STMR_IE1

GX Works2

STMR_GE1

Variables Data Type

Set Data Meaning
MELSEC IEC
BIN 16-bit
s Number of timer ANY16
(timer only)
n Time setting BIN 16-bit ANY16
d+0: OFF delay timer output
d+1: One shot timer output after OFF (Set by trailing edge) Array [1..4] of
d Bit
d+2: One shot timer output after ON (Set by leading edge) BOOL

d+3: ON delay and OFF delay timer output

6 – 214
Other convenient instructions STMR

Functions Special function timer

STMR Timer instruction for low speed timers
The STMR instruction uses outputs designated by d+0 through d+3 (array_d [0] through
array_d [3]) to perform four different timer functions:
● OFF delay timer output (d+0) (array_d [0])
The output designated by d+0 (array_d [0]) is set (1) with leading edge from the execution
condition. With trailing edge from the execution condition and after a period of time
designated by n the output is reset (0) again.
● One shot timer output after OFF (Set by trailing edge, d+1 (array_d [1]))
The output designated by d+1 (array_d [1]) is set (1) with trailing edge from the execution
condition. After a period of time designated by n or with leading edge from the execution
condition the output is reset (0) again.
● One shot timer output after ON (Set by leading edge, d+2 (array_d [2]))
The output designated by d+2 (array_d [2]) is set (1) with leading edge from the execution
condition. After a period of time designated by n or with trailing edge from the execution
condition the output is reset (0) again.
● ON delay and OFF delay timer output (d+3 (Array [3]))
The output designated by d+3 (array_d [3]) is set (1) with trailing edge from the timer coil.
This corresponds to an ON delay time designated by n.
The output d+3 is reset (0) when the amount of time designated by n has passed.

The timer coil of the timer designated by s is set (0) with leading edge from the execution con-
dition and starts measuring the time designated by n.
The timer coil measures time until the measurement value matches the time setting n and then
drops out.
If the execution condition is reset before the time setting n has passed, the timer coil remains
set and time measurement is suspended at that point.
If the execution condition is set again the measurement value is cleared to 0 and time meas-
urement starts again.
The timer contact designated by s is either set by trailing edge from the execution condition and
set timer coil or by trailing edge from the timer coil and set execution condition. The timer con-
tact is reset by trailing edge from the execution condition and reset timer coil. The timer contact
is supplied for CPU internal use only.

Programming MELSEC System Q and L series 6 – 215

STMR Other convenient instructions

1 Execution condition
2
Timer coil designated by s
3
Timer contact designated by s
4 Time setting n

STMR_0E1
Time measurement is performed during the execution of an STMR instruction. Applying a JMP
instruction or a similar instruction to the STMR instruction causes inaccurate time measure-
ment.
The realtime designated by d can be calculated by multiplying the time setting n with the time
unit for low speed timers (default value = 100 ms).
The constant n has to range within 0 and 32767.
The timer designated by s cannot be used by an OUT instruction. If an OUT instruction and an
STMR instruction use the same timer, the STMR instruction cannot be performed accurately.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by d exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU) (Error code 4101)

6 – 216
Other convenient instructions STMR

Program STMR
Example
If X20 is set, the following program alternately sets the outputs Y0 and Y1 for 1 second each.
The used timer is a 100 ms timer. The time period of 1 second is calculated by multiplying K10
with 100 ms.

MELSEC Instruction List Ladder Diagram IEC Instruction List

STMR_MB1. STMR_KB1, STMR_IB1, STUR_0B1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 217

ROTC Other convenient instructions

6.8.5 ROTC

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
s —   — — — — — —
n1         —
n2         —
d  — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

ROTC_ME1, ROTC_KE1, ROTC_IE1

GX Works2

ROTC_ME1

Variables Data Type

Set Data Meaning
MELSEC IEC
s+0: Measurement of table rpm (internal use only)
Array [1..3]
s s+1: Number of position
of ANY16
s+2: Number of sector BIN 16-bit
n1 Number of sectors (divisions) on table (2 to 32767) ANY16
n2 Number of low speed sectors (0 to n1) ANY16
d+0: A-phase input signal
d+1: B-phase input signal
d+2: Zero position detection input signal
d+3: High speed forward output signal (internal use only) Array [1..8]
d Bit
d+4: Low speed forward output signal (internal use only) of Bool

d+5: Stop output signal (internal use only)

d+6: High speed reverse output signal (internal use only)
d+7: Low speed reverse output signal (internal use only)

6 – 218
Other convenient instructions ROTC

Functions Positioning instruction for rotary tables

ROTC Positioning instruction
The ROTC instruction rotates a sector designated by s+2 (array_s [2]) on a table with a spec-
ified number of sectors (divisions) designated by n1 to a specified position designated by s+1
(array_s [1]).
The positions and sectors on the rotary table are numbered counterclockwise.
The value in s+0 (array_s [0]) is internally used by the system to determine which sector is
located where in relation to the zero position. This value must not be changed, otherwise the
table will not be positioned accurately.
The value in n2 determines the number of sectors the table can be rotated by at low speed.
This value must be equal or less than that designated by n1.
The A/B-phase inputs designated by d+0 (array_d [0]) and d+1 (array_d [1]) detect the direction
of the rotation. Both inputs receive pulses. If the A-phase input d+0 (array_d [0]) is set, the
direction of the rotation is determined by the pulse edge of the B-phase input d+1 (array_d [1]):
● If the B-phase is at leading edge at that moment the table rotates clockwise (to the right).
● If the B-phase is at trailing edge at that moment the table rotates counterclockwise (to the
left).
The input designated by d+2 (array_d [2]) detects the zero position. This input is set, if sector 0
reaches position 0. If this input is set during the execution of a ROTC instruction, the value in
s+0 (array_s [0]) is reset. For accurate positioning this value in s+0 (array_s [0]) should be reset
before positioning via the ROTC instruction.
Data in d+3 (array_d [3]) through d+7 (array_d [7]) store output signals for operating the rotary
table. Which output signal is set depends on the current operation result of the ROTC instruc-
tion.
If all operation results were 0 just before executing a ROTC instruction, the outputs designated
by d+3 (array_d [3]) through d+7 (array_d [7]) are reset without positioning the table. After
resetting the execution condition these outputs are reset either.
A ROTC instruction can only be executed once in a program. Repeated application within one
program causes faulty operation of the instruction.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by s or d exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU) (Error code 4101)

Programming MELSEC System Q and L series 6 – 219

ROTC Other convenient instructions

Program ROTC
Example
In the following program the contacts X0, X1 (incremental encoder), and X2 address the
internal relays for detection of the rotating direction and zero position M0 (var_M0 array [0])
through M2 (var_M0 array [2]). The contact X2 is activated, if sector 0 is located at position 0
(zero position detection).
The rotary table shown below is divided into 10 sectors.
Which item (sector) will be moved to which station (position) has to be specified in D201
(var_D200 array [1]) and D202 (var_D200 array [2]) before the execution of the ROTC instruc-
tion.
Due to the value n1=10 the contact of the counter register outputs 10 pulses each rotation
(division). The value n2=2 specifies the number of low speed divisions.
For example, if register D201 (var_D200 array [1]) stores the value 0 and register D202
(var_D200 [2]) stores the value 3, the rotary table moves item 3 (sector 3) to station 0
(position 0) travelling the shortest distance (clockwise). The sectors 1 through 3 rotate at low
speed.
For an allocation of single registers and internal relays or array elements respectively to the
corresponding functions see the table following the example.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
Station 0 (position 0)
2
Station 1 (position 1)
3 Detection switch

ROTC_MB1, ROTC_KB1, ROTC_IB1, ROTC0B1

6 – 220
Other convenient instructions ROTC

Data register Meaning Remark

D200 (var_D200 Array [0]) Counter register
D201 (var_D200 Array [1]) Position of station These values are written to the data
registers D201 (var_D200 array [1]) and
D202 (var_D200 Array [2]) Position of item D202 (var_D200 array [2]) via a MOV
instruction.
M0 (var_M0 Array [0]) A-phase signal The internal relays M0 (var_M0 array [0])
through M2 (var_M0 array [2]) are
M1 (var_M0 Array [1]) B-phase signal
addressed by the inputs X0 through X2
M2 (var_M0 Array [2]) Zero position detection signal (see program example).

M3 (var_M0 Array [3]) High speed forward rotation

After X10 is set the ROTC instruction is
M4 (var_M0 Array [4]) Low speed forward rotation activated and the internal relays M3
(var_M0 array [3]) through M7 (var_M0
M5 (var_M0 Array [5]) Stop signal
array [7]) are assigned specified functions.
M6 (var_M0 Array [6]) High speed reverse rotation After resetting X10 these internal relays
are reset either.
M7 (var_M0 Array [7]) Low speed reverse rotation

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

Programming MELSEC System Q and L series 6 – 221

RAMP Other convenient instructions

6.8.6 RAMP

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register Constant
Other
Register Module Zn K, H (16#)
Bit Word Bit Word U\G
n1         —
n2         —
d1        — —
n3         —
d2  — — — — — — — —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

RAMP_ME1, RAMP_KE1, RAMP_IE1

GX Works2

RAMP_GE1

Variables Data Type

Set Data Meaning
MELSEC IEC
n1 Initial value of operation ANY16
n2 Final value of operation ANY16
(d1)+0: Device storing current value
BIN 16-bit Array [1..2]
d1 (d1)+1: Device storing number of executed moves of ANY16
(internal use only)
n3 Number of moves to be executed ANY16
(d2)+0: Bit to be set after completion Array [1..2]
d2 Bit
(d2)+1: Bit determining storage of operation result of Bool

6 – 222
Other convenient instructions RAMP

Functions Ramp signal

RAMP Instruction for changing the content of a device gradually
A RAMP instruction changes the content in (d1)+0 (array_d1 [0]) gradually from the initial value
designated by n1 to the final value designated by n2.
The number of moves performing the gradual changes is designated by n3.
The number of moves already executed is stored in (d1)+1 (array_d1 [1]) for internal system
use.
When the operation is completed the device designated by (d2)+0 (array_d2 [0]) is set.
The signal condition of the device (d2)+0 (array_d2 [0]) and the content of the device (d1)+0
(array_d1 [0]) depend on the signal condition of the device (d2)+1 (array_d2 [1]):
● If the device (d2)+1 (array_d2 [1]) is not set, the device (d2)+0 (array_d2 [0]) will be reset
during the next scan and the RAMP instruction will begin a new move operation from the
value currently stored in (d1)+0 (array_d1 [0]).
● If the device (d2)+1 (array_d2 [1]) is set, the device (d2)+0 (array_d2 [0]) remains set and
the value in (d1)+0 (array_d1 [0]) is not changed (storage).
If the execution condition is reset during the operation, the content in (d1)+0 (array_d1 [0]) does
not change. If the execution condition is set once again, the RAMP instruction changes the cur-
rent content in (d1)+0 (array_d1 [0]) stored before the reset.
During the processing of the instruction the values in n1 and n2 must not be changed.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by d1 or d2 exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU) (Error code 4101)

NOTE When the digit specification of bit device is made to d1, the digit specification of bit device can
only be used when the specification of digits is "K8".

Programming MELSEC System Q and L series 6 – 223

RAMP Other convenient instructions

Program RAMP
Example
The following program increases the content in D0 within 6 moves from 10 to 100 and stores
the content in D0 when the operation is completed.

MELSEC Instruction List Ladder Diagram IEC Instruction List

RAMP_MB1, RAMP_KB1, RAMP_IB1, RAMP0B1

NOTE This program will not run without variable definition in the header of the program organization
unit (POU). It would cause compiler or checker error messages. For details see section 3.5.2
"Addressing of arrays and registers in the GX IEC Developer" of this manual.

6 – 224
Other convenient instructions SPD

6.8.7 SPD

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register
Constant Other
Register Module Zn
Bit Word Bit Word U\G
s 1) — —      —
n 2) 2) 2) — — — — — —
d — 2) 2)      —
1
Only X
2
Local devices and the file registers set for individual programs cannot be used.

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

SPD_ME1, SPD_KE1, SPD_IE1

GX Works2

SPD_GE1

Variables Set Data Meaning Data Type

s Pulse input signal Bit
n Measurement time (unit: ms)
BIN 16-bit
d First number of device storing measurement result

Programming MELSEC System Q and L series 6 – 225

SPD Other convenient instructions

Functions Pulse density measurement

SPD Pulse density measurement
The SPD instruction counts pulses at the input designated by s for a period of time specified
by n. The result of the measurement is stored in d.

1 Execution condition.
2
The result of the measurement is stored in d.
3
Begin of measurement.
SPD_0E1
While the execution condition is set, the measurement begins again from 0 after the measure-
ment time has passed. In order to stop the SPD measurement the execution condition has to
be reset.
The SPD instruction stores the data from the designated devices in the CPU work area, and
performs the current count operation during a 5 ms system interrupt. For this reason, the
number of times the instruction can be used is limited. The SPD instructions exceeding this
limit are not processed.

NOTES The count processing for pulses used with the SPD instruction is conducted during an interrupt.
Therefore, to count the pulses, it is necessary to provide their ON and OFF time as long as the
interrupt time of the CPU or longer. The interrupt time is 1 ms.
When the High Performance model QCPU or Process CPU is used, the SPD instruction is not
processed if n = 0.
The SPD instruction can be used as many as 6 times within all the programs being executed.
The seventh and the subsequent SPD instructions are not processed.
While the measurement is in execution (while the command input is ON) by the SPD instruction,
the setting value cannot be changed. Turn OFF the command input before changing the setting
value.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by s exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU) (Error code 4101)

6 – 226
Other convenient instructions SPD

Program SPD
Example
If X10 is set, the following program counts the pulses at X0 during a period of time of 500 ms.
The result is stored in D0.

MELSEC Instruction List Ladder Diagram IEC Instruction List

SPD__MB1, SPD__KB1, SPD__IB1

Programming MELSEC System Q and L series 6 – 227

PLSY Other convenient instructions

6.8.8 PLSY

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register
Constant Other
Register Module Zn
Bit Word Bit Word U\G
s1         —
s2         —
d 1) — — — — — — — —


1 Y only

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

PLSY_ME1, PLSY_KE1, PLSY_IE1

GX Works2

PLSY_GE1

Variables Set Data Meaning Data Type

s1 Frequency or device storing pulse frequency setting.
Outputs count or the number of the device storing number of output pulses BIN 16-bit
s2
setting.
d Device storing output destination. Bit

6 – 228
Other convenient instructions PLSY

Functions Pulse output with adjustable number of pulses

PLSY Pulse output instruction
The PLSY instruction outputs a number of pulses specified by s2 at a frequency specified by
s1 to an output designated by d.
The frequency range in s1 can be specified from 1 to 100 Hz. If s1 is other than 1 to 100 Hz,
the PLSY instruction will not be executed.
The number of output pulses in s2 can be specified from 0 to 65535 (0000H to FFFFH). If s2 is
set to "0", pulses are continuously output.
Only outputs corresponding to the output module can be designated by d.
Pulse output begins with leading edge from the execution condition of the PLSY instruction.
During pulse output the execution condition must not be reset. Resetting the execution condi-
tion suspends the pulse output.

NOTE The PLSY instruction stores the data from the designated devices in the CPU work area, and
and counting operation is processed as a system interrupt. The pulses that can be output must
have longer ON and OFF times than the interrupt interval of the CPU module. The interrupt in-
terval of individual modules is 1 ms.
Do not change the argument for the PLSY instruction during pulse output directed by the PLSY
instruction (while the execution command is ON). To change the argument, turn OFF the exe-
cution command.
The PLSY instruction can be used only once in all programs executed by the CPU module. The
second and the subsequent PLSY instructions are not processed.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by d exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU) (Error code 4101)

Program PLSY
Example
If X0 is set, the following program outputs five 10 Hz pulses to Y20.

MELSEC Instruction List Ladder Diagram IEC Instruction List

PLSY_MB1, PLSY_KB1, PLSY_IB1

Programming MELSEC System Q and L series 6 – 229

PWM Other convenient instructions

6.8.9 PWM

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register
Constant Other
Register Module Zn
Bit Word Bit Word U\G
n1         —
n2         —
d 1) — — — — — — — —


1 Only Y

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

PWM_ME1, PWM_KE1, PWM_IE1

GX Works2

PWM_GE1

Variables Set Data Meaning Data Type

n1 ON time or the number of device storing ON time setting.
BIN 16-bit
n2 Frequency or the number of device storing cycle time setting.
d Number of device storing output destination. Bit

6 – 230
Other convenient instructions PWM

Functions Pulse width modulation

PWM Modulation instruction
The PWM instruction outputs pulses at a cycle time specified by n2 and with an ON time speci-
fied by n1 to an output designated by d.

PWM_0E1
The times in n1and n2 can be specified from 1 to 65535 ms. The value set in n1 has to be less
than that in n2.

NOTES The PWM instruction registers the data from the designated devices in the work area of the CPU,
and performs the current output operation during a system interrupt (1 ms).
For this reason, the PWM instruction can only be used once in a program.
The instruction is not processed in the following cases:
– When both n1 and n2 are 0
– When n2 is smaller or equal to n1
– When the PWM instruction is executed twice or more.
Do not change the argument for the PLSY instruction during pulse output directed by the PLSY
instruction (while the execution command is ON). To change the argument, turn OFF the exe-
cution command.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device specified by d exceeds the range of the corresponding device.
(For the Universal model QCPU, LCPU) (Error code 4101)

Program PWM
Example
If X0 is set, the following program outputs pulses at a cycle time of 1 second and with an ON
time of 100 ms to Y20.

MELSEC Instruction List Ladder Diagram IEC Instruction List

PWM_MB1, PWM_KB1, PWM_IB1

Programming MELSEC System Q and L series 6 – 231

MTR Other convenient instructions

6.8.10 MTR

CPU High
Basic Process Redundant Universal LCPU
Performance
   

Devices Usable Devices

Internal Devices MELSECNET/H Special
(System, User) File Direct J\ Function Index Register
Constant Other
Register Module Zn
Bit Word Bit Word U\G
s  — — — — — — — —
d1  — — — — — — — —
d2  — — — — — — — —
n         —

GX IEC
Developer MELSEC Instruction List Ladder Diagram IEC Instruction List

MTR__ME1, MTR__KE1, MTR__IE1

GX Works2

MTR__GE1

Variables Set Data Meaning Data Type

s Initial input device.
d1 Initial output device. Bit
d2 First number of device storing matrix input data.
n Number of input rows. BIN 16-bit

6 – 232
Other convenient instructions MTR

Functions Building an input matrix

MTR Instruction for reading n data rows into an input matrix.
The MTR instruction reads the information of 16 bits (0/1) beginning from the device desig-
nated by s. The number of repetitions (rows) is designated by n. The conditions of read data
are stored in the device designated by d2 onwards. This way, a matrix of 16 bits and n rows is
built.
One row (16 bits) can be read each scan.
The reading process is continuously repeated from the first to the nth row.
Due to the format of the input matrix (16 bits x n rows) the device designated by d2 has to
supply space for 16 bits x n rows either to store the data.
Each row is selected beginning with the output designated by d1. The corresponding output for
each row of 16 bits to be read is set or reset by the system automatically. The number of out-
puts is identical with the number of rows. Thus, each single row can be addressed accurately
by the system
The device numbers designated by s, d1, and d2 must be divisible by 16.
The number of rows n can be designated from 2 to 8.
Note, that the MTR instruction directly operates on current input and output data.
No processing is performed in the following cases:
● The device numbers designated by s, d1, and d2 are not divisible by 16.
● The device designated by s exceeds the current input range.
● The device designated by s exceeds the current output range.
● The matrix space 16 bits x n rows exceeds the relevant device range of d2.
● The value in n does not range within 2 and 8.

Operation In the following cases an operation error occurs, the error flag (SM0) turns ON, and an error
Errors code is stored into SD0.
● The device other than the input (X) was specified at s. (Error code 4101)
● The device other than the output (Y) was specified at d1. (Error code 4101)

Programming MELSEC System Q and L series 6 – 233

MTR Other convenient instructions

Program MTR
Example
If X0 is set, the following program reads the inputs X10 through X1F three times and stores the
results in M30 through M77. A matrix is built with 16 bits x 3 rows. The rows are addressed via
the outputs Y20 through Y22.

MELSEC Instruction List Ladder Diagram IEC Instruction List

1
1st row
2
2nd row
3
3rd row
MTR_MB1, MTR_KB1, MTR_IB1, MTR_0B1

6 – 234
7 Application Instructions, Part 2
The application instructions, part 2 are specific instructions for several special functions.
The following table shows the division of these functions:

Instruction Meaning
Logical operation instructions Logical AND / OR, logical exclusive OR / exclusive NOR
Rotation instructions 16-bit and 32-bit data right / left rotation
Shift instructions Shift data by bit or word
Bit processing instructions Set, reset, and test bits
Data processing instructions Search, encode, and decode data at specified devices
Disunite and unite data
Structured program instructions Repeated operation, subroutine program calls,
subroutine calls between program files, switching
between main and subprogram parts, micro computer
program calls, index qualification of entire ladders, store
index qualification values in data tables
Data table operation instructions Write to and read data from a data table, delete and
insert data blocks in a data table
Buffer memory access instructions Buffer memory access of special function modules
Display instructions Output ASCII characters to the outputs of a module or to
an LED display
Debugging and failure diagnosis instructions Failure checks, setting and resetting status latch,
sampling trace, program trace
Character string processing instructions Character string (ASCII code) processing
Special function instructions Trigonometrical functions, square root and exponential
calculation with BCD data and floating point data
Data control instructions Upper and lower limit control and storage of checked
data
File register switching instructions Switching between file register blocks and files
Clock instructions Reading/writing of the values of year, month, day, hour,
minute, second, and day of the week; addition/
subtraction of the values of hour, minute, and second;
conversion of the values of hour, minute, and second into
second; comparison between the values of year, month,
and day; and comparison between the values of hour,
minute, and second.
Expansion clock instruction Reading of the values of year, month, day, hour, minute,
second, millisecond, and day of the week; addition/
subtraction of the values of hour, minute, second, and
millisecond
Peripheral device instructions Message output and key input on peripheral units
Program instructions Select different program execution modes
Other instructions Reset watchdog timer (WDT), pulse generation, direct
read from indirect access file registers, numerical key
input from keyboard, batch save or recovery of index
registers, reading module information/model name, trace
set/trace reset, writing to and reading from files/standard
ROM, program instructions, data transfer, user message

Programming MELSEC System Q and L series 7–1

 Logical operation instructions

7.1 Logical operation instructions

Via the logical operation instructions logical connections such as logical sum or logical product
are programmed.
The following table gives an overview of these instructions:

MELSEC Instruction MELSEC Instruction

Function in MELSEC Editor in IEC Editor
WAND WAND_M, WAND_3_M
WANDP WANDP_M, WANDP_3_M
AND DAND DAND_M, DAND_3_M
(logical product) DANDP DANDP_M, DANDP_3_M
BKAND BKAND_M
BKANDP BKANDP_M
WOR WOR_M, WOR_3_M
WORP WORP_M, WORP_3_M
OR DOR DOR_M, DOR_3_M
(logical sum) DORP DORP_M, DORP_3_M
BKOR BKOR_M
BKORP BKORP_M
WXOR WXOR_M, WXOR_3_M
WXORP WXORP_M, WXORP_3_M
Exclusive OR DXOR DXOR_M, DXOR_3_M
(XOR) DXORP DXORP_M, DXORP_3_M
BKXOR BKXOR_M
BKXORP BKXORP_M
WXNR WXNR_M, WXNR_3_M
WXNRP WXNRP_M, WXNRP_3_M
Exclusive NOR DXNR DXNR_M, DXNR_3_M
(XNR) DXNRP DXNRP_M, DXNRP_3_M
BKXNR BKXNR_M
BKXNRP BKXNRP_M

NOTE Within the IEC editors please use the IEC instructions.

Logical instructions are processed bit by bit as binary data. The two conditions (0 and 1) are
connected and the result of the connection is output to a destination address.

7–2
Logical operation instructions

The following table shows the logical connection results of the conditions 0 and 1. A and B are
input variables and Y is the output variable.

Logical Operation Example

Processing Details
Connection Expression A B Y
0 0 0

Output Y set to 1, only if both inputs A and B are 0 1 0

Logical AND Y=AxB
set to 1. 1 0 0
1 1 1
0 0 0

Output Y set to 1, if at least one of the inputs A or 0 1 1

Logical OR Y=A+B
B is set to 1. 1 0 1
1 1 1
0 0 0
Logical exclusive 0 1 1
Output Y set to 1, if the inputs A and B are
OR Y=AxB+AxB
different, and is set to 0 if A and B are equal. 1 0 1
(XOR)
1 1 0
0 0 1
Logical exclusive