ELECTRICAL ENGINEERING DEPARTMENT
ACADEMIC SESSION: __2021/2022___________
DEE20033 – DIGITAL ELECTRONICS
PRACTICAL WORK : LAB INTRODUCTION
LECTURER’S NAME:
PUAN ISMAWATI
9
GROUP NO. : CLASS: DEP2A
STUDENT ID & NAME :AISYAH BINTI MANAF
16DEP20F2001
PRACTICAL LAB INTRODUCTION
1 COURSE LEARNING OUTCOME (CLO)
Construct the logic diagrams, truth tables and timing diagrams using logic gates and flip-flop.
2 OBJECTIVES
i. To understand the schematic diagram of IC’s layout.
ii. To identify fundamental logic gates and its functions.
3 THEORY
A logic gate has one output terminal and one or more input terminals. Its output will be HIGH
(1) or LOW (0) depending on the digital level(s) at the input terminals. Through the use of
logic gates, we can design digital systems that will evaluate digital input levels and produce
a specific output response based on that particular logic circuit design.
(Refer Lecturer Notes)
4 EQUIPMENT / TOOLS
i) Digital trainer
ii) Power supply
iii) Breadboard
iii) ICs 7400, 7402,7404, 7408, 7432, 7486
iv) Jumper wires
5 PROCEDURES
1. Connect the Not Gate logic circuit as in Figure i(1).
2. Set the switch to the values in the Truth Table i(1) and record the output results in the
Table i(1).
3. Repeat the above procedures for the Figure i(2) to Figure i(7) and record the answer in
Table i(2) to Table i(7), respectively.
S1
Lp1
S1 Lp1 S2
Fig. i(2): AND Gate
Fig. i(1): NOT Gate A
A X X
B
A
S1 A
Lp1 S1 Lp
X1
X
B
S2 B
S2
Fig. i(3): OR Gate Fig.i(4) : NAND Gate
A A
S1 A
B Lp
X1 F=A B
X
S2
BB
Fig. i(5) : NOR Gate Fig. i(6) : Exclusive-OR
A
XF
B
B
Fig. i(7) : Exclusive-NOR
6 RESULT
A X A B X
0 1
0 0 0
1 0
0 1 0
Table i(1): NOT Gate 1 0 0
1 1 1
Table i(2): AND Gate
A B X A B X
0 0 0 0 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
Table i(3): OR Gate Table i(4) : NAND Gate
A B X A B X
0 0 1 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0
Table i(5): NOR Gate Table i(6) : Exclusive OR Gate
A B X
0 0 1
0 1 0
1 0 0
1 1 1
Table i(7) : Exclusive NOR Gate