Analysis and simulation of a multilevel inverter

converter NPC Cascade.

F.Bouchafaa1, E.M.Berkouk2, M.S.Boucherit2
1
Laboratory of Instrumentation and engineering system. University of Science and Technology Houari Boumediene,
BP N°32 EL-Alia Beb-Ezouar Algiers, ALGERIA.
2
Laboratory of Process Control. Polytechnic National School Algiers.Street Hassen Badi, El Harrach, Algiers.
BP N°182 ALGERIA.

Irect2 Irect
Abstract-This paper describes the control and regulation of
input DC voltages of nine-level NPC voltage source inverter. The T23 T33
C4 Urect2
analysis and simulation of a cascade constituted by three phase’s
five-level PWM rectifier-nine levels NPC voltage source inverter T13
C3
(VSI). In the first part, the authors present the five-level PWM Irect1
rectifier. After, we present a topology of nine levels NPC VSI for T12 T17 T22 T27 T32
T37
then we propose a model of this inverter and the SVPWM Vnet1 Rs-Ls C2 Urect1
Inet1
strategy which uses eight bipolar carriers to control it. The
study of this cascade shows that the input DC voltages of the T21 T31
C1
Vnet2 T11
inverter are not stable and not equals. To remedy to this Urect
Inet2 Rload
problem, the authors propose to introduce in the cascade a G A B
Irect0
C
clamping bridge and regulation using PI regulator. In the
second part, we study speed control of the Permanent magnet Vnet3 T14
T24 T34 C5 Urect3
synchronous machine (PMSM) by using the field oriented Inet3
control. The results obtained are full of promise to use the C6
inverter in high voltage and great power applications as T15
electrical traction. T25 T35 Irect3

C7
T18 T28 T38
I. INTRODUCTION T16 C8
Urect4
T26 T36
The apparition of new power components controllables in Irect4

the opened and closed states (GTO and IGBT) has let to the
conception of new and fast converters for high power Fig.1. Five-level PWM rectifier topology
applications. Thus, the speed variator (static converter-AC
The reversibility of the five-level source inverter allows it
machines) has seen its cost decreasing considerably. The
to work as current rectifier [1,2].
progress accomplished in the micro-computer tools (micro-
controllers, DSP,...) has let the synthesis of more performant
and robust control algorithms for sets of converter-machine.  B i1 = B i5
The authors propose a new cascade constituted by five- 
 B i2 = B i4
level PWM rectifiers-nine-level NPC VSI. The performances 
= B i6 (1)
of this cascade show the instability problem of the input DC  B i3
voltages of the inverter. As solution to this problem, the B = B i1 B i2 B i3
authors propose to control strategy of DC link voltage of  i7
multilevel NPC inverter structure who, we introduction  B i8 = B i4 B i5 B i6
clamping bridge and regulation by using PI regulator. This
cascade lets to absorb, in network, sinusoidal currents with BiS is the control signal of the semiconductor TiS.
unity power factor. The results obtained confirm the good Where:
performances of the proposed solution. This cascade can find i: is the number of the of the commutation cell, i∈{1,2,3}.
applications in high voltage and field’s great power. s: is the number of the semi-conductor.

II. MODELLING AND CONTROL OF CONVERTER The input voltages of five-level PWM rectifier are defined
AND INVERTER as follow:

A. Modelling of five-level PWM rectifier

The advantages of five-Level PWM rectifier topology V KG = S i1bT U rect1 + S i1b U rect2
(fig.1) are well known and have been applied in medium and (2)
high power applications in the last years [1]. − S i0bT U rect3 − S i0b U rect4
With
  S i1bT = S i7 + S i1b  S i1b = S i1 S i2 S i3  Bi1 = Bi7
 bT and  b (3)  =
Bi2 Bi6
 S i0 = S i8 + S i0 S i0 = S i4 S i5 S i6
b
 =
 Bi3 Bi8 (6)
The rectifier output current is given as follows:  Bi4 = Bi9

Bi5 = Bi10
 i rect1 = S 17 i net1 + S 27 i net2 + S 37 i net3
 b
 i rect2 = S 11 i net1 + S b21 i net2 + S 31
b
i net3 To modelize the nine-level NPC Voltage source inverter,
 (4) use the DESIGN method. Table 1 gives the electrical
 i rect3 = S 18 i net1 + S 28 i net2 + S 38 i net3 quantities which characterise every configuration [3,6].
i b
= S 10 i net1 + S b20 i net2 + S 30
b
i net3
 rect4
With:

i rect0
= −(irect1 + irect2 + irect3 + irect4) (5)

B. Modelling of nine-level NPC VSI

Three phases nine levels NPC VSI is a new structure of
power conversion used to feed with variable frequency and
voltage, a great power alternative current machine. Several
structures are possible for nine-level inverters. In this paper,
we study the neutral point clamping (NPC) structure (fig.2)
[4]. This structure is constituted by three arms and eight DC
voltages sources. Every arm has sixteen bi-directional Table 1. A known grandeur for each of an arm i of the nine-level
switches, ten in series and six in parallel and two diodes DDi0 NPC VSI
and DDi1 Which let to have zero voltage for VKM (VKM is the
voltage of the phase K relatively to the middle point M) [2,3]. The input voltage of the inverter, relatively to the middle
Id4 T 35
point M, is given by the following system:
T 15 T 25
Uc4 D 111 D1 5 D2 11 D 25 D 31 1 D3 5

Uc3
Id3 T 11 1
T
T 21 1 T 3 11
T (
VKM = Si1.Si2 1 − Si3 .UC1 )
( )( )
D 112 1 4 D2 12 T D 24 D 312 34 D3 4
D1 4
Id2 T 1 12
24
T 2 12
+ Si1.Si2.Si3 1 − Si4 . UC1 + UC2
Uc2 D1 13 T D1 3 D 21 3 T D 23
T 312
D3 13 T D 33 ( )(
+ Si1.Si2Si3.Si4 1− Si5 . UC1 + UC2 + UC3 )
( )
13 23 33

Id1
T 1 13 T 2 13 T 31 3
+ Si1.Si2.Si3.Si4.Si5. UC1 + UC2 + UC3 + UC4 (7)
Uc1 T 12
D 12 T 22 D2 2 T 32 D 32
(
− Si6.Si7 1− Si8 .UC5 )
M Id0
DD 11
T 11 D1 1
DD 21
T 21 D2 1
DD 31
T 31
D 31 ( )(
− Si6.Si7.Si8 1− Si9 . UC5 + UC6 )
T 16 A
DD1 0 D1 6
I1
T 26 B
DD2 0 D 26
I2 T 36 C
DD 30 D 36
I3 ( )(
− Si6.Fi7.Si8.Si9 1 − Si10 . UC5 + UC6 + UC7 )
Uc5
D 114
T 17
D 17
T 27
D2 14 D 27
T 37
D 314 D 37
(
− Si6.Si7.Si8.Si9.Si10. UC5 + UC6 + UC7 + UC8 )
Id5
T 1 14 T 21 4 T 3 14 T 3 8
D 18 D 28
Uc6 T 18 T 28
D3 15
D3 8 Where k∈{A,B,C} and i∈{1,2,3}.
Id6 D D 215
11 5
The simple voltages of the three phases nine-level NPC
T 115 T 2 15 T 31 5
Uc7 T 19 D1 9 T 29 D 29
D 316 T 3 9
D 39 VSI are given by the following system:
Id7 D1 16 D 21 6
T 116 T 2 16
Uc8 T 1 10 T 21 0 D 210 T 3 16 D 310 VA   2 −1 −1 S11bT bT
− S10 
.SbT − SbT 

T 31 0
  1 (8)
Id8
V =
 B 3 −1 2 −1 20 UC
VA VB VC
  21
bT 
VC  −1 −1 2  S31 − S30
bT
Fig.2. A nine-level NPC voltage source inverter structure    
Several complementary laws are possible for the nine-level b b
Who, we define the half arm connection function ( S i1 , Si0)
NPC VSI. The optimal complementary law used for this bT bT
and a global half arm ( S i1 , S i0 ) connection function
converter is presented below:
associated respectively to the upper and lower half
commutation cells.
 the period. Then, only odd harmonics exist. But for odd
 S = S i1 .S i2 .S i3 .S i4 .S i5
b
i1
values of m, the output voltages don’t present any symmetry
 b relatively to the quarter of the period. Then, all harmonics
S = S i6 .S i7 .S i8 .S i9 .S i10
i0
(even and odd) exist. They together by families centred
 and (9)
around frequencies multiple of 8mf.
 S bT = S + 2S + 3S + 4 S b
 i1 i13 i12 i11 i1
 Si0bT = Si14 + 2 Si15 + 3S i16 + 4 Si0b

C. Optimal PWM strategies method

Other authors have extended two-level carrier-based
PMWM techniques to multilevel inverters by making the use
of several triangular carrier signals and one reference signal
par phase. For N-level inverter, (N-1) carriers with the same
frequency fc and same peak to peak amplitude Ac are
disposed such that the bands they occupy are contiguous. The
reference, or modulation, wave form has peak to peak
amplitude Am and frequency fm, and its centred in the middle
of the carrier set. The reference is continuously compared
with each of the carrier signals. If the reference is greater than
a carrier signal, then the active device corresponding to that
carrier is switched on; and if the reference is less than a
carrier signal, then the active corresponding to that carrier is
switched off [2]. In multilevel inverters, the amplitude
modulation index, ma, and the frequency ratio, mf, are defined
as [3]

 Am
 m a = A
c
 f (10) Fig.3. Optimal PWM strategy of the nine-level NPC VSI
 mf = c (simple and spectrum voltage)
 fm

III. FIVE-LEVEL PWM RECTIFIER –NINE6LEVEL

The principle of this strategy optimal PWM which is NPC VSI CASCADE
similar to subharmonic PWM except that a zero sequence
(triple harmonic) voltage is added to each of the carrier Until now, we have supposed the input DC voltages of nine-
waveforms. This method takes the instantaneous average of level NPC VSI constants. In this part, the authors study a new
the maximum and minimum of the three reference voltages generation input DC voltages manner. For these we propose a
V sref= ( V * , V * , V * ) and subtracts this value from each
a b c
cascade presented in the figure 4. This cascade is constituted
of the individual reference voltages to obtain the by five-level PWM rectifier-filter-nine-level inverter-PMSM.
mo dulation waveform [3]. I rect id4
The volt age Voffset is given by the following equation: Uc4 C4 i
Nin e - lev el NPC Vo ltag e So u re In v erter

d3
Vnet1
Voffset =
[max (VSref ) + min (VSref )] (11)
Rs-Ls Uc3 C3 id2
Fiv e- lev el PWM rectifier

Inet1
i1
2 Uc2 C2
id1 i2
Vnet2 Urect Uc1
The new reference vectors are defined as follows: Inet2
C1
id0 i3
G
Uc5 C5
V * = V * - V Vnet3
id5
 aref a offset
Uc6 C6 id6
* * Inet3
 V bref = V b - V offset (12)
 * Uc7 C7
id7
P-M-S-M
= *-
 V cref V c V offset
Uc8 C8
I rect id8
In this parts, the different DC input voltages of the inverter
are supposed constant and equals Uci(i=1÷8)=Uc.
Figure 3 represents the simple output voltage of the nine-
level NPC VSI controlled by the proposed PWM strategy for Fig.4. Five level PWM rectifier-filter-nine-level NPC VSI-PMSM cascade
m=15,18 and r=0.9. We note that, for even values of m, the
output voltage present symmetry relatively to the quarter of
A. Simulation result B. Modelling and control of clamping bridge
We note the instability of the output voltage (fig.5). We The clamping bridge cell is a simple circuit constituted by
note that, the upper input DC voltages of the inverter Uci(i=1÷8) a transistor and a resistor in series linked in parallel of
are practically not equals to the lower one. This fact capacitor as shown in figure 7. The transistors are controlled
accentuates the problem of unbalance of the different input in order to maintain an equality of the different voltages.
DC voltages sources of nine-level NPC VSI. In this part, the model of the intermediate filter with
Figure 5 shows that the different input voltages of the VSI clamping bridge is defined by following equation:
are not equals by pairs (Urect1≠ Urect3 and Urect2≠Urect4) and
their differences (Urect1-Urect3 and Urect2-Urect4) are weak. We dUci
Ci = Irecti + ir(i + 1) + ic(i + 1) − idi − iri (13)
note the instability of the output voltage of five-level PWM dt
rectifier (fig.6).
With:
Uci
ir i = Ti. (14)
Rpi
To control the transistor, we propose the following
algorithm:

- (Uci-Uref)=ε i
- if ε i>0 Then Ti=1⇒ ir i = Ti. Uci (15)
Rpi
Fig.5. The different input DC voltage source intermediate - Else Ti=0⇒ iri=0

iri+1 ici+1
idi
Irecti iri
ici
Ti Ci
Uci

Rpi

iri-1 ici-1 idi-1

Irecti-1

Fig.7. The clamping bridge cell

Fig.6. The difference ∆UCi of different input DC voltages and output
DC voltages of the five-level PWM rectifier C. Multi DC bus link voltage controller
In the second part, we propose to enslave the input DC
IV. CONTROL STRATEGY OF THE INPUT DC voltages of multilevel inverter by using feedback linear
VOLTAGES OF MULTILEVEL INVERTER NPC control. The synoptic diagram of five-level PWM current
rectifier control is given in figure 8.
To remedy to the problem of the instability of the output As we can see on this scheme, this control is composed by
DC voltage of the PWM rectifier [5,6], we propose to use two loops [3,6]. The first is the network current Ineti The
clamping bridge, and feedback control of the input DC second one concerns the voltage loop control of the voltage
voltages of multilevel inverter. Ucm [3,6,7].
We control the network current of the phase 1,2 and 3 by
proportional- Integral regulator [3,7]. The algorithm of this
sin(ωt+2π/3)
current loop is given in figure 9.
sin(ωt-2πi/3) Ucm
V net1
sin(ωt) V net1 V net2 V net3
-+ Gc(S) i1
i load +- ++
RI P V net2
Ucref 3Veff
W
+- RV ++
4Ucm
+- RI ++ -+ Gc(S) i2
Icref Irect .ref M
+- RI ++ V net3
-+ Gc(S) i3
i1 i2 i3
Calcul
of
Irect

iload
+- GV(S) Ucm

Fig.8. Synoptic diagram of the five-level PWM rectifier

 Vnet λ Vnet λ
controlled by the proposed SVPWM strategies.
Irefλ -
Inet λ The model of the actuator (PMSM) presented above is not
+ +
- PI + - Gc(S)
linear and strong coupling between d and q axes exists. To
eliminate this coupling, we use the field oriented control. For
Control process
the PMsynchronous machine used, we develop the algorithm
Fig.9. Control algorithm five-level PWM rectifier of network current
ids=0. [9].
This control strategy often used consists to maintain the
In the second part, we propose to enslave it using current ids to zero, and to control the speed by the current iqs
integrator-proportional regulator . We have observed then the via the voltage Vqs. Regulate the current ids to zero lets have,
application of the enslavement algorithm for a cascade for a given stator currents magnitude, a maximum torque.
constituted by five levels PWM rectifier-clamping bridge-
A. Simulation result
nine levels NPC VSI.
We use the algorithm enslavement elaborate for to control
The modelling of this loop is based on the instantaneous
the rectifier of the cascade applied load variation between
power conservation principle with no loss hypothesis. This
two instants t=0.4s and t=0.8s.
loop imposes efficient network current [7,8].
Figures 11 and 12 show the simulation results when we use
Input power and output power:
full clamping bridge and feedback control with PI regulator.
We note that, the output voltage of each PWM rectifier
 3 L di2netλ follows perfectly its reference which is constant (fig.11).
P = ∑ (V i
 in λ =1 netλ netλ − R i 2
netλ − )
We show the performances of the feedback control of the
 2 dt (16)
4 output voltage of the five-level PWM rectifier (fig.11).
Pout = ∑ (Ucmi.Irecti) = 4.Ucm (ic + iload )
 i =1

We define the different grandeurs ic, iload and Ucm as follow:

 4

 ∑ i ci
 iC =
i = 1

4
 4
 ∑ i loadi (17)
 i load = i=1
 4
4
 ∑ U cmi
 U = i=1
 cm
4
 Fig.11. Output voltage of five-level PWM rectifier and its reference

Using of the power conservation principle and neglecting

of joules loss in the resistor Rs, and we suppose the network
currents sinusoidal and in phase with corresponding voltage
Vnetλ, we can write:
3V eff I eff = 4 U cm (i c + i load ) (18)
The voltage loop model of five-level rectifier, deduct from
the relation (19), is shows by figure 10.

iload
Ieff 3Veff Irectm - ic -1 Ucm Fig.12. Output DC voltages of five-level PWM rectifier
+
4Ucm C'.S
Therefore the different input DC voltages of the nine-level
Fig.10. Five-level rectifier voltage model NPC VSI are constant and practically equal by pairs too.
(UC1=UC5, UC2=UC6, UC3=UC7 and UC4=UC8) (fig.12). In
consequence the output voltage of the nine-level NPC VSI is
V. APPLICATION OF FEEDBACK CONTROL symmetrical. The current id0 has a mean value practically null
ALGORITHM OF RECTIFIER FOR THE
CASCADE (fig.13).
The rectifier current Irect1, Irect2 are respectively the opposite
In this part, we will study the performances of the speed of the current Irect2, and the current Irect0 has a mean value
control of the PMSM fed by nine-level NPC inverter practically null (fig.14).
 We remark that the network currents ineti feeding rectifier Figure 16 present the performances of the speed control
follow perfectly their sinusoidal references (fig.15).The algorithm, proposed in this paper. We show the
network voltage and current are in phases then the power electromagnetic torque in steady state. The driver of the
factor of network is uniting (fig.15). PMSM fed quietly its reference.
The driver of the PMSM fed follows quietly its reference
and the torque effect for the load variation between two
instants t=0.4s and t=0.8s.

VI. CONCLUSION
In this paper, we have studied analysis and simulation of a
multilevel inverter converter NPC Cascade.
The study of the stability problem of the input voltages of
nine-level NPC inverter using a cascade constituted by Five-
Fig.13. Input current id0 of nine-level NPC VSI level PWM rectifier-filter-nine-level NPC VSI.
The input DC voltages are generated by the five-level
PWM current rectifier by this study, we have particularly
shown the problem of the middle point of DC voltages source
supplied the nine-level VSI and its effects the serious
problems of the speed control of PMSM and the output
voltages source of the nine-level inverter is asymmetric.
In the last part of this paper, we propose a solution to this
problem to use a clamping bridge and feedback linear control
with using prtoportional-intergral regulator.
The application of the proposed feedback control
algorithm to the rectifiers of the studied cascade shows a
good following of the output voltages of this rectifier to this
reference. Then, they are more stables. The cascade studied
absorbs network currents with minimum harmonics and unity
power factor. The results obtained shows that the proposed
solution is very efficient to solve the instability problem of
the multilevel inverter. So, now is possible to conceiver with
frequency charger using in output the nine-level inverter,
Fig.14.Output currents of five levels rectifier PMSM variator with feeble rate of harmonics, a power factor
of network unity and great charge dynamics performance.
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Fig.16. Five-level PWM rectifier-nine-level NPC inverter-PMSM Cascade