USN 16ELD154
Ph.D./M.Sc. (Engg.) by Research Degree Examination, Feb./Mar. 2020
Advanced Computer Architecture
Time: 3 hrs. Max. Marks: 100
Note: Answer any FIVE full questions, choosing ONE full question from each module.
2. Any revealing of identification, appeal to evaluator and /or equations written eg, 42+8 = 50, will be treated as malpractice.
Module-1
1 a. With a neat sketch describe NUMA model for multiprocessor system. (06 Marks)
b. Explain how several program segments are executed in parallel. (08 Marks)
c. With neat sketch, explain vector supercomputer architecture. (06 Marks)
OR
Important Note : 1. On completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.
2 a. With a neat sketch, describe SIMD supercomputers. (08 Marks)
b. Explain how hardware and software support addresses parallelism. (06 Marks)
c. Explain the concept of multiprocessor using COMA model. (06 Marks)
Module-2
3 a. Define: (i) Grain size (ii) Latency (iii) Communication Latency (06 Marks)
b. Explain the data flow architecture for a MIT tagged token data flow computer. (08 Marks)
c. Derive the expression for average parallelism. (06 Marks)
OR
4 a. Explain the characterization of parallelism levels and their implementation issues in view of
a programmer and compiler writer. (10 Marks)
b. Define Amdahl’s law for a fixed workload and obtain the expression for fixed load speed up.
(10 Marks)
Module-3
5 a. Distinguish between CISC and RISC Architecture with respect to its characteristics.
(06 Marks)
b. Explain how the operations can be simultaneously executed using VLIW architecture.
(08 Marks)
c. With neat sketch, explain asynchronous pipeline model. (06 Marks)
OR
6 a. With neat sketch, explain the architectural models of a basic scalar computer system.
(06 Marks)
b. What is a superscalar processor and discuss pipelining in superscalar processor for degree
m = 3? (08 Marks)
c. Explain the execution of instruction phase and depict the pipelined execution of X = Y + Z
and A = B C. (06 Marks)
Module-4
7 a. Describe pipelined processor with multiple functional unit and explain how the internal data
forwarding takes place. (10 Marks)
b. Explain arithmetic pipeline stages and illustrate Carry Propagation Adder (CPA) and Carry
Save Adder (CSA). (10 Marks)
1 of 2
16ELD154
OR
8 a. Discuss static and dynamic instruction scheduling. (10 Marks)
b. With neat sketch, explain the architecture of T1 Advanced Scientific Computer (ASC).
(10 Marks)
Module-5
9 a. With neat sketch, explain the Stanford Dash Prototype System that performs
multiprocessing. (10 Marks)
b. Describe symmetric shared memory architecture. (10 Marks)
OR
10 a. With an example, explain Data Flow graphs. (10 Marks)
b. Describe Distributed Shared Memory Architecture. (10 Marks)
*****
2 of 2
