SDH Technical Note

Technical Note

Functionality, Testing of bytes B1, B2 and B3 in SDH Protocol

Overview

The limitations regarding the maximum error rates for B1, B2 and B3 in SDH transmission systems can be
confusing, especially when using a test-set. It is not always clear that practical values change according to
the line rate and the STM-N format. The following attempts to provide some explanation. A basic
understanding of the SDH frame structure and layout is assumed.

Introduction

The function of the SDH overhead "B" bytes is more easily understood if they are associated with the phrase
"Block Errors"9(1). Each byte (or combination of bytes) provides essentially a parity error check for a "block"
of data, either the entire STM-N frame or a sub-section.

A B1 byte is provided in each STM-N frame for Regenerator Section error-performance monitoring(2).

B2 bytes are allocated for a Multiplex Section error monitoring function. They are used in conjunction with
the M1 Byte which reports the parity check errors detected (REI -Remote Error Indication).

One B3 byte is allocated in each VC-4(3) for a Path error monitoring function. The B3 byte provides an end-
to-end error-monitoring function. It is used in conjunction with the G1 Byte which reports the parity check
errors detected. Figure 7 shows the relationship in diagram form.

Figure 7. Block Error Bytes

BIP-X definition per ITU-T G.707

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 SDH Technical Note

Bit Interleaved Parity-X (BIP-X) code is defined as a method of error monitoring. With "even" parity (as
opposed to "odd" parity), an X-bit(4) code is generated by the transmitting equipment over a specified
portion of the signal. The first bit of the code provides even parity over the first bit of all X-bit sequences in
the covered portion of the signal, the second bit provides even parity over the second bit of all X-bit
sequences within the specified portion, etc. Even parity is generated by setting the BIP-X bits, so that there
is an even number of 1s in each monitored partition of the signal. A monitored partition comprises all bits
which are in the same bit position within the X-bit sequences in the covered portion of the signal. The
covered portion includes BIP-X.

BIP-8

The X in BIP-X becomes 8 for B1 and B3 because of the eight bits or single byte employed. This Bit
Interleaved Parity 8 code (using even parity) employs a technique which counts all the Binary "One"
occurrences in bit positions 1 through 8 for all bytes in a frame (or block). For example, if the Binary "One"
occurrences in a given bit position (column) total 157 (an odd number) across some number of bytes
(rows), then a Binary "One" is placed in the same bit position of the parity byte. This effectively makes a
new column total of 158, an even number, for even parity. If the number of occurrences in bit position 1
had been 150, then a Binary "Zero" would have been sent in that position of the Parity Byte.

Figure 8 shows another example where BIP-8 is applied to a five byte sequence. The count of Binary "One's
in bit position 3 totals 2. This is an even number, and meets the even parity requirement. The value in bit
position 3 of the BIP-8 is therefore a Binary "0".

Bit Position 1 2 3 4 5 6 7 8 Notes

Byte 1 1 0 101 0 10>
Byte 2 0 1 0 1 0 1 0 1 >Data
Byte 3 1 0 1 0 1 0 1 0 >to be
Byte 4 0 1 0 1 0 1 0 1 >protected
Byte 5 1 1 001 1 00>
Ones Count 3 3 2 2 3 3 2 2
Odd/Even O O E E O O E E See note below
Parity Byte 1 1 0 0 1 1 0 0 See note below

An "O" or odd total in the Ones Count row causes a Binary "1" to be placed in the same bit position below.

The value of the BIP-8 byte to be sent in overhead byte Bn using even parity.

Figure 8. BIP-8 example calculation

B1 (Regenerator Section Overhead - RSOH)

B1 Byte is calculated over all bits of the previous STM-N frame after it has been scrambled (5, 6). This
calculated value of B1 is then placed in the next following frame before it is scrambled. In the case of an
STM-1 frame, the value of the parity byte (B1) is calculated over 9 rows by 270 columns or 2430 bytes (7).

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 SDH Technical Note

This represents 19440 bits which would be protected by 8 parity bits. This means mathematically B1 can
only detect that up to 4.11 bits in 10,000 are errored (4.11E-4) for an STM-1 frame, the actual rate may in
fact be higher. The parity method of error checking is also known to have minor limitations, where two
errors occurring in the same bit position may emulate a ones count that is already even. Generally parity-
error monitoring is in excess of 90% accurate in detecting one or more bit errors. The maximum B1 error
rates that can be reported (or the maximum number of errors that can be detected for the given block size)
for common line rates are shown below:

MAX rate
STM-1 155 Mb/s 4.11E-4 around 4 errors in 10,000 bits
STM-4 622 Mb/s 1.37E-4 around 1 error in 10,000 bits
STM-16 2.4 Gb/s 3.43E-5 around 3 errors in 100,000 bits

Regardless of the line rate, only one B1 byte is currently used in the first STM-1 of an STM-N frame.
Although , as shown, the parity is calculated over the entire STM-N frame. Essentially the block size
increases with the line rate, the number of parity bits remains the same and maximum detectable error rate
worsens.

On receipt of the B1 byte, the RSOH terminating network element compares the result with its own
calculation on the previous frame (See Figure 3). If the result is different, an error is declared indicating that
one specific frame has been corrupted up to the extent of the X in BIP-X.

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 SDH Technical Note

Figure 9. Compute parity, Compare with stored

A combination of the number of bits in error in the parity byte and the number of frames over which these
extend is used to compute the B1 error rate, this becomes a representation, within limits, of the degradation
across the entire Regenerator Section. (See Figure 4). Remember that B1 is recomputed at each
regenerator (thus it is necessary to have MS-BIP B2 and Path B3).

Figure 10. Computing the B1 error rate

When sending a B1 error rate from a test instrument, the usual technique is to force one or more parity bits
to an incorrect value for one or more frames. The intent is to "falsify" the B1 calculation at the origin in
order to exercise the error monitoring functions of the network element under test (and potentially any
associated reporting). Given that the test instrument can only modify up to eight bits for each B1 in an STM-
N frame over a specified number of frames, then it can only insert up to the maximum equivalent error rate
available. Further, the integration time for the error rate has to be considered.

For example an equivalent Error Rate of 1e-4 can be introduced by changing 2 BIP-8 bits in one STM-1
frame if only that single frame is considered. The same Error Rate can be inserted over 32 STM-1 frames
with a total of 64 parity bit errors. Of course, random errors do not occur on a frame-aligned basis. Network
Elements integrate parity errors over time, for example, 20mS. The time period is designed to take into
account the persistence of the problem and the required overall response time for a given action, for
example, protection switching.

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 SDH Technical Note

Test Instruments also take into account the integration time of the monitoring network element vs. the
sequence of the inserted errors. They typically do not introduce the same number of total parity errors per
frame on a continual basis. This would not provide enough flexibility in the BIP error insertion rate selection
range to support appropriate testing of the monitoring network element.

B2 (Multiplex Section Overhead MSOH)

The B2 bytes are used to provide an error monitoring function for the Multiplex Section. In this case, the
function BIP-N x 24 is employed, with even parity. This is explained by use of 3 x B2 bytes in an STM-1, i.e.,
where N=1. Where N=4, i.e., in an STM -4, BIP-96 is used, and BIP-384 with STM-16 (See Figure 5.)

Figure 11. Examples of STM-1 and STM-4 frames

B2 bytes are calculated prior to scrambling, but exclude the Regenerator Section Overhead bytes (A1, A2,
J0, B1, E1, Dn, etc.). They are then placed in the appropriate column, i.e., B2 Col.1, B2 Col.2, B2 Col.3 (for
an STM-1). of the next following frame before it is scrambled.

It can be seen that the granularity of the protection, i.e., Number of Parity Bytes vs. the size of the frame,
remains the same, for all multiplex sections independent of SDH rate. The maximum B2 Error Rate is 1.25E-
3. This translates to being able to detect slightly in excess of 1 error in 1000 bits. This is linked to the design
requirements to trigger APS (Automatic Protection Switching).

Sending a B2 error rate from a test instrument, again the technique is to force one or more bits per STM-N
to an incorrect value for one or more frames. To "falsify" the parity is to exercise the error-monitoring
functions and the protection switching of the network element (and trigger the associated reporting). Given
that the test instrument can only modify up to BIP-N x 24 in an STM-N frame, over a specified number of
frames, then a similar restriction exists for B1 up to the maximum equivalent error rate.

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 SDH Technical Note

B3

The B3 Byte is used to provide an error-monitoring function for Path data including the payload and the
Path Overhead POH. It uses the BIP-8 format as discussed, with even parity. B3 specifically does not include
either the RSOH or the MSOH in its calculation which is made prior to scrambling. The results of the all the
B3 calculations are placed in the next following STM-N frame for each VC-4 (8). The PTE (Path Terminating
Equipment) (9) deals with the received values of B3 in the same way as B1 and logs any discrepancy. This
information or REI (Remote Error Indication) (10) is made available via the return Path in the first four bit
positions of the G1 byte.

The maximum equivalent error rate that can be conveyed using the B3 Byte is governed by the type of
mapping used. If VC-4 is used, then the number of bytes is given by 261 columns by 9 rows, or 2349. The
number of bits protected by 1 byte (B3) is 18792. The mathematical limit on the maximum detectable B3
error rate when using VC-4 is then 4.25E-4.

If a Test Instrument (as mentioned above) is used to insert a B3 error rate by manipulating the bits in that
byte, it is also restricted by this limit.

Conclusions

B1

The maximum number of errors that B1 can detect is reduced with an increase in the line rate. This is
because the number of parity bits remains the same while the size of the block increases. B1 is used as an
Application Specific Primitive in Network Management Systems, generally a "Class B" performance
parameter associated only with regenerators (11). A "Class B" performance parameter is one that is not
always used and may be optioned depending upon the system.

B2

The maximum number of errors that B2 can detect remains constant with an increase in line rate. This is
because the quantity of parity bits increases relative to the increase in the size of the block. B2 performs a
key role in Automatic Protection (APS) switch initiation criteria, particularly with regard to Signal Degrade
(SD) or "soft" failures where a pre-selected error rate is exceeded. This service-dependent threshold is
typically in the range of 1.0E-5 to 1.0E-9. B2 is therefore a mandatory "Class A" performance primitive. This
is a parameter which is often used to anticipate problems that affect service, and is a critical part of the
Network Operators' commitment to minimum service interruption.

B3

The maximum number of errors that B3 can detect remains constant with an increase in line rate, but it is
dependent on the mapping type. B3 is the path-error monitoring function associated with the payload and is
a required performance primitive for Management purposes. In the case of VC-4 this is also referred to as
HOVC (High Order Virtual Container) path (12). Pre-Selected error-rate thresholds are also used to initiate
protection switching from a path perspective. This can be critical in a network where certain paths have
higher priority than others.

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 SDH Technical Note

SDH Test Instruments can exercise a range of basic functions in the Overhead and measure bit error
performance in the payload. However when testing, the Block error-monitoring bytes B1, B2 and B3 care
should be taken relative to the intended overall network behavior. The threshold at which action is to be
taken by the network node vis-à-vis the detectable error rate should be incorporated into the test
procedure.

Footnotes for Technical Note

Functionality and Testing of bytes B1, B2 and B3 in the SDH Protocol

(1) ITU-T Rec. O.181, February 1996, ANNEX A: A.1.2, A.1.3, A.1.4

(2) ITU-T Rec. G.707 (draft), November 1995, Section 9.2.2

(3) Virtual Container-n is the structure used to support the path layer, it includes payload and Path
Overhead

(4) B1 and B3 use BIP-8 where X = 8 from BIP-X i.e. 8 parity bits. B2 uses BIP-24 for STM-1 where the X in
BIP-X is 24 because of the 24 parity bits used.

(5) STM-1, 4, 16, 24 signals must have sufficient bit timing content at the Network Node Interface. This is
achieved using a scrambling pattern which prevents long sequences of "1"s or "0"s. See ITU-T
Recommendations. G.707, G.703, G.957

(6) A1, A2, J0 bytes are never scrambled

(7) Understanding SONET/SDH Standards & Applications - Ming-Chwan Chow - IBSN 0-9650448-2-3 (1995)

(8) The term VC4 (Virtual Container {Type} 4) is used here to also refer to VC-4-Xc per G.707 Section 9.3.1

(9) ITU-T Rec. G.707 (draft) November 1995: Section 4 also ITU-T Rec. G783.

(10) REI Remote Error Indication was formally known as FEBE or Far End Block Error.

(11) Class A - Mandatory, Class B - Application Specific/Optional. Understanding SONET/SDH Standards &
Applications - Ming-Chwan Chow. See also ITU-T Rec. G.783

(12) ITU-T Rec. G.707 (draft) November 1995. See also ITU-T Rec. G.783

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