1.

A microcontroller at-least should consist of:

a) RAM, ROM, I/O ports and timers

b) CPU, RAM, I/O ports and timers
c) CPU, RAM, ROM, I/O ports and timers
d) CPU, ROM, I/O ports and timers
Answer: c
Explanation: A microcontroller at-least consists of a processor as its CPU with RAM, ROM, I/O ports and timers. It
may contain some additional peripherals like ADC, PWM, etc.

2. Unlike microprocessors, microcontrollers make use of batteries because they have:

a) high power dissipation

b) low power consumption
c) low voltage consumption
d) low current consumption
Answer: b
Explanation: Micro Controllers are made by using the concept of VLSI technology. So here, CMOS based logic gate
s are coupled together by this technique that consumes low power.

3. What is the order decided by a processor or the CPU of a controller to execute an instruction?

a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
Answer: d
Explanation: First instruction is fetched from Program Memory. After fetching, instruction is decoded to generate co
ntrol signals to perform the intended task. After decoding, instruction is executed and the complete intended task of t
hat particular instruction.

4. If we say microcontroller is 8-bit then here 8-bit denotes size of:

a) Data Bus
b) ALU
c) Control Bus
d) Address Bus
Answer: b
Explanation: If we say a microcontroller is 8-bit it means that it is capable of processing 8-bit data at a time. Data pr
ocessing is the task of ALU and if ALU is able to process 8-bit data then the data bus should be 8-bit wide. In most
books it tells that size of data bus but to be precise it is the size of ALU because in Harvard Architecture there are tw
o sets of data bus which can be of same size but it is not mandatory.

5. How are the performance and the computer capability affected by increasing its internal bus width?

a) it increases and turns better

b) it decreases
c) remains the same
d) internal bus width doesn’t affect the performance in any way
Answer: a
Explanation: As the bus width increases, the number of bits carried by bus at a time increases as a result of which th
e total performance and computer capability increases.
6. Abbreviate CISC and RISC.

a) Complete Instruction Set Computer, Reduced Instruction Set Computer

b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
Answer: b
Explanation: CISC means Complete Instruction Set Computer because in this a microcontroller has an instruction se
t that supports many addressing modes for the arithmetic and logical instructions, data transfer and memory accesses
instructions. RISC means Reduced Instruction Set Computer because here a microcontroller has an instruction set t
hat supports fewer addressing modes for the arithmetic and logical instructions and for data transfer instructions.

7. Give the names of the buses present in a controller for transferring data from one place to another?

a) data bus, address bus

b) data bus
c) data bus, address bus, control bus
d) address bus
Answer: c
Explanation: There are 3 buses present in a microcontroller they are data bus (for carrying data from one place to an
other), address bus (for carrying the address to which the data will flow) and the control bus (which tells the controll
er to execute which type of work at that address may be it read or write operation).

8. What is the file extension that is loaded in a microcontroller for executing any instruction?

a) .doc
b) .c
c) .txt
d) .hex
Answer: d
Explanation: Microcontrollers are loaded with .hex extension as they understand the language of 0’s and 1’s only.

9. What is the most appropriate criterion for choosing the right microcontroller of our choice?

a) speed
b) availability
c) ease with the product
d) all of the mentioned
Answer: d
Explanation: For choosing the right microcontroller for our product we must consider its speed so that the instructio
ns may be executed in the least possible time. It also depends on the availability so that the particular product may b
e available in our neighboring regions or market in our need. It also depends on the compatibility with the product s
o that the best results may be obtained.

10. Why microcontrollers are not called general purpose computers?

a) because they have built in RAM and ROM

b) because they design to perform dedicated task
c) because they are cheap
d) because they consume low power
Answer: b
Explanation: Microcontrollers are designed to perform dedicated tasks. While designing general purpose computers
end use is not known to designers.
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1. How many types of architectures are available, for designing a device that is able to work on its own?

a) 3
b) 2
c) 1
d) 4
Answer: b
Explanation: There are basically two main types of architectures present, they are Von Neumann and Harvard archit
ectures.

2. Which architecture is followed by general purpose microprocessors?

a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: b
Explanation: General purpose microprocessors make use of Von Neumann architecture as here a simpler design is of
fered.

3. Which architecture involves both the volatile and the non volatile memory?

a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: In Harvard architecture, both the volatile and the non volatile memories are involved. This is done to in
crease its efficiency as both the memories are being used over here.

4. Which architecture provides separate buses for program and data memory?

a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: Harvard Architecture provides separated buses for data and program memory to fetch program and dat
a simultaneously. By doing this access time is reduced and hence performance is increased.

5. Which microcontroller doesn’t match with its architecture below?

a) Microchip PIC- Harvard

b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
Answer: b
Explanation: MSP430 supports Von Neumann architecture.

6. Harvard architecture has _____________

a) dedicated buses for data and program memory
b) pipeline technique
c) complex architecture
d) all of the mentioned
Answer: d
Explanation: Harvard Architecture has dedicated buses for data and program memory and pipeline technique becaus
e of this architecture is complex.

7. Which out of the following supports Harvard architecture?

a) ARM7
b) Pentium
c) SHARC
d) All of the mentioned
Answer: c
Explanation: SHARC supports harvard architecture for signal processing in DSP.

8. Why most of the DSPs use Harvard architecture?

a) they provide greater bandwidth

b) they provide more predictable bandwidth
c) they provide greater bandwidth & also more predictable bandwidth
d) none of the mentioned
Answer: c
Explanation: Most of the DSPs use harvard architecture because they provide a wider predictable bandwidth.

9. Which of the following supports CISC as well as Harvard architecture?

a) ARM7
b) ARM9
c) SHARC
d) None of the mentioned
Answer: c
Explanation: SHARC supports both the CISC and the Harvard architecture.

10. Which of the two architecture saves memory?

a) Harvard
b) Von Neumann
c) Harvard & Von Neumann
d) None of the mentioned
Answer: b
Explanation: As only one memory is present in the Von Neumann architecture so it saves a lot of memory.

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1. 8051 microcontrollers are manufactured by which of the following companies?

a) Atmel
b) Philips
c) Intel
d) All of the mentioned
Answer: d
Explanation: 8051 microcontrollers are manufactured by Intel, Atmel, Philips/Signetics, Infineon, Dallas Semi/Maxi
m.

2. AT89C2051 has RAM of:

a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Answer: a
Explanation: It has 128 bytes of RAM in it.

3. 8051 series has how many 16 bit registers?

a) 2
b) 3
c) 1
d) 0
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.

4. When 8051 wakes up then 0x00 is loaded to which register?

a) PSW
b) SP
c) PC
d) None of the mentioned
Answer: c
Explanation: When 8051 wakes up, Program Counter (P
c) loaded with 0000H. Because of this in 8051 first opcode is stored in ROM address at 0000H.

5. When the microcontroller executes some arithmetic operations, then the flag bits of which register are affected?

a) PSW
b) SP
c) DPTR
d) PC
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity, register bank se
lect bits etc which are affected during such operations.

6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction

a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are set to 1. In t
he result, the number of 1’s present are even so parity flag is set to zero.

7. How are the bits of the register PSW affected if we select Bank2 of 8051?

a) PSW.5=0 and PSW.4=1

b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and RS0=0 wh
ich are fourth and third bit of the register respectively.

8. If we push data onto the stack then the stack pointer

a) increases with every push

b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push of element.

9. On power up, the 8051 uses which RAM locations for register R0- R7

a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.

10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?

a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.

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1. “DJNZ R0, label” is ________ byte instruction.

a) 2
b) 3
c) 1
d) Can’t be determined
Answer: a
Explanation: DJNZ is 2-byte instruction. This means jump can be of -128 to +127 locations with respect to PC. Here
-128 means upward or backward jump and +127 means downward or forward jump.

2. JZ, JNZ, instructions checked content of _______ register.

a) DPTR
b) B
c) A
d) PSW
Answer: c
Explanation: JZ and JNZ instructions checked the content of A register and if condition was satisfied or true then ju
mp to target address.

3. Calculate the jump code for again and here if code starts at 0000H

a) F3,02
b) F9,01
c) E9,01
d) E3,02
Answer: c
Explanation: Loop address is calculated by subtracting destination address and the address next to the source address
.

4. When the call instruction is executed the topmost element of stack comes out to be

a) the address where stack pointer starts

b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
Answer: b
Explanation: The topmost element of the stack is the address of the instruction next to the call instruction so that wh
en RET is executed then PC is filled with that address and so the pointer moves to the main program and continue w
ith its routine task.

5. LCALL instruction takes

a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
Answer: c
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte instruction.

6. Are PUSH and POP instructions are a type of CALL instructions?

a) yes
b) no
c) none of the mentioned
d) cant be determined
Answer: b
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH instructions the poi
nter does not move to any location specified by its address which is the fundamental of CALL instruction, so it is no
t a type of CALL instruction.

7. What is the time taken by one machine cycle if crystal frequency is 20MHz?

a) 1.085 micro seconds

b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
Answer: b
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal frequency) /12

8. Find the number of times the following loop will be executed

a) 100
b) 200
c) 20000
d) 2000
Answer: c
Explanation: It will be executed 200*100 times.

9. What is the meaning of the instruction MOV A,05H?

a) data 05H is stored in the accumulator

b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
Answer: c
Explanation: If we need to store the address in the accumulator, then directly the address is moved to it unlikely of u
sing # used for storing data in any register.

10. Do the two instructions mean the same?

a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
Answer: b
Explanation: In the first statement, when the decrements approach zero then the jump moves back and in the second
statement, when the result after decrements is not zero, then it jumps back.

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1. To initialize any port as an output port what value is to be given to it?

a) 0xFF
b) 0x00
c) 0x01
d) A port is by default an output port
Answer: d
Explanation: In 8051, a port is initialized by default in its output mode no need to pass any value to it.

2. Which out of the four ports of 8051 needs a pull-up resistor for using it is as an input or an output port?

a) PORT 0
b) PORT 1
c) PORT 2
d) PORT 3
Answer: a
Explanation: These pins are the open drain pins of the controller which means it needs a pull-up resistor for using it
as an input or an output ports.

3. Which of the ports act as the 16 bit address lines for transferring data through it?

a) PORT 0 and PORT 1

b) PORT 1 and PORT 2
c) PORT 0 and PORT 2
d) PORT 1 and PORT 3
Answer: c
Explanation: PORT 0 and PORT 2 are used as the 16 bit address lines where PORT0 act as lower bit address lines a
nd PORT 2 as higher bit address lines.

4. Which of the following registers are not bit addressable?

a) SCON
b) PCON
c) A
d) PSW
Answer: b
Explanation: PCON register is not a bit addressable register.

5. Which instruction is used to check the status of a single bit?

a) MOV A,P0
b) ADD A,#05H
c) JNB PO.0, label
d) CLR P0.05H
Answer: b
Explanation: JNB which stands for Jump if no bit checks the status of the bit P0.0 and jumps if the bit is 0.

6. Which addressing mode is used in pushing or popping any element on or from the stack?

a) immediate
b) direct
c) indirect
d) register
Answer: c
Explanation: If we want to push or pop any element on or from the stack then direct addressing mode has to be used
in it, as the other way is not accepted.

7. Which operator is the most important while assigning any instruction as register indirect instruction?

a) $
b) #
c) @
d) &
Answer: b
Explanation: In register, indirect mode data is copied at that location where R0 or R1 are present, so @ operator is u
sed ex. MOV @R0,A

8. What is the advantage of register indirect addressing mode?

a) it makes use of registers R0 and R1

b) it uses the data dynamically
c) it makes use of operator @
d) it is easy
Answer: b
Explanation: Register indirect addressing mode is useful if a series of data is to be assigned to that address, with the
help of this quality the number of instructions decreases as a result of which performance increases.
9. Which of the following comes under the indexed addressing mode?

a) MOVX A, @DPTR
b) MOVC @A+DPTR,A
c) MOV A,R0
d) MOV @R0,A
Answer: b
Explanation: Indexed addressing mode stands for that instruction where the bits of the accumulator is also indexed w
ith the 16 bit registers.

PSST! You better watch out, something's buggy above.

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1. When we add two numbers the destination address must always be.

a) some immediate data

b) any register
c) accumulator
d) memory
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator. Example- ADD A,R0;
ADD A, @R1; ADD A,@ DPTR

2. DAA command adds 6 to the nibble if:

a) CY and AC are necessarily 1

b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.

3. If SUBB A,R4 is executed, then actually what operation is being applied?

a) R4+A
b) R4-A
c) A-R4
d) R4+A
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of the register or some
immediate value. So A-R4 is being executed.

4. A valid division instruction always makes:

a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.

5. In 8 bit signed number operations, OV flag is set to 1 if:

a) a carry is generated from D7 bit

b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to 1.

6. In unsigned number addition, the status of which bit is important?

a) OV
b) CY
c) AC
d) PSW
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is important and in signed num
ber operation the status of OV flag is important.

7. Which instructions have no effect on the flags of PSW?

a) ANL
b) ORL
c) XRL
d) All of the mentioned
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the data copy instructions,
so all these instructions don’t affect the bits of the flag.

8. ANL instruction is used _______

a) to AND the contents of the two registers

b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to mask the status of
the bits of the register.

9. CJNE instruction makes _______

a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
Answer: d
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not equal and it resets CY if
the destination address is larger then the source address and sets CY if the destination address is smaller then the so
urce address.

10. XRL, ORL, ANL commands have _______

a) accumulator as the destination address and any register, memory or any immediate data as the source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the source address
d) any register as the destination address and any immediate data as the source address
Answer: a
Explanation: These commands have accumulator as the destination address and any register, memory or any immedi
ate data as the source address.

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1. What is the clock source for the timers?

a) some external crystal applied to the micro-controller for executing the timer
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
Answer: b
Explanation: Timer’s clock source is the crystal that is applied to the controller.

2. What is the frequency of the clock that is being used as the clock source for the timer?

a) some externally applied frequency f’

b) controller’s crystal frequency f
c) controller’s crystal frequency /12
d) externally applied frequency/12
Answer: c
Explanation: The frequency of the clock source for the timer is equal to f/12(where f is the frequency of the crystal).

3. What is the function of the TMOD register?

a) TMOD register is used to set various operation modes of timer/counter

b) TMOD register is used to load the count of the timer
c) Is the destination or the final register where the result is obtained after the operation of the timer
d) Is used to interrupt the timer
Answer: a
Explanation: TMOD is used to set various operation modes of timer/counter by the programmer.

4. What is the maximum delay that can be generated with the crystal frequency of 22MHz?

a) 2978.9 sec
b) 0.011 msec
c) 11.63 sec
d) 2.97 msec
Answer: d
Explanation: For generating the maximum delay we have to multiply the maximum number of counts with the time
period required to execute one machine cycle( 65536*1/22MHz).

5. Auto reload mode is allowed in which mode of the timer?

a) Mode 0
b) Mode 1
c) Mode 2
d) Mode 3
Answer: c
Explanation: Auto reload is allowed in the Mode 2 of the timer because here in this mode, we don’t need to load the
count again and again in the register.

6. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
a) 00FFH,0FFFH,FFFFH
b) 1FFFH,0FFFH,FFFFH
c) 1FFFH,FFFFH,00FFH
d) 1FFFH,00FFH,FFFFH
Answer: c
Explanation: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll over value. Similarly for Mode 1 FF
FFH and for Mode 2 FFH is the roll over value for the timers and counter.

7. What steps are followed when we need to turn on any timer?

a) load the count, start the timer, keep monitoring it, stop the timer
b) load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer
c) load the TMOD register, start the timer, load the count, keep monitoring it, stop the timer
d) none of the mentioned
Answer: b
Explanation: When any timer is to turn on, then firstly we have to load the TMOD register and the count. Then the ti
mer is to get started. After then, we need to monitor the timer properly and then when the roll over condition arises t
hen the timer is to be stopped.

8. If Timer 0 is to be used as a counter, then at what particular pin clock pulse need to be applied?

a) P3.3
b) P3.4
c) P3.5
d) P3.6
Answer: b
Explanation: If Timer 0 is to be used as a counter, then a pulse has to be applied at P3.4 and if it is for Timer 1 then t
he clock pulse has to be applied at the pin P3.5.

9. In the instruction “MOV TH1,#-3”, what is the value that is being loaded in the TH1 register?

a) 0xFCH
b) 0xFBH
c) 0xFDH
d) 0xFEH
Answer: c
Explanation: Negative value is loaded in 2’s complement form. -3 represented in 2’s complement form as FDH.

10. TF1, TR1, TF0, TR0 bits are of which register?

a) TMOD
b) SCON
c) TCON
d) SMOD
Answer: c
Explanation: All of these bits are part of TCON (Timer Control) register. TF0 and TF1 are used to check overflow o
f timer 0 and timer 1 respectively. TR0 and TR1 are timer control bits used to start and stop of timer 0 and timer 1 re
spectively.

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1. Which devices are specifically being used for converting serial to parallel and from parallel to serial respectively?
a) timers
b) counters
c) registers
d) serial communication
Answer: c
Explanation: Some registers like the parallel in serial out and serial in parallel out are used to convert serial data into
parallel and vice versa respectively.

2. What is the difference between UART and USART communication?

a) they are the names of the same particular thing, just the difference of A and S is there in it
b) one uses asynchronous means of communication and the other uses synchronous means of communication
c) one uses asynchronous means of communication and the other uses asynchronous and synchronous means of com
munication
d) one uses angular means of the communication and the other uses linear means of communication
Answer: c
Explanation: UART stands for Universal Asynchronous receiver-transmitter and USART stands for Universal Sync
hronous and Asynchronous receiver-transmitter.

3. Which of the following best describes the use of framing in asynchronous means of communication?

a) it binds the data properly

b) it tells us about the start and stops of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Answer: b
Explanation: In data framing in asynchronous means of communication, the data is packed between the start and the
stop bit. This is done so as to tell the other computer about the start and the end of the data.

4. Which of the following signal control the flow of data?

a) RTS
b) DTR
c) RTS & DTR
d) None of the mentioned
Answer: a
Explanation: RTS is a request to send control signal which is a control for the flow of data. On the other hand DTR i
s a Data Terminal Ready control signal which tells about the current status of the DTE.

5. Which of the following is the logic level understood by the micro-controller/micro-processor?

a) TTL logic level

b) RS232 logic level
c) None of the mentioned
d) TTL & RS232 logic level
Answer: a
Explanation: TTL logic or the transistor logic level is the logic that is understood by the micro-controllers/microproc
essors.

6. What is a null modem connection?

a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Answer: c
Explanation: In null modem connection the RxD of one is the TxD for the other.

7. Which of the following best states the reason that why baud rate is mentioned in serial communication?

a) to know about the no of bits being transmitted per second

b) to make the two devices compatible with each other, so that the transmission becomes easy and error free
c) to use Timer 1
d) for wasting memory
Answer: b
Explanation: To make two devices compatible with each other baud rate is mentioned in the serial communication s
o that the transmission becomes easy and error free.

8. With what frequency UART operates( where f denoted the crystal frequency )?

a) f/12
b) f/32
c) f/144
d) f/384
Answer: d
Explanation: UART frequency is the crystal frequency f/12 divided by 32, that comes out to be f/384.

9. What is the function of the SCON register?

a) to control SBUF and SMOD registers

b) to program the start bit, stop bit, and data bits of framing
c) to control SMOD registers
d) none of the mentioned
Answer: b
Explanation: SCON register is mainly used for programming the start bits, stop bits and data bits of framing. As it c
onsists of bits like RB8, TB8, SM0, SM1, SM2 etc.

10. What should be done if we want to double the baud rate?

a) change a bit of the TMOD register

b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Answer: b
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this bit then the baud rate gets doubled.

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1. When an interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?

a) to the next instruction which is to be executed

b) to the first instruction of ISR
c) to a fixed location in memory called interrupt vector table
d) to the end of the program
Answer: c
Explanation: When an interrupt occurs, then it jumps to a fixed memory location in memory called the interrupt vect
or table that holds the address of the Interrupt Service Routine.

2. What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?

a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Answer: b
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or th
e contents of the IE register becomes null.

3. After RETI instruction is executed then the pointer will move to which location in the program?

a) next interrupt of the interrupt vector table

b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
d) none of the mentioned
Answer: b
Explanation: When the RETI instruction is executed, PC will fetch 2-bytes (address) from top of stack which is store
d when interrupt is occurred. This will return to the place where interrupt is occurred and starts executing instruction
s.

4. Which pin of the external hardware is said to exhibit INT0 interrupt?

a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
Answer: c
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low le
veled pulse.

5. Which bit of the IE register is used to enable TxD/RxD interrupt?

a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Answer: d
Explanation: IE.D4 is used to enable RS interrupt or the serial communication interrupt.

6. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assu
ming initially all bits of the IE register are zero)?

a) EX0=1
b) EA=1
c) any of the mentioned
d) EX0=1 & EA=1
Answer: d
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enab
le all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled in
terrupts.
7. Why normally LJMP instructions are the topmost lines of the ISR?

a) so as to jump to some other location where there is a wider space of memory available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: There is a small space of memory present in the vector table between two different interrupts so in orde
r to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is availab
le.

8. Which register is used to make the interrupt level or an edge triggered pulse?

a) TCON
b) IE
c) IPR
d) SCON
Answer: a
Explanation: TCON register is used to make any interrupt level or edge triggered.

9. What is the disadvantage of a level triggered pulse?

a) a constant pulse is to be maintained for a greater span of time

b) another interrupt may be generated if the low-level signal is not removed before the ISR is finished
c) it is difficult to produce
d) another interrupt may be caused if the signal is still low before the completion of the last instruction
Answer: d
Explanation: In a level triggered interrupt, if the low signal at interrupt pin must be removed before the execution of
last instruction of the ISR i.e. RETI. If low signal at interrupt pin is not removed before completing the ISR then it w
ill be generating another interrupt.

10. What is the correct order of priority that is set after a controller gets reset?

a) RI/TI > TF1 > TF0 > INT1 > INT0

b) RI/TI < TF1 < TF0 < INT1 < INT0
c) INT0 > TF0 > INT1 > TF1 > RI/TI
d) INT0 < TF0 < INT1 < TF1 < RI/TI
Answer: c
Explanation: On reset Interrupt Priorities are as INT0 > TF0 > INT1 > TF1 > RI/TI, where ‘>’ is used to denote high
est priority.

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1. How many rows and columns are present in a 16*2 alphanumeric LCD?

a) rows=2, columns=32
b) rows=16, columns=2
c) rows=16, columns=16
d) rows=2, columns=16
Answer: d
Explanation: 16*2 alphanumeric LCD has 2 rows and 16 columns.

2. How many data lines are there in a 16*2 alphanumeric LCD?

a) 16
b) 8
c) 1
d) 0
Answer: b
Explanation: There are eight data lines from pin no 7 to pin no 14 in an LCD.

3. Which pin of the LCD is used for adjusting its contrast?

a) pin no 1
b) pin no 2
c) pin no 3
d) pin no 4
Answer: c
Explanation: Pin no 3 is used for controlling the contrast of the LCD.

4. For writing commands on an LCD, RS bit is

a) set
b) reset
c) set & reset
d) none of the mentioned
Answer: b
Explanation: For writing commands on an LCD, RS pin is reset.

5. Which command of an LCD is used to shift the entire display to the right?

a) 0x1C
b) 0x18
c) 0x05
d) 0x07
Answer: a
Explanation: 0x1C is used to shift the entire display to the right.

6. Which command is used to select the 2 lines and 5*7 matrix of an LCD?

a) 0x01
b) 0x06
c) 0x0e
d) 0x38
Answer: d
Explanation: 0x38 is used to select the 2 lines and 5*7 matrix of an LCD.

7. Which of the following step/s is/are correct for sending data to an LCD?

a) set the R/W bit

b) set the E bit
c) set the RS bit
d) all of the mentioned
Answer: d
Explanation: To send data to an LCD, RS pin should be set so that LCD will come to know that it will receive data
which has to display on the screen. R/W pin should be reset as data has to be displayed (i.e. write to the LCD). High
to low pulse must be applied to the E pin when data is supplied to data pins of the LCD.
8. Which of the following step/s is/are correct to perform reading operation from an LCD?

a) low to high pulse at E pin

b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set high
d) none of the mentioned
Answer: c
Explanation: For reading operations, R/W pin should be made high and added to it, a low to high pulse is also gener
ated at the E pin.

9. Which instruction is used to select the first row first column of an LCD?

a) 0x08
b) 0x0c
c) 0x80
d) 0xc0
Answer: c
Explanation: 0x80 is used to select the first row first column of an LCD.

10. The RS pin is _________ for an LCD.

a) input
b) output
c) input & output
d) none of the mentioned
Answer: a
Explanation: The RS pin is an input pin for an LCD.

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1. Which of the following steps detects the key in a 4*4 keyboard matrix about the key that is being pressed?

a) masking of bits
b) ensuring that initially, all keys are open
c) checking that whether the key is actually pressed or not
d) all of the mentioned
Answer: d
Explanation: For detecting that whether the key is actually pressed or not, firstly this must be ensured that initially al
l the keys are closed. Then we need to mask the bits individually to detect that which key is pressed. Then we need t
o check that is the key actually pressed or not, by checking that whether the key pressed for a time more than 20 mic
ro seconds.

2. What is described by this command: CJNE A,#00001111b, ROW1

a) it masks the bit and then jumps to the label where ROW1 is written
b) it makes the value of the accumulator 0FH and then jumps at the address where ROW1 label is written
c) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the val
ue becomes equal
d) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the val
ue is not equal
Answer: d
Explanation: This particular command CJNE A,#00001111b, ROW1 compares the value of the accumulator with O
FH and jumps to ROW1 address if the value is not equal.

3. To detect that in which column, the key is placed?

a) we can mask the bits and then check it

b) we can rotate the bits and then check that particular bit which is set or reset(according to the particular condition)
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: We can mask or we can even rotate the bits to check that particularly in which column is the key place
d.

4. In reading the columns of a matrix, if no key is pressed we should get all in binary notation

a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: If no key is pressed, then all the keys show 1 as they are all connected to power supply.

5. If we need to operate a key of a keyboard in an interrupt mode, then it will generate what kind of interrupt?

a) ES
b) EX0/EX1
c) T0/T1
d) RESET
Answer: b
Explanation: If a key is to operate in an interrupt mode then it will generate an external hardware interrupt.

6. To identify that which key is being pressed, we need to:

a) ground all the pins of the port at a time

b) ground pins of the port one at a time
c) connect all the pins of the port to the main supply at a time
d) none of the mentioned
Answer: b
Explanation: To detect that which key is being pressed, we need to ground the pins one by one.

7. Key press detection and Key identification are:

a) the same processes

b) two different works are done in Keyboard Interfacing
c) none of the mentioned
d) any of the mentioned
Answer: b
Explanation: They are two different works that are involved in Keyboard Interfacing. One is used for checking that
which key is being actually pressed and the other is used to check that is the key actually pressed or not.

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1. Why two pins for ground are available in ADC0804?

a) for controlling the ADCON0 and ADCON1 register of the controller
b) for controlling the analog and the digital pins of the controller
c) for both parts of the chip respectively
d) for isolate analog and digital signal
Answer: d
Explanation: Two grounds are available in ADC0804 to isolate analog signal from digital signal. This isolation prov
ides accuracy in digital output.

2. What is the function of the WR pin?

a) its active high input used to inform ADC0804 to the end of conversion
b) its active low input used to inform ADC0804 to the end of conversion
c) its active low input used to inform ADC0804 to the start of conversion
d) its active high input used to inform ADC0804 to the start of conversion
Answer: c
Explanation: WR is active low input used to inform the ADC0804 to start the conversion process.

3. State which of the following statements are false?

a) CLK IN pin used for External Clock Input or Internal Clock with external RC element
b) INTR pin tells about the end of the conversion
c) ADC0804 IC is an 8 bit parallel ADC in the family of the ADC0800 series
d) None of the mentioned
Answer: d
Explanation: CLK IN pin is used to tell about the conversion time, INTR pin tells about the end of the conversion an
d ADC0804 has a resolution of 8 bits only so all three statements are true.

4. While programming the ADC0808/0809 IC what steps are followed?

a) select the analog channel, start the conversion, monitor the conversion, display the digital results
b) select the analog channel, activate the ALE signal (L to H pulse), start the conversion, monitor the conversion, rea
d the digital results
c) select the analog channel, activate the ALE signal (H to L pulse), start the conversion, monitor the conversion, rea
d the digital results
d) select the channel, start the conversion, end the conversion
Answer: b
Explanation: While programming the ADC0808/0809 IC firstly we need to select the channel from the A, B, C pins.
Then we need to activate the ALE signal, this is needed to latch the address. Then we start the conversion from the
WR pin. After monitoring the INTR pin we get to know about the end of the conversion. Then we activate the OE e
nable to read out data out of the ADC chip.

5. In ADC0808/0809 IC which pin is used to select Step Size?

a) Vref
b) Vin
c) Vref/2 & Vin
d) None of the mentioned
Answer: a
Explanation: Step Size is calculated by formula Vref/(2n). As ADC0808/0809 8-bit ADC value of n=8. Therefore fo
rmula becomes Vref/(28) = Vref/256. If Vref = 5V then Step Size will be 5/256 i.e. 19.53mV.

6. What is the difference between ADC0804 and MAX1112?

a) ADC0804 has 8 bits and MAX1112 has 1 bit for data output
b) ADC0804 is used for adc and dac conversions whereas MAX1112 is used for serial data transmissions
c) ADC0804 has 32 bits and MAX1112 has 3 bit for data output
d) None of the mentioned
Answer: a
Explanation: ADC0804 is used for parallel ADC and MAX1112 is used for serial ADC.

7. Which of the following statements are true about DAC0808?

a) parallel digital data to analog data conversion

b) it has current as an output
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: DAC0804 is used for parallel data to analog data conversion.

8. 8 input DAC has ________

a) 8 discrete voltage levels

b) 64 discrete voltage levels
c) 124 discrete voltage levels
d) 256 discrete voltage levels
Answer: d
Explanation: For n input DAC has 2^n discrete voltage levels.

9. INTR, WR signal is an input/output signal pin?

a) both are output

b) both are input
c) one is input and the other is output
d) none of the mentioned
Answer: c
Explanation: INTR pin tells about the end of the conversion (output) and WR pin tells us to start the conversion (inp
ut).

10. What is the function of the SCLK pin in MAX1112?

a) It is used to bring data in

b) It is used to bring data out and send in the control byte, one at a time
c) It is used to get output clock
d) It is used to get serial output
Answer: b
Explanation: SCLK is used to bring data out and send in the control byte.

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1. A thermistor is a __________

a) sensor
b) adc
c) transducer
d) micro controller
Answer: c
Explanation: A thermistor is a device which is used to convert the temperature into electrical signals, so it acts as a tr
ansducer.

2. What is the difference between LM 34 and LM 35 sensors?

a) one is a sensor and the other is a transducer

b) one’s output voltage corresponds to the Fahrenheit temperature and the other corresponds to the Celsius temperat
ure
c) one is of low precision and the other is of higher precision
d) one requires external calibration and the other doesn’t require it
Answer: b
Explanation: LM 34’s output voltage corresponds to the Fahrenheit temperature and LM 35 corresponds to the Celsi
us temperature.

3. An electronic device which converts physical quantity or energy from one form to another is called ______

a) Sensor
b) Transistor
c) Transducer
d) Thyristor
Answer: c
Explanation: An electronic device that converts physical quantity or energy from one form to another is called Trans
ducer. Examples: Sensor, Speaker, Microphone, etc.

4. What is signal conditioning?

a) to analyse any signal

b) conversion or modification is referred to as conditioning
c) conversion from analog to digital is signal conditioning
d) conversion from digital to analog is signal conditioning
Answer: b
Explanation: Signal Conditioning is referred to as the conversion of a signal from one form to other, now this may b
e from analog to digital conditioning or digital to analog conditioning.

5. What steps have to be followed for interfacing a sensor to a microcontroller 8051?

a) make the appropriate connections with the controller, ADC conversion, analyse the results
b) interface sensor with ADC and ADC with 8051
c) interface sensor with the MAX232, send now to microcontroller, analyse the results
d) none of the mentioned
Answer: b
Explanation: For interfacing a sensor with an 8051 microcontroller, we need ADC in between because output of sen
sor is analog and microcontroller works on digital signals only. So whatever signal generated by the sensor is conver
ted into its digital equivalent using ADC and equivalent digital signal is given to the microcontroller for processing.

6. LM35 has how many pins?

a) 2
b) 1
c) 3
d) 4
Answer: c
Explanation: LM35 has 3 pins.

7. Why Vref is set of ADC0848 to 2.56 V if analog input is connected to the LM35?
a) to set the step size of the sampled input
b) to set the ground for the chip
c) to provide supply to the chip
d) all of the mentioned
Answer: a
Explanation: Vref is used to set the step size of the ADC conversion, if it is selected to 2.56 then the step size will be
selected to 10mV, so for every step increase of the analog voltage an increase of 10 mV will be there.

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1. The 8255 is a ______ chip.

a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Answer: a
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to exp
and the I/O ports of microcontrollers.

2. Which pins of a microcontroller are directly connected with 8255?

a) RD
b) WR
c) D0-D7
d) All of the mentioned
Answer: d
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and
also for transferring the data.

3. Find the control word for PA = out, PB = in, PCL = out, PCH = out (Mode0)?

a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Answer: b
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others a
s the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.

4. Which pins are used to select the ports and the control register?

a) CS
b) A1
c) A0
d) All of the mentioned
Answer: d
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used f
or select ports and the control register.

5. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Answer: d
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is acti
vated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the sam
e as it is even when the RESET button is set to zero.

6. Why MOVX instruction is being used to access the ports of the 8255?

a) because 8255 is connecting a microcontroller in memory mapped I/O configuration

b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Answer: a
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memor
y space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external
memory locations.

7. What is correct about the BSR mode from below?

a) In BSR mode, only the individual bits of PORT A can be programmed

b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Answer: c
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.

8. How many pins of the 8255 can be used as the I/O ports?

a) 8
b) 16
c) 24
d) 32
Answer: c
Explanation: There are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.

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1. DS12887 is a ____________

a) Timer IC
b) Serial communication IC
c) RTC IC
d) Motor
Answer: c
Explanation: DS12887 is a real time clock that is widely used to provide accurate time and date for many application
s.

2. DS12887 has _____ amount of RAM.

a) 14 bytes
b) 114 bytes
c) 128 bytes
d) 64 bytes
Answer: c
Explanation: DS12887 has 128 bytes of non-volatile RAM.

3. DS12887 has _____ amount of RAM for general purpose applications.

a) 9 bytes
b) 114 bytes
c) 128 bytes
d) 14 bytes
Answer: b
Explanation: DS12887 has 128 bytes of non-volatile RAM. Out of 128 bytes, 14 bytes of RAM for clock/calendar a
nd control registers, and another 114 bytes of RAM for general purpose data storage.

4. In DS12887, which bits of the Register A are used to turn on the oscillator?

a) D4
b) D5
c) D6
d) All of the mentioned
Answer: d
Explanation: In DS12887, D4-D6 bits of register A are used to turn on the oscillator. A specific value of 010 of D4-
D6 is desirable for turning on the oscillator.

5. In DS12887, which out of the following is correct about the SQW pin?

a) it is an output pin
b) it can provide up to 15 different square waves
c) the frequency of the square wave is set by the register A
d) all of the mentioned are correct
Answer: d
Explanation: In DS12887, SQW pin stands for SQuare Wave. It is an output pin that can provide us with 15 differen
t square waves. The frequency of the square wave is selected by programming register A.

6. In DS12887, what is correct about the UIP bit of the register A?

a) it is a read only bit

b) it is used to know about the result
c) it is used to select the DS12887 datasheet
d) all of the mentioned
Answer: a
Explanation: In DS12887, UIP bit of register A stands for Update In Progress. The update-in-progress (UIP) bit is a
status flag i.e. read-only bit.

7. In DS12887, what is the range of RAM addresses which are used to store the values of time, calendar and alarm d
ata?

a) 00-7FH
b) 00-09H
c) 0EH-7FH
d) 0A-0DH
Answer: b
Explanation: In DS12887, the first ten locations i.e. 00-09H are used to store the values of time, calendar and alarm
data.

8. Is DS12887 has non-volatile RAM?

a) Yes
b) No
c) Can’t be determined
d) None of the mentioned
Answer: a
Explanation: Yes, DS12887 has non-volatile RAM.

9. Name the read only registers are present in the DS12887?

a) register A, register B
b) register B, register C
c) register C, register D
d) register D, register A
Answer: c
Explanation: Register C and D are the read only registers in the DS12887 found at memory locations 0C-0DH.

10. In DS12887, when the external source is turned-off, how does DS12887 get power to retain its data?

a) Internal Lithium Battery

b) Internal Lead Battery
c) Additional external Alkaline Battery
d) Additional external Lithium Battery
Answer: a
Explanation: When Vcc falls below 3V or external voltage source is switched-off, internal lithium battery provides p
ower to DS12887. And this will prevent loss of data.

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1. What is the principle on which electromagnetic relays operate?

a) electromagnetic induction
b) motor control
c) switching
d) none of the mentioned
Answer: a
Explanation: Electromagnetic relays work on the principle of electromagnetic induction. It is used as a switch in ind
ustrial controls, automobile and appliances. It allows the isolation of the sections of a system with two different volt
age sources.

2. What are DPDT relays?

a) Single pole, single throw

b) Single pole, double throw
c) Double pole, double throw
d) None of the mentioned
Answer: c
Explanation: In DPDT relay, there are two poles and two throws (i.e.contacts). For each pole there are two contacts i
.e. normally open (NO) and normally closed (NC). The contacts can be NO or NC. Generally, contact is NC when th
e coil is not energized. When the coil is energized both poles become NC.

3. Why do we need a ULN2803 in driving a relay?

a) for switching a motor

b) for increasing the current
c) for increasing the power
d) for switching the voltage
Answer: b
Explanation: We need a ULN2803 for driving a relay because the relay coil requires 10mA or more current to be en
ergized. If microcontroller pins are not able to provide sufficient current to drive relays then we need ULN2803 for
driving relays.

4. Why are solid-state relays advantageous over electromechanical relays?

a) they need zero voltage circuit

b) they need less current to be energised
c) they need less voltage to be energised
d) none of the mentioned
Answer: b
Explanation: Solid-state relays are advantageous over electromechanical relays because their switching response tim
e is much faster than electromechanical relays as solid-state relays are made-up of semiconductor materials. Also, so
lid-state relays required low input current for operation and small packaging make them ideal for microcontrollers.

5. What are optoisolators?

a) it is a driver
b) it is a thing isolated from the entire world
c) it is a device that can be used as an electromagnetic relay without a driver
d) none of the mentioned
Answer: c
Explanation: Optoisolators are devices that can be used as an electromagnetic relay without a driver. It usually consi
sts of a led (transmitter) and a photoresistive receiver.

6. How can we control the speed of a stepper motor?

a) by controlling its switching rate

b) by controlling its torque
c) by controlling its wave drive 4 step sequence
d) cant be controlled
Answer: a
Explanation: Speed of a stepper motor can be controlled by changing its switching speed or by changing the length o
f the time delay loop.

7. Which of the following can be a unit for torque?

a) kg/m2
b) ounce-inch
c) kg-m3
d) g/m
Answer: b
Explanation: Torque is equal to the force applied at a particular distance. So its unit can be ounce-inch.

8. The RPM rating given for the DC motor is for?

a) no-loaded
b) loaded
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: RPM rating given for a DC motor is for a no-loaded condition.

9. How can we change the speed of a DC motor using PWM?

a) By changing amplitude of PWM

b) By keeping fixed duty cycle
c) By changing duty cycle of PWM
d) By increasing power of PWM
Answer: c
Explanation: We can change the speed of a DC motor using PWM by changing the duty cycle of PWM. Changing d
uty cycle means changing ON and OFF timing of PWM. Even if amplitude of PWM is fixed by increasing the ON ti
me of PWM increases the speed of the DC motor.

10. How can the direction of the DC motor be changed?

a) by changing the torque

b) by changing the switching speed
c) by changing the polarity of voltages connected to the leads
d) by changing the RPM rating
Answer: c
Explanation: The direction of the DC motor can be changed by changing the polarity of the voltages connected to its
leads.

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1. Is the following instruction correct LDI R3,50?

a) Yes
b) No
c) Cant be said
d) None of the mentioned
Answer: b
Explanation: If LDI Rd,k is written then the range of Rd varies from R16-R31, as R3 is less than R16 so this instruct
ion will generate an error.

2. Registers R0-R31 are used for what type of works?

a) they are used for arithmetic and logic instructions

b) they are used for data copy
c) they are used for calculations
d) none of the mentioned
Answer: a
Explanation: GPRs are used for implementing arithmetic and logic instructions in the controller. They do the same
work as the accumulator does in the other microcontrollers and microprocessors.

3. The largest value that can be loaded in an 8 bit register is?

a) 11111111H
b) FH
c) FFH
d) 00H
Answer: c
Explanation: The largest value that can be loaded in an 8 bit register is 11111111b or FFH.

4. The total space for the data memory available in the AVR based microcontroller is?

a) FFH
b) FFFH
c) FFFFH
d) FFFFFH
Answer: c
Explanation: The maximum value that can be loaded in the code memory of an AVR based microcontroller is FFFF
H.

5. Which of the following instructions affect the flags of the status register?

a) AND
b) INC
c) OR
d) All of the mentioned
Answer: d
Explanation: AND, INC, OR could affect status register flags. All arithmetic and logical instructions affect status re
gister flags except SER Rd instruction. SER Rd is used to SEt Register i.e. after the execution of this instruction Rd l
oaded with FFH value and no flag is affected.

6. What is the difference between the two given instructions?

a) One copies the hexadecimal value to R16 and the other copies the decimal value to the R16 register
b) One is for command, other is for data
c) One is for assignment, other is for operations
d) Both the commands are the same
Answer: d
Explanation: Both the above commands are the same. They both are used for assigning the hexadecimal values to th
e registers.

7. Which out of the following is not a directive?

a) .EQU
b) .DEVICE
c) .ORG
d) .LDI
Answer: d
Explanation: .EQU, .DEVICE, .ORG all are the directives to the assembler whereas LDI is a command.

8. Is an assembly language a high level language?

a) Yes
b) No
c) Can’t be said
d) None of the mentioned
Answer: b
Explanation: Assembly language is not high level language rather it is low level language because it deals directly w
ith the internal structure of CPU. To program in assembly, the internal structure of the CPU must be known. Wherea
s in high level programming languages programmers don’t bother about the internal structure of the CPU because th
is is done by the compiler.

9. A 14-bit program counter can access __________ bytes of memory locations.

a) 4K
b) 8K
c) 16K
d) 64K
Answer: c
Explanation: A 14-bit program counter can access 214 bytes of memory locations i.e. 16k bytes.

214 = 24 x 210

a) 00H
b) 000H
c) 0000H
d) 00000H
Answer: d
Explanation: When an AVR wakes up, then the PC starts at the memory location 00000H.

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1. Which of the following is correct about BRNE instruction in avr microcontrollers?

a) it is used to compare two registers

b) it is used to compare two values
c) it is used to check the zero flag
d) it is used to jump to the given mentioned label when the zero flag accounts to 0
Answer: d
Explanation: BRNE label instruction is used to jump to that particular address denoted by label if condition (Z=0) is
true or satisfied. If the condition is not satisfied then it will execute the next immediate instruction.

2. How many times is this loop going to get executed?

a) 10
b) 70
c) 700
d) none of the mentioned
Answer: b
Explanation: As the R21 register is loaded with 70, so to make it zero it needs to be decremented 70 times then only
the OUT instruction will be executed so this loop repeats 70 times.

3. Which of the below mentioned are not the conditional jumps?

a) BRLO
b) BRMI
c) BRVC
d) None of the mentioned
Answer: d
Explanation: BRLO is used to branch if C=1, BRMI is used when N=1 and BRVC are used when V=0, so all are the
conditional jumps.

4. What is the relation between the target and the relative address?

a) target address= PC address + relative address

b) target address= relation address*2
c) relative address= PC address + target address
d) none of the mentioned
Answer: a
Explanation: Target address can be calculated by calculating the sum of the address of the program counter and the r
elative address.

5. In the JMP instruction, how many bits are there for determining the target address?

a) 16
b) 32
c) 22
d) 10
Answer: c
Explanation: In the JMP instruction of 4 bytes space, 22 bits are there for determining the target address and the othe
r 10 are for the op code verification.

6. Which of the following statements are correct?

a) relative address of RJMP instruction varies from 000-fffH

b) target address of JMP instruction varies from 000000-3fffffH
c) IJMP instruction jumps to that address that points to by the Z register
d) all of the mentioned
Answer: d
Explanation: The relative address of the RJMP instruction varies from 000-fffH. The target address of the JMP instr
uction varies from 000000-3fffffH. IJMP instruction is used to jump at that particular address pointed to by the Z reg
ister. So all are the correct statements.

7. Which of the following is used to represent the last RAM address?

a) MEM
b) LASTRAM
c) RAMEND
d) None of the mentioned
Answer: c
Explanation: RAMEND is a micro used to represent the last RAM address. In AVR, Stack Pointer is initialized on t
op of the stack i.e. last address of RAM.

8. Which of the following statements are correct about the RCALL instruction?

a) it is a 2 byte instruction
b) it is a 4 byte instruction
c) it is a 16 byte instruction
d) none of the mentioned
Answer: a
Explanation: RCALL instruction is used to go to the target address in the memory from -2048 to 2047.

9. On power on SP points to the address?

a) ffffH
b) fffH
c) 00h
d) all of the mentioned
Answer: c
Explanation: On power on SP register points to the 00H address.

10. Which of the following statements is true?

a) CALL instruction is used to transfer control anywhere in the 4M memory space

b) PUSH instruction is used to take out the value from the stack into some register
c) POP instruction is used to jump to any location
d) RCALL is a 4 byte instruction
Answer: a
Explanation: CALL instruction is used to transfer control anywhere in the 4M memory space available in the AVR.

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1. In AVR, which registers are there for the I/O programming of ports?

a) PORT
b) PIN
c) DDR
d) All of the mentioned
Answer: d
Explanation: For I/O programming of the ports in AVR microcontrollers, there are basically three main registers. Th
ey are PORT, PIN, DDR, so all of the mentioned is the right option.

2. The data will not go from the port registers to the pin unless:

a) DDR register of that port is set to 0

b) PORT register of that port is set to 1
c) DDR register of that port is set to 1
d) PORT register of that port is set to 0
Answer: c
Explanation: The data will not go from the port registers to the pin unless the DDR register of that port is set to 1 be
cause by doing this we make that port an output port after which data can be taken from the PORT registers to the pi
n.

3. On reset DDR registers of all ports are set to:

a) 0
b) 1
c) None of the mentioned
d) 0 & 1
Answer: a
Explanation: On reset, the DDR registers of all the ports are set to 0 which means that the by default all ports are set
as input ports.

4. Which of the following statements are correct?

a) PIN register of a port is used to bring data into CPU from pins
b) PORT register is used to send data out to pins
c) DDR register is used to control the direction of a port
d) All of the mentioned
Answer: d
Explanation: There are three registers that are related to a port. They are PIN, PORT, DDR. PIN register is used to b
ring data into CPU from pins, PORT register is used to send data to pins and DDR register is used to control the dire
ction of the data transfer. So all are the right options.

5. In the AVR family, all I/O ports have 8 pins?

a) true
b) false
c) none of the mentioned
d) can’t be determined
Answer: b
Explanation: In the AVR family, all I/O ports don’t have 8 pins. Number of I/O pins depends on the total number of
pins of the controller. Eg. ATtinyxx is an 8 pin controller and it has 6 I/O pins.

6. Which of the following is not a single bit instruction in AVR?

a) SBI
b) PORT
c) CBI
d) All of the mentioned
Answer: b
Explanation: PORT is not an instruction. It is the name of a register in AVR.

7. Which of the following is correct about the SBIS instruction?

a) it is used to monitor status of bit in I/O register

b) it is a byte oriented instruction
c) It is a 4 byte instruction
d) all of the mentioned
Answer: a
Explanation: SBIS (Skip if Bit in I/O register Set) is used to check status of bit in I/O register. If the bit mentioned in
the instruction is SET or HIGH then the controller will skip the immediate next instruction.

8. Instruction CBI PORTB,1 means

a) clearing the PORTB register

b) clearing the first bit of the PORTB register
c) setting the PORTB register
d) setting the first bit of the PORTB register
Answer: b
Explanation: CBI PORTB, 1 means to clear the first bit of the PORTB register. It is a bit oriented instruction.

9. Which of the following instruction can be used to toggle a bit of the PORT?

a) SBI
b) CBI
c) SBI & CBI
d) None of the mentioned
Answer: c
Explanation: If SBI and CBI are used together, then they can be used to toggle a bit of a port successfully.
10. What is the main function of the SBIC instruction?

a) it is used to clear a particular bit of a port

b) it is used to jump unconditionally
c) it is used to skip the instruction if a particular bit of a port is zero
d) none of the mentioned
Answer: c
Explanation: SBIC (Skip if Bit in I/O register Clear) is used to check status of bit in I/O register. If the bit mentioned
in the instruction is CLEAR or LOW then the controller will skip the immediate next instruction.

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1. In AVR microcontrollers, ADD instruction affects the status of which of the following bits of a status register?

a) Z
b) C
c) N
d) All of the mentioned
Answer: d
Explanation: ADD instruction affects the status of Z, C, N, V, H and S bits of a status register.

2. ADC instruction is used for?

a) addition of two 16 bit numbers

b) analog to digital conversion
c) automatic digital control
d) none of the mentioned
Answer: a
Explanation: ADC instruction can be used for addition of two 16 bit numbers as here two 8 bit numbers are added si
multaneously along with the carry coming from the previous 8 bits. So it can be used for the addition of two 16 bit n
umbers.

3. AVR supports which of the following mentioned subtraction instructions?

a) SUB
b) SBC
c) SUBI
d) All of the mentioned
Answer: d
Explanation: AVR supports five types of subtraction instructions. They are SUB, SBC, SUBI, SBCI, SBIW.

4. What steps are involved when we subtract two numbers present at two different locations?

a) take the two’s complement of the subtrahend

b) add it to the minuend
c) invert the carry
d) all of the mentioned
Answer: d
Explanation: When we need to subtract two numbers present at two different locations then firstly we need to take th
e 2’s complement of the subtrahend, then we add it with the minuend and then when we invert the carry then the co
mplete procedure of the subtraction is completed.

5. In executing subtraction based instructions, state the role of the C flag?

a) if C=1, the result is negative
b) if C=1, the result is positive
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: If the C flag comes out to be 1, then the result is assumed to be negative and vice versa.

6. Which of the following is correct about the MUL instruction?

a) it is a byte-by-byte multiplication instruction

b) the product is stored in two registers R1 and R0
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: MUL instruction is a byte-by-byte multiplication instruction whose result is stored in two registers R1
and R0.

7. In AVR, when is the V flag set?

a) there is a carry from D7 bit

b) there is a carry from D6 to D7 bit
c) when carry is generated only from D6 to D7 or carry is generated only from D7
d) none of the mentioned
Answer: c
Explanation: In AVR, V i.e. Overflow flag is set when carry is generated only from D6 to D7 or carry is generated o
nly from D7. Overflow flag is used to detect errors in signed arithmetic operations.

8. To set the bits of a register R1 to 1, we must OR the contents of the register with?

a) 00H
b) 11H
c) FFH
d) 0FH
Answer: c
Explanation: To make the contents of the register R1 to 1 we must OR the contents of that register with FFH becaus
e according to Or algorithm 0+1=1 and 1+0=1.

9. CP instruction alters the value of the register?

a) true
b) false
c) none of the mentioned
d) can’t be said
Answer: b
Explanation: CP command is used to compare the contents of the two registers. It doesn’t actually alter the value of t
he register.

10. What is right about the ROR instruction?

a) it rotates the contents of the register left to right

b) it rotates the contents of the register from right to left
c) it rotates the contents of the register from left to right through carry
d) it rotates the contents of the register from right to left through carry
Answer: c
Explanation: ROR instruction is used to rotate the contents of the register from left to right through carry.

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1. In AVR, which of the following registers are not used for programming timers?

a) TCNT
b) TCON
c) TIFR
d) None of the mentioned
Answer: b
Explanation: In the timer programming of an AVR microcontroller, mainly used registers are TCNTn that stores the
values of the count. TCCRn that is used to assign the mode of operation of a timer and TIFR that stores the status of
various flags of the timers. Two more registers are used they are OCRn and OCFn. They are used for comparison wi
th the count register.

2. What is the use of the prescalar in the operation of the timer?

a) for fast calculations

b) for increasing the time delay given by the timer by decreasing its frequency of operation
c) for removing the concept the reloading of count
d) for easy counter operations
Answer: b
Explanation: Prescalars are used in the operation of the timers because they generally increase the time delay generat
ion by decreasing the frequency of its operation.

3. What modes are generally used in the operation of the timer0?

a) Normal mode
b) CTC mode
c) PWM mode
d) All of the mentioned
Answer: d
Explanation: Modes of a timer are decided by the WGM00 and WGM01 bit of the TCCR0 register and for timer0 th
ese modes are normal mode, CTC mode, pwm mode and the fast pwm mode.

4. Timer 0 can act as a counter ____________

a) if the CS02-CS00 are 110 or 111

b) if the FOC0 bit is set to 110
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: Timer0 can act as a counter if the CS02-CS00 bits are from 110-111.

5. Which of the timer can operate in the 16 bit condition?

a) timer0
b) timer1
c) timer2
d) all of the mentioned
Answer: b
Explanation: Timer0 and Timer2 can operate in the 8 bit condition while only Timer 1 operates in the 16 bit conditio
n.

6. Which of the following will generate the maximum time delay?

a) f/2
b) f/4
c) f/16
d) f/32
Answer: d
Explanation: f/32 has the lowest frequency as it is divided by the maximum value of the constant, so as time and fre
quency are inversely related to each other so this will generate the maximum amount of machine cycle which will as
a result generate the greatest delay.

7. What is the difference in the operation of a normal and a CTC mode of a timer?

a) in CTC mode PWM is used

b) here serial timer is monitored
c) in CTC mode, timer counts up until contents of TCNT register becomes equal to the contents of OCR
d) none of the mentioned
Answer: c
Explanation: In CTC mode, timer counts up until the contents of TCNT register becomes equal to the contents of O
CR; then the timer will be cleared and the OCF0 flag will be set when the next clock occurs. In Normal mode, timer
counts until max i.e. 0xFFH. When it rolls over from 0xFFH to 0x00H, it sets TOV(Timer Overflow).

8. We can count the pulses on the positive or the negative edge triggered pulse of the clock?

a) true
b) false
c) can’t be determined
d) depends on the circumstances
Answer: a
Explanation: A counter can count pulses on the positive or the negative edge of the clock.

9. Which pin is used for the input clock of the counter0?

a) PORTB.0
b) PORTB.1
c) PORTB.2
d) PORTB.3
Answer: a
Explanation: In ATmega32/16, T0 is the alternative function of PORTB.0. T0 is Timer/Counter 0 External Clock In
put.

10. Which resource provides the clock pulse to AVR timers if CS02-00=6?

a) internal clock of the AVR

b) external clock of the AVR
c) none of the mentioned
d) all of the mentioned
Answer: b
Explanation: The External clock is used for providing the pulse to the AVR timers if CS02-00=6.
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1. On reset, what are the contents of the SREG register?

a) 00h
b) ffh
c) 1fh
d) 11h
Answer: a
Explanation: On reset, all the interrupts are masked and so the contents of the SREG register is also set to zero as it s
hows the status of the flags.

2. TIMSK register is used for?

a) knowing the status of the timer count

b) used for masking the interrupts flags of the Timer0, Timer1 and Timer2
c) it is used for enabling all the timer interrupts
d) it is used for resetting the value of the interrupts
Answer: b
Explanation: TIMSK is used for masking the interrupt flags of the timers. They mask the bits of the timer flags if the
D7 bit of the SREG register is set to 1 or when firstly all interrupts are enabled.

3. Why RETI instruction be the last instruction of ISR?

a) because it returns with carry

b) because it returns to the main program with all the flags of the SREG raised
c) because it returns to the main program where interrupt is generated and set the global interrupt enable bit in SRE
G
d) none of the mentioned
Answer: c
Explanation: When an interrupt occurs, the global interrupt enable bit is cleared. If global interrupt enable is cleared
it means interrupts are disabled. RETI instruction must last instruction of ISR because it returns to the main program
where interrupt is generated and sets the global interrupt enable bit in SREG.

4. In AVR what is the ISR address for an external hardware interrupt?

a) 0002h
b) 0004h
c) 0006h
d) all of the mentioned
Answer: d
Explanation: The ISR addresses for the external hardware interrupts are 0002h, 0004h, 0006h.

5. What is the address in the interrupt service routine assigned for the timer0 overflow flag?

a) 0012h
b) 000Ah
c) 0016h
d) all of the mentioned
Answer: c
Explanation: 0016h is the address in the interrupt service routine assigned for the timer0 overflow flag.

6. Is the same address is assigned for the timer0 and timer1 overflow flag in the interrupt vector table of the interrupt
s?
a) true
b) false
c) can’t be determined
d) depends on the situation
Answer: b
Explanation: Different addresses are assigned for Timer0 and Timer1 overflow flags in the interrupt vector table. Th
ey are 0016h and 0012h for timer0 and timer1 respectively.

7. External hardware interrupts are assigned to which pins of the atmega32?

a) PORTD.2
b) PORTD.3
c) PORTB.2
d) All of the mentioned
Answer: d
Explanation: There are three external hardware interrupts in the atmega32 microcontrollers. They are assigned to bit
s PORTD.2, PORTD.3 and PORTB.2.

8. Which register is responsible for handling all the external hardware interrupts?

a) TIMSK
b) GICR
c) MCUCR
d) IVCE
Answer: b
Explanation: GICR register is responsible for all the external hardware interrupts in the AVR.

9. By default, INT0-INT2 interrupts are?

a) edge triggered
b) level triggered
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: By default, INT0-INT2 are the level triggered pulses. The low level of the pulse generates the interrupt
.

10. What will happen in that condition, if an interrupt occurs while the microcontroller is serving any other interrupt
?

a) both the interrupts will be handled simultaneously

b) the interrupt which is being done first will be served first
c) the interrupt that is more priority in the interrupt vector table will be served first
d) the interrupt having low priority in the interrupt vector table will be served first
Answer: c
Explanation: If two or more interrupts occur simultaneously then the interrupt that is having more priority in the inte
rrupt vector table will be served first.

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1. What actually are the DB9, DB25 ports available in our computers?
a) they are connectors used to transfer data either serially or parallelly
b) they are the RS232 connectors used to connect two incompatible devices
c) they are the TTL logic connector pins used for communication
d) they are just data transfer pins used to transfer the data
Answer: b
Explanation: DB9 and the DB25 ports are the ports that are based on the RS232 logic that is basically used for com
municating two incompatible devices.

2. What does RI handshaking signal refer to according to the RS232 logic?

a) if this logic is high then a receive interrupt is generated

b) this pin is high during transmission
c) this pin is high during a reception in order to tell that the device is busy at this particular time
d) none of the mentioned
Answer: c
Explanation: RI pin of the RS232 logic tells us about the ring indicator i.e it sends a busy signal if the device is curre
ntly receiving any data.

3. What is the major difference between a MAX232 and a MAX233 device?

a) one has one serial port other has two

b) one has inbuilt UART other doesn’t have that
c) one needs some additional circuitry to operate while the other doesn’t have that
d) one is used just for transmission while the other is used for both transmission as well as reception
Answer: c
Explanation: MAX232 needs some extra capacitors at pins like 1,2 and 3,4 while on the other hand MAX233 has th
at inbuilt capacitors built inside it only.

4. Which of the following is correct about the baud rate during serial transmission?

a) it tells us about the speed at which the transmission is going to place

b) it tells us about the number of bits transferred during a second
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: Baud Rate tells us about the speed in which the transmission is being done and this speed is measured i
n terms of bits per second.

5. With fosc=8 MHz, what will the count that has to filled in the UBRR register to account for the 9600 baud rate?

a) 67H
b) CEH
c) 33H
d) 34H
Answer: c
Explanation: The count that had to be filled in the UBRR register is calculated as (fosc/16(desired baud rate))-1.

6. The USART in AVR based microcontrollers operate at which of the following modes?

a) double speed asynchronous mode

b) master synchronous
c) slave synchronous
d) all of the mentioned
Answer: d
Explanation: The USART in AVR consists of the following modes. They are the normal asynchronous mode, doubl
e speed asynchronous mode, slave synchronous and the master synchronous mode.

7. Which bit of the UCSRA is used for doubling the baud rate of the transmission?

a) DOR
b) PE
c) U2X
d) MPCM
Answer: c
Explanation: U2X bit of the UCSRA is used for doubling the baud rate of the transmission.

8. What is the use of the PE and the FE bits of the UCSRA register?

a) they are used for keeping a check at the speed of transmission and reception
b) they are used for keeping a check at the data bits to be transferred
c) they are used to keep the transmission error free
d) they are used as extra redundant bits with no use
Answer: c
Explanation: PE and the FE bits of the UCSRA register are used for error checking in the transmission.

9. Which of the following bits are used for setting the data frame size?

a) UCSZ0
b) U2X
c) DOR
d) MPCM
Answer: a
Explanation: UCSZ0 and UCSZ1 bits of the UCSRB register and the UCSZ2 bit of the UCSRC register are used for
setting the data frame size in AVR based microcontrollers.

10. Which of the following parameters should the transmitter and the receiver agree upon before starting a serial tran
smission?

a) baud rate
b) frame size
c) stop bit
d) all of the mentioned
Answer: d
Explanation: Before starting the serial transmission, the following parameters should be taken care of. They are the b
aud rate, frame size, stop bit and the parity bit.

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1. In AVR, the LCD operates in two main modes, it can be in 8 bit or 4 bit data.

a) true
b) false
c) depends on the situation
d) can’t be said
Answer: a
Explanation: In AVR, the LCD operates in two main modes, they are in the 8 bit data transfer mode and the 4 bit dat
a transfer mode.
2. What can be the sequence of commands that may be used for initializing an LCD?

a) 0x06, 0x0e, 0x01

b) 0x0e, 0x01, 0x80
c) 0x38, 0x0e, 0x01
d) all of the mentioned
Answer: c
Explanation: For initializing an LCD, we can use commands like 0x38 for selecting the 5*7 matrix, 0x0e for display
on and the cursor blinking and 0x01 for clearing the screen.

3. When the LCD operates in the 4 bit mode, then what more commands are added to it?

a) 33
b) 32
c) 28
d) all of the mentioned
Answer: d
Explanation: When an LCD operates in the 4 bit mode than 33, 32, 28 in hex are sent to it. They represent 3, 3, 3, 2
nibbles which tell the LCD to do into the 4 bit mode for saving the i/o pins of the port.

4. What is the main function of the LPM instruction used in LCD?

a) for initializing the LCD in the read mode

b) for initializing the LCD in the write mode
c) for sending a long string of characters to the LCD
d) all of the mentioned
Answer: c
Explanation: LPM instruction is used for sending a long string of characters to the LCD.

5. The RS pin acts as an

a) input pin
b) output pin
c) any of the mentioned depending on the conditions
d) none of the mentioned
Answer: a
Explanation: The RS pin of the LCD is used for selecting a particular register used for sending a command or the dat
a to the LCD.

6. To latch in information at the data pins of the LCD, we send

a) H-L pulse at the E pin

b) L-H pulse at the E pin
c) A constant H pulse at the E pin
d) A constant L pulse at the E pin
Answer: a
Explanation: For latching in information at the data pins of the LCD, we send a H-L pulse at the LCD.

7. What is the function of the 0x06 command?

a) to clear the LCD

b) to blink the cursor
c) to shift the cursor to the right
d) for selecting the matrix
Answer: c
Explanation: 0x06 command is used for shifting the cursor to the right after every data send to it.

8. What is the address of the second column and the second row of the 2*20 LCD?

a) 0x80
b) 0x81
c) 0xc0
d) 0xc1
Answer: d
Explanation: 0xc0 acts as the address for selecting the second row and the first column of the LCD, so according to i
t if we need to select the second row and the second column of the LCD, then the address should be 0xc1.

9. Which of the following commands takes more than 100 microseconds to run?

a) shift cursor left

b) shift cursor right
c) set address location of the DDRAM
d) clear screen
Answer: d
Explanation: Clear screen is a command that takes more than 100 microseconds to run.

10. For selecting the data pins in an LCD, RS pin should be

a) 1
b) 0
c) F
d) 10
Answer: a
Explanation: For selecting the data pins of the LCD, the RS pin of the LCD should be set to 1.

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1. In reading the columns of a keyboard matrix, when no key is pressed then all the pins show?

a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: When no key is pressed, in a keyboard then all the pins will read 1 as they all are connected to the main
power supply.

2. To see if any key is pressed, all rows are grounded.

a) true
b) false
c) can’t be said
d) depends on the conditions
Answer: a
Explanation: To see that whether any key is pressed or not then all the rows are grounded so that columns can be rea
d to deliver the better results.
3. Identify the row and the column for the following case when for the row D3-D0= 1110 and for the column D3-D0
= 1101

a) first row and second column

b) first row and third column
c) second row and first column
d) second row and second column
Answer: a
Explanation: To identify the key that is pressed from this particular combination, we obtain that the key belongs to t
he first row and the second column as the D0 bit of the row port and the D1 bit of the column port are zero.

4. What are the actual steps that are followed in identifying any key that is being pressed?

a) wait for the debounce time

b) identify the key that is pressed
c) initially no key should be pressed
d) all of the mentioned
Answer: d
Explanation: In order to identify that which key is actually pressed form a particular format of a 3*3 matrix keyboar
d, we firstly ensure all initially all the keys are open, then we press a key and check that whether the key is actually
pressed or not by waiting for a time span of 20mseconds, after this we identify the key that is pressed by masking th
e bits of the port. In this particular format, we can identify the key that is actually pressed.

5. To identify that the key is present in which row and the column

a) we ground the bits of the row one by one

b) we ground the bits of the column one by one
c) we connect the bits of the row to the logic level 1 one by one
d) we can connect the columns to the logic level 1 one by one
Answer: a
Explanation: To determine that the pressed key is in which row and column, we ground the rows one by one to deter
mine the column by masking the bits separately.

6. The key detection and the key identification are two different procedures?

a) true
b) false
c) depends on the circumstances
d) difficult to tell
Answer: a
Explanation: The key detection and the key identification are the two different procedures, one is used to detect that
whether any key is pressed or not and the other technique is used to find that the pressed key is located in which row
and column.

7. What is described by the following command?

a) load KCODE0 with 0

b) rotate the contents of the KCODE0 register to the right
c) rotate the contents of the KCODE0 register to the left
d) none of the mentioned
Answer: b
Explanation: KCODE0<<1 means to rotate the contents of the KCODE0 register to the left after every loop.
8. If the pins of the keyboard are used as an interrupt, then these pins will cause an interrupt of what type?

a) External hardware interrupt

b) Timer interrupt
c) TI/RI interrupt
d) None of the mentioned
Answer: a
Explanation: The pins of the keyboard act as an external hardware interrupt as some external pulse is helping in gene
rating this interrupt.

9. What will happen if the two keys of the keyboard are pressed at a time?

a) both the keys will be displayed on the screen

b) the key which is being actually pressed(for more then 20microseconds) will be displayed
c) the key that is pressed first will be displayed
d) none of the mentioned
Answer: b
Explanation: If two or more keys are pressed at a time, then the key that will be pressed for more then 20 microseco
nds will be displayed on the screen.

10. Why initially all keys are considered open before detecting the key pressed?

a) to make the task easy

b) to remove the errors caused by other pressing keys during detection
c) to remove the flow problems
d) none of the mentioned
Answer: b
Explanation: Initially all keys are considered open in order to ensure the accuracy while identification of the pressed
key.

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1. Which of the following is correct about the word resolution in ADC DAC converters in AVR’s?

a) it is the smallest change that can be described by an ADC

b) it is equal to Vref/2n (where n represents the number of bits)
c) it is 0.076mV or 76uV for n=16 and Vref=5V
d) all of the mentioned
Answer: d
Explanation: Resolution is defined as the smallest change in the step size that is described by an ADC, it is equal to
Vref/2n.

2. In an ADC, we can calculate the output voltage from the formula

a) Step size / Vin

b) Step size * Vin
c) Vin / step size
d) Vref / step size
Answer: c
Explanation: The output voltage can be calculated by using the formula Vin / step size.

3. ADC0848 is a ____________ bit converter?

a) 16
b) 4
c) 8
d) 48
Answer: c
Explanation: ADC0848 is a 8 bit converter.

4. Which of the following factors can affect the step size calculation?

a) number of bits
b) input current
c) output current
d) all of the mentioned
Answer: a
Explanation: There are mainly two factors that can affect the step size calculation of an ADC converter, they are the
number of bits and the Vref voltage.

5. MAX1112 is a _________ type of ADC converter?

a) parallel
b) 12 bit
c) serial
d) all of the mentioned
Answer: c
Explanation: MAX1112 is a serial ADC converter, as it has only one pin for the data output.

6. Why do we connect a capacitor between the Vref and the Gnd pin?

a) to remove the leakage

b) to ensure more current at that place
c) to make more Vref
d) to make Vref stable and also to increase the precision of the ADC
Answer: d
Explanation: A capacitor is connected between the Vref and the Gnd pin in order to stabilize the Vref value and also
to increase the precision of the ADc converter.

7. Which of the following are the registers that are used for controlling the ADC conversion in the AVR?

a) ADCSRA
b) ADMUX
c) SPIOR
d) All of the mentioned
Answer: d
Explanation: For programming the ADC conversion in an AVR, we require the following registers. They are ADCS
RA, ADMUX, SPIOR. There are two more registers used for handling the output data, they are ADCH and ADCL r
egisters.

8. What is the internal Vref of an Atmega32 series?

a) 5V
b) 3.3V
c) 2.56V
d) all of the mentioned
Answer: c
Explanation: 2.56V is the internal Vref selected for an Atmega32 series based microcontrollers.

9. The output of a DAC0808 is in the form of ____________

a) electrical pulse
b) current
c) voltage
d) all of the mentioned
Answer: b
Explanation: The output of a DAC0808 is in the form of a current.

10. In a DAC the input is ______ and the output is ______

a) analog, digital
b) current, voltage
c) digital, analog
d) analog, current
Answer: c
Explanation: In a DAC, the input is digital and the output is analog in nature.

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1. Which of the following is correct about the word sensors?

a) that senses something

b) it is a type of a transducer that converts one form of energy to another
c) it can produce output in the form of electrical pulses, current or voltage
d) all of the mentioned
Answer: d
Explanation: Sensors are the devices that are used to sense a particular thing by converting one form of energy into a
nother, this converted form can be in the form of some analog output, or in the form of current or the voltage as the c
ase may be.

2. Why do we need to apply the concept of signal conditioning to a sensor?

a) in order to convert it into a desirable form of energy

b) for testing
c) for sensing something
d) all of the mentioned
Answer: a
Explanation: Signal Conditioning is the concept that is used for data acquisition of the signal. For measuring and ana
lyzing this value at a practical stage, by converting it into a desirable form of energy.

3. Which of the following is correct about LM35 based sensors?

a) its output voltage is directly proportional to the Celsius scale

b) its output voltage is directly proportional to the Fahrenheit scale
c) none of the mentioned
d) all of the mentioned
Answer: a
Explanation: LM35 based sensors are those sensors whose output voltage is directly proportional to the Celsius scale
.
4. What is the difference between the LM34 and the LM35 based sensors?

a) one requires external calibration while other does not

b) one has output voltage proportional to the Celsius scale while others have to the Fahrenheit scale
c) one is fast other is slow
d) all of the mentioned
Answer: b
Explanation: LM35 has the output voltage proportional to the Celsius scale while the LM35 based sensors have outp
ut voltage proportional to the Fahrenheit scale.

5. Every transducer must be connected with the signal conditioning circuit?

a) true
b) false
c) can’t say
d) depends on the conditions
Answer: a
Explanation: For analyzing purposes, every transducer must be connected to a signal conditioning circuit in order to
measure its value as a practical platform.

6. LM35 provides _______ V for each degree count?

a) 1
b) 0.1
c) 0.001
d) 10
Answer: c
Explanation: LM35 provides 10mV for every degree change of the Celsius scale.

7. Why for the 8 bit analog input we select Vref as the 2.56V?

a) to obtain each degree count as the 2.56V

b) to get 2.56V at the output
c) to obtain each degree count as the 10mV
d) to get 10mV as the output
Answer: c
Explanation: For an 8 bit analog input, each degree count is calculated as the Vref/256, so if Vref is selected as 2.56
V then we can obtain 10mV for each degree count of the scale.

8. What is the temperature for LM35 sensor if the analog output is 0011 1001?

a) 3
b) 9
c) 57
d) 41
Answer: c
Explanation: The binary for the above output is 57, so in case of LM35 sensors we obtain the output as 57 C.

9. In an external hardware, there are how many pins available for the LM35 and the LM34 based sensors?

a) 2
b) 3
c) 10
d) 1
Answer: b
Explanation: LM35 consists of mainly 3 pins, they are Vcc, Gnd, analog output.

10. Do LM34 and LM35 based sensors have linear output?

a) yes
b) no
c) depends on the conditions
d) can’t say
Answer: a
Explanation: LM34 and the LM35 based sensors are linearly proportional to their corresponding Fahrenheit and the
Celsius scale, so they are linear by nature.

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1. The 8255 is a ______ chip.

a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Answer: a
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to exp
and the I/O ports of microcontrollers.

2. Which pins of a microcontroller are directly connected with 8255?

a) RD
b) WR
c) D0-D7
d) All of the mentioned
Answer: d
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and
also for transferring the data.

3. Find the control word for PA= out, PB= in, PCL=out, PCH=out (Mode0)?

a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Answer: b
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others a
s the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.

4. Which pins are used to select the ports and the control register?

a) CS
b) A1
c) A0
d) All of the mentioned
Answer: d
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used f
or select ports and the control register.

5. What is the value of the control register when RESET button is set to zero?

a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Answer: d
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is acti
vated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the sam
e as it is even when the RESET button is set to zero.

6. Why MOVX instruction is being used to access the ports of the 8255?

a) because 8255 is connecting a microcontroller in memory mapped I/O configuration

b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Answer: a
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memor
y space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external
memory locations.

7. What is correct about the BSR mode from below?

a) In BSR mode, only the individual bits of PORT A can be programmed

b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Answer: c
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.

8. How many pins of the 8255 can be used as the I/O ports?

a) 8
b) 16
c) 24
d) 32
Answer: c
Explanation: They are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.

9. 8255 is a ____ pin IC.

a) 16
b) 8
c) 40
d) 60
Answer: c
Explanation: 8255 is a 40 pin IC.

10. 8255 has handshaking capability?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: 8255 is a device that with the help of its handshaking property gets interfaced with any microcontroller
.

11. The 8255 can be programmed in any of the __________

a) 2 modes
b) 3 modes
c) 4 modes
d) 5 modes
Answer: c
Explanation: 8255 can be programmed in any of the 4 modes.

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1. RTC is used for __________

a) conversion
b) communication
c) real time and clock measurement
d) memory management
Answer: c
Explanation: RTC is a device that is basically used for all the real time clock related issues.

2. RTC chips use ______ to compute time, date when the power is off.

a) ac supply
b) generators
c) rectifiers
d) battery
Answer: d
Explanation: RTC chips require batteries in order to calculate the time and date when the power of the device is off.

3. DS12887 is known for as a ________

a) Communication device
b) Good battery device
c) RTC chip
d) All of the mentioned
Answer: c
Explanation: DS12887 is known as an RTC chip.

4. DS1307 is a parallel RTC with I2C bus.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: DS1307 is a serial RTC with I2C bus.
5. DS1307 is a _______ pin IC and operates on _______ clock frequency.

a) 16, 8Mhz
b) 8, 16Mhz
c) 16, 32Mhz
d) 8, 32Khz
Answer: d
Explanation: DS1307 is a 8 pin IC and operates on a 32KHz clock frequency.

6. Vbat requires a positive signal of

a) 3V
b) 5V
c) 9V
d) 12V
Answer: a
Explanation: Vbat requires a positive signal of 3V which can be obtained through a battery.

7. In DS1307, which out of the following is correct about the SQW pin?

a) input pin
b) output pin
c) i/o pin
d) none of the mentioned
Answer: b
Explanation: In DS1307, SQW pin is an output pin. It provides a clock of frequency 1khz, 4khz, 8khz, 32khz if the p
in is enabled.

8. DS1307 has a total of _______ bytes of RAM space.

a) 32
b) 64
c) 128
d) 256
Answer: c
Explanation: DS1307 has a total of 64 bytes(00-3F) of RAM space.

9. DS1307 control register has an address of _________

a) 00H
b) 03H
c) 07H
d) 10H
Answer: b
Explanation: DS1307 control register has an address of 07H.

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1. Why are relays used for driving the motors?

a) they can be used as switch as well as they provide isolation

b) they increase the current capability required by the motors
c) they are used to reduce the back emf from the motors
d) all of the mentioned
Answer: a
Explanation: Relay is the electrically controlled switch and it allows isolation of two separate sections of the system.
It has three main components: the coil, the common pole and the contacts. When an electric field is applied to the c
oil; it gets energized and generates a magnetic field which will force the common pole to change contact from Norm
ally Closed to Normally Open.

2. Why are ULN2803 normally used between the microcontrollers and the relays?

a) for switching purposes

b) for increasing the current capability required by a relay
c) for increasing the voltage capability required by a relay
d) all of the mentioned
Answer: b
Explanation: More current is desired for driving a motor with the help of a relay, so a ULN2803 is used for increasin
g the current as per the requirement of the relay.

3. Why are opto isolators normally used between the microcontrollers and the ULN2803?

a) to optimize the current

b) to reduce the back emf
c) to increase the current
d) to increase the voltage
Answer: b
Explanation: Opto isolators are used between the microcontrollers and the ULN2803 chips in order to decrease the b
ack emf from the ULN2803 and to save the microcontrollers for a long time.

4. Which of the following is a type of an electromagnetic relay?

a) SPST
b) SPDT
c) DPDT
d) All of the mentioned
Answer: d
Explanation: There are normally three kinds of electromagnetic relays. They are SPST(single pole single throw), SP
DT(single pole double throw) and the DPDT(double pole double throw) relays.

5. Reed switches show connectivity whenever they are in the presence of an electrical field?

a) true
b) false
c) can’t say
d) depends on the conditions
Answer: b
Explanation: Reed switches are the devices that show connectivity whenever they are in the presence of some magne
tic field.

6. Which of the following is an application of stepper motors?

a) in printers
b) in robots
c) in vehicles
d) all of the mentioned
Answer: d
Explanation: Stepper motors are used wherever there is a need of a movement at an angle, maybe it in printers, in m
otors or in vehicles stepper motors are used everywhere.

7. What are normal 4 step sequence of a stepper motor if we start to move in clockwise direction with 0110 value?

a) 1100,1001,0011,0110
b) 0011,1001,1100,0110
c) 1001,1100,0110,0011
d) 0101,1010,0101,1010
Answer: b
Explanation: For a normal 4 step sequence of a stepper motor, if we start to move in a clockwise direction then we r
otate towards right direction with every rotation.

8. What is the meaning of a step angle?

a) angle which a stepper motor has

b) angle between the two windings of the stator in a stepper motor
c) minimum degree of rotation associated with a single step
d) angle between the stator and the rotor
Answer: c
Explanation: Step angle is the minimum degree of rotation associated with a single step.

9. For a normal 4 step sequence, what are the number of teeth required to accomplish a 2 degree step angle?

a) 180
b) 90
c) 360
d) 45
Answer: d
Explanation: For a 2 degree step angle there will be 180 step per rotation, so the total number of rotor teeth are (180/
4=45).

10. Ounch-inch is a unit of a torque.

a) true
b) false
c) can’t say
d) depends on the situation
Answer: a
Explanation: Torque is a quantity which is obtained by multiplying the amount of force that is applied at a particular
angle. It is measured in terms of ounch-inch.

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1. Why do we make the connection of the SCLK for communicating serially between two devices?

a) to get a clock output from the device

b) to synchronize the two devices
c) to obtain an analog output
d) all of the mentioned
Answer: d
Explanation: We need an SCLK in order for the two devices to communicate with each other properly. It acts as a p
ulse according to which one device sends a message and the other receives it.

2. What is the function of the CE pin in SPI?

a) it is used for synchronization

b) it is used as a transmitting pin
c) it is used as a receiving pin
d) it is used to initiate and terminate the data transfer
Answer: c
Explanation: CE pin is used to initiate and terminate the data transfer in the controller via SPI interface.

3. Which of the following is correct?

a) MOSI has the same meaning as the SDO

b) SCLK is used to initiate and terminate the data transfer
c) In 3 wire SPI, there is only one pin for transmission and reception
d) In 3 wire SPI, there are three pins MOSI, MISO and SCLK
Answer: b
Explanation: In 3 wire SPI, there is only one pin for transmission and reception and the other two pins SCLK and C
E are used for synchronization of data and for initialization and termination of data.

4. If CPHA= 0 and CPOL=1, then which of the following is true?

a) read on rising edge, changed on a falling edge

b) read on falling edge, changed on a rising edge
c) write on rising edge, changed on a falling edge
d) write on rising edge, changed on a falling edge
Answer: b
Explanation: If CPOL= 1 and CPHA= 0, then reading operation is performed on the rising edge and the change occu
rs at every falling edge.

5. In SPI write, LSB goes first?

a) true
b) false
c) can’t be said
d) depends on the cases
Answer: d
Explanation: In SPI write, MSB goes first.

6. In AVR, which of the following registers are used for SPI?

a) SPSR
b) SPCR
c) SPDR
d) All of the mentioned
Answer: b
Explanation: In AVR, SPSR(SPI Status Register), SPCR(SPI Control Register) and SPDR(SPI Data Register) are us
ed for programming the SPI module.

7. How do we set the SPI, to operate in the master mode 1?

a) We set the MSTR bit, and make the CPOL= 1 and CPHA=0
b) We set the MSTR bit, and make the CPOL= 0 and CPHA=1
c) We reset the MSTR bit, and make the CPOL= 1 and CPHA=0
d) We reset the MSTR bit, and make the CPOL= 0 and CPHA=1
Answer: b
Explanation: In SPI, to make it work in the master mode, we make the MSTR bit is equal to 1 and for operating it in
the mode 1 we make the CPOL=0 and CPHA=1.

8. SPI can act as a half duplex transmission?

a) true
b) false
c) depends on the conditions
d) can’t be said
Answer: d
Explanation: No, SPI can’t work in the half duplex transmission mode.

9. Which frequency is not recommended for SPI clock?

a) fosc/4
b) fosc/64
c) fosc/16
d) fosc/2
Answer: a
Explanation: fosc/2 is not recommended frequency for SPI transfer in AVR.

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1. Which of the following is correct?

a) I2C is a technique by which data is transmitted with the help of only eight pins
b) SDA is used to synchronize data transfer between two chips
c) TWI is another name for I2C
d) All of the mentioned
Answer: c
Explanation: I2C is a technique by which data is transmitted between two devices by the help of only 2 pins so it is a
lso called Two wire Serial Interface.

2. Which of the following is true about the I2C protocols?

a) the data line cannot change when the clock line is high
b) the data line can change when the clock line is high
c) the clock line cannot change when the data line is high
d) the clock line can change when the data line is high
Answer: a
Explanation: According to I2C protocols, the data line(SD
a) changes only if the clock line(SCL) is at its active low level.

3. I2C is a connection oriented communication protocol.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: I2C is a connection oriented protocol i.e each transmission is initiated by a START condition and is ter
minated by a STOP condition.

4. The STOP condition is generated by a

a) high to low change in the SDA line when the SCL is low
b) high to low change in the SDA line when the SCL is high
c) low to high change in the SDA line when the SCL is low
d) low to high change in the SDA line when the SCL is high
Answer: c
Explanation: The STOP condition is generated when there is a low to high change in the SDA line when the SCL is l
ow.

5. For receiving the acknowledgment

a) SDA from the transmitter should be high

b) SDA from the transmitter should be low
c) SDA from receiver should be high
d) SDA from receiver should be low
Answer: d
Explanation: The packet format in I2C consists of 9 bits, out of which first 8 are the data bits while the ninth bit is th
e acknowledgment bit. For obtaining the acknowledgment, the SDA line of the receiver should be pushed to low.

6. What steps are followed to complete the data transfer?

a) START condition, STOP condition

b) Address packet
c) One or more data packet
d) All of the mentioned
Answer: d
Explanation: For having the complete data transfer, the steps that are actually being followed are START condition,
address packet, one or more data packet, STOP condition.

7. I2C is ideal for short distances?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: I2C is that module of the AVR, which is used for short distances.

8. Which of the following is a register used for programming AVR’s I2C module?

a) TWBR
b) TWCR
c) TWSR
d) All of the mentioned
Answer: d
Explanation: TWBR( TWI Bit rate register), TWCR( TWI Control Register), TWSR(TWI Status Register), TWAR(
TWI Address Register), TWDR( TWI Data Register) are used for programming an AVR’s I2C module.

9. Which bit is polled to know that whether the TWI is ready or not?
a) TWWC
b) TWINT
c) TWEA
d) All of the mentioned
Answer: b
Explanation: TWINT is the bit that is polled to know that whether the TWI is ready or not.

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1. In MSP430, the size of the status register is ________

a) 1 byte
b) 2 bytes
c) 1 bit
d) 2 bit
Answer: b
Explanation: In MSP430, the size of the status register is 2 bytes. The bits of the status register consists of the C flag
, Z flag, N flag, GIE flag, CPU off, OSC off, SCG0, SCG1, V flag and 7 reserved bits.

2. Which of the following bit/s of the status register that allows the microcontroller to operate in its low power mode
?

a) Z
b) Reserved
c) CPU off
d) N
Answer: d
Explanation: The CPU off bit, OSC off bit, SCG0 bit, SCG1 bit of the status register are used to allow the microcont
roller to operate in its low power mode.

3. What is actually done to improve the efficiency of a RISC processor?

a) instructions are reduced

b) they have two or more processors inbuilt connected between
c) they have many instructions that are interrelated to each other
d) they have one or more registers hard wired to the commonly used values
Answer: d
Explanation: To improve the efficiency of the RISC processor, the registers that are hard wired to commonly used v
alues are used instead of other ones.

4. To improve the efficiency of an MSP430 based microcontroller, for one register

a) there is only one value for all addressing modes

b) there are two values for each addressing mode
c) there are 2 values for four addressing modes
d) there are 4 values for four addressing modes
Answer: d
Explanation: In MSP430, there are namely 4 addressing modes. So the main advantage of this controller( which basi
cally increases its efficiency )is that for one register their exists 4 different values for 4 different addressing modes o
f the controller.

5. Their are_______________ number of emulated instructions found in the MSP430?

a) 4
b) 8
c) 16
d) 24
Answer: c
Explanation: The constants CG1 and CG2 are combined together to give 27 native instructions. These instructions ar
e further converted into 24 emulated instructions. So, there are 24 emulated instructions found in an MSP430 based
controller.

6. .w form is used for operations

a) that uses bytes

b) that uses words
c) that uses both
d) that uses none
Answer: b
Explanation: .w form is used for operations, that uses both bytes and words for operations.

7. Pre increment addressing is available in MSP430?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: MSP430 supports only post increment addressing. For performing pre increment addressing, we requir
e some special functions that accomplish that work.

8. Which out of the following is a correct emulated instruction?

a) ADC(.
b) dst
b) ADD(.
b) src,dst
c) ADDC(.
b) src,dst
d) AND(.
b) src,dst
Answer: a
Explanation: “ADC(.
b) dst” this is emulated to “ADDC.B #0,dst” hence this is an emulated instruction. The emulated instructions use cor
e instructions combined with the architecture and implementation of the CPU for higher code efficiency and faster e
xecution.

9. dadd instruction can act as _____________

a) valid BCD addition

b) valid adder with carry
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: Dadd instruction can act as a valid BCD addition instruction if the numbers are initially in BCD state(0
-9).
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1. There are _____ number of addressing modes found for the source and _____ number of modes for the destinatio
n part.

a) 4,4
b) 2,4
c) 7,4
d) 2,2
Answer: c
Explanation: In MSP430, Seven addressing modes for the source operand and four addressing modes for the destinat
ion operand can address the complete address space with no exceptions.

2. MSP430 describes reti instruction as ___________

a) Format1 addressing
b) Format2 addressing
c) Jump addressing
d) None of the mentioned
Answer: b
Explanation: MSP430 describes reti instruction as that type of addressing which consists of only single operand, so i
t comes under Format2 addressing.

3. mov.w R3, R4 takes _________

a) one cycle
b) two cycles
c) four cycles
d) eight cycles
Answer: a
Explanation: mov.w R3, R4 takes only one cycle to transfer the data from register R3 to R4. This type of mode of ad
dressing is called the register mode of addressing.

4. Indexed addressing can be used for _________

a) source
b) destination
c) source & destination
d) none of the mentioned
Answer: c
Explanation: Indexed addressing is used for both the source and the destination addresses.

5. What do you understand form this instruction mov.w X(PC), R6

a) R6 = X+PC
b) R6 = PC-X
c) R6 = -X-PC
d) R6 = -X+PC
Answer: a
Explanation: This instruction mov.w X(PC), R6 means that the contents of X+PC address are copied to the R6 regist
er.

6. Absolute mode uses which of the following operators?

a) %
b) /
c) $
d) &
Answer: d
Explanation: Absolute mode uses the & operator to transfer a constant to a register.

7. Indirect register mode is used by _________

a) source register
b) destination register
c) source & destination register
d) none of the mentioned
Answer: a
Explanation: Indirect addressing mode is used only by the source register.

8. Indirect mode and the indirect auto increment mode have which common operator in them

a) +
b) –
c) @
d) &
Answer: c
Explanation: Both the indirect and the indirect auto increment mode use the @ operator for the source register to tra
nsfer the data from one memory location to a register.

9. Are the following two instructions similar?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: MOV @R10,0(R11) → Move the contents of the source address (contents of R10) to the destination ad
dress (contents of R11).

10. MOV @R10,0(R11) is a type of ________

a) Register Mode
b) Indirect Register Mode
c) Immediate Mode
d) Indirect Autoincrement Mode
Answer: b
Explanation: The type of given instruction is Indirect Register Mode.

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1. Which instruction is used to call functions?

a) MOV
b) GO
c) CALL
d) All of the mentioned
Answer: c
Explanation: CALL instruction is used for going to a particular address in MSP430. It actually causes the pointer to j
ump at a particular address and push the current address of the PC to the stack.

2. ret instruction is used for _________

a) determining the end of the program

b) for returning back from the subroutine to the main program
c) for transferring data from one place to another
d) none of the mentioned
Answer: b
Explanation: Ret instruction is basically used for returning back from a subroutine. It actually pops the top address fr
om the stack and moves that address to its PC, so that it now returns to the main program and continue the execution
normally.

3. According to conventions being followed, R12 to R15 are used for _________

a) parameter passing
b) preserved for call
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: According to the conventions, R12 to R15 are used for parameter passing and hence are not preserved f
or the call.

4. We can store the temporary results across a call instruction with the help of which of the following registers

a) R1-R4
b) R4-R11
c) R12-R15
d) All of the mentioned
Answer: b
Explanation: Temporary results are stored by the registers R4-R11.

5. Can we allocate variables on the stack?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, we can allocate the variables on the stack, it is a very effective way of storing the variables.

6. Which registers are reserved for passing the parameters to a subroutine and then returning the final result?

a) R1-R4
b) R4-R11
c) R12-R15
d) All of the mentioned
Answer: c
Explanation: Originally, R12-R15 registers are reserved for passing the parameters to a subroutine and then returnin
g the final result.
7. What actually is the order of stack frame for a parameter to pass to a subroutine?

a) parameter passed to a subroutine

b) return address
c) saved copies of registers(R4-R11)
d) all of the mentioned
Answer: d
Explanation: All the steps i.e. parameter passed to a subroutine, return address, saved copies of registers(R4-R11), lo
cal variables in subroutines are required for passing a parameter to a subroutine.

8. When any subroutine is called, then the first value of stack will be

a) value of PC
b) the return address
c) none of the mentioned
d) both are one and the same things
Answer: d
Explanation: When any subroutine is called then the first place of the stack will be filled with the return address, or t
he address of the PC so that the pointer may return back to its appropriate place after the return instruction of the sub
routine.

9. Which of the following instruction/s is/are used to return back to the main program after the subroutine is complet
ed?

a) ret
b) reti
c) ret and reti
d) none of the mentioned
Answer: c
Explanation: For returning back from the subroutine, both ret and reti can be used, the main difference between the t
wo is that reti just resets the interrupt flag before the return, so that the interrupt can occur again.

10. Is the approach of making subroutines effective or not?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The approach of making subroutine is indeed very effective, as with its help we don’t need to retrace/w
rite a particular set of codes again and again. It makes our approach modular.

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1. MSP430 uses vectored interrupts?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: MSP430 has vectored interrupts i.e. the address of each ISR is stored in a vector table, that’s why it has
vectored interrupts.
2. Which of the following is true?

a) interrupts are required to wake a CPU from sleep

b) same vector address associated with multiple flags
c) most interrupts are maskable
d) all of the mentioned
Answer: d
Explanation: All of the above mentioned statements are true i.e. interrupts are required to wake a CPU from sleep, sa
me vector address associated with multiple flags and most of the interrupts are maskable.

3. After the interrupt has occurred, the stack is filled with ______________

a) return address
b) status register
c) return address & status register
d) none of the mentioned
Answer: c
Explanation: When an interrupt had occurred, the top place of the stack is filled with the return address, so that imm
ediately after the reti instruction the pointer moves to the main program, the stack is also filled with the bits of the st
atus register so that all the temporary values get stored in it.

4. What is the purpose of __interrupt() function?

a) it is used to enable the interrupt

b) it is used to disable the interrupt
c) it denotes that the routine is an ISR
d) all of the mentioned
Answer: c
Explanation: The purpose of __interrupt() function is to denote that the routine is an ISR.

5. What is the purpose of .intvec assembler directive?

a) it creates an interrupt vector entry that points to an interrupt routine name

b) one is used for storage, other for display
c) one stores locally other stores globally
d) the two are the same
Answer: a
Explanation: The .intvec directive creates an interrupt vector entry that points to an interrupt routine name.

6. For enabling any interrupt, firstly _____________

a) GIE=0
b) GIE=1
c) None of the mentioned
d) GIE=0 & 1
Answer: b
Explanation: If GIE is set to 1, then only other hardware interrupts are enabled.

7. Nonmaskable vectors are stored at different vector locations?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Nonmaskable interrupts are stored in the same vector location, it may be of higher or the lower priority
.

8. Which of the following can generate a nonmaskable interrupt?

a) access violation to flash memory, ACCVIFG

b) timer_A interrupt
c) compare / capture interrupt
d) all of the mentioned
Answer: a
Explanation: A nonmaskable interrupt is generated by an access violation to flash memory, ACCVIFG.

9. External RST/NMI pin is a nonmaskable interrupt?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, external RST/NMI pin is a nonmaskable interrupt( The function of the RST/NMI pin is configure
d in the control register for the watchdog timer module, WDTCTL).

10. How many cycles are used by MSP430, when reti instruction is executed?

a) 3
b) 4
c) 5
d) depends on the conditions
Answer: c
Explanation: When reti instruction is executed, five cycles are used because it firstly pops the stack register complet
ely and then takes the top of the stack into the PC to return to the next address of the main program.

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1. There are how many MSP430’s low power modes available in the chip?

a) two
b) three
c) four
d) five
Answer: d
Explanation: There are five low power modes available in the MSP430, out of which two are rarely employed in the
current devices.

2. Which of the following are the low power modes?

a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned
Answer: d
Explanation: LPM0, LPM3, LPM4 all are the low power modes that are available in the MSP430.

3. Which of the following modes is also known as the RAM retention mode?

a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned
Answer: c
Explanation: LPM4 is known as the RAM retention mode. Here, the CPU and all clocks are disabled, I ≈ 0.1A. The
device can be woken only by an external signal.

4. Waking a device simply means that switching that device’s operation from a low power mode to an active mode.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: When a device is operating in a low power mode, it can also be assumed that the device is sleeping, so
waking a device simply means to turn that device’s operation from a low power mode to an active mode.

5. When an interrupt is accepted, the contents of the status register are ___________

a) set
b) reset
c) remains the same
d) cant be said
Answer: d
Explanation: When an interrupt is accepted, the contents of the status register are cleared, it actually puts the process
or in the active mode.

6. Which of the following basic clock modules supplies clock signals to the MSP430?

a) ACLK
b) MCLK
c) SMCLK
d) All of the mentioned
Answer: a
Explanation: All of the mentioned options are correct. The basic clock module supplies the MSP430 with three cloc
k signals as follows:

7. _ _low_ power_mode_0() states the processor to __________

a) enable the interrupt

b) disable the interrupt
c) nothing
d) to go in an active mode
Answer: b
Explanation: _ _low_ power_mode_0() puts the processor in the LPM0 mode.

8. More power can be saved by using low_power mode 0 than low_power mode 3.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: More power is saved in low_ power mode 3.

9. _BIC_SR_IRQ() is used to _______________

a) set the particular bits of the SR

b) reset the particular bits of the SR
c) any of the above mentioned depending on the conditions
d) none of the mentioned
Answer: b
Explanation: _BIC_SR_IRQ() is used to clear the bits of the SR.

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1. Which of the following registers are related to port P1?

a) P1SEL
b) P1DIR
c) P1IES
d) All of the mentioned
Answer: d
Explanation: All of the mentioned registers are related to Port1.

2. A pull-up or pull-down resistor ___________

a) removes the full output drive on the output pin

b) gives only a feeble current through the pull-up to resistor
c) removes the full output drive on the output pin & gives only a feeble current through the pull-up to resistor
d) none of the mentioned
Answer: c
Explanation: A pull-up or pull-down resistor is used to remove the full output drive on the output pin. It also gives a
feeble current through the pull-up to a resistor.

3. P1.3 is the ___________

a) input CCI1A to Timer_A

b) is connected to the voltage reference VREF of SD16_A
c) is output TA0 from Timer_A
d) are digital inputs with pull-up resistors
Answer: b
Explanation: P1.3 is connected to the voltage reference VREF of SD16_A.

4. What actually is SD16_A?

a) it is an interrupt
b) it is a timer
c) it is an analog to Digital Converter
d) it is a serial communication module
Answer: c
Explanation: SD16_A is an analog to the digital module.
5. P1IE and P1IES are registers that are used to ___________

a) control the Port1 digital i/o ports

b) control the Port1 interrupts
c) control the Port1 serial communication interfaces
d) all of the mentioned
Answer: b
Explanation: P1IE and P1IES both registers are used to control the Port1 interrupts.

6. Unused pins must never be left unconnected in their default state as inputs.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Unused pins must never be left unconnected in their default state as inputs. This follows a general rule
that inputs to CMOS must never be left unconnected or “floating”.

7. Which of the following is an effect of a Schmidt trigger?

a) it turns slowly varying inputs, which might cause problems while they pass slowly through the undefined range of
input voltages, into abrupt, clean logical transitions
b) It eliminates the effect of noise on the input, provided that it is not large enough to span the gap between the upwa
rd and downward thresholds
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: Schmidt trigger has two of the above mentioned effects in it.

8. To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the input down
through VIT−, we must choose

a) minimum hysteresis
b) maximum hysteresis
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the i
nput down through VIT−, we must choose a minimum hysteresis of 0.3V.

9. The SPDT switch can be used as a ___________

a) detecting circuit
b) debouncing circuit
c) devaluing circuit
d) degenerating circuit
Answer: b
Explanation: The SPDT(single pole, double pole) switch can be used as a debouncing circuit of a switch.

10. Debouncing can be carried out at a hardware as well as the software end?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Debouncing can be carried out at both the fronts both at the software as well as the hardware front, to c
arry out the process appropriately.

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1. What are the basic functions of a timer?

a) it provided a time delay

b) it can act as a counter
c) it can control the compare, capture mode
d) all of the mentioned
Answer: d
Explanation: Timers are used to provide a time delay, they can even act as a counter and control the compare capture
mode of a microcontroller.

2. Most of the MSP430’s devices have __________ number of timers in it.

a) three
b) four
c) five
d) seven
Answer: c
Explanation: MSP430 has mainly five types of timers in it. They are Watchdog Timer, Basic Timer1, Real clock Ti
me, Timer_A, Timer_B.

3. A Watchdog Timer can act as an interval timer?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: A Watchdog Timer can act as an interval timer if the protection is not needed for it.

4. Which out of the following is the main function of a Watchdog timer?

a) control the compare mode

b) control the capture mode
c) protection from failures to the system
d) all of the mentioned
Answer: c
Explanation: Its main function is to protect the system against malfunctions.

5. Basic Timer1 can provide __________

a) clock for the LCD

b) an internal timer
c) clock to the LCD and can & also used as an interval timer
d) none of the mentioned
Answer: c
Explanation: Basic Timer1 device is used to provide the clock to the LCD and can also be used as an interval timer.

6. LCD_A controllers make use of the Basic Timer1 timer for providing a clock to the LCD?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Basic Timer1 is not used in LCD_A controllers, because these provide an internal clock of its own to al
l of its devices.

7. Real time clock is an extension of Basic Timer1?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Real time clock is an extension of Basic Timer1 and is present in almost all devices for controlling its r
eal time clock.

8. Timer_A can be used to _________

a) generate interrupts
b) handle external inputs
c) drive outputs
d) all of the mentioned
Answer: d
Explanation: Timer_A can be used to generate the interrupts, handle the external inputs or for driving the outputs.

9. Time stamp inputs can be measured by a Timer_A?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, time stamp inputs can be measured by a Timer_A.

10. Timer_B includes _________

a) sampling inputs
b) driving outputs
c) sampling inputs & driving outputs
d) none of the mentioned
Answer: b
Explanation: Timer_B is used for driving the outputs as with Timer_A but it lacks the property of Timer_A of sampl
ing inputs.

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1. The watchdog counts up and resets the MSP430 when it reaches the limit?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The watchdog timer is used for the protection of the device. It keeps a track at the counter so that the c
ode doesn’t reach an infinite unending loop. So it actually resets the counter before this particular condition.

2. Which of the following is correct about WDTCTL?

a) it is a 16 bit register
b) it is guided against accidental writes that require a password
c) a reset will occur if a value with an incorrect password is written to WDTCTL
d) all of the mentioned
Answer: d
Explanation: WDTCTL is a 16 bit register that is used for protecting the microcontroller. It actually resets the value
when an incorrect password is written to WDTCTL.

3. WDTNMI is found in the _________

a) higher byte of WDTCTL

b) lower byte of WDTCTL
c) its first four bits
d) its last four bits
Answer: b
Explanation: WDTNMI is the fifth bit of the WDTCTL register.

4. Which of the following bits reads 0 under normal conditions but goes 1 when it wants to initiate some action?

a) WDTNMI
b) WDTHOLD
c) WDTTMSEL
d) WDTCNTCL
Answer: d
Explanation: WDTCNTCL is the bit that reads 0 under normal conditions but goes 1 when it wants to initiate some a
ction like resetting the counter.

5. WDTISx bits control the _________

a) period of the clock

b) act as “Nonmaskable Interrupts”
c) stop the watchdog timer
d) start the watchdog timer
Answer: a
Explanation: WDTISx bits of the WDTCTL register is responsible for controlling the period of the clock.

6. The process of setting the WDTCNTCL bit in WDTCTL is through

a) petting
b) feeding
c) kicking
d) all of the mentioned
Answer: d
Explanation: the process of setting the WDTCNTCL bit in the WDTCTL register is by the processes like petting, fee
ding and kicking.

7. What is the function of this instruction “WDTCTL = WDTPW | WDTCONFIG”, where **#define WDTCONFIG
(WDTCNTCL|WDTSSEL)**

a) it sets the watchdog timer

b) it configures and clears the watchdog timer
c) it stops the watchdog timer
d) it configures and sets the watchdog timer
Answer: b
Explanation: WDTCTL = WDTPW | WDTCONFIG instruction is used to clear and configure the watchdog timer of
a microcontroller.

8. Is this instruction correct?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: No WDTCTL_bit.WDTCNTCL = 1; is an incorrect way of setting the bits of the WDTCTL register be
cause it violates the password protection.

9. Setting the WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as

a) interrupt
b) communication device
c) converter
d) interval timer
Answer: d
Explanation: The WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as the interval timer.

10. WDTIFG flag gets cleared if

a) if is interrupt had occurred

b) if the interrupt is serviced
c) if there can be no interrupt
d) all of the mentioned
Answer: b
Explanation: WDTIFG flag gets cleared if the interrupt is serviced so that again the interrupt can occur.

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1. Which of the following is true about the FRFQx bits of the BTCTL register?

a) these bits are used for clock input

b) these bits are used for setting a particular frequency fLCD
c) these bits start the timer
d) these bits stop the timer
Answer: b
Explanation: FRFQx bits of the BTCTL register are used for selecting a particular frequency fLCD varying from fA
CLK/256 to fACLK/32.

2. Timer1 is responsible for ________

a) providing a clock to the LCD module

b) cause an interrupt
c) a pulse for the RTC
d) all of the mentioned
Answer: d
Explanation: Timer1 is responsible for providing a clock for the LCD module. It can also cause an interrupt if the B
TIE bit is high. It also provides the clock to the RTC.

3. For fACLK = 32 KHz, what would be the desirable range of fLCD?

a) 2hz-256hz
b) 12hz-512hz
c) 128hz-1khz
d) 1khz-10khz
Answer: c
Explanation: For fACLK = 32khz, the desirable range of the fLCD is the fACLK/256 to fACLK/32. This value com
es out to be in the range of 128hz-1khz.

4. Normally BTCNT1 only function is to provide a prescalar for the BNTCNT2?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: LCD’s controllers nowadays don’t require a clock pulse, so the only main function of the BTCNT1 is t
o provide a prescalar for the BNTCNT2.

5. BTCNT2 provides 2 output signals?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: BNTCNT2 has no outputs. Instead, it raises the BTIFG flag at a frequency determined by the BTIPx bi
ts.

6. RTCSEC, RTCMIN, RTCDOW etc. are the bytes of a set of registers that are used to store

a) seconds
b) minutes
c) days of a week
d) all of the mentioned
Answer: d
Explanation: The current time and date are held in a set of registers that contain the following bytes like RTCSEC, R
TCMIN, RTCHOUR, RTCDOW etc.

7. The RTC module is configured in the calendar mode if __________

a) RTCMODE bit is reset
b) RTCMODE is set
c) RTCRDY is reset
d) RTCRDY is set
Answer: d
Explanation: Calendar mode is selected when RTCMODE is set.

8. The RTC module makes use of the Basic Timer1 because of _________

a) its bytes are controlled in the Basic Timer1 register

b) it is started by timer1
c) it is ended by basic timer1
d) it needs a clock pulse of 1hz that is provided by basic timer1
Answer: c
Explanation: The RTC module requires a clock of worth 1hz that is provided by basic timer1 so that why it makes u
se of basic timer1.

9. IF RTCIE interrupt is generated then _________

a) BTIFG flag is set

b) RTCFG flag is set
c) Both flags are set
d) None of the flag is set
Answer: c
Explanation: When RTCIE interrupt is generated then both BTIFG and RTCFG flags are set simultaneously.

PSST! You better watch out, something's buggy above.

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1. All channels within Timer_A share the same timer block?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: There is only one TAR in Timer_A so all of its channels share the same timer block.

2. Timer_A has _________

a) RTC module in it
b) Compare/ capture channel
c) Communication channel
d) Converter channel
Answer: b
Explanation: Timer_A has compared/ capture channel inbuilt inside it.

3. TACLK and INCLK are _________

a) internally generated clock pulses

b) externally fed clock pulses
c) of no use in Timer_A
d) very slow
Answer: b
Explanation: TACLK and INCLK clock pulses are the externally fed pulses that are required by the Timer_A.

4. In continuous mode of the counter _________

a) counter moves from 0000-ffff

b) counter moves from ffff-0000-ffff
c) counter moves from 0000-ffff and then again returns to 0
d) all of the mentioned
Answer: c
Explanation: In a continuous mode of the counter, the counter firstly increases from 0000-ffff, then after this value t
he roll over condition comes and it again gets started from 0000. This particular mode is very useful for capturing in
puts.

5. TACLR bit in TACTL _________

a) clear the interrupt flag

b) clear the status flags
c) clear the count in TAR
d) all of the mentioned
Answer: c
Explanation: TACLR bit in TACTL clears the count in the TAR.

6. TAxCCTLn is a _________

a) set of 2 bits used for selecting the mode of operation of the timer
b) a register of 8 bits used for giving the count to the timer
c) a register of 16 bits used to select the compare/capture channel of the Timer_Ax
d) a register of 16 bits used to cause the timer interrupt
Answer: c
Explanation: TAxCCTLn is a register of 16 bits used to select the compare/capture channel of the Timer_Ax.

7. CCI1B comes from _________

a) ACLK
b) CAOUT
c) SCLK
d) TACLK
Answer: b
Explanation: CCI1B comes from CAOUT.

8. Which of the following parameters are given by the TAxCCRn?

a) Capture/compare input. The selected input signal can be read by this bit
b) Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be re
ad from this bit
c) Holds the data for the comparison to the timer value in the Timer_A Register, TAR
d) None of the mentioned
Answer: c
Explanation: Compare mode: TAxCCRn holds the data for the comparison to the timer value in the Timer_A Regist
er, TAR.

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1. Why Timer_B is not considered as most suitable one for receiving asynchronous signals?

a) because of the absence of the TBOUTH input pin

b) because of the presence of the TBOUTH input pin
c) because of the absence of the SCCI bit
d) because of the presence of the SCCI bit
Answer: c
Explanation: The SCCI bit is absent in the Timer_B which means that the sampling mode is absent in it that’s why it
is considered as unsuitable for receiving asynchronous signals.

2. There is double buffering in the immediate mode?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Immediate mode offers no double buffering condition. As here, values are copied to TBCLn as soon as
they are written to TBCCRn.

3. Double buffering protects channel 0.

a) as it acts as the limit in the Up and up/down modes

b) it doesn’t actually protect it
c) as it does not accept the inputs
d) none of the mentioned
Answer: a
Explanation: Double buffering protects channel 0 as it acts as the limit in the Up and Up/Down modes.

4. Timer_B has _________

a) three serial communication ports

b) seven LCD driver
c) seven compare/capture channels
d) three LED driver ports
Answer: c
Explanation: Timer_B has seven compare/capture channels.

5. The capture/compare registers TBCCRn are double-buffered when used for compare events?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The capture/compare registers TBCCRn are double-buffered when used for compare events.

6. The length of TBR can be programmed to be _________

a) 8 bits
b) 12 bits
c) 16 bits
d) all of the mentioned
Answer: d
Explanation: The length of TBR can be programmed to be 8, 12, 16 or 10 bits long.

7. TBOUTH can pin can be used to _________

a) values are moved from one place to another

b) the length of the number of bits is selected by this register
c) it can be used to put all the outputs of the Timer_B register in the high impedance state
d) it can be used for outputting the input values of the timers
Answer: c
Explanation: TBOUTH pin is used to put all the outputs of the Timer_B register in the high impedance state by a hig
h external signal applied to this pin.

8. TBCLn provided in each channel is actually _________

a) a comparator
b) compare latch
c) controller
d) control logic
Answer: b
Explanation: TBCLn is actually a compare latch that is provided in its every channel.

9. When TBR counts to zero?

a) TBCLn is updated from TBCCRn

b) CLLDx is updated to TBCCTLn
c) CLLDx is updated to TBCCRn
d) TBCLn is updated to CLLDx
Answer: a
Explanation: When TBR counts to zero, TBCLn is updated from TBCCRn.

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1. Which of the following is the analog to digital converter that is present in the MSP430 based processors?

a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned
Answer: d
Explanation: A comparator module, a successive approximation ADC module and a sigma delta ADC converters are
found in the MSP based processors.

2. Higher resolution along with the slow speed is given by which ADC module?

a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned
Answer: c
Explanation: Higher resolution along with the slow speed is given by the sigma delta ADC module.

3. The technical terms that help us in differentiating between converters are:

a) resolution
b) accuracy
c) precision
d) all of the mentioned
Answer: d
Explanation: While selecting the converter, necessary for our work we had to take care of the factors like resolution,
accuracy and precision in it.

4. The number of repeated closeness to the true value is accounted by

a) resolution
b) accuracy
c) precision
d) all of the mentioned
Answer: c
Explanation: The degree of closeness of the measured value to the actual true value is its accuracy, while on the othe
r hand the measure of the repeated accuracy is termed as the precision.

5. Resolution is _________

a) change in measured value from the true value

b) the amount of change in the input value for the corresponding change of 1 unit in the output value
c) as the measure of the repeated accuracy
d) all of the mentioned
Answer: b
Explanation: Resolution is defined as the amount of change in the input value for the corresponding change of 1 unit
in the output value.

6. The process of reduction of a continuous input to a discrete output is

a) levelling
b) signalling
c) quantization
d) converting
Answer: c
Explanation: The process of reduction of a continuous input to a discrete output is called as quantization.

7. Which of the following functions can be used for converting the nearest integer to its argument?

a) int
b) mint
c) uint
d) nint
Answer: d
Explanation: nint is the function that is priorly used for converting the nearest integer to its argument.

8. Integral nonlinearity is termed as

a) process of reduction of a continuous input to a discrete output

b) change in measured value from the true value
c) maximum deviation between this corrected staircase and the actual transfer characteristic
d) the function used in the quantization
Answer: c
Explanation: Integral nonlinearity is termed as the maximum deviation between this corrected staircase and the actua
l transfer characteristic.

9. The SNR_______ with the increase of the number of bits.

a) remains constant
b) goes up
c) goes down
d) goes asymmetrically
Answer: b
Explanation: The SNR goes up with the number of bits.

10. The intervals between the samples are obtained from _________

a) Fs
b) Ts
c) Us
d) Ks
Answer: b
Explanation: The intervals between the samples is obtained by Ts that is equal to 1/fs.

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1. Comparator_A+ is controlled by which of the following peripheral registers?

a) CACTL1
b) CACTL2
c) CACTL1 & CACTL2
d) None of the mentioned
Answer: c
Explanation: Comparator_A+ is controlled by the CACTL1 and the CACTL2 registers.

2. CAON bit is used to ___________

a) start a timer
b) start an A/D conversion
c) switch on the comparator module
d) switch on the bit transmission
Answer: c
Explanation: CAON bit is used to switch on the comparator module namely, Comparator_A+.

3. P2CA4-P2CA0 bits are used for _______

a) giving the power supply to the comparator module

b) for selecting the mode of operation of the comparator
c) for connecting the non inverting inputs to the CA0-CA2 pins
d) all of the mentioned
Answer: c
Explanation: P2CA4-P2CA0 bits are used for connecting the non inverting inputs to the CA0-CA2 pins.

4. CAREFx bits are used for _______

a) inputting a positive reference voltage

b) inputting a negative reference voltage
c) selecting the internal reference voltage
d) all of the mentioned
Answer: c
Explanation: CAREFx bits are used for selecting the appropriate reference voltage for the comparator.

5. Which of the following bits are not actually associated with the comparator module?

a) CAREFx
b) CLLDx
c) CAON
d) CAIFG
Answer: b
Explanation: CLLDx bit is related to the Timer_2 module. All others are related to the comparator module.

6. Flag CAIFG is raised,

a) at a low level triggered pulse

b) at a high level triggered pulse
c) at the falling and rising edge of the pulse
d) at the falling or rising edge of the pulse
Answer: d
Explanation: Flag CAIFG is raised, at the falling or rising edge of the pulse that is selected by the CAIES bit.

7. Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output buffers to
be disconnected from the appropriate pin.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output
buffers to be disconnected from the appropriate pin.

8. Which bit is used for exchanging the two inputs of the comparator and invert its output to compensate?

a) CAIFG
b) CASHORT
c) CAPD
d) CAEX
Answer: d
Explanation: CAEX is used for exchanging the two inputs of the comparator and invert its output to compensate.

9. Changes in Vcc changes the value of V+?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: When some variation is made in the value of Vcc, in the same manner, itself the value of the V+ chang
es because, the voltage from the potential divider is proportional to Vcc. This changing effect can be reduced if the s
imilar change takes place in the value of V- itself.
10. The relaxation oscillator circuit helps in _______

a) calculating the duration single RC transient

b) setting the reference voltage
c) setting the clock frequency
d) calculating the conversion speed
Answer: a
Explanation: The relaxation oscillator is a circuit that with the help of charging and discharging of an oscillator, help
us in calculating the duration of the single RC transient.

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1. The successive approximation converters have a resolution of _________

a) 8-10 bits
b) 10-12 bits
c) 12-16 bits
d) 16-32 bits
Answer: b
Explanation: The successive approximation converters have a resolution of about 10-12 bits in it.

2. In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a comparison and
set up the new voltage.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a com
parison and set up the new voltage.

3. The main operations that are basically performed in a SAR ADC are?

a) logic to control the operation

b) some way of generating the voltages, for comparison
c) logic to control the operation and finding some way of generating the voltages for comparison
d) none of the mentioned
Answer: c
Explanation: The main operations that are basically performed in a SAR ADC are the logic to control the operation a
nd finding some way of generating the voltages, for comparison.

4. Usually, a capacitor is inserted between an analog input and the ground because

a) it blocks the analog voltage

b) it suppresses the noise
c) it increases the gain
d) none of the mentioned
Answer: b
Explanation: A capacitor is inserted between the analog input and the ground because it suppresses the noise.

5. ADC10 and ADC12 are _________

a) The converters
b) SAR modules available in the MSP430
c) Sigma delta modules available in the MSP430
d) Comparator modules available in the MSP430
Answer: b
Explanation: ADC10 and ADC12 are the SAR modules available in the MSP430.

6. ADC10 needs external capacitors on its voltage reference.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: ADC12 needs external capacitors on its voltage reference as compared to the ADC10 module.

7. ADC10CTL0 and ADC10CTL1 are registers

a) for controlling SAR module

b) for controlling the sigma delta module
c) for controlling the comparator module
d) all of the mentioned
Answer: a
Explanation: ADC10CTL0 and ADC10CTL1 are the registers that are used for controlling the SAR module in the
MSP430.

8. While conversion is in progress, which of the flag is affected.

a) ADC10ON
b) ADC10MEM
c) ADC10BUSY
d) ADC10DF
Answer: c
Explanation: While conversion is in progress, then ADC10BUSY flag is set.

9. ADC10SHTx bits allow_________cycles of the ADC10CLK.

a) 4
b) 8
c) 16
d) all of the mentioned
Answer: d
Explanation: ADC10SHTx bits allow 4,8,16 and 64 cycles of the ADC10CLK.

10. The input to the ADC10 is selected from_______bits of the ADC10CTL1 register?

a) INCHx
b) ADC10SC
c) ADC10ON
d) ENC
Answer: a
Explanation: The input to the ADC10 is selected from the INCHx bits of the ADC10CTL1 register.
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1. The basic idea behind the sigma delta converter is that

a) to carry out the conversion

b) to carry out communication
c) to reduce the circuit to its simplest way possible and then carry out the conversion
d) all of the mentioned
Answer: c
Explanation: The main idea behind the sigma delta converter is that to reduce the circuit to its simplest way possible
and then carry out the conversion.

2. Sigma delta converter is a __________

a) 1 bit converter
b) 2 bit converter
c) 3 bit converter
d) 4 bit converter
Answer: a
Explanation: Sigma delta converter is a 1 bit converter.

3. Sigma delta converter is having good resolution.

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Sigma delta converter is having poor resolution quality.

3. Oversampling ratio is defined as the _________

a) final frequency
b) oversampling frequency
c) oversampling frequency/final frequency
d) final frequency/oversampling frequency
Answer: c
Explanation: Oversampling ratio is defined as the ration of the oversampling frequency fm to the final frequency fs.

4. Here the word sigma represents _________

a) subtraction
b) differentiation
c) integration
d) none of the mentioned
Answer: c
Explanation: In a sigma delta converter, sigma word represents that the output obtained from the delta function is get
ting integrated.

5. SD16_A features are controlled by _________

a) memory mapped registers

b) register mapped registers
c) data mapped registers
d) none of the mentioned
Answer: a
Explanation: SD16_A features are controlled by the memory mapped registers.

6. The second part of the ADC handles purely digital signals.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: The second part of the ADC handles purely digital signals.

7. The second part of the ADC’s output is in the form of _________

a) the fast stream of single bits

b) the fast stream of multiple bits
c) the slow stream of single bits
d) the slow stream of multiple bits
Answer: d
Explanation: The second part of the ADC take in fast stream of single bit and give out a slow stream of multiple bit
values.

8. The filtered digital signal is then decimated to

a) reduce the rate of samples from fm to fs

b) reduce the rate of samples from fs to fm
c) increase the rate of samples from fm to fs
d) increase the rate of samples from fs to fm
Answer: a
Explanation: The filtered digital output is then decimated in order to reduce the rate of samples from fm to fs.

9. Decimated means _________

a) multipled by 10
b) multiplied by 100
c) divided by 10
d) divided by 100
Answer: c
Explanation: Decimated means to divide the result by 10.

10. The SD16 has a second-order modulator with a _________

a) sinc filter
b) sinc2 filter
c) sinc3 fiter
d) rect filter
Answer: c
Explanation: The SD16 has a second-order modulator with a sinc3 filter.

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1. What actually is a bit bagging?

a) it actually refers to the technique of assigning the bits with their inputs
b) a technique by which an MSP430 can communicate through hardware
c) a technique by which MSP430 can communicate through software
d) a technique through which conversion becomes possible
Answer: c
Explanation: Bit bagging is the technique through which a processor can communicate to its associate partners when
an appropriate hardware is not available for its purpose. This communication is made possible through the software.

2. SPI, I2C, Asynchronous serial communication are the means of communicating a processor with its associate part
ners?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: SPI, I2C, Asynchronous serial communication are the means for the processor by which communicatio
n is made possible.

3. All digital communications don’t require any clock.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Clock is the prior need for any communication to occur. This is because synchronization is maintained
with the help of a clock.

4. SPI needs______ wires than I2C?

a) less
b) same
c) more
d) depends on the conditions
Answer: c
Explanation: In SPI, there is no control of transmission in software—no addresses or acknowledgment, that’s why it
requires more amount of wires.

5. USI handles _________

a) SPI
b) I2C
c) SPI & I2C
d) None of the mentioned
Answer: c
Explanation: USI(Universal Serial Interface) supports both the types of synchronous communication i.e. SPI and I2
C.

6. USCI consists of _________

a) one channel
b) two channels
c) three channels
d) four channels
Answer: b
Explanation: USCI consists of mainly two channels, A and B. These are largely independent but share a few register
s and interrupt vectors.

7. LIN is enabled in which of the following channels?

a) A
b) B
c) C
d) D
Answer: a
Explanation: Channel A is the asynchronous receiver/ transmitter channel. It can detect the baud rate of an incoming
signal, which enables its use on a local interconnect network (LIN).

8. Can one device have more than one USC interfaces?

a) yes
b) no
c) depends on the conditions
d) cant be said
Answer: a
Explanation: Yes, one device can have more than one USC interfaces. There is a small difference because the interru
pt flags and enable bits for the “0” modules are in a special function registers IFG2 and IE2, while those for the “1”
modules are in their own registers, UC1IFG and UC1IE.

9. Which of the following conditions is more difficult to attain?

a) synchronous masters
b) synchronous slaves
c) asynchronous masters
d) asynchronous slaves
Answer: d
Explanation: Synchronous slaves are the most difficult to attain because the problem is that the slave must react quic
kly when a clock transition arrives from the master.

10. Timer_A is used in _________

a) SPI
b) I2C
c) Asynchronous Serial Communication
d) All of the mentioned
Answer: c
Explanation: Timer_A is used in the Asynchronous Serial Communication.

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1. Is SPI a full duplex technique?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, SPI is a technique where a data can be transmitted/ received in both the directions.

2. The concept of SPI is based on __________

a) two counters
b) four flip flops
c) two shift registers
d) four steady state machines
Answer: c
Explanation: The concept of the SPI is based on the two shift registers, one for the transmitter and the other is there f
or the receiver terminal.

3. Writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse is done when

a) CPHA is set
b) CPHA is reset
c) CPOL is set
d) CPOL is reset
Answer: b
Explanation: When CPHA is reset to zero, then writing on the trailing edge of the clock pulse and reading on the lea
ding edge of the clock pulse.

4. When CPOL=1 then,

a) clock idles high between transfers

b) clock idles low between transfers
c) bit idles high between transfers
d) bit ideals low between transfers
Answer: a
Explanation: When CPOL=1, clock idles high between transfers.

5. Is CPKH and CPOL the same.

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: CPKL=CPOL and CPKH=(not CPHA).

6. SPI with the USI can be selected by ________

a) setting the USII2C bit in the register USICTL1

b) clearing the USII2C bit in the register USICTL1
c) setting the USIPE5–7 bits in USICTL0
d) clearing the USIPE5–7 bits in USICTL0
Answer: b
Explanation: SPI with the USi can be selected by clearing the USII2C bit in the register USICTL1.

7. SCLK, SDO, and SDI are found ___________ on F20x3.

a) P1.0-2
b) P1.2-4
c) P1.4-6
d) P1.5-7
Answer: d
Explanation: SCLK, SDO, and SDI are found at P1.5-7 on F20x3.

8. Transmission and reception are made at a time in SPI?

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Transmission and reception occur at a time in SPI. This means that a value is received only if the trans
mitter is active.

9. When the buffer is ________ the low power mode is__________

a) empty, reset
b) having one byte, reset
c) full, reset
d) empty, two
Answer: c
Explanation: When the buffer is full, the low power mode is cleared.

10. Falling edge of the SS pin denotes ________

a) end of the transfer

b) starts a new transfer
c) selects a new master
d) none of the mentioned
Answer: b
Explanation: Falling edge of the SS pin denotes the start of a new transfer over SPI.

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1. The I2C bus uses which of the following lines?

a) CLK
b) MISO
c) SDA
d) All of the mentioned
Answer: c
Explanation: The I2C bus uses only two lines. They are SDA and SCL.

2. I2C is a faster means of data transfer than SPI?

a) yes
b) no
c) depends on the conditions
d) cant be said
Answer: b
Explanation: I2C is a slower means of transfer than SPI because here only one line is there for the two way commun
ication to occur.

3. Each slave has its unique address.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, in I2C protocol each slave has its own unique address, in order to differentiate it from others.

4. Pull-up resistors Rp keep the lines at VCC when _____________

a) all the drivers are active

b) none of the drivers are active
c) some the drivers are at sleep
d) none of the drivers is at sleep
Answer: b
Explanation: Pull-up resistors Rp keep the lines at VCC when all of the drivers are active.

5. Rising edge on SDA while SCL is high denotes __________

a) start condition (S)

b) stop condition (P)
c) transfer in progress
d) none of the mentioned
Answer: b
Explanation: Rising edge on SDA while SCL is high denotes the stop condition of the transfer.

6. Which of the following is an issue while programming I2C using the software?

a) open-collector output
b) open-drain output
c) totem pole output
d) all of the mentioned
Answer: b
Explanation: There are two main issues while programming I2C using software, they are the open-drain output and t
he detection of start and stop conditions.

7. Which of the following is the slave to be addressed when a device acts as a master?

a) UCB0I2COA
b) UCB0I2CSA
c) UCB0I2CIE
d) All of the mentioned
Answer: b
Explanation: UCB0I2CSA is the slave to be addressed when a device acts as a master.

8. Is baud rate selected in I2C?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: a
Explanation: Yes, baud rate is also selected in the I2C module, as is the case with the SPI module.

9. How is I2C with USI different from I2C with USI_B?

a) there is only one common pin between the two devices

b) here in this case no synchronization is important
c) the outputs of SDA and SCL are open drain
d) none of the mentioned
Answer: c
Explanation: I2C is different in USI than that of USI_B module because here in this module, the output pins SDA an
d the SCL are open drains in nature.

10. UCB0RXIFG is set when ________

a) complete byte is acknowledged

b) complete byte is transmitted
c) complete byte is received
d) none of the mentioned
Answer: c
Explanation: UCB0RXIFG is set when the complete byte sent via I2C is received.

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1. Asynchronous serial communication usually requires two wires for each direction plus a common ground.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: b
Explanation: Asynchronous serial communication usually requires only a single wire for each direction plus a comm
on ground.

2. In an asynchronous mode of transmission, usually the data is sent along with the

a) the start bit

b) the stop bit
c) the start & stopbit
d) none of the mentioned
Answer: c
Explanation: In an asynchronous mode of transmission, both the start and the stop bits are present that are basically
used for intimating the other terminal that whether the data had received correctly the other destination or not.

3. The _____ rate gives the frequency at which the bits are transmitted on the line.

a) bit rate
b) packet rate
c) baud rate
d) data rate
Answer: c
Explanation: Baud rate is the rate which determines us the frequency at which the bits are transmitted on the line.
4. Baud rate is the reverse of the ________

a) baud time
b) baud period
c) bit time
d) bit period
Answer: b
Explanation: Baud rate is the reverse of the baud period.

5. Clock is transmitted in the asynchronous communication?

a) yes
b) no
c) cant be said
d) depends on the conditions
Answer: b
Explanation: No clock is transmitted in the asynchronous communication, so the transmitter and the receiver are allo
wed to work independently at their own terminals.

6. A framing error occurs is the bit is ________

a) high
b) low
c) same
d) changed
Answer: b
Explanation: Framing error occurs if the bit is low.

7. What is the non return to zero format?

a) the bits are either high or low and have no gaps between them
b) the bits are either high or low and have gaps between them
c) the bits are high and have gaps between them
d) the bits are low and have no gaps between them
Answer: a
Explanation: Non-return to zero format represents a format in which the bits are either high or low and have no gaps
between them.

8. LSB is sent first in case of the non return to zero format.

a) true
b) false
c) cant be said
d) depends on the conditions
Answer: a
Explanation: In non-return to zero format, normally LSB is sent first.

9. There are _______ clocks in the USCI_A.

a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: they are 3 clocks in the USCI_A. They are BRCLK, BITCLK and BITCLK16.

10. BITCLK16 is the ________

a) sampling clock in the undersampling mode

b) sampling clock in the oversampling mode
c) quantising clock in the undersampling mode
d) quantising clock in the oversampling mode
Answer: b
Explanation: BITCLK16 is the sampling clock in the oversampling mode.

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 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Date-16/06/2021
Subject Name-KCS-403-Microprocessor_CSE-Semester 4
UNIT-1

1. In 8085 microprocessor, the RST6 instruction transfer programme execution

to following location

a. 0030H

b. 0024H

c. 0048H

d. 0060H

Answer: (a).0030H

2. HLT opcode means

a. load data to accumulator

b. store result in memory

c. load accumulator with contents of register

d. end of program

Answer: (d).end of program

3. What is SIM?

a. Select interrupt mask

b. Sorting interrupt mask

c. Set interrupt mask

d. None of these
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Answer: (c).Set interrupt mask

4. The ROM programmed during manufacturing process itself is called

a. MROM

b. PROM

c. EPROM

d. EEPROM

Answer: (a).MROM

5. A field programmable ROM is called

a. MROM

b. PROM

c. FROM

d. FPROM

Answer: (b).PROM

6. The operations executed by two or more control units are referred as

a. Micro-operations

b. Macro-operations

c. Multi-operations

d. Bi control-operations

Answer: (b).Macro-operations
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

7. Program counter in a digital computer

a. Counts the numbers of programs run in the machine.

b. Counts the number of times a subroutine is called.

c. Counts the number of times the loops are executed.

d. Points the memory address of the next instruction to be fetched.

Answer: (d).Points the memory address of the next instruction to be fetched.

8. At the beginning of a fetch cycle, the contents of the program

counter are

a. incremented by one.

b. transferred to address bus.

c. transferred to memory address register.

d. transferred to memory data register.

Answer: (c).transferred to memory address register.

9. Which components are NOT found on chip in a microprocessor but may be

found on chip in a micro-controller?

a. SRAM & USART

b. EPROM & PORTS

c. EPROM, USART & PORTS

d. SRAM, EPROM & PORTS

Answer: (c).EPROM, USART & PORTS

 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

10. For the purpose of data processing an efficient assembly language

programmer makes use of the general purpose registers rather than
memory. The reason is

a. the set of instructions for data processing with memory is limited

b. data processing becomes easier when register are used

c. more memory related instructions are required

d. data processing with registers takes fewer cycles than that with memory

Answer: (d).data processing with registers takes fewer cycles than that with memory

11. The first machine cycle of an instruction is always

a. A memory read cycle

b. A fetch cycle

c. An I/O read cycle

d. A memory write cycle

Answer: (b).A fetch cycle

12. The output data lines of microprocessor and memories are usually tristated
because

a. More than one device can transmit information over the data bus by enabling
only one device at a time

b. More than one device can transmit over the data bus at the same time

c. The data line can be multiplexed for both input and output

d. It increases the speed of data transfer over the data bus

Answer: (a).More than one device can transmit information over the data bus by
enabling only one device at a time
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

13. The correct sequence of steps in the instruction cycle of a basic computer is

a. Fetch, Execute, Decode and Read effective address.

b. Read effective address,Decode,Fetch and Execute.

c. Fetch, Decode, Read effective address and ,Execute.

d. Fetch, Read effective address, Decode and Execute.

Answer: (c).Fetch, Decode, Read effective address and ,Execute.

14. The register which holds the information about the nature of results of
arithmetic and logic operations is called as

a. Accumulator

b. Condition code register

c. Flag register

d. Process status register

Answer: (c).Flag register

15. Consider the following statements:

Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?

a. 1, 2, 3 and 4

b. 1, 2 and 3

c. 1 and 2 only
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

d. 3 and 4 only

Answer: (c).1 and 2 only

16. Ready pin of microprocessor is used

a. to indicate that microprocessor is ready to receive inputs

b. to indicate that microprocessor is ready to receive outputs

c. to introduce wait state

d. to provide direct memory access

Answer: (c).to introduce wait state

17. Both the ALU and control section of CPU employ which special purpose
storage location?

a. Buffers

b. Decoders

c. Accumulators

d. Registers

Answer: (c).Accumulators

18. A high on RESET OUT signifies that

a. all the registers of the CPU are being reset

b. all the registers and counters are being reset

c. all the registers and counters are being reset and this signal can be used to
reset external support chip
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

d. processing can begin when this signal goes high

Answer: (c).all the registers and counters are being reset and this signal can be
used to reset external support chip

19. In a vector interrupt

a. the branch address is assigned to a fixed location in memory

b. the interrupting source supplies the branch information to the processor

through an interrupt vector

c. the branch address is obtained from a register in the processor

d. none of the above

Answer: (a).the branch address is assigned to a fixed location in memory

20. The content of the A15-A8 (higher order address lines) while executing “IN
8-bit port address” instruction are

a. same as the content of A7-A0

b. irrelevant

c. all bits reset (i.e. 00H)

d. all bits set (i.e. FFH)

Answer: (a).same as the content of A7-A0

21. Which one of the following interrupt is only level triggering?

a. TRAP

b. RST 7.5

c. RST 6.5 and RST 5.5

d. RST 6.5
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Answer: (c).RST 6.5 and RST 5.5

22. Which one of the following instruction may be used to clear the
accumulator content irrespective of its initial value?

a. CLR A

b. ORA A

c. SUB A

d. MOV A, 00H

Answer: (c).SUB A

23. ___________ signal prevent the microprocessor from reading the same data
more than one.

a. pipelining

b. handshaking

c. controlling

d. signaling

Answer: (b).handshaking

24. Data transfer between the microprocessor for peripheral takes place
through __________.

a. I/O port

b. input port

c. output port
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

d. multi port

Answer: (a).I/O port

25. 8255A operates with ________ power supply.

a. +5V

b. -5V

c. -10V

d. +10V

Answer: (a).+5V

26. The _______ allow data transfer between memory and peripherals.

a. DMA technique

b. Microprocessor

c. Register

d. Decoder

Answer: (a).DMA technique

27. Expansion of SPGA is _________.

a. Staggered Pin Grid-Array package

b. Staggered Point Grid-Array package

c. Staggered Plus Grid-Array package

d. Staggered per grid-Array package

 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Answer: (a).Staggered Pin Grid-Array package

28. Pentium-pro processor design implements________ micro architecture.

a. P2

b. P4

c. P6

d. P8

Answer: (c).P6

29. The number of hardware chips needed for multiple digit display can be
minimized by using the technique called ______.

a. interfacing

b. multiplexing

c. demultiplexing

d. multiprocessing

Answer: (b).multiplexing

30. An RS-232 interface is ____________.

a. a parallel interface

b. a serial interface

c. printer interface

d. a modem interface
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Answer: (b).a serial interface

31. Expansion for DTE is ______.

a. data terminal equipment

b. data trap equipment

c. data text equipment

d. data terminal extension

Answer: (a).data terminal equipment

32. Compared with RS-232, USB is faster and uses___________.

a. medium voltage

b. higher voltage

c. lower voltage

d. None of the above

Answer: (c).lower voltage

33. Expansion for HMOS technology is _______.

a. high level mode oxygen semiconductor

b. high level metal oxygen semiconductor

c. high performance medium oxide semiconductor

d. high performance metal oxide semiconductor

Answer: (d).high performance metal oxide semiconductor

 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

34. RIM is used to check whether, the ___________.

a. write operation is done or not

b. interrupt is Masked or not

c. interrupt is Masked

d. interrupt is not Masked

Answer: (b).interrupt is Masked or not

35. What does microprocessor speed depends on?

a. clock

b. data bus width

c. address bus width

d. signal bus

Answer: (c).address bus width

36. The advantage of memory mapped I/O over I/O mapped I/O is _________

a. faster operation

b. many instructions supporting memory mapped I/O

c. require a bigger address decoder

d. all the above

Answer: (d).all the above

37. In 8279 Status Word, data is read when ________ pins are low, and write to
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

the display RAM with ____________ are low.

a. A0, CS, RD & A0, WR, CS

b. CS, WR, A0 & A0, CS, RD

c. A0, RD & WR, CS

d. CS, RD & A0, CS

Answer: (a).A0, CS, RD & A0, WR, CS

38. In 8279, the keyboard entries are de bounced and stored in an _________,
that is further accessed by the CPU to read the key codes.

a. 8-bit FIFO

b. 8-byte FIFO

c. 16 byte FIFO

d. 16 bit FIFO

Answer: (b).8-byte FIFO

39. For the most Static RAM the write pulse width should be at least

a. 10 ns

b. 60 ns

c. 300 ns

d. 350 ns

Answer: (b).60 ns
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

40. Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently

introduced microprocessor by__________.

a. Motorala

b. Intel

c. Stephen Mors

d. HCL

Answer: (b).Intel

41. The address bus flow in __________.

a. bidirection

b. unidirection

c. mulidirection

d. circular

Answer: (b).unidirection

42. The 8085 microprocessor is based in a ________ pin DIP.

a. 40

b. 45

c. 20

d. 35

Answer: (a).40
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

43. The 8085 Microprocessor uses__________ power supply.

a. +5V

b. -5V

c. +12V

d. -12V

Answer: (a).+5V

44. Which is used to store critical pieces of data during subroutines and
interrupts ?

a. Stack

b. Queue

c. Accumulator

d. Data register

Answer: (a).Stack

45. The data in the stack is called

a. Pushing data

b. Pushed

c. Pulling

d. None of these

Answer: (a).Pushing data

 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

46. The external system bus architecture is created using from ______
architecture.

a. Pascal

b. Dennis Ritchie

c. Charles Babbage

d. Von Neumann

Answer: (d).Von Neumann

47. Secondary memory can store____.

a. Program store code

b. Compiler

c. Operating system

d. All of these

Answer: (d).All of these

48. Secondary memory is also called____.

a. Auxiliary

b. Backup store

c. Both A and B

d. None of these

Answer: (c).Both A and B

 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

49. The lower red curvy arrow show that CPU places the address extracted
from the memory location on the_____.

a. Address bus

b. System bus

c. Control bus

d. Data bus

Answer: (a).Address bus

50. The CPU sends out a ____ signal to indicate that valid data is available on
the data bus.

a. Read

b. Write

c. Both a and b

d. None of these

Answer: (b).Write

UNIT-2
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

9. In a Microprocessor, the address of the new next instruction to be executed is

stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c. 4
d. 5
Answer. c
11. The insruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
12. Which one of the following statements is correct regarding the instruction
CMP A ?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

a. top of stack with contents of register pair

b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer. c
20. When referring to instruction words, a mnemonic is
a. a short abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. a short abbreviation for the data word stored at the operand address.
d. Shorthand for machine language.
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

There is a ‘cross-over frequency’ below which the period mode is preferred.

Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer. b
22. In a 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer. c
24. Ready pin 0f microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer. b
26. The operations executed by two or more control units are referred as
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit
register?
a. (a) 1, 3 and 4
b. 2, 3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
Answer. b
28. The first microprocessor to include virtual memory in the Intel
microprocessor family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine ,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (undefined) in Flag Register of an 8085 microprocessor?
a. 1, 3, 5
b. 2, 3, 5
c. 1, 2, 5
d. 1, 3, 4
Answer. a
31. At the beginning of a fetch cycle, the contents of the program counter are
a. incremented by one
 Allenhouse Institute of Technology (UPTU Code : 505)
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b. transferred to address bus

c. transferred to memory address register
d. transferred to memory data register
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
3. Operand field
4. Comment field
What is the correct sequence of these fields?
a. 1, 2, 3 and 4
b. 2, 1, 4 and 3
c. 1,3, 2 and 4
d. 2, 4, 1 and 3
Answer. a
33. The relation among IC (lnstruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC − EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC = IC+FC
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device.
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer. d
36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and
an indeterminate number of wait state clock cycles denoted by TW. The wait
states are always inserted between
a. T1 and T2
b. T2 and T3
 Allenhouse Institute of Technology (UPTU Code : 505)
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c. T3 and T4
d. T4 and T1
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0— D7 from the data bus
c. To disable data bus
d. To achieve all the functions listed above
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
d. Symbolic addressing
Answer. a
41. Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
 Allenhouse Institute of Technology (UPTU Code : 505)
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43. Which one of the following statements is correct regarding the instruction
CMP A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2, 3 and 4
c. 5 only
d. 1 only
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1, 2 and 3 only
b. 1 and 2 only
c. 1 and 3 only
d. 2 and 3 only
Answer. b
47. Among the given instructions, the one which affects maximum number of
flags is
a. RAL
b. POP PSW
c. XRA A
d. DCR A
 Allenhouse Institute of Technology (UPTU Code : 505)
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Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
49. Direction flag is used with
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer. d

UNIT-3
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
52. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
counter contains
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a.
the memory address as the instruction that is to be executed next.
b.
the memory address of the instruction that is being currently matched.
c.
the total number of instructions in the program being executed.
d.
the number of instructions in the current program that have already been
executed.
Answer. a
54. Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
55. LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer. b
56. Which of the following instructions is closest match to the instruction POP
PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
58. Which of the following 8085 instruction will require maximum T-states for
execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP
M use?
 Allenhouse Institute of Technology (UPTU Code : 505)
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a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
60. With reference to 8085 microprocessor, which of the following statements
are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor
contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C

b. ADD B; JNZ LOOP; DCR C

c. DCR C; JNZ LOOP; ADD B

d. ADD B; DCR C; JNZ LOOP

Answer. d
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63. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
64. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
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How many times DCR instruction will be executed?

a. 255
b. 510
c. 65025
d. 65279
Answer. d
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?

a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
70. The instruction PCHL, in 8085 is used for

a. Load PC with contents of HL.

b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction

a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
72. The instruction that exchanges top of stack with HL pair is

a. XTHL
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b. SPHL
c. PUSH H
d. POP H
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is

a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
74. While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be
executed.
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor
is performing
a. Reset operation
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer. c
77. LXI SP, 7FFF H
MVI A, 25 H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10 H
HLT
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What are the contents of A, H, L, SP and PSW registers after executing the above
set of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, 00H. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.

b. the total number of times a subroutine is called.

c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry”
in 8085 microprocessor is

a. ADI
b. ACI
c. ADC
d. ADD
Answer. b
80. MVI A, AA H
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer. b
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82. An 8085 microprocessor is executing the programme as follows:

MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
a. 4
b. 3
c. 2
d. 1
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of
execution of the sequence of instructions, what will be the content of the stack
pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
84. What is the correct 8085 assembly language instruction that stores the
contents of H and L registers into the memory locations 1080 H and 1081 H
respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H

Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer. b
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86. Which one of the following addressing technique is not used in 8085
microprocessor?

a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?

a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
88. Which one is the indirect addressing mode in the following instructions?

a. LXI H 2050 H
b. MOV A, B
c. LDAX B
d. LDA 2050 H
Answer. c
89. The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?

a. Direct
b. Register—indirect
c. Implicit
d. Immediate
Answer. d
90. Carry flag is not affected after the execution of

a. ADD B
b. SBB B
c. INR B
d. ORA B
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be

a. 2FFE H
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b. 2FFF H
c. 3000 H
d. 3001 H
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed

a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.

PUSH PSW
XTHL
PUSH D
JMP EC75 H
At the end of the execution of the above instructions, what would be the content
of the stack pointer?

a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?

a. Op-code for the instruction being executed

b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor
specifies which one of the following?

a. The address of the instruction being executed

b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
 Allenhouse Institute of Technology (UPTU Code : 505)
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Answer. c
96. Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085 microprocessor?

a. It points to the top of the stack.

b. It is UP/DOWN counter
c. It is automatically initialized to 0000 H on power-on
d. It is a 16-bit register
Answer. c
97. Which one of the following instructions is a 3-byte instruction?

a. MVI A
b. LDAX B
c. JMP 2050 H
d. MOV A,M
Answer. c
98. In 8085, the DAA instruction is used for

a. Direct Address Accumulator

b. Double Add Accumulator
c. Decimal Adjust Accumulator
d. Direct Access Accumulator
Answer. c
99. When an 8086 executes an INT type instruction, it?

a. Resets both IF and TF flags

b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
100. When an 8086 executes an INT type instruction, it?

a. Resets both IF and TF flags

b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
 Allenhouse Institute of Technology (UPTU Code : 505)
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UNIT-4

ASSEMBLY LANGUAGE PROGRAMMING Multiple Choice Questions :-

1) Assembly language programs are written using
A) Hex code
B) Mnenonics
C) ASCII code
D) None of these View

ANS: B

2) For execution of an interrupt applied at INTR, number of states required by

8085 Microprocessor are
A) 4
B) 6
C) 12
D) 18

ANS: C

3) In 8085 which is/are the 16 bit registers?

A) Program Counter
B) Stack Pointer
C) Both A) & B)
D) None of the above

ANS: C

4) How many memory locations are required to store the instruction LXIH,
0800H in an 8085 assembly language program?
A) 1
B) 2
C) 3
D) 4

ANS: B

5) The instruction DEC N inform the assembler to....

A) Decrement the content of N
B) Decrement the data addressed by N
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C) Convert signed decimal number to binary

D) None of the above

ANS: A

6) In 8085 microprocessor, the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction is stored in
the
A) carry status flag
B) auxiliary carry status flag
C) sign status flag
D) zero status flag

ANS: C

7) Instructions performing actions in assembly language are called

A) imperative statements
B) declarative statements
C) directive statements
D) none of the above
ANS: A

8) What is the content of Stack Pointer ?

A) Address of the current instruction
B) Address of the next instruction
C) Address of the top element of the stack
D) None of the above
ANS: C

9) Which of the following interrupt has highest Priority?

A) INTR
B) TRAP
C) RST 7.5
D) RST 6.5

ANS: B

10) Number of machine cycles required for RET instruction in 8085

microprocessor is
A) 1
B) 2
C) 3
D) 5
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ANS: C

11) __________ converts the programs written in assembly language into

machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter

Answer: c
Clarification: An assembler is a software used to convert the programs into
machine instructions.
12) The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned

Answer: a
Clarification: This OP – codes tell the system what operation to perform on the
operands.
13) The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way

Answer: b
Clarification: The ADDI instruction, means the addition is in immediate
addressing mode.
14) Instructions which won’t appear in the object program are called as
_____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives

Answer: d
Clarification: The directives help the program in getting compiled and hence
won’t be there in the object code.
15) The assembler directive EQU, when used in the instruction: Sum EQU
200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
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c) Re-assigns the address of Sum by adding 200 to its original address

d) Assigns 200 bytes of memory starting the location of Sum

Answer: b
Clarification: This basically is used to replace the variable with a constant value.
16) The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is
to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used

Answer: a
Clarification: This does the function similar to the main statement.
17) The directive used to perform initialization before the execution of
the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU

Answer: c
Clarification: None.
18) _____ directive is used to specify and assign the memory required for
the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve

Answer: d
Clarification: This instruction is used to allocate a block of memory and to store
the object code of the program there.
19) _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate

Answer: b
Clarification: This instruction directive is used to terminate the program
execution.
20) The last statement of the source program should be _______
a) Stop
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b) Return
c) OP
d) End

Answer: d
Clarification: This enables the processor to load some other process.
21) When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive

Answer: c
Clarification: When the assembler comes across the branch code, it immediately
finds the branch offset and replaces it with it.
22) The assembler stores all the names and their corresponding values in
______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned

Answer: b
Clarification: The table where the assembler stores the variable names along with
their corresponding memory locations and values.
23) The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk

Answer: d
Clarification: After compiling the object code, the assembler stores it in the
magnetic disk and waits for further execution.
24) The utility program used to bring the object code into memory for
execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker

Answer: a
Clarification: The program is used to load the program into memory.
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25) To overcome the problems of the assembler in dealing with

branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler

Answer: d
Clarification: This creates entries into the symbol table first and then creates the
object code.
26) In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
27) A ‘DAD H” instruction is the same as shifting each bit by one position
to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
28) When a program is being executed in an 8085 microprocessor, its
program counter contains
a. the memory address as the instruction that is to be executed next.
b. the memory address of the instruction that is being currently matched.
c. the total number of instructions in the program being executed.
d. the number of instructions in the current program that have already been
executed.
Answer. a
29) Which of the following data transfer is not possible in
microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
30) LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
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d. loads English like command and generates the binary code

Answer. b
31) Which of the following instructions is closest match to the
instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
32) How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
33) Which of the following 8085 instruction will require maximum T-
states for execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
34) In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
35) With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
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36) Assume that the accumulator and the register C of 8085

microprocessor contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution
of instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
37) It is desired to multiply the numbers 0A H by OB H and store the
result in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C

b. ADD B; JNZ LOOP; DCR C

c. DCR C; JNZ LOOP; ADD B

d. ADD B; DCR C; JNZ LOOP

Answer. d
38) Find the content of the accumulator after the execution of the
following program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
39) The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
 Allenhouse Institute of Technology (UPTU Code : 505)
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a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
40) The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
41) The content of accumulator are 70 H. Initially all flags are zero. What
will be values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
42) A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?

a. 255
b. 510
c. 65025
d. 65279
Answer. d
43) What is content of accumulator of 8085 microprocessor after the
execution of XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
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44) The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a frequency
of 2.5 MHz, how long is an instruction Cycle?

a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
45) The instruction PCHL, in 8085 is used for

a. Load PC with contents of HL.

b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
46) The following instruction copies a byte of data from the accumulator
into the memory address given in the instruction

a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
47) The instruction that exchanges top of stack with HL pair is

a. XTHL
b. SPHL
c. PUSH H
d. POP H
Answer. a
48) In 8085 microprocessor, during PUSH PSW Operation, Stack pointer
is

a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
49) While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
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a.The memory address of the instruction that is being currently executed.

b.The memory address of the instruction that is to be executed next.
c.The number of instructions that have already been executed.
d.The total number of instructions in the current program still to be
executed.
Answer. b
50) The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c

UNIT-5

Microprocessors Questions and Answers – Programmable DMA Interface

8237 (Part-1)

1. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned

Answer: b
Explanation: The program control block decodes various commands given to the
8237 by the CPU before servicing a DMA request.

2. The priority between the DMA channels requesting the services can be
resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned

Answer: c
Explanation: The priority encoder block resolves the priority between the DMA
channels requesting the services.
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3. The register that holds the current memory address is

a) current word register
b) current address register
c) base address register
d) command register

Answer: b
Explanation: The current address register holds the current memory address. The
current address register is accessed during the DMA transfer.

4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register

Answer: a
Explanation: The current word register is a 16-bit register that holds the data
transfers. The word count is decremented after each transfer, and the new value
is stored again in the register.

5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated

Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can
be written in successive bytes by the CPU, in program mode.

6. The current address register is programmed by the CPU as

a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Explanation: The current address register is byte-wise programmed by the CPU,
i.e. lower byte first and the higher byte later.

7. Which of these register’s contents is used for auto-initialization (internally)?

a) current word register
 Allenhouse Institute of Technology (UPTU Code : 505)
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b) current address register

c) base address register
d) command register

Answer: c
Explanation: The contents of base address register cannot be read by the CPU.
These contents are used internally for auto-initialization.

8. The register that maintains an original copy of the respective initial current
address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register

Answer: b
Explanation: The base address register maintains an original copy of the current
address register and current word register, before incrementing or
decrementing.

9. The register that can be automatically incremented or decremented, after each

DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register

Answer: d
Explanation: The address is automatically incremented or decremented after
each DMA transfer, and the resulting address value is again stored in the current
address register.

10. Which of the following is a type of DMA transfer?

a) memory read
b) memory write
c) verify transfer
d) all of the mentioned

Answer: d
Explanation: Memory read, memory write and verify transfer are the three types
of DMA transfer.
 Allenhouse Institute of Technology (UPTU Code : 505)
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Microprocessors Questions and Answers – 8255 programmable peripheral

interface-(Part-2)

Question 1: How many pins does the 8255 PPI IC contains?

a. 24
b. 20
c. 32
d. 40

Answer: d. 40

Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: b. Mode 0 of I/O mode

Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?

a. CS'
b. RD'
c. WR'
d. ALL of the above

Answer: d. All of the above

Question 4: In which of the following modes is the 8255 PPI capable of

transferring data while handshaking with the interfaced device?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: c. Mode 1 of I/O mode

 Allenhouse Institute of Technology (UPTU Code : 505)
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Question 5: How many bits of data can be transferred between the 8255 PPI and
the interfaced device at a time? or What is the size of internal bus of the 8255
PPI?

a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above

Answer: c. 8 bits

Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?

a. Port A
b. Port B
c. Port C
d. All of the above

Answer: c. Port C

Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: a. BSR mode

Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?

a. Port A
b. Port B
c. Port C
d. All of the above

Answer: a. Port A

Question 9: In which of the following modes we do not consider the D6, D5 and
D4 bits of the control word?

a. BSR mode
b. Mode 0 of I/O mode
 Allenhouse Institute of Technology (UPTU Code : 505)
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c. Mode 1 of I/O mode

d. Mode 2 of I/O mode

Answer: a. BSR mode

Question 10: How many data lines in total are there in the 8255 PPI IC?

a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above

Answer: c. 24 data lines

Microprocessors Questions and Answers – 8253/8254programmable

timer/counter-(Part-3)

1. The number of counters that are present in the programmable timer device
8254 is
a) 1
b) 2
c) 3
d) 4

Answer: c
Explanation: There are three counters that can be used as either counters or
delay generators.

2. The operation that can be performed on control word register is

a) read operation
b) write operation
c) read and write operations
d) none

Answer: b
Explanation: The control word register can only be written and cannot be read.

3. The mode that is used to interrupt the processor by setting a suitable terminal
count is
a) mode 0
 Allenhouse Institute of Technology (UPTU Code : 505)
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b) mode 1
c) mode 2
d) mode 3

Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.

4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output
becomes low for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles

Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If
the count N is reloaded and again the output becomes high and remains so for (N-
1) clock pulses.

5. The generation of a square wave is possible in the mode

a) mode 1
b) mode 2
c) mode 3
d) mode 4

Answer: c
Explanation: When the count N loaded is even, then for half of the count, the
output remains high and for the remaining half it remains low. If the count loaded
is odd, the first clock pulse decrements it by 1 resulting in an even count value.

6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none

Answer: b
Explanation: SC denotes select counter.
 Allenhouse Institute of Technology (UPTU Code : 505)
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7. In control word format, if RL1=1, RL0=1 then the operation performed is

a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB

Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.

8. If BCD=0, then the operation is

a) decimal count
b) hexadecimal count
c) binary count
d) octal count

Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is
BCD count.

9. The counter starts counting only if

a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high

Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.

10. The control word register contents are used for

a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned

Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
 Allenhouse Institute of Technology (UPTU Code : 505)
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Microprocessors Questions and Answers – 8259 programmable interrupt

controller-(Part-4)

1. The number of hardware interrupts that the processor 8085 consists of is

a) 1
b) 3
c) 5
d) 7
View Answer

Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these
five, four pins were alloted fixed vector addresses but the pin INTR was not
alloted by vector address, rather an external device was supposed to hand over
the type of the interrupt to the microprocessor.

2. The register that stores all the interrupt requests in it in order to serve them
one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register

Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request
Register internally.

3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None

Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request
Register) at the direction of the Priority Resolver.
 Allenhouse Institute of Technology (UPTU Code : 505)
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4. The interrupt control logic

a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned

Answer: d
Explanation: The interrupt control logic performs all the operations that are
involved within the interrupts like accepting and managing interrupt
acknowledge signals, interrupts.

5. In a cascaded mode, the number of vectored interrupts provided by 8259A is

a) 4
b) 8
c) 16
d) 64

Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64
vectored interrupts can be provided.

6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode,
then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none

Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a
buffer enable to control buffer transreceivers. If it is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master or
a slave.

7. Once the ICW1 is loaded, then the initialization procedure involves

a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned

Answer: d
Explanation: The initialization procedure involves
 Allenhouse Institute of Technology (UPTU Code : 505)
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i) edge sense circuit is reset.

ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.

8. When non-specific EOI command is issued to 8259A it will automatically

a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR

Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR.

9. In the application where all the interrupting devices are of equal priority, the
mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI

Answer: a
Explanation: The automatic rotation is used in the applications where all the
interrupting devices are of equal priority.

Microprocessors Questions and Answers – 8251 USART and

RS232C- (Part-5)

1. Which of the following is not a mode of data transmission?

a) simplex
b) duplex
c) semi duplex
d) half duplex

Answer: c
Explanation: Basically, there are three modes of data transmission. simplex,
duplex and half duplex.
 Allenhouse Institute of Technology (UPTU Code : 505)
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2. If the data is transmitted only in one direction over a single communication

channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode

Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For
example, a CPU may transmit data for a CRT display unit in this mode.

3. If the data transmission takes place in either direction, but at a time data may
be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode

Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a
time. For example, Walkie-Talkie.

4. In 8251A, the pin that controls the rate at which the character is to be
transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)

Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the
rate at which the character is to be transmitted.

5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted

data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned

Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

transmitted data bits along with other information like start bits, stop bits and
parity bits etc.

6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)

Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the
CPU or polled by the CPU.

7. The disadvantage of RS-232C is

a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned

Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like
limited speed of communication, high-voltage level signaling and big-size
communication adapters.

8. The USB supports the signaling rate of

a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned

Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.

9. The bit packet that commands the device either to receive data or transmit
data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
 Allenhouse Institute of Technology (UPTU Code : 505)
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Answer: b
Explanation: The token packet is the second type of packet which commands the
device either to receive data or transmit data.

10. High speed USB devices neglect

a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet

Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
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www.studymaterialz.in
IMPORTANT MCQ- MICROPROCESSORS
1. The minimum number of transistors required to implement a two input AND gate is
A. 2
B. 4
C. 6
D. 8
Answer: C
2. Using DeMorgan’s Theorem we can convert any AND-OR structure into
A. NAND-NAND
B. OR-NAND
C. NAND-NOR
D. NOR-NAND
Answer: A
3. For a memory with a 16-bit address space, the addressability is
A. 16 bits
B. 8 bits
C. 2^16 bits
D. Cannot be determined
Answer: D
4. Because we wish to allow each ASCII code to occupy one location in memory, most memories are
_____ addressable.
A. BYTE
B. NIBBLE
C. WORD (16 bits)
D. DOUBLEWORD (32 bits)
Answer: A
5. Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.
A. Circuit A has more gates than circuit B
B. Circuit B has more gates than circuit A
C. Circuit A has the same number of gates as circuit B
(Hint: Construct the truth table for the adder and the multiplier)
Answer: A
6. When the write enable input is not asserted, the gated D latch ______ its output.
A. can not change
B. clears
C. sets
D. complements
Answer: A
7. A structure that stores a number of bits taken “together as a unit” is a
A. gate
B. mux
C. decoder
D. register
Answer: D
www.studymaterialz.in
8. We say that a set of gates is logically complete if we can build any circuit without using any other
kind of gates. Which of the following sets are logically complete
A. set of {AND,OR}
B. set of {EXOR, NOT}
C. set of {AND,OR,NOT}
D. None of the above
Answer: C
9. Of the following circuits, the one which involves storage is
A. RS Latch
B. mux
C. nand
D. decoder
Answer: A
10. If the number of address bits in a memory is reduced by 2 and the
addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)
A. doubles
B. remains unchanged
C. halves
D. increases by 2^(address bits)/addressability
Answer : C
12. If m is a power of 2, the number of select lines required for an m-input mux is:
A. m
B. 2^m
C. log2 (m)
D. 2*m
Answer: C
13. For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2].
A. less than
B. greater than
C. the same as
d . cannot be determined
Answer: C
14. Which of the following conditions is not allowed in an RS latch?
A. R is asserted, S is asserted
B. R is asserted, S is negated
C. R is negated, S is asserted
D. R is negated, S is negated
Answer: A
15. Which of the following pair of gates can form a latch?
A. a pair of cross coupled OR
B. a pair of cross copled AND
C. a pair of cross coupled NAND
D. a cross coupled NAND/OR
Answer: C
www.studymaterialz.in
16. ‘Burst refresh’ in DRAM is also called
A. Concentrated refresh
B. Distributed refresh
C. Hidden refresh
D. None of the above
Answer: A
17. The number of interrupt lines in 8085 is
A. 2
B. 3
C. 4
D. 5
Answer: D
18. A real number consists of
A. integer part
B. integer part and fraction part
C. integer part, fraction part along with positive or negative sign
D. none of the above
Answer: C
19. Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but
not in earlier versions of Fortran.
Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct R is wrong
D. A is wrong R is correct
Answer: B
20. Which of the following is not treated as hexadecimal constant by assembler in 8085?
A. 45 H
B. 6 AFH
C. 234
D. 64 H
Answer: C
21. IC 7485 cannot be cascadeD.
A. True
B. False
Answer: B
22. An I/O processor controls the flow of information between
A. cache memory and I/O devices
B. main memory and I/O devices
C. two I/O devices
D. cache and main memory
Answer: B
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23. MS Access is a DBMS software.
A. True B. False
Answer: A
24. When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode
A. none of the numbers is changed
B. .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed
C. .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed
D. both Ihe numbers are changed and their exponents are, made equal to -5
Answer: B
25. DS directive in 8085
A. forces the assembler to reserve one byte of memory
B. forces the assembler to reserve a specified number of bytes in the memory
C. forces the assembler to reserve a specified number of consecutive bytes in the memory
D. none of the above
Answer: C
26. Which of the following is a valid integer constant?
A. 127
B. 127.0
C. 127
D. 125 + 3
Answer: A
27. The five flags in 8085 are designated as
A. Z, CY, S, P and AC
B. D, Z, S, P, AC
C. Z, C, S, P, AC
D. Z, CY, S, D, AC
Answer: A
28. In 8085 which addressing mode is also called inherent addressing?
A. Direct
B. Register
C. Implicit
D. Immediate
Answer: C
29. It is possible to copy a file in the same directory.
A. True
B. False
Answer: A
30. In a computer the data transfer between hard disk and CPU is nearly the same as that between
diskette and CPU.
A. True
B. False
Answer: B
www.studymaterialz.in
31. The timing difference between a slow memory and fast processor can be resolved if
A. processor is capable of waiting
B. external buffer is used
C. either (a) or (b)
D. neither (a) nor (b)
Answer: C
32. In 8086 the number of bytes which can be addressed directly is about
A. 1000
B. 10000
C. 100000
D. one million
Answer: D
33. In Fortran 77 a variable name can contain special characters.
A. True
B. False
Answer: B
34. Which of the following is not a general purpose peripheral?
A. I/O port
B. Programmable interrupt controller
C. Programmable CRT controller
D. Programmable interval timer
Answer: C
35. Each instruction in assembly language program has the following fields:
Lable field
Mnemonic field
Operand field
Comment field
The correct sequence of these fields is?
A. 1, 2, 3, 4
B. 1, 2, 4, 3
C. 2, 1, 3, 4
D. 2, 1, 4, 3
Answer: A
36. In one’s complement 8 bit representation 11111111 represents
A. +0
B. -0
C. +1
D. -1
Answer: B
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37. The operating modes of 8255 A are called
A. mode 0 and mode 1
B. mode 0, mode 1 and mode 2
C. mode 0 and mode 2
D. mode 0, mode 2 and mode 3
Answer: B
38. Which of the following is type declaration statement in C?
A. int bar
B. s = s + 1
C. king = horse + 1
D. prin = prin * prin
Answer: A
39. Internet is a worldwide network of computers where most of the information is freely available.
A. True
B. False
Answer: A
40. A 37 bit mantissa has an accuracy of
A. 6 decimal places
B. 8 decimal places
C. 10 decimal places
D. 11 decimal places
Answer: D
41. In a C expression using assignment operators, relational operators and arithmetic operators, the
hierarchy of operations (in the absence of parenthesis) is
A. assignment, relational, arithmetic
B. relational, assignment, arithmetic
C. arithmetic, assignment, relational
D. arithmetic, relational, assignment
Answer: D
42. In 8085, the pins for SID and SOD are
A. 4 and 5 respectively
B. 5 and 4 respectively
C. 3 and 4 respectively
D. 4 and 3 respectively
Answer: B
43. Assertion (A): Each memory chip has its own address latch.
Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip.
A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is correct R is wrong
D. A is wrong R is correct
Answer: D
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44. An e-mail message can be sent to many recipients.
A. True
B. False
Answer: A
45. In C the keywords are also called
A. special words
B. reserved words
C. class words
D. character words
Answer: B
46. The character set of Fortran 77 includes lower case alphabets a to z.
A. True
B. False
Answer: B
47. Which memory has read operation, byte erase, byte write and chip erase?
A. RAM
B. UVEPROM
C. EEPROM
D. both (b) and (c)
Answer: C
48. The forms of IF statements in FORTRAN 77 are called
A. logical IF and Block IF
B. logical IF, block IF and arithmetic IF
C. logic IF, block IF, arithmetic IF and negate IF
D. logical IF and arithmetic IF
Answer: B
49. In 8085
A. P flag is set when the result has even parity
B. P flag is set when the result has odd parity
C. P flag is reset when the result has odd parity
D. P flag is reset when the result has even parity
Answer: A
50. If the sign bit of mantissa is 0 and the exponent is increased from a positive to a more negative
number the result is
A. a larger floating point number
B. a smaller floating point number
C. either (a) or (b) depending on the actual number
D. a negative floating point number
Answer: A
Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors

1. Which interrupt has the highest priority?

a) INTR b) TRAP c) RST6.5
2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter c) a & b
3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b
4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4
5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising edge-trigging interrupt.
b) RST7.5 is a raising edge-trigging interrupt.
c) a & b.
7. What are software interrupts?
a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP
8. Which stack is used in 8085?
a) FIFO b) LIFO c) FILO
9. Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU.
b) Because 8085 processor has 8 bit data bus.
c) a & b.
10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
11. RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
12. What is meant by Maskable interrupts?
a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none
13. In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR
14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width
15. Can ROM be used as stack?
a) Yes b) No c) sometimes yes, sometimes no
16. Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H
18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/1

Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors

d) During subtraction
19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
c) Require a bigger address decoder
d) All the above
20. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory
b) Odd bank memory
c) I/O
d) DMA
21. In 8086 microprocessor the following has the highest priority among all type
interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode
b) Coprocessor is interfaced in MIN mode
c) I/O can be interfaced in MAX / MIN mode
d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output
b) Address capability
c) Support of coprocessor
d) Support of MAX / MIN mode
24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/2

Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors

Key:
1.1 C 1.2 C 1.3 C 1.4 B 1.5 B 1.6 B
1.7 A 1.8 B 1.9 A 1.10 C 1.11 B 1.12 B
1.13 A 1.14 C 1.15 B 1.16 C 1.17 C 1.18 B
1.19 D 1.20 B 1.21 A 1.22 B 1.23 A 1.24 B

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/3

Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors

1. Which interrupt has the highest priority?

a) INTR b) TRAP c) RST6.5
2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter c) a & b
3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b
4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4
5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising edge-trigging interrupt.
b) RST7.5 is a raising edge-trigging interrupt.
c) a & b.
7. What are software interrupts?
a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP
8. Which stack is used in 8085?
a) FIFO b) LIFO c) FILO
9. Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU.
b) Because 8085 processor has 8 bit data bus.
c) a & b.
10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
11. RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
12. What is meant by Maskable interrupts?
a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none
13. In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR
14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width
15. Can ROM be used as stack?
a) Yes b) No c) sometimes yes, sometimes no
16. Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H
18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/1

Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors

d) During subtraction
19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
c) Require a bigger address decoder
d) All the above
20. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory
b) Odd bank memory
c) I/O
d) DMA
21. In 8086 microprocessor the following has the highest priority among all type
interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode
b) Coprocessor is interfaced in MIN mode
c) I/O can be interfaced in MAX / MIN mode
d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output
b) Address capability
c) Support of coprocessor
d) Support of MAX / MIN mode
24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/2

Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors

Key:
1.1 C 1.2 C 1.3 C 1.4 B 1.5 B 1.6 B
1.7 A 1.8 B 1.9 A 1.10 C 1.11 B 1.12 B
1.13 A 1.14 C 1.15 B 1.16 C 1.17 C 1.18 B
1.19 D 1.20 B 1.21 A 1.22 B 1.23 A 1.24 B

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/3

 MICROPROCESSOR 49 IMPORTANT MCQ

Q.1 If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is
(A) 2.5 MHz. (B) 5 MHz.
(C) 7.5 MHz. (D) 10 MHz.

Ans: (A)

Q.2 In which T-state does the CPU sends the address to memory or I/O and the ALE signal
for demultiplexing
(A) T1. (B) T2.
(C) T3. (D) T4.

Ans, During the first clocking period in a bus cycle, which is called T1, the address of
the memory or I/O location is sent out and the control signals ALE, DT/R’ and IO/M’
are also output. Hence answer is (A).

Q.3 If a 1M ×1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no
more than _ of time must pass before another row is refreshed.
(A) 64 ms. (B) 4 ns.
(C) 0.5 ns. (D) 15.625 µs .

Ans Answer is (B)

Q.4 In a DMA write operation the data is transferred

(A) from I/O to memory. (B) from memory to I/O.
(C) from memory to memory. (D) from I/O to I/O.

Ans A DMA writes operation transfers data from an I/O device to memory. Hence
answer is (A).
Q.5 Which type of JMP instruction assembles if the distance is 0020 h bytes
(A) near. (B) far.
(C) short. (D) none of the above.

Ans The three byte near jump allows a branch or jump within ± 32K bytes. Hence
answer is (A).

Q.6 A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following

modes this SRAM is operating

(A) Read (B) Write

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(C) Stand by (D) None of the above

Ans For CS’=WE’=0, write operation. Hence answer is (B).

Q.7 Which of the following is true with respect to EEPROM?

(A) contents can be erased byte wise only.
(B) contents of full memory can be erased together.
(C) contents can be erased using ultra violet rays
(D) contents can not be erased

Ans Answer is (C).

Q.8 Pseudo instructions are basically

(A) false instructions.
(B) instructions that are ignored by the microprocessor.
(C) assembler directives.
(D) instructions that are treated like comments.

Ans Pseudo-instructions are commands to the assembler. All pseudo-operations start

with a period. Pseudo-instructions are composed of a pseudo-operation which may be
followed by one or more expressions. Hence answer is (C).

Q.9 Number of the times the instruction sequence below will loop before coming out of
loop is
MOV AL, 00h
A1: INC AL
JNZ A1
(A) 00 (B) 01
(C) 255 (D) 256

Ans Answer is (D)

Q.10 What will be the contents of register AL after the following has been executed
MOV BL, 8C
MOV AL, 7E
ADD AL, BL
(A) 0A and carry flag is set (B) 0A and carry flag is reset
(C) 6A and carry flag is set (D) 6A and carry flag is reset

Ans, Result is 1,0A. Hence answer is (A).

Q.11 Direction flag is used with

(A) String instructions. (B) Stack instructions.
(C) Arithmetic instructions. (D) Branch instructions.

Ans The direction flag is used only with the string instructions. Hence answer is (A).

Q.12 Ready pin of a microprocessor is used

(A) to indicate that the microprocessor is ready to receive inputs.
(B) to indicate that the microprocessor is ready to receive outputs.
(C) to introduce wait states.
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(D) to provide direct memory access.

Ans This input is controlled to insert wait states into the timing of the microprocessor.
Hence answer is (C).

Q.13 These are two ways in which a microprocessor can come out of Halt state.
(A) When hold line is a logical 1.
(B) When interrupt occurs and the interrupt system has been enabled.
(C) When both (A) and (B) are true.
(D) When either (A) or (B) are true.

Ans Answer is (A)

Q.14 In the instruction FADD, F stands for

(A) Far. (B) Floppy.
(C) Floating. (D) File.

Ans Adds two floating point numbers. Hence answer is (C).

Q.15 SD RAM refers to

(A) Synchronous DRAM (B) Static DRAM
(C) Semi DRAM (D) Second DRAM

Ans, Answer is (A)

Q.16 In case of DVD, the speed is referred in terms of n X (for example 32 X). Here, X
refers to
(A) 150 KB/s (B) 300 KB/s
(C) 1.38 MB/s (D) 2.4 MB/s

Ans Answer is (C).

Q.17 Itanium processor of Intel is a

(A) 32 bit microprocessor. (B) 64 bit microprocessor.
(C) 128 bit microprocessor. (D) 256 bit microprocessor.

Ans The Itanium is a 64-bit architecture microprocessor. Hence answer is (B).

Q.18 LOCK prefix is used most often

(A) during normal execution. (B) during DMA accesses
(C) during interrupt servicing. (D) during memory accesses.

Ans LOCK is a prefix which is used to make an instruction of 8086 non-interruptable.

Hence answer is (C).

Q.19 The Pentium microprocessor has execution units.

(A) 1 (B) 2
(C) 3 (D) 4

Ans The Pentium microprocessor is organized with three execution units. One
executes floating-point instructions, and the other two (U-pipe and V-pipe) execute
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integer instructions. Hence answer is (C).

Q.20 EPROM is generally erased by using

(A) Ultraviolet rays (B) infrared rays
(C) 12 V electrical pulse (D) 24 V electrical pulse

Ans The EPROM is erasable if exposed to high-intensity ultraviolet light for about 20
minutes or less. Hence answer is (A)

Q.21 Signal voltage ranges for a logic high and for a logic low in RS-232C standard are
(A) Low = 0 volt to 1.8 volt, high = 2.0 volt to 5 volt
(B) Low =-15 volt to –3 vol, high = +3 volt to +15 volt
(D) Low = +3 volt to +15 volt, high = -3 volt to -15 volt
(E) Low = 2 volt to 5.0 volt, high = 0 volt to 1.8 volt

Ans Answer is (B)

Q.22 The PCI bus is the important bus found in all the new Pentium systems because
(A) It has plug and play characteristics
(B) It has ability to function with a 64 bit data bus
(C) Any Microprocessor can be interfaced to it with PCI controller or bridge
(D) All of the above

Ans, Answer is (D).

Q.23 Which of the following statement is true?
(A) The group of machine cycle is called a state.
(B) A machine cycle consists of one or more instruction cycle.
(C) An instruction cycle is made up of machine cycles and a machine cycle is
made up of number of states.
(D) None of the above

Ans An instruction cycle consists of several machine cycles. Hence Answer is (B).

Q.24 8251 is a
(A) UART
(B) USART
(C) Programmable Interrupt controller
(D) Programmable interval timer/counter

Ans The Intel 8251 is a programmable communication interface. It is USART.

Q.25 8088 microprocessor has

(A) 16 bit data bus (B) 4 byte pre-fetch queue

(C) 6 byte pre-fetch queue (D) 16 bit address bus

Ans The 8088 is a 16-bit microprocessor with an 8-bit data bus. The 16-bit address
bus. Hence answer is (D).

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Q.26 By what factor does the 8284A clock generator divide the crystal oscillator’s output
frequency?
(A) One (B) Two
(C) Three (D) Four

Ans When F/C’ is at logic 0; The oscillator output is steered through to the divide- by-
3 counter. Hence answer is (c).

Q.27 The memory data bus width in Pentium is

(A) 16 bit (B) 32 bit
(C) 64 bit (D) None of these

Ans The Data bus width is 64 bits. Hence answer is (C).

Q.28 When the 82C55 is reset, its I/O ports are all initializes as
(A) output port using mode 0 (B) Input port using mode 1
(C) output port using mode 1 (D) Input port using mode 0

Ans A RESET input to the 82C55 causes all ports to be set up as simple input ports
using mode 0 operations. Hence answer is (D).

Q.29 Which microprocessor pins are used to request and acknowledge a DMA transfer?
(A) reset and ready (B) ready and wait
(C) HOLD and HLDA (D) None o these

Ans, The HOLD pin is an input that is used request a DMA action and the HLDA
pin is an output that that acknowledges the DMA action. Hence answer is (C).

Q.30 Which of the following statement is false?

(A) RTOS performs tasks in predictable amount of time
(B) Windows 98 is RTOS
(C) Interrupts are used to develop RTOS
(D) Kernel is the one of component of any OS

Ans Operating systems, like Windows, defer many tasks and do not guarantee their
execution in predictable time. Hence answer is (B).

Q.31 The VESA local bus operates at

(A) 8 MHz (B) 33 MHz
(C) 16 MHz (D) None of these

Ans The VESA local bus operates at 33 MHz. Hence answer is (B).

Q.32 The first modern computer was called .

(A) FLOW-MATIC (B) UNIVAC-I
(C) ENIAC (D) INTEL

Ans, ENIAC (Electronic Numerical Integrator And Computer) was the first general-
purpose electronic computer. It was a Turing-complete, digital computer capable of
being reprogrammed to solve a full range of computing problems. ENIAC was

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designed to calculate artillery firing tables for the U.S. Army's Ballistic Research
Laboratory. Hence answer is (c).

Q.33 Software command CLEAR MASK REGISTER in DMA

(A) Disables all channels.
(B) Enables all channels.
(C) None.
(D) Clears first/last flip-flop within 8237.

Ans Enables all four DMA channels. Hence answer is (B).

Q.34 The first task of DOS operating system after loading into the memory is to use the file
called .
(A) HIMEM.SYS (B) CONFIG.SYS
(C) AUTOEXEC.BAT (D) SYSTEM.INI

Ans, The first task of the DOS operating system, after loading into memory, is to
use a file called the CONFIG.SYS file. This file specifies various drivers that load
into the memory, setting up or configuring the machine for operation under DOS.

Q.35 If the programmable counter timer 8254 is set in mode 1 and is to be used to count
six events, the output will remain at logic 0 for number of counts
(A) 5 (B) 6
(C) 0 (D) All of the above

Ans. OUT continues for the total length of the count. Hence answer is (B).

Q.36 The flash memory is programmed in the system by 12 V programming pulse.

(A) TRUE (B) FALSE

Ans The flash memory device requires a 12V programming voltage to erase and write
new data. Hence answer is (A).

Q.37 A plug and play (PnP) interface is one that contains a memory that holds
configuration information of the system.
(A) TRUE (B) FALSE

Ans Answer is (A)

Q.38 The accelerated graphics port (AGP) allows virtually any microprocessor to be
interfaced with PCI bus via the use of bridge interface.
(A) TRUE (B) FALSE

Ans, this port probably will never be used for any devices other than the video card.
Hence answer is (B).

Q.39 A Bus cycle is equal to how many clocking periods

(A) Two (B) Three
(C) Four (D) Six

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Ans Typically, the bus-cycle of the 8086 and 8088 processors consist of four clock
cycles or pulses. Thus, duration of a bus-cycle is = ‘4*T’. Hence Answer is (C).

Q.40 The time required to refresh a typical DRAM is

(A) 2 – 4 us (B) 2 – 4 ns
(C) 2 – 4 ms (D) 2 – 4 ps

Ans The capacitor Cs discharges through the internal resistance of the NMOS transistor
T1. Typically Cs = 0.2 pF and the internal resistance Rin = 1010 ohms, so:
Cs x Rin = 0.2 x 10-12 x 1010 x 103 ms = 2 ms
So the typical refresh time interval is 2 ms. Hence Answer is (C).

Q.41 The no. of address lines required to address a memory of size 32 K is

(A) 15 lines (B) 16 lines
(C) 18 lines (D) 14 lines
5 10 15
Ans 32K = 32 X 1024 bits = 2 X 2 =2 Hence answer is ( A).

Q.42 The no. of wait states required to interface 8279 to 8086 with 8MHz clock are
(A) Two (B) Three
(C) One (D) None

Ans Two wait states used so that device can function with an 8 MHz. Hence answers is
( A).

Q.43 NMI input is

(A) Edge sensitive (B) Level sensitive
(C) Both edge and level triggered (D) edge triggered and level sensitive

Ans Non-maskable interrupt (NMI) is an edge –triggered input that requests an

interrupt on the positive edge (0 to 1 transition).

Q.44 Data rate available for use on USB is

(A) 12 Mbits per second (B) 1.5 Mbits per second
(C) Both (A) and (B) (D) No restriction

Ans Data transfer speeds are 12 Mbps for full speed operation and 1.5 Mbps for slow
speed operation. Hence answer is (c).
Q.45 In 80186, the timer which connects to the system clock is
(A) timer 0 (B) timer 1
(C) timer 2 (D) Any one can be connected

Ans. Timer 2 is internal and clocked by the master clock. Hence answer is (c).

Q.46 Conversion of the +1000 decimal number into signed binary word results
(A) 0000 0011 1110 1000 (B) 1111 1100 0001 1000
(C) 1000 0011 1110 1000 (D) 0111 1100 0001 1000

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Ans

1000 /2 =>500 €0
500/2=>250€0
250/2=>125€0
125/2=>62€1
62/2=>31€0
31/2=>15€1
15/2=>7€1
7/2=>3€1
3/2=>1€1
16 bit signed number is 1000,0011,1110,1000
Hence Answer is (C).

Q.47 What do the symbols [ ] indicate?

(A) Direct addressing (B) Register Addressing
(C) Indirect addressing (D) None of the above

Ans Answer is (C).

Q.48 SDRAM refers to

(A) static DRAM (B) synchronous DRAM
(C) sequential DRAM (D) semi DRAM

Ans, Answer is (B)

Q.49 Which pins are general purpose I/O pins during mode-2 operation of the 82C55?
(A) PA0 – PA7 (B) PB0-PB7
(C) PC3-PC7 (D) PC0-PC2

Ans In mode 2 Port-A can be programmed to operate as bidirectional port. The mode-2
operation is only for Port-A. Hence Answer is (A)

8
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Date-16/06/2021
Subject Name-KCS-403-Microprocessor_CSE-Semester 4
UNIT-1

1. In 8085 microprocessor, the RST6 instruction transfer programme execution

to following location

a. 0030H

b. 0024H

c. 0048H

d. 0060H

Answer: (a).0030H

2. HLT opcode means

a. load data to accumulator

b. store result in memory

c. load accumulator with contents of register

d. end of program

Answer: (d).end of program

3. What is SIM?

a. Select interrupt mask

b. Sorting interrupt mask

c. Set interrupt mask

d. None of these
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Answer: (c).Set interrupt mask

4. The ROM programmed during manufacturing process itself is called

a. MROM

b. PROM

c. EPROM

d. EEPROM

Answer: (a).MROM

5. A field programmable ROM is called

a. MROM

b. PROM

c. FROM

d. FPROM

Answer: (b).PROM

6. The operations executed by two or more control units are referred as

a. Micro-operations

b. Macro-operations

c. Multi-operations

d. Bi control-operations

Answer: (b).Macro-operations
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

7. Program counter in a digital computer

a. Counts the numbers of programs run in the machine.

b. Counts the number of times a subroutine is called.

c. Counts the number of times the loops are executed.

d. Points the memory address of the next instruction to be fetched.

Answer: (d).Points the memory address of the next instruction to be fetched.

8. At the beginning of a fetch cycle, the contents of the program

counter are

a. incremented by one.

b. transferred to address bus.

c. transferred to memory address register.

d. transferred to memory data register.

Answer: (c).transferred to memory address register.

9. Which components are NOT found on chip in a microprocessor but may be

found on chip in a micro-controller?

a. SRAM & USART

b. EPROM & PORTS

c. EPROM, USART & PORTS

d. SRAM, EPROM & PORTS

Answer: (c).EPROM, USART & PORTS

 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

10. For the purpose of data processing an efficient assembly language

programmer makes use of the general purpose registers rather than
memory. The reason is

a. the set of instructions for data processing with memory is limited

b. data processing becomes easier when register are used

c. more memory related instructions are required

d. data processing with registers takes fewer cycles than that with memory

Answer: (d).data processing with registers takes fewer cycles than that with memory

11. The first machine cycle of an instruction is always

a. A memory read cycle

b. A fetch cycle

c. An I/O read cycle

d. A memory write cycle

Answer: (b).A fetch cycle

12. The output data lines of microprocessor and memories are usually tristated
because

a. More than one device can transmit information over the data bus by enabling
only one device at a time

b. More than one device can transmit over the data bus at the same time

c. The data line can be multiplexed for both input and output

d. It increases the speed of data transfer over the data bus

Answer: (a).More than one device can transmit information over the data bus by
enabling only one device at a time
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

13. The correct sequence of steps in the instruction cycle of a basic computer is

a. Fetch, Execute, Decode and Read effective address.

b. Read effective address,Decode,Fetch and Execute.

c. Fetch, Decode, Read effective address and ,Execute.

d. Fetch, Read effective address, Decode and Execute.

Answer: (c).Fetch, Decode, Read effective address and ,Execute.

14. The register which holds the information about the nature of results of
arithmetic and logic operations is called as

a. Accumulator

b. Condition code register

c. Flag register

d. Process status register

Answer: (c).Flag register

15. Consider the following statements:

Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?

a. 1, 2, 3 and 4

b. 1, 2 and 3

c. 1 and 2 only
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

d. 3 and 4 only

Answer: (c).1 and 2 only

16. Ready pin of microprocessor is used

a. to indicate that microprocessor is ready to receive inputs

b. to indicate that microprocessor is ready to receive outputs

c. to introduce wait state

d. to provide direct memory access

Answer: (c).to introduce wait state

17. Both the ALU and control section of CPU employ which special purpose
storage location?

a. Buffers

b. Decoders

c. Accumulators

d. Registers

Answer: (c).Accumulators

18. A high on RESET OUT signifies that

a. all the registers of the CPU are being reset

b. all the registers and counters are being reset

c. all the registers and counters are being reset and this signal can be used to
reset external support chip
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

d. processing can begin when this signal goes high

Answer: (c).all the registers and counters are being reset and this signal can be
used to reset external support chip

19. In a vector interrupt

a. the branch address is assigned to a fixed location in memory

b. the interrupting source supplies the branch information to the processor

through an interrupt vector

c. the branch address is obtained from a register in the processor

d. none of the above

Answer: (a).the branch address is assigned to a fixed location in memory

20. The content of the A15-A8 (higher order address lines) while executing “IN
8-bit port address” instruction are

a. same as the content of A7-A0

b. irrelevant

c. all bits reset (i.e. 00H)

d. all bits set (i.e. FFH)

Answer: (a).same as the content of A7-A0

21. Which one of the following interrupt is only level triggering?

a. TRAP

b. RST 7.5

c. RST 6.5 and RST 5.5

d. RST 6.5
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Answer: (c).RST 6.5 and RST 5.5

22. Which one of the following instruction may be used to clear the
accumulator content irrespective of its initial value?

a. CLR A

b. ORA A

c. SUB A

d. MOV A, 00H

Answer: (c).SUB A

23. ___________ signal prevent the microprocessor from reading the same data
more than one.

a. pipelining

b. handshaking

c. controlling

d. signaling

Answer: (b).handshaking

24. Data transfer between the microprocessor for peripheral takes place
through __________.

a. I/O port

b. input port

c. output port
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

d. multi port

Answer: (a).I/O port

25. 8255A operates with ________ power supply.

a. +5V

b. -5V

c. -10V

d. +10V

Answer: (a).+5V

26. The _______ allow data transfer between memory and peripherals.

a. DMA technique

b. Microprocessor

c. Register

d. Decoder

Answer: (a).DMA technique

27. Expansion of SPGA is _________.

a. Staggered Pin Grid-Array package

b. Staggered Point Grid-Array package

c. Staggered Plus Grid-Array package

d. Staggered per grid-Array package

 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Answer: (a).Staggered Pin Grid-Array package

28. Pentium-pro processor design implements________ micro architecture.

a. P2

b. P4

c. P6

d. P8

Answer: (c).P6

29. The number of hardware chips needed for multiple digit display can be
minimized by using the technique called ______.

a. interfacing

b. multiplexing

c. demultiplexing

d. multiprocessing

Answer: (b).multiplexing

30. An RS-232 interface is ____________.

a. a parallel interface

b. a serial interface

c. printer interface

d. a modem interface
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Answer: (b).a serial interface

31. Expansion for DTE is ______.

a. data terminal equipment

b. data trap equipment

c. data text equipment

d. data terminal extension

Answer: (a).data terminal equipment

32. Compared with RS-232, USB is faster and uses___________.

a. medium voltage

b. higher voltage

c. lower voltage

d. None of the above

Answer: (c).lower voltage

33. Expansion for HMOS technology is _______.

a. high level mode oxygen semiconductor

b. high level metal oxygen semiconductor

c. high performance medium oxide semiconductor

d. high performance metal oxide semiconductor

Answer: (d).high performance metal oxide semiconductor

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34. RIM is used to check whether, the ___________.

a. write operation is done or not

b. interrupt is Masked or not

c. interrupt is Masked

d. interrupt is not Masked

Answer: (b).interrupt is Masked or not

35. What does microprocessor speed depends on?

a. clock

b. data bus width

c. address bus width

d. signal bus

Answer: (c).address bus width

36. The advantage of memory mapped I/O over I/O mapped I/O is _________

a. faster operation

b. many instructions supporting memory mapped I/O

c. require a bigger address decoder

d. all the above

Answer: (d).all the above

37. In 8279 Status Word, data is read when ________ pins are low, and write to
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the display RAM with ____________ are low.

a. A0, CS, RD & A0, WR, CS

b. CS, WR, A0 & A0, CS, RD

c. A0, RD & WR, CS

d. CS, RD & A0, CS

Answer: (a).A0, CS, RD & A0, WR, CS

38. In 8279, the keyboard entries are de bounced and stored in an _________,
that is further accessed by the CPU to read the key codes.

a. 8-bit FIFO

b. 8-byte FIFO

c. 16 byte FIFO

d. 16 bit FIFO

Answer: (b).8-byte FIFO

39. For the most Static RAM the write pulse width should be at least

a. 10 ns

b. 60 ns

c. 300 ns

d. 350 ns

Answer: (b).60 ns
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40. Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently

introduced microprocessor by__________.

a. Motorala

b. Intel

c. Stephen Mors

d. HCL

Answer: (b).Intel

41. The address bus flow in __________.

a. bidirection

b. unidirection

c. mulidirection

d. circular

Answer: (b).unidirection

42. The 8085 microprocessor is based in a ________ pin DIP.

a. 40

b. 45

c. 20

d. 35

Answer: (a).40
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43. The 8085 Microprocessor uses__________ power supply.

a. +5V

b. -5V

c. +12V

d. -12V

Answer: (a).+5V

44. Which is used to store critical pieces of data during subroutines and
interrupts ?

a. Stack

b. Queue

c. Accumulator

d. Data register

Answer: (a).Stack

45. The data in the stack is called

a. Pushing data

b. Pushed

c. Pulling

d. None of these

Answer: (a).Pushing data

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46. The external system bus architecture is created using from ______
architecture.

a. Pascal

b. Dennis Ritchie

c. Charles Babbage

d. Von Neumann

Answer: (d).Von Neumann

47. Secondary memory can store____.

a. Program store code

b. Compiler

c. Operating system

d. All of these

Answer: (d).All of these

48. Secondary memory is also called____.

a. Auxiliary

b. Backup store

c. Both A and B

d. None of these

Answer: (c).Both A and B

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49. The lower red curvy arrow show that CPU places the address extracted
from the memory location on the_____.

a. Address bus

b. System bus

c. Control bus

d. Data bus

Answer: (a).Address bus

50. The CPU sends out a ____ signal to indicate that valid data is available on
the data bus.

a. Read

b. Write

c. Both a and b

d. None of these

Answer: (b).Write

UNIT-2
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
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3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
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9. In a Microprocessor, the address of the new next instruction to be executed is

stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c. 4
d. 5
Answer. c
11. The insruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
12. Which one of the following statements is correct regarding the instruction
CMP A ?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
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a. top of stack with contents of register pair

b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer. c
20. When referring to instruction words, a mnemonic is
a. a short abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. a short abbreviation for the data word stored at the operand address.
d. Shorthand for machine language.
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
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There is a ‘cross-over frequency’ below which the period mode is preferred.

Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer. b
22. In a 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer. c
24. Ready pin 0f microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer. b
26. The operations executed by two or more control units are referred as
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a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit
register?
a. (a) 1, 3 and 4
b. 2, 3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
Answer. b
28. The first microprocessor to include virtual memory in the Intel
microprocessor family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine ,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (undefined) in Flag Register of an 8085 microprocessor?
a. 1, 3, 5
b. 2, 3, 5
c. 1, 2, 5
d. 1, 3, 4
Answer. a
31. At the beginning of a fetch cycle, the contents of the program counter are
a. incremented by one
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b. transferred to address bus

c. transferred to memory address register
d. transferred to memory data register
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
3. Operand field
4. Comment field
What is the correct sequence of these fields?
a. 1, 2, 3 and 4
b. 2, 1, 4 and 3
c. 1,3, 2 and 4
d. 2, 4, 1 and 3
Answer. a
33. The relation among IC (lnstruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC − EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC = IC+FC
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device.
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer. d
36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and
an indeterminate number of wait state clock cycles denoted by TW. The wait
states are always inserted between
a. T1 and T2
b. T2 and T3
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c. T3 and T4
d. T4 and T1
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0— D7 from the data bus
c. To disable data bus
d. To achieve all the functions listed above
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
d. Symbolic addressing
Answer. a
41. Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
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43. Which one of the following statements is correct regarding the instruction
CMP A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2, 3 and 4
c. 5 only
d. 1 only
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1, 2 and 3 only
b. 1 and 2 only
c. 1 and 3 only
d. 2 and 3 only
Answer. b
47. Among the given instructions, the one which affects maximum number of
flags is
a. RAL
b. POP PSW
c. XRA A
d. DCR A
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Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
49. Direction flag is used with
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer. d

UNIT-3
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
52. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
counter contains
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a.
the memory address as the instruction that is to be executed next.
b.
the memory address of the instruction that is being currently matched.
c.
the total number of instructions in the program being executed.
d.
the number of instructions in the current program that have already been
executed.
Answer. a
54. Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
55. LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer. b
56. Which of the following instructions is closest match to the instruction POP
PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
58. Which of the following 8085 instruction will require maximum T-states for
execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP
M use?
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a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
60. With reference to 8085 microprocessor, which of the following statements
are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor
contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C

b. ADD B; JNZ LOOP; DCR C

c. DCR C; JNZ LOOP; ADD B

d. ADD B; DCR C; JNZ LOOP

Answer. d
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63. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
64. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
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How many times DCR instruction will be executed?

a. 255
b. 510
c. 65025
d. 65279
Answer. d
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?

a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
70. The instruction PCHL, in 8085 is used for

a. Load PC with contents of HL.

b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction

a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
72. The instruction that exchanges top of stack with HL pair is

a. XTHL
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b. SPHL
c. PUSH H
d. POP H
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is

a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
74. While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be
executed.
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor
is performing
a. Reset operation
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer. c
77. LXI SP, 7FFF H
MVI A, 25 H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10 H
HLT
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What are the contents of A, H, L, SP and PSW registers after executing the above
set of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, 00H. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.

b. the total number of times a subroutine is called.

c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry”
in 8085 microprocessor is

a. ADI
b. ACI
c. ADC
d. ADD
Answer. b
80. MVI A, AA H
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer. b
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82. An 8085 microprocessor is executing the programme as follows:

MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
a. 4
b. 3
c. 2
d. 1
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of
execution of the sequence of instructions, what will be the content of the stack
pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
84. What is the correct 8085 assembly language instruction that stores the
contents of H and L registers into the memory locations 1080 H and 1081 H
respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H

Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer. b
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86. Which one of the following addressing technique is not used in 8085
microprocessor?

a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?

a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
88. Which one is the indirect addressing mode in the following instructions?

a. LXI H 2050 H
b. MOV A, B
c. LDAX B
d. LDA 2050 H
Answer. c
89. The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?

a. Direct
b. Register—indirect
c. Implicit
d. Immediate
Answer. d
90. Carry flag is not affected after the execution of

a. ADD B
b. SBB B
c. INR B
d. ORA B
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be

a. 2FFE H
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b. 2FFF H
c. 3000 H
d. 3001 H
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed

a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.

PUSH PSW
XTHL
PUSH D
JMP EC75 H
At the end of the execution of the above instructions, what would be the content
of the stack pointer?

a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?

a. Op-code for the instruction being executed

b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor
specifies which one of the following?

a. The address of the instruction being executed

b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
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Answer. c
96. Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085 microprocessor?

a. It points to the top of the stack.

b. It is UP/DOWN counter
c. It is automatically initialized to 0000 H on power-on
d. It is a 16-bit register
Answer. c
97. Which one of the following instructions is a 3-byte instruction?

a. MVI A
b. LDAX B
c. JMP 2050 H
d. MOV A,M
Answer. c
98. In 8085, the DAA instruction is used for

a. Direct Address Accumulator

b. Double Add Accumulator
c. Decimal Adjust Accumulator
d. Direct Access Accumulator
Answer. c
99. When an 8086 executes an INT type instruction, it?

a. Resets both IF and TF flags

b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
100. When an 8086 executes an INT type instruction, it?

a. Resets both IF and TF flags

b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
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UNIT-4

ASSEMBLY LANGUAGE PROGRAMMING Multiple Choice Questions :-

1) Assembly language programs are written using
A) Hex code
B) Mnenonics
C) ASCII code
D) None of these View

ANS: B

2) For execution of an interrupt applied at INTR, number of states required by

8085 Microprocessor are
A) 4
B) 6
C) 12
D) 18

ANS: C

3) In 8085 which is/are the 16 bit registers?

A) Program Counter
B) Stack Pointer
C) Both A) & B)
D) None of the above

ANS: C

4) How many memory locations are required to store the instruction LXIH,
0800H in an 8085 assembly language program?
A) 1
B) 2
C) 3
D) 4

ANS: B

5) The instruction DEC N inform the assembler to....

A) Decrement the content of N
B) Decrement the data addressed by N
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C) Convert signed decimal number to binary

D) None of the above

ANS: A

6) In 8085 microprocessor, the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction is stored in
the
A) carry status flag
B) auxiliary carry status flag
C) sign status flag
D) zero status flag

ANS: C

7) Instructions performing actions in assembly language are called

A) imperative statements
B) declarative statements
C) directive statements
D) none of the above
ANS: A

8) What is the content of Stack Pointer ?

A) Address of the current instruction
B) Address of the next instruction
C) Address of the top element of the stack
D) None of the above
ANS: C

9) Which of the following interrupt has highest Priority?

A) INTR
B) TRAP
C) RST 7.5
D) RST 6.5

ANS: B

10) Number of machine cycles required for RET instruction in 8085

microprocessor is
A) 1
B) 2
C) 3
D) 5
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ANS: C

11) __________ converts the programs written in assembly language into

machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter

Answer: c
Clarification: An assembler is a software used to convert the programs into
machine instructions.
12) The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned

Answer: a
Clarification: This OP – codes tell the system what operation to perform on the
operands.
13) The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way

Answer: b
Clarification: The ADDI instruction, means the addition is in immediate
addressing mode.
14) Instructions which won’t appear in the object program are called as
_____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives

Answer: d
Clarification: The directives help the program in getting compiled and hence
won’t be there in the object code.
15) The assembler directive EQU, when used in the instruction: Sum EQU
200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
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c) Re-assigns the address of Sum by adding 200 to its original address

d) Assigns 200 bytes of memory starting the location of Sum

Answer: b
Clarification: This basically is used to replace the variable with a constant value.
16) The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is
to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used

Answer: a
Clarification: This does the function similar to the main statement.
17) The directive used to perform initialization before the execution of
the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU

Answer: c
Clarification: None.
18) _____ directive is used to specify and assign the memory required for
the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve

Answer: d
Clarification: This instruction is used to allocate a block of memory and to store
the object code of the program there.
19) _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate

Answer: b
Clarification: This instruction directive is used to terminate the program
execution.
20) The last statement of the source program should be _______
a) Stop
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b) Return
c) OP
d) End

Answer: d
Clarification: This enables the processor to load some other process.
21) When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive

Answer: c
Clarification: When the assembler comes across the branch code, it immediately
finds the branch offset and replaces it with it.
22) The assembler stores all the names and their corresponding values in
______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned

Answer: b
Clarification: The table where the assembler stores the variable names along with
their corresponding memory locations and values.
23) The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk

Answer: d
Clarification: After compiling the object code, the assembler stores it in the
magnetic disk and waits for further execution.
24) The utility program used to bring the object code into memory for
execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker

Answer: a
Clarification: The program is used to load the program into memory.
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25) To overcome the problems of the assembler in dealing with

branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler

Answer: d
Clarification: This creates entries into the symbol table first and then creates the
object code.
26) In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
27) A ‘DAD H” instruction is the same as shifting each bit by one position
to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
28) When a program is being executed in an 8085 microprocessor, its
program counter contains
a. the memory address as the instruction that is to be executed next.
b. the memory address of the instruction that is being currently matched.
c. the total number of instructions in the program being executed.
d. the number of instructions in the current program that have already been
executed.
Answer. a
29) Which of the following data transfer is not possible in
microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
30) LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
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d. loads English like command and generates the binary code

Answer. b
31) Which of the following instructions is closest match to the
instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
32) How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
33) Which of the following 8085 instruction will require maximum T-
states for execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
34) In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
35) With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
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36) Assume that the accumulator and the register C of 8085

microprocessor contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution
of instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
37) It is desired to multiply the numbers 0A H by OB H and store the
result in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C

b. ADD B; JNZ LOOP; DCR C

c. DCR C; JNZ LOOP; ADD B

d. ADD B; DCR C; JNZ LOOP

Answer. d
38) Find the content of the accumulator after the execution of the
following program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
39) The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
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a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
40) The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
41) The content of accumulator are 70 H. Initially all flags are zero. What
will be values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
42) A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?

a. 255
b. 510
c. 65025
d. 65279
Answer. d
43) What is content of accumulator of 8085 microprocessor after the
execution of XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
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44) The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a frequency
of 2.5 MHz, how long is an instruction Cycle?

a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
45) The instruction PCHL, in 8085 is used for

a. Load PC with contents of HL.

b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
46) The following instruction copies a byte of data from the accumulator
into the memory address given in the instruction

a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
47) The instruction that exchanges top of stack with HL pair is

a. XTHL
b. SPHL
c. PUSH H
d. POP H
Answer. a
48) In 8085 microprocessor, during PUSH PSW Operation, Stack pointer
is

a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
49) While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
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a.The memory address of the instruction that is being currently executed.

b.The memory address of the instruction that is to be executed next.
c.The number of instructions that have already been executed.
d.The total number of instructions in the current program still to be
executed.
Answer. b
50) The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c

UNIT-5

Microprocessors Questions and Answers – Programmable DMA Interface

8237 (Part-1)

1. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned

Answer: b
Explanation: The program control block decodes various commands given to the
8237 by the CPU before servicing a DMA request.

2. The priority between the DMA channels requesting the services can be
resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned

Answer: c
Explanation: The priority encoder block resolves the priority between the DMA
channels requesting the services.
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3. The register that holds the current memory address is

a) current word register
b) current address register
c) base address register
d) command register

Answer: b
Explanation: The current address register holds the current memory address. The
current address register is accessed during the DMA transfer.

4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register

Answer: a
Explanation: The current word register is a 16-bit register that holds the data
transfers. The word count is decremented after each transfer, and the new value
is stored again in the register.

5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated

Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can
be written in successive bytes by the CPU, in program mode.

6. The current address register is programmed by the CPU as

a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Explanation: The current address register is byte-wise programmed by the CPU,
i.e. lower byte first and the higher byte later.

7. Which of these register’s contents is used for auto-initialization (internally)?

a) current word register
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b) current address register

c) base address register
d) command register

Answer: c
Explanation: The contents of base address register cannot be read by the CPU.
These contents are used internally for auto-initialization.

8. The register that maintains an original copy of the respective initial current
address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register

Answer: b
Explanation: The base address register maintains an original copy of the current
address register and current word register, before incrementing or
decrementing.

9. The register that can be automatically incremented or decremented, after each

DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register

Answer: d
Explanation: The address is automatically incremented or decremented after
each DMA transfer, and the resulting address value is again stored in the current
address register.

10. Which of the following is a type of DMA transfer?

a) memory read
b) memory write
c) verify transfer
d) all of the mentioned

Answer: d
Explanation: Memory read, memory write and verify transfer are the three types
of DMA transfer.
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Microprocessors Questions and Answers – 8255 programmable peripheral

interface-(Part-2)

Question 1: How many pins does the 8255 PPI IC contains?

a. 24
b. 20
c. 32
d. 40

Answer: d. 40

Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: b. Mode 0 of I/O mode

Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?

a. CS'
b. RD'
c. WR'
d. ALL of the above

Answer: d. All of the above

Question 4: In which of the following modes is the 8255 PPI capable of

transferring data while handshaking with the interfaced device?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: c. Mode 1 of I/O mode

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Question 5: How many bits of data can be transferred between the 8255 PPI and
the interfaced device at a time? or What is the size of internal bus of the 8255
PPI?

a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above

Answer: c. 8 bits

Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?

a. Port A
b. Port B
c. Port C
d. All of the above

Answer: c. Port C

Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: a. BSR mode

Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?

a. Port A
b. Port B
c. Port C
d. All of the above

Answer: a. Port A

Question 9: In which of the following modes we do not consider the D6, D5 and
D4 bits of the control word?

a. BSR mode
b. Mode 0 of I/O mode
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c. Mode 1 of I/O mode

d. Mode 2 of I/O mode

Answer: a. BSR mode

Question 10: How many data lines in total are there in the 8255 PPI IC?

a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above

Answer: c. 24 data lines

Microprocessors Questions and Answers – 8253/8254programmable

timer/counter-(Part-3)

1. The number of counters that are present in the programmable timer device
8254 is
a) 1
b) 2
c) 3
d) 4

Answer: c
Explanation: There are three counters that can be used as either counters or
delay generators.

2. The operation that can be performed on control word register is

a) read operation
b) write operation
c) read and write operations
d) none

Answer: b
Explanation: The control word register can only be written and cannot be read.

3. The mode that is used to interrupt the processor by setting a suitable terminal
count is
a) mode 0
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b) mode 1
c) mode 2
d) mode 3

Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.

4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output
becomes low for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles

Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If
the count N is reloaded and again the output becomes high and remains so for (N-
1) clock pulses.

5. The generation of a square wave is possible in the mode

a) mode 1
b) mode 2
c) mode 3
d) mode 4

Answer: c
Explanation: When the count N loaded is even, then for half of the count, the
output remains high and for the remaining half it remains low. If the count loaded
is odd, the first clock pulse decrements it by 1 resulting in an even count value.

6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none

Answer: b
Explanation: SC denotes select counter.
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7. In control word format, if RL1=1, RL0=1 then the operation performed is

a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB

Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.

8. If BCD=0, then the operation is

a) decimal count
b) hexadecimal count
c) binary count
d) octal count

Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is
BCD count.

9. The counter starts counting only if

a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high

Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.

10. The control word register contents are used for

a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned

Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
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Microprocessors Questions and Answers – 8259 programmable interrupt

controller-(Part-4)

1. The number of hardware interrupts that the processor 8085 consists of is

a) 1
b) 3
c) 5
d) 7
View Answer

Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these
five, four pins were alloted fixed vector addresses but the pin INTR was not
alloted by vector address, rather an external device was supposed to hand over
the type of the interrupt to the microprocessor.

2. The register that stores all the interrupt requests in it in order to serve them
one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register

Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request
Register internally.

3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None

Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request
Register) at the direction of the Priority Resolver.
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4. The interrupt control logic

a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned

Answer: d
Explanation: The interrupt control logic performs all the operations that are
involved within the interrupts like accepting and managing interrupt
acknowledge signals, interrupts.

5. In a cascaded mode, the number of vectored interrupts provided by 8259A is

a) 4
b) 8
c) 16
d) 64

Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64
vectored interrupts can be provided.

6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode,
then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none

Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a
buffer enable to control buffer transreceivers. If it is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master or
a slave.

7. Once the ICW1 is loaded, then the initialization procedure involves

a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned

Answer: d
Explanation: The initialization procedure involves
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

i) edge sense circuit is reset.

ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.

8. When non-specific EOI command is issued to 8259A it will automatically

a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR

Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR.

9. In the application where all the interrupting devices are of equal priority, the
mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI

Answer: a
Explanation: The automatic rotation is used in the applications where all the
interrupting devices are of equal priority.

Microprocessors Questions and Answers – 8251 USART and

RS232C- (Part-5)

1. Which of the following is not a mode of data transmission?

a) simplex
b) duplex
c) semi duplex
d) half duplex

Answer: c
Explanation: Basically, there are three modes of data transmission. simplex,
duplex and half duplex.
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

2. If the data is transmitted only in one direction over a single communication

channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode

Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For
example, a CPU may transmit data for a CRT display unit in this mode.

3. If the data transmission takes place in either direction, but at a time data may
be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode

Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a
time. For example, Walkie-Talkie.

4. In 8251A, the pin that controls the rate at which the character is to be
transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)

Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the
rate at which the character is to be transmitted.

5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted

data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned

Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

transmitted data bits along with other information like start bits, stop bits and
parity bits etc.

6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)

Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the
CPU or polled by the CPU.

7. The disadvantage of RS-232C is

a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned

Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like
limited speed of communication, high-voltage level signaling and big-size
communication adapters.

8. The USB supports the signaling rate of

a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned

Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.

9. The bit packet that commands the device either to receive data or transmit
data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
 Allenhouse Institute of Technology (UPTU Code : 505)
Rooma, Kanpur – 208 008

Answer: b
Explanation: The token packet is the second type of packet which commands the
device either to receive data or transmit data.

10. High speed USB devices neglect

a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet

Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
 Microprocessor Interview
Questions And Answers Guide.

Global Guideline.
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 Microprocessor Interview Questions And Answers

G
Microprocessor Job Interview Preparation Guide.
lo
ba
lG
Question # 1
What is a Microprocessor?
ui
Answer:-
Microprocessor is a program-controlled device, which fetches the instructions from memory, decodes and executes the instructions. Most Micro Processor are single-
chip devices.
de
Read More Answers.

Question # 2
What are the flags in 8086?
lin
Answer:-
In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.
Read More Answers.
e
Question # 3
Why crystal is a preferred clock source?
.C
Answer:-
Because of high stability, large Q (Quality Factor) & the frequency that doesn't drift with aging. Crystal is used as a clock source most of the times.
Read More Answers.
O
Question # 4
In 8085 which is called as High order / Low order Register?
M
Answer:-
Flag is called as Low order register & Accumulator is called as High order Register.
Read More Answers.

Question # 5
What is Tri-state logic?
Answer:-
Three Logic Levels are used and they are High, Low, High impedance state. The high and low are normal logic levels & high impedance state is electrical open
circuit conditions. Tri-state logic has a third line called enable line.
Read More Answers.

Question # 6
What happens when HLT instruction is executed in processor?
Answer:-
The Micro Processor enters into Halt-State and the buses are tri-stated.
Read More Answers.

Question # 7
Which Stack is used in 8085?
Answer:-
LIFO (Last In First Out) stack is used in 8085.In this type of Stack the last stored information can be retrieved first
Read More Answers.

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 Microprocessor Interview Questions And Answers

Question # 8
What is Program counter?
Answer:-
Program counter holds the address of either the first byte of the next instruction to be fetched for execution or the address of the next byte of a multi byte instruction,
which has not been completely fetched. In both the cases it gets incremented automatically one by one as the instruction bytes get fetched. Also Program register
keeps the address of the next instruction
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Read More Answers.

Question # 9
lo
What are the various registers in 8085?
Answer:-
ba
Accumulator register, Temporary register, Instruction register, Stack Pointer, Program Counter are the various registers in 8085
Read More Answers.

Question # 10
lG
What is 1st / 2nd / 3rd / 4th generation processor?
Answer:-
The processor made of PMOS / NMOS / HMOS / HCMOS technology is called 1st / 2nd / 3rd / 4th generation processor, and it is made up of 4 / 8 / 16 / 32 bits.
Read More Answers.
ui
Question # 11
Name the processor lines of two major manufacturer?
de
Answer:-
High-end: Intel - Pentium (II, III, 4), AMD - Athlon. Low-end: Intel - Celeron, AMD - Duron. 64-bit: Intel - Itanium 2, AMD - Opteron.
Read More Answers.
lin
Question # 12
What's the speed and device maximum specs for Firewire?
e
Answer:-
IEEE 1394 (Firewire) supports the maximum of 63 connected devices with speeds up to 400 Mbps. Where's MBR located on the disk? Main Boot Record is located
in sector 0, track 0, head 0, cylinder 0 of the primary active partition.
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Read More Answers.

Question # 13
Where does the CPU Enhanced mode originate from?
O
Answer:-
Intel's 80386 was the first 32-bit processor, and since the company had to backward-support the 8086. All the modern Intel-based processors run in the Enhanced
mode, capable of switching between Real mode (just like the real 8086) and Protected mode, which is the current mode of operation.
M
Read More Answers.

Question # 14
How many bit combinations are there in a byte?
Answer:-
Byte contains 8 combinations of bits.
Read More Answers.

Question # 15
Have you studied buses? What types?
Answer:-
There are three types of buses.
Address bus: This is used to carry the Address to the memory to fetch either Instruction or Data.
Data bus : This is used to carry the Data from the memory.
Control bus : This is used to carry the Control signals like RD/WR, Select etc.
Read More Answers.

Question # 16
What is the Maximum clock frequency in 8086?
Answer:-
5 Mhz is the Maximum clock frequency in 8086.
Read More Answers.

Question # 17
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 Microprocessor Interview Questions And Answers

What is meant by Maskable interrupts?

Answer:-
An interrupt that can be turned off by the programmer is known as Maskable interrupt.
Read More Answers.

Question # 18
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What is Non-Maskable interrupts?
Answer:-
lo
An interrupt which can be never be turned off (ie. disabled) is known as Non-Maskable interrupt
Read More Answers.
ba
Question # 19
What are the different functional units in 8086?
Answer:-
lG
Bus Interface Unit and Execution unit, are the two different functional units in 8086.
Read More Answers.

Question # 20
ui
What are the various segment registers in 8086?
Answer:-
Code, Data, Stack, Extra Segment registers in 8086.
de
Read More Answers.

Question # 21
What does the EU do?
lin
Answer:-
Execution Unit receives program instruction codes and data from BIU, executes these instructions and store the result in general registers.
Read More Answers.
e
Question # 22
Which Stack is used in 8086? k is used in 8086?
.C
Answer:-
FIFO (First In First Out) stack is used in 8086.In this type of Stack the first stored information is retrieved first.
Read More Answers.
O
Question # 23
What are the major flags in 8086?
M
Answer:-
In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.
Read More Answers.

Question # 24
What is SIM and RIM instructions?
Answer:-
SIM is Set Interrupt Mask. Used to mask the hardware interrupts.
RIM is Read Interrupt Mask. Used to check whether the interrupt is Masked or not.
Read More Answers.

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 Computer Hardware Most Popular Interview Topics.

1 : Basic Computer Frequently Asked Interview Questions and Answers Guide.

2 : A + (Plus) Hardware Frequently Asked Interview Questions and Answers Guide.

3 : Computer Architecture Frequently Asked Interview Questions and Answers Guide.

4 : Electronics Frequently Asked Interview Questions and Answers Guide.

5 : Embedded System Frequently Asked Interview Questions and Answers Guide.

6 : Motherboard Frequently Asked Interview Questions and Answers Guide.

7 : 8085 Frequently Asked Interview Questions and Answers Guide.

8 : Basic Input Output System Frequently Asked Interview Questions and Answers Guide.

9 : Random Access Memory Frequently Asked Interview Questions and Answers Guide.

10 : 8086 Frequently Asked Interview Questions and Answers Guide.

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1. A Process Control Block(PCB) does not contain which of the following?

a) Code
b) Stack
c) Bootstrap program
d) Data
Answer: d
Explanation: Process Control Block (PC
b) contains information related to a process such as Process State, Program Counter, CPU Register, etc. Process Con
trol Block is also known as Task Control Block. Bootstrap program is a program which runs initially when the syste
m or computer is booted or rebooted.

2. The number of processes completed per unit time is known as __________

a) Output
b) Throughput
c) Efficiency
d) Capacity
Answer: a
Explanation: The number of processes completed per unit time is known as Throughput. Suppose there are 4 process
es A, B, C & D they are taking 1, 3, 4 & 7 units of time respectively for their executions. For 10 units of time, throu
ghput is high if process A, B & C are running first as 3 processes can execute. If process C runs first then throughput
is low as maximum only 2 processes can execute. Throughput is low for processes which take a long time for execu
tion. Throughput is high for processes which take a short time for execution.

3. The state of a process is defined by __________

a) the final activity of the process

b) the activity just executed by the process
c) the activity to next be executed by the process
d) the current activity of the process
Answer: c
Explanation: The state of a process is defined by the current activity of the process. A process state changes when th
e process executes. The process states are as New, Ready, Running, Wait, Terminated.

1. Which of the following do not belong to queues for processes?

a) Job Queue
b) PCB queue
c) Device Queue
d) Ready Queue
Answer: c
Explanation: PCB queue does not belong to queues for processes. PCB is a process control block which contains inf
ormation related to process. Each process is represented by PCB.

2. When the process issues an I/O request __________

a) It is placed in an I/O queue

b) It is placed in a waiting queue
c) It is placed in the ready queue
d) It is placed in the Job queue
Answer: c
Explanation: When the process issues an I/O request it is placed in an I/O queue. I/O is a resource and it should be u
sed effectively and every process should get access to it. There might be multiple processes which requested for I/O.
Depending on scheduling algorithm I/O is allocated to any particular process and after completing I/O operation, I/
O access is returned to the OS.

3. What will happen when a process terminates?

a) It is removed from all queues

b) It is removed from all, but the job queue
c) Its process control block is de-allocated
d) Its process control block is never de-allocated
Answer: a
Explanation: When a process terminates, it removes from all queues. All allocated resources to that particular proces
s are deallocated and all those resources are returned back to OS.

4. What is a long-term scheduler?

a) It selects processes which have to be brought into the ready queue

b) It selects processes which have to be executed next and allocates CPU
c) It selects processes which heave to remove from memory by swapping
d) None of the mentioned
Answer: b
Explanation: A long-term scheduler selects processes which have to be brought into the ready queue. When processe
s enter the system, they are put in the job queue. Long-term scheduler selects processes from the job queue and puts
them in the ready queue. It is also known as Job Scheduler.

5. If all processes I/O bound, the ready queue will almost always be ______ and the Short term Scheduler will have
a ______ to do.

a) full, little
b) full, lot
c) empty, little
d) empty, lot
Answer: c
Explanation: If all processes are I/O bound, the ready queue will almost empty and the short-term scheduler will hav
e a little to do. I/O bound processes spend more time doing I/O than computation.

6. What is a medium-term scheduler?

a) It selects which process has to be brought into the ready queue

b) It selects which process has to be executed next and allocates CPU
c) It selects which process to remove from memory by swapping
d) None of the mentioned
Answer: b
Explanation: A medium-term scheduler selects which process to remove from memory by swapping. The medium-te
rm scheduler swapped out the process and later swapped in. Swapping helps to free up memory.

7. What is a short-term scheduler?

a) It selects which process has to be brought into the ready queue

b) It selects which process has to be executed next and allocates CPU
c) It selects which process to remove from memory by swapping
d) None of the mentioned
Answer: d
Explanation: A short-term scheduler selects a process which has to be executed next and allocates CPU. Short-term
scheduler selects a process from the ready queue. It selects processes frequently.

8. The primary distinction between the short term scheduler and the long term scheduler is __________

a) The length of their queues

b) The type of processes they schedule
c) The frequency of their execution
d) None of the mentioned
Answer: b
Explanation: The primary distinction between the short-term scheduler and the long-term scheduler is the frequency
of their execution. The short-term scheduler executes frequently while the long-term scheduler executes much less fr
equently.

9. The only state transition that is initiated by the user process itself is __________

a) block
b) wakeup
c) dispatch
d) none of the mentioned
Answer: c
Explanation: The only state transition that is initiated by the user process itself is block. Whenever a user process ini
tiates an I/O request it goes into block state unless and until the I/O request is not completed.

1. Restricting the child process to a subset of the parent’s resources prevents any process from __________

a) overloading the system by using a lot of secondary storage

b) under-loading the system by very less CPU utilization
c) overloading the system by creating a lot of sub-processes
d) crashing the system by utilizing multiple resources
Answer: c
Explanation: Restricting the child process to a subset of the parent’s resources prevents any process from overloadin
g the system by creating a lot of sub-processes. A process creates a child process, child process requires certain reso
urces to complete its task. A child process can demand required resources directly from the system, but by doing this
system will be overloaded. So to avoid overloading of the system, the parent process shares its resources among chi
ldren.

2. A parent process calling _____ system call will be suspended until children processes terminate.

a) wait
b) fork
c) exit
d) exec
Answer: a
Explanation: A parent process calling wait system call will be suspended until children processes terminate. A para
meter is passed to wait system call which will obtain exit status of child as well as wait system call returns PID of ter
minated process.

3. Cascading termination refers to termination of all child processes if the parent process terminates ______

a) Normally
b) Abnormally
c) Normally or abnormally
d) None of the mentioned
Answer: c
Explanation: Cascading termination refers to termination of all child processes if the parent process terminates Norm
ally or Abnormally. Some systems don’t allow child processes to exist if the parent process has terminated. Cascadin
g termination is normally initiated by the operating system.

4. With _____________ only one process can execute at a time; meanwhile all other process are waiting for the proc
essor. With ______________ more than one process can be running simultaneously each on a different processor.

a) Multiprocessing, Multiprogramming
b) Multiprogramming, Uniprocessing
c) Multiprogramming, Multiprocessing
d) Uniprogramming, Multiprocessing
Answer: d
Explanation: With Uniprogramming only one process can execute at a time; meanwhile all other processes are waiti
ng for the processor. With Multiprocessing more than one process can run simultaneously each on different processo
rs. The Uniprogramming system has only one program inside the core while the Multiprocessing system has multipl
e processes inside multiple cores. The core is one which executes instructions and stores data locally into registers.

5. In UNIX, each process is identified by its __________

a) Process Control Block

b) Device Queue
c) Process Identifier
d) None of the mentioned
Answer: c
Explanation: In Unix, each process is identified by its Process Identifier or PID. The PID provides unique value to e
ach process in the system so that each process can be identified uniquely.

6. In UNIX, the return value for the fork system call is _____ for the child process and _____ for the parent process.

a) A Negative integer, Zero

b) Zero, A Negative integer
c) Zero, A nonzero integer
d) A nonzero integer, Zero
Answer: c
Explanation: In Unix, the return value of the fork system call is Zero for the child process and Non-zero value for pa
rent process. A fork system call returns the PID of a newly created (chil
d) process to the parent and returns Zero to that newly created (chil
d) process.

7. The child process can __________

a) be a duplicate of the parent process

b) never be a duplicate of the parent process
c) cannot have another program loaded into it
d) never have another program loaded into it
Answer: a
Explanation: The child process can be a duplicate of the parent process. The child process created by fork consists of
a copy of the address space of the parent process.

8. The child process completes execution, but the parent keeps executing, then the child process is known as ______
____
a) Orphan
b) Zombie
c) Body
d) Dead
Answer: b
Explanation: The child process completes execution, but the parent keeps executing, then the child process is known
as Zombie. When a child process terminates, its resources get deallocated but its entry in the Process Control Block
(PC
b) remains there until its parent calls wait system call.

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1. What is Interprocess communication?

a) allows processes to communicate and synchronize their actions when using the same address space
b) allows processes to communicate and synchronize their actions
c) allows the processes to only synchronize their actions without communication
d) none of the mentioned
Answer: b
Explanation: Interprocess Communication allows processes to communicate and synchronize their actions. Interproc
ess Communication (IP
c) mechanism is used by cooperating processes to exchange data and information.

2. Message passing system allows processes to __________

a) communicate with each other without sharing the same address space
b) communicate with one another by resorting to shared data
c) share data
d) name the recipient or sender of the message
Answer: a
Explanation: Message Passing system allows processes to communicate with each other without sharing the same ad
dress space.

3. Which of the following two operations are provided by the IPC facility?

a) write & delete message

b) delete & receive message
c) send & delete message
d) receive & send message
Answer: d
Explanation: Two operations provided by the IPC facility are receive and send messages. Exchange of data takes pla
ce in cooperating processes.

4. Messages sent by a process __________

a) have to be of a fixed size

b) have to be a variable size
c) can be fixed or variable sized
d) none of the mentioned
Answer: c
Explanation: Messages sent by a process can be fixed or variable size. If the message size of the process is fixed the
n system level implementation is straightforward but it makes the task of programming more difficult. If the messag
e size of the process is variable then system level implementation is more complex but it makes the task of program
ming simpler.

5. The link between two processes P and Q to send and receive messages is called __________

a) communication link
b) message-passing link
c) synchronization link
d) all of the mentioned
Answer: a
Explanation: The link between two processes P and Q to send and receive messages is called communication link. T
wo processes P and Q want to communicate with each other; there should be a communication link that must exist b
etween these two processes so that both processes can able to send and receive messages using that link.

6. Which of the following are TRUE for direct communication?

a) A communication link can be associated with N number of process(N = max. number of processes supported by s
ystem)
b) A communication link is associated with exactly two processes
c) Exactly N/2 links exist between each pair of processes(N = max. number of processes supported by system)
d) Exactly two link exists between each pair of processes
Answer: b
Explanation: For direct communication, a communication link is associated with exactly two processes. One commu
nication link must exist between a pair of processes.

7. In indirect communication between processes P and Q __________

a) there is another process R to handle and pass on the messages between P and Q
b) there is another machine between the two processes to help communication
c) there is a mailbox to help communication between P and Q
d) none of the mentioned
Answer: c
Explanation: In indirect communication between processes P and Q there is a mailbox to help communication betwe
en P and Q. A mailbox can be viewed abstractly as an object into which messages can be placed by processes and fr
om which messages can be removed.

8. In the non blocking send __________

a) the sending process keeps sending until the message is received

b) the sending process sends the message and resumes operation
c) the sending process keeps sending until it receives a message
d) none of the mentioned
Answer: b
Explanation: In the non blocking send, the sending process sends the message and resumes operation. Sending proce
ss doesn’t care about reception. It is also known as asynchronous send.

9. In the Zero capacity queue __________

a) the queue can store at least one message

b) the sender blocks until the receiver receives the message
c) the sender keeps sending and the messages don’t wait in the queue
d) none of the mentioned
Answer: b
Explanation: In the Zero capacity queue the sender blocks until the receiver receives the message. Zero capacity que
ue has maximum capacity of Zero; thus message queue does not have any waiting message in it.
10. The Zero Capacity queue __________

a) is referred to as a message system with buffering

b) is referred to as a message system with no buffering
c) is referred to as a link
d) none of the mentioned
Answer: b
Explanation: The Zero capacity queue is referred to as a message system with no buffering. Zero capacity queue has
maximum capacity of Zero; thus message queue does not have any waiting message in it.

11. Bounded capacity and Unbounded capacity queues are referred to as __________

a) Programmed buffering
b) Automatic buffering
c) User defined buffering
d) No buffering
Answer: b
Explanation: Bounded capacity and Unbounded capacity queues are referred to as Automatic buffering. Buffer capa
city of the Bounded capacity queue is finite length and buffer capacity of the Unbounded queue is infinite.

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1. Remote Procedure Calls are used ____________

a) for communication between two processes remotely different from each other on the same system
b) for communication between two processes on the same system
c) for communication between two processes on separate systems
d) none of the mentioned
Answer: c
Explanation: None.

2. To differentiate the many network services a system supports ______ are used.

a) Variables
b) Sockets
c) Ports
d) Service names
Answer: c
Explanation: None.

3. RPC provides a(an) _____ on the client-side, a separate one for each remote procedure.

a) stub
b) identifier
c) name
d) process identifier
Answer: a
Explanation: None.

4. What is stub?

a) transmits the message to the server where the server side stub receives the message and invokes procedure on the
server side
b) packs the parameters into a form transmittable over the network
c) locates the port on the server
d) all of the mentioned
Answer: d
Explanation: None.

5. To resolve the problem of data representation on different systems RPCs define _____________

a) machine dependent representation of data

b) machine representation of data
c) machine-independent representation of data
d) none of the mentioned
Answer: c
Explanation: None.

6. What is the full form of RMI?

a) Remote Memory Installation

b) Remote Memory Invocation
c) Remote Method Installation
d) Remote Method Invocation
Answer: d
Explanation: None.

7. The remote method invocation __________

a) allows a process to invoke memory on a remote object

b) allows a thread to invoke a method on a remote object
c) allows a thread to invoke memory on a remote object
d) allows a process to invoke a method on a remote object
Answer: b
Explanation: None.

8. A process that is based on IPC mechanism which executes on different systems and can communicate with other
processes using message based communication, is called ________

a) Local Procedure Call

b) Inter Process Communication
c) Remote Procedure Call
d) Remote Machine Invocation
Answer: c
Explanation: None.

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1. The initial program that is run when the computer is powered up is called __________

a) boot program
b) bootloader
c) initializer
d) bootstrap program
Answer: d
Explanation: None.

2. How does the software trigger an interrupt?

a) Sending signals to CPU through bus

b) Executing a special operation called system call
c) Executing a special program called system program
d) Executing a special program called interrupt trigger program
Answer: b
Explanation: None.

3. What is a trap/exception?

a) hardware generated interrupt caused by an error

b) software generated interrupt caused by an error
c) user generated interrupt caused by an error
d) none of the mentioned
Answer: b
Explanation: None.

4. What is an ISR?

a) Information Service Request

b) Interrupt Service Request
c) Interrupt Service Routine
d) Information Service Routine
Answer: c
Explanation: None.

5. What is an interrupt vector?

a) It is an address that is indexed to an interrupt handler

b) It is a unique device number that is indexed by an address
c) It is a unique identity given to an interrupt
d) None of the mentioned
Answer: a
Explanation: None.

6. DMA is used for __________

a) High speed devices(disks and communications network)

b) Low speed devices
c) Utilizing CPU cycles
d) All of the mentioned
Answer: a
Explanation: None.

7. In a memory mapped input/output __________

a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready
b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available
c) the CPU receives an interrupt when the device is ready for the next byte
d) the CPU runs a user written code and does accordingly
Answer: b
Explanation: None.

8. In a programmed input/output(PIO) __________

a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready
b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available
c) the CPU receives an interrupt when the device is ready for the next byte
d) the CPU runs a user written code and does accordingly
Answer: a
Explanation: None.

9. In an interrupt driven input/output __________

a) the CPU uses polling to watch the control bit constantly, looping to see if a device is ready
b) the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available
c) the CPU receives an interrupt when the device is ready for the next byte
d) the CPU runs a user written code and does accordingly
Answer: c
Explanation: None.

10. In the layered approach of Operating Systems __________

a) Bottom Layer(0) is the User interface

b) Highest Layer(N) is the User interface
c) Bottom Layer(N) is the hardware
d) Highest Layer(N) is the hardware
Answer: b
Explanation: None.

11. How does the Hardware trigger an interrupt?

a) Sending signals to CPU through a system bus

b) Executing a special program called interrupt program
c) Executing a special program called system program
d) Executing a special operation called system call
Answer: a
Explanation: None.

12. Which operation is performed by an interrupt handler?

a) Saving the current state of the system

b) Loading the interrupt handling code and executing it
c) Once done handling, bringing back the system to the original state it was before the interrupt occurred
d) All of the mentioned
Answer: d
Explanation: None.

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1. CPU scheduling is the basis of ___________

a) multiprocessor systems
b) multiprogramming operating systems
c) larger memory sized systems
d) none of the mentioned
Answer: b
Explanation: None.

2. With multiprogramming ______ is used productively.

a) time
b) space
c) money
d) all of the mentioned
Answer: a
Explanation: None.

3. What are the two steps of a process execution?

a) I/O & OS Burst

b) CPU & I/O Burst
c) Memory & I/O Burst
d) OS & Memory Burst
Answer: b
Explanation: None.

4. An I/O bound program will typically have ____________

a) a few very short CPU bursts

b) many very short I/O bursts
c) many very short CPU bursts
d) a few very short I/O bursts
Answer: c
Explanation: None.

5. A process is selected from the ______ queue by the ________ scheduler, to be executed.

a) blocked, short term

b) wait, long term
c) ready, short term
d) ready, long term
Answer: c
Explanation: None.

6. In the following cases non – preemptive scheduling occurs?

a) When a process switches from the running state to the ready state
b) When a process goes from the running state to the waiting state
c) When a process switches from the waiting state to the ready state
d) All of the mentioned
Answer: b
Explanation: There is no other choice.

7. The switching of the CPU from one process or thread to another is called ____________

a) process switch
b) task switch
c) context switch
d) all of the mentioned
Answer: d
Explanation: None.

8. What is Dispatch latency?

a) the speed of dispatching a process from running to the ready state

b) the time of dispatching a process from running to ready state and keeping the CPU idle
c) the time to stop one process and start running another one
d) none of the mentioned
Answer: c
Explanation: None.

9. Scheduling is done so as to ____________

a) increase CPU utilization

b) decrease CPU utilization
c) keep the CPU more idle
d) none of the mentioned
Answer: a
Explanation: None.

10. Scheduling is done so as to ____________

a) increase the throughput

b) decrease the throughput
c) increase the duration of a specific amount of work
d) none of the mentioned
Answer: a
Explanation: None.

11. What is Turnaround time?

a) the total waiting time for a process to finish execution

b) the total time spent in the ready queue
c) the total time spent in the running queue
d) the total time from the completion till the submission of a process
Answer: d
Explanation: None.

12. Scheduling is done so as to ____________

a) increase the turnaround time

b) decrease the turnaround time
c) keep the turnaround time same
d) there is no relation between scheduling and turnaround time
Answer: b
Explanation: None.

13. What is Waiting time?

a) the total time in the blocked and waiting queues

b) the total time spent in the ready queue
c) the total time spent in the running queue
d) the total time from the completion till the submission of a process
Answer: b
Explanation: None.

14. Scheduling is done so as to ____________

a) increase the waiting time

b) keep the waiting time the same
c) decrease the waiting time
d) none of the mentioned
Answer: c
Explanation: None.

15. What is Response time?

a) the total time taken from the submission time till the completion time
b) the total time taken from the submission time till the first response is produced
c) the total time taken from submission time till the response is output
d) none of the mentioned
Answer: b
Explanation: None.

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1. Round robin scheduling falls under the category of ____________

a) Non-preemptive scheduling
b) Preemptive scheduling
c) All of the mentioned
d) None of the mentioned
Answer: b
Explanation: None.

2. With round robin scheduling algorithm in a time shared system ____________

a) using very large time slices converts it into First come First served scheduling algorithm
b) using very small time slices converts it into First come First served scheduling algorithm
c) using extremely small time slices increases performance
d) using very small time slices converts it into Shortest Job First algorithm
Answer: a
Explanation: All the processes will be able to get completed.

3. The portion of the process scheduler in an operating system that dispatches processes is concerned with ________
____

a) assigning ready processes to CPU

b) assigning ready processes to waiting queue
c) assigning running processes to blocked queue
d) all of the mentioned
Answer: a
Explanation: None.
4. Complex scheduling algorithms ____________

a) are very appropriate for very large computers

b) use minimal resources
c) use many resources
d) all of the mentioned
Answer: a
Explanation: Large computers are overloaded with a greater number of processes.

5. What is FIFO algorithm?

a) first executes the job that came in last in the queue

b) first executes the job that came in first in the queue
c) first executes the job that needs minimal processor
d) first executes the job that has maximum processor needs
Answer: b
Explanation: None.

6. The strategy of making processes that are logically runnable to be temporarily suspended is called ____________

a) Non preemptive scheduling

b) Preemptive scheduling
c) Shortest job first
d) First come First served
Answer: b
Explanation: None.

7. What is Scheduling?

a) allowing a job to use the processor

b) making proper use of processor
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: None.

8. There are 10 different processes running on a workstation. Idle processes are waiting for an input event in the inp
ut queue. Busy processes are scheduled with the Round-Robin time sharing method. Which out of the following qua
ntum times is the best value for small response times, if the processes have a short runtime, e.g. less than 10ms?

a) tQ = 15ms
b) tQ = 40ms
c) tQ = 45ms
d) tQ = 50ms
Answer: a
Explanation: None.

9. Orders are processed in the sequence they arrive if _______ rule sequences the jobs.

a) earliest due date

b) slack time remaining
c) first come, first served
d) critical ratio
Answer: c
Explanation: None.

10. Which of the following algorithms tends to minimize the process flow time?

a) First come First served

b) Shortest Job First
c) Earliest Deadline First
d) Longest Job First
Answer: b
Explanation: None.

11. Under multiprogramming, turnaround time for short jobs is usually ________ and that for long jobs is slightly _
__________

a) Lengthened; Shortened
b) Shortened; Lengthened
c) Shortened; Shortened
d) Shortened; Unchanged
Answer: b
Explanation: None.

12. Which of the following statements are true? (GATE 2010)

a) I only
b) I and III only
c) II and III only
d) I, II and III
Answer: d
Explanation: I) Shortest remaining time first scheduling is a preemptive version of shortest job scheduling. It may ca
use starvation as shorter processes may keep coming and a long CPU burst process never gets CPU.

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1. Which is the most optimal scheduling algorithm?

a) FCFS – First come First served

b) SJF – Shortest Job First
c) RR – Round Robin
d) None of the mentioned
Answer: b
Explanation: None.

2. The real difficulty with SJF in short term scheduling is ____________

a) it is too good an algorithm

b) knowing the length of the next CPU request
c) it is too complex to understand
d) none of the mentioned
Answer: b
Explanation: None.

3. The FCFS algorithm is particularly troublesome for ____________

a) time sharing systems
b) multiprogramming systems
c) multiprocessor systems
d) operating systems
Answer: b
Explanation: In a time sharing system, each user needs to get a share of the CPU at regular intervals.

4. Consider the following set of processes, the length of the CPU burst time given in milliseconds.

a) The waiting time for process P1 is 3ms

b) The waiting time for process P1 is 0ms
c) The waiting time for process P1 is 16ms
d) The waiting time for process P1 is 9ms
Answer: a
Explanation: None.

5. Preemptive Shortest Job First scheduling is sometimes called ____________

a) Fast SJF scheduling

b) EDF scheduling – Earliest Deadline First
c) HRRN scheduling – Highest Response Ratio Next
d) SRTN scheduling – Shortest Remaining Time Next
Answer: d
Explanation: None.

6. An SJF algorithm is simply a priority algorithm where the priority is ____________

a) the predicted next CPU burst

b) the inverse of the predicted next CPU burst
c) the current CPU burst
d) anything the user wants
Answer: a
Explanation: The larger the CPU burst, the lower the priority.

7. Choose one of the disadvantages of the priority scheduling algorithm?

a) it schedules in a very complex manner

b) its scheduling takes up a lot of time
c) it can lead to some low priority process waiting indefinitely for the CPU
d) none of the mentioned
Answer: c
Explanation: None.

8. What is ‘Aging’?

a) keeping track of cache contents

b) keeping track of what pages are currently residing in memory
c) keeping track of how many times a given page is referenced
d) increasing the priority of jobs to ensure termination in a finite time
Answer: d
Explanation: None.

9. A solution to the problem of indefinite blockage of low – priority processes is ____________

a) Starvation
b) Wait queue
c) Ready queue
d) Aging i) Shortest remaining time first scheduling may cause starvation
Answer: d
Explanation: None.

10. Which of the following statements are true? (GATE 2010)

a) i only
b) i and iii only
c) ii and iii only
d) i, ii and iii
Answer: d
Explanation: None.

11. Which of the following scheduling algorithms gives minimum average waiting time?

a) FCFS
b) SJF
c) Round – robin
d) Priority
Answer: b
Explanation: None.

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1. Concurrent access to shared data may result in ____________

a) data consistency
b) data insecurity
c) data inconsistency
d) none of the mentioned
Answer: c
Explanation: None.

2. A situation where several processes access and manipulate the same data concurrently and the outcome of the exe
cution depends on the particular order in which access takes place is called ____________

a) data consistency
b) race condition
c) aging
d) starvation
Answer: b
Explanation: None.

3. The segment of code in which the process may change common variables, update tables, write into files is known
as ____________

a) program
b) critical section
c) non – critical section
d) synchronizing
Answer: b
Explanation: None.

4. Which of the following conditions must be satisfied to solve the critical section problem?

a) Mutual Exclusion
b) Progress
c) Bounded Waiting
d) All of the mentioned
Answer: d
Explanation: None.

5. Mutual exclusion implies that ____________

a) if a process is executing in its critical section, then no other process must be executing in their critical sections
b) if a process is executing in its critical section, then other processes must be executing in their critical sections
c) if a process is executing in its critical section, then all the resources of the system must be blocked until it finishes
execution
d) none of the mentioned
Answer: a
Explanation: None.

6. Bounded waiting implies that there exists a bound on the number of times a process is allowed to enter its critical
section ____________

a) after a process has made a request to enter its critical section and before the request is granted
b) when another process is in its critical section
c) before a process has made a request to enter its critical section
d) none of the mentioned
Answer: a
Explanation: None.

7. A minimum of _____ variable(s) is/are required to be shared between processes to solve the critical section proble
m.

a) one
b) two
c) three
d) four
Answer: b
Explanation: None.

8. In the bakery algorithm to solve the critical section problem ____________

a) each process is put into a queue and picked up in an ordered manner

b) each process receives a number (may or may not be unique) and the one with the lowest number is served next
c) each process gets a unique number and the one with the highest number is served next
d) each process gets a unique number and the one with the lowest number is served next
Answer: b
Explanation: None.

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1. An un-interruptible unit is known as ____________

a) single
b) atomic
c) static
d) none of the mentioned
Answer: b
Explanation: None.

2. TestAndSet instruction is executed ____________

a) after a particular process

b) periodically
c) atomically
d) none of the mentioned
Answer: c
Explanation: None.

3. Semaphore is a/an _______ to solve the critical section problem.

a) hardware for a system

b) special program for a system
c) integer variable
d) none of the mentioned
Answer: c
Explanation: None.

4. What are the two atomic operations permissible on semaphores?

a) wait
b) stop
c) hold
d) none of the mentioned
Answer: a
Explanation: None.

5. What are Spinlocks?

a) CPU cycles wasting locks over critical sections of programs

b) Locks that avoid time wastage in context switches
c) Locks that work better on multiprocessor systems
d) All of the mentioned
Answer: d
Explanation: None.

6. What is the main disadvantage of spinlocks?

a) they are not sufficient for many process

b) they require busy waiting
c) they are unreliable sometimes
d) they are too complex for programmers
Answer: b
Explanation: None.
7. The wait operation of the semaphore basically works on the basic _______ system call.

a) stop()
b) block()
c) hold()
d) wait()
Answer: b
Explanation: None.

8. The signal operation of the semaphore basically works on the basic _______ system call.

a) continue()
b) wakeup()
c) getup()
d) start()
Answer: b
Explanation: None.

9. If the semaphore value is negative ____________

a) its magnitude is the number of processes waiting on that semaphore

b) it is invalid
c) no operation can be further performed on it until the signal operation is performed on it
d) none of the mentioned
Answer: a
Explanation: None.

10. The code that changes the value of the semaphore is ____________

a) remainder section code

b) non – critical section code
c) critical section code
d) none of the mentioned
Answer: c
Explanation: None.

11. The following program consists of 3 concurrent processes and 3 binary semaphores. The semaphores are initializ
ed as S0 = 1, S1 = 0, S2 = 0.

a) At least twice
b) Exactly twice
c) Exactly thrice
d) Exactly once
Answer: a
Explanation: None.

12. Each process Pi, i = 0,1,2,3,……,9 is coded as follows.

a) 1
b) 2
c) 3
d) None of the mentioned
Answer: c
Explanation: Any one of the 9 processes can get into critical section after executing P(mutex) which decrements the
mutex value to 0. At this time P10 can enter critical section by incrementing the value to 1. Now any of the 9 proces
ses can enter the critical section by again decrementing the mutex value to 0. None of the remaining processes can g
et into their critical sections.

13. Two processes, P1 and P2, need to access a critical section of code. Consider the following synchronization cons
truct used by the processes.

a) It does not ensure mutual exclusion

b) It does not ensure bounded waiting
c) It requires that processes enter the critical section in strict alternation
d) It does not prevent deadlocks but ensures mutual exclusion
Answer: d
Explanation: None.

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1. What will happen if a non-recursive mutex is locked more than once?

a) Starvation
b) Deadlock
c) Aging
d) Signaling
Answer: b
Explanation: If a thread which had already locked a mutex, tries to lock the mutex again, it will enter into the waitin
g list of that mutex, which results in a deadlock. It is because no other thread can unlock the mutex.

2. What is a semaphore?

a) is a binary mutex
b) must be accessed from only one process
c) can be accessed from multiple processes
d) none of the mentioned
Answer: c
Explanation: None.

3. What are the two kinds of semaphores?

a) mutex & counting

b) binary & counting
c) counting & decimal
d) decimal & binary
Answer: b
Explanation: None.

4. What is a mutex?

a) is a binary mutex
b) must be accessed from only one process
c) can be accessed from multiple processes
d) none of the mentioned
Answer: b
Explanation: None.
5. At a particular time of computation the value of a counting semaphore is 7.Then 20 P operations and 15 V operati
ons were completed on this semaphore. The resulting value of the semaphore is? (GATE 1987)

a) 42
b) 2
c) 7
d) 12
Answer: b
Explanation: P represents Wait and V represents Signal. P operation will decrease the value by 1 every time and V
operation will increase the value by 1 every time.

6. A binary semaphore is a semaphore with integer values ____________

a) 1
b) -1
c) 0.8
d) 0.5
Answer: a
Explanation: None.

7. The following pair of processes share a common variable X.

a) two
b) three
c) four
d) eight
Answer: c
Explanation: Here are the possible ways in which statements from A and B can be interleaved.

8. The program follows to use a shared binary semaphore T.

a) one
b) two
c) three
d) four
Answer: a
Explanation: The semaphore T ensures that all the statements from A finish execution before B begins. So now there
is only one way in which statements from A and B can be interleaved:

9. Semaphores are mostly used to implement ____________

a) System calls
b) IPC mechanisms
c) System protection
d) None of the mentioned
Answer: b
Explanation: None.

10. Spinlocks are intended to provide __________ only.

a) Mutual Exclusion
b) Bounded Waiting
c) Aging
d) Progress
Answer: b
Explanation: None.

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1. The bounded buffer problem is also known as ____________

a) Readers – Writers problem

b) Dining – Philosophers problem
c) Producer – Consumer problem
d) None of the mentioned
Answer: c
Explanation: None.

2. In the bounded buffer problem, there are the empty and full semaphores that ____________

a) count the number of empty and full buffers

b) count the number of empty and full memory spaces
c) count the number of empty and full queues
d) none of the mentioned
Answer: a
Explanation: None.

3. In the bounded buffer problem ____________

a) there is only one buffer

b) there are n buffers ( n being greater than one but finite)
c) there are infinite buffers
d) the buffer size is bounded
Answer: b
Explanation: None.

4. To ensure difficulties do not arise in the readers – writers problem _______ are given exclusive access to the shar
ed object.

a) readers
b) writers
c) readers and writers
d) none of the mentioned
Answer: b
Explanation: None.

5. The dining – philosophers problem will occur in case of ____________

a) 5 philosophers and 5 chopsticks

b) 4 philosophers and 5 chopsticks
c) 3 philosophers and 5 chopsticks
d) 6 philosophers and 5 chopsticks
Answer: a
Explanation: None.

6. A deadlock free solution to the dining philosophers problem ____________

a) necessarily eliminates the possibility of starvation
b) does not necessarily eliminate the possibility of starvation
c) eliminates any possibility of any kind of problem further
d) none of the mentioned
Answer: b
Explanation: None.

7. All processes share a semaphore variable mutex, initialized to 1. Each process must execute wait(mutex) before e
ntering the critical section and signal(mutex) afterward.

a) a deadlock will occur

b) processes will starve to enter critical section
c) several processes maybe executing in their critical section
d) all of the mentioned
Answer: c
Explanation: None.

8. All processes share a semaphore variable mutex, initialized to 1. Each process must execute wait(mutex) before e
ntering the critical section and signal(mutex) afterward.

a) a deadlock will occur

b) processes will starve to enter critical section
c) several processes maybe executing in their critical section
d) all of the mentioned
Answer: a
Explanation: None.

9. Consider the methods used by processes P1 and P2 for accessing their critical sections whenever needed, as given
below. The initial values of shared boolean variables S1 and S2 are randomly assigned. (GATE 2010)

a) Mutual exclusion but not progress

b) Progress but not mutual exclusion
c) Neither mutual exclusion nor progress
d) Both mutual exclusion and progress
Answer: d
Explanation: None.

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1. A monitor is a type of ____________

a) semaphore
b) low level synchronization construct
c) high level synchronization construct
d) none of the mentioned
Answer: c
Explanation: None.

2. A monitor is characterized by ____________

a) a set of programmer defined operators

b) an identifier
c) the number of variables in it
d) all of the mentioned
Answer: a
Explanation: None.

3. A procedure defined within a ________ can access only those variables declared locally within the _______ and i
ts formal parameters.

a) process, semaphore
b) process, monitor
c) semaphore, semaphore
d) monitor, monitor
Answer: d
Explanation: None.

4. The monitor construct ensures that ____________

a) only one process can be active at a time within the monitor

b) n number of processes can be active at a time within the monitor (n being greater than 1)
c) the queue has only one process in it at a time
d) all of the mentioned
Answer: a
Explanation: None.

5. What are the operations that can be invoked on a condition variable?

a) wait & signal

b) hold & wait
c) signal & hold
d) continue & signal
Answer: a
Explanation: None.

6. Which is the process of invoking the wait operation?

a) suspended until another process invokes the signal operation

b) waiting for another process to complete before it can itself call the signal operation
c) stopped until the next process in the queue finishes execution
d) none of the mentioned
Answer: a
Explanation: None.

7. If no process is suspended, the signal operation ____________

a) puts the system into a deadlock state

b) suspends some default process execution
c) nothing happens
d) the output is unpredictable
Answer: c
Explanation: None.

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1. A collection of instructions that performs a single logical function is called ____________

a) transaction
b) operation
c) function
d) all of the mentioned
Answer: a
Explanation: None.

2. A terminated transaction that has completed its execution successfully is ____________ otherwise it is ________
__

a) committed, destroyed
b) aborted, destroyed
c) committed, aborted
d) none of the mentioned
Answer: c
Explanation: None.

3. The state of the data accessed by an aborted transaction must be restored to what it was just before the transaction
started executing. This restoration is known as ________ of transaction.

a) safety
b) protection
c) roll – back
d) revert – back
Answer: c
Explanation: None.

4. Write ahead logging is a way ____________

a) to ensure atomicity
b) to keep data consistent
c) that records data on stable storage
d) all of the mentioned
Answer: d
Explanation: None.

5. In the write ahead logging a _____________ is maintained.

a) a memory
b) a system
c) a disk
d) a log record
Answer: d
Explanation: None.

6. An actual update is not allowed to a data item ____________

a) before the corresponding log record is written out to stable storage

b) after the corresponding log record is written out to stable storage
c) until the whole log record has been checked for inconsistencies
d) all of the mentioned
Answer: a
Explanation: None.

7. The undo and redo operations must be _________ to guarantee correct behaviour, even if a failure occurs during r
ecovery process.

a) idempotent
b) easy
c) protected
d) all of the mentioned
Answer: a
Explanation: Idempotent – Multiple executions of an operation have the same result as does one execution.

8. The system periodically performs checkpoints that consists of the following operation(s) ____________

a) Putting all the log records currently in main memory onto stable storage
b) putting all modified data residing in main memory onto stable storage
c) putting a log record onto stable storage
d) all of the mentioned
Answer: d
Explanation: None.

9. Consider a transaction T1 that committed prior to checkpoint. The <T1 commits> record appears in the log before
the <checkpoint> record. Any modifications made by T1 must have been written to the stable storage either with th
e checkpoint or prior to it. Thus at recovery time ____________

a) There is a need to perform an undo operation on T1

b) There is a need to perform a redo operation on T1
c) There is no need to perform an undo and redo operation on T1
d) All of the mentioned
Answer: c
Explanation: None.

10. Serializable schedules are ones where ____________

a) concurrent execution of transactions is equivalent to the transactions executed serially

b) the transactions can be carried out one after the other
c) a valid result occurs after execution transactions
d) none of the mentioned
Answer: a
Explanation: None.

11. A locking protocol is one that ____________

a) governs how locks are acquired

b) governs how locks are released
c) governs how locks are acquired and released
d) none of the mentioned
Answer: c
Explanation: None.

12. The two phase locking protocol consists of ____________

a) growing & shrinking phase

b) shrinking & creation phase
c) creation & growing phase
d) destruction & creation phase
Answer: a
Explanation: None.

13. The growing phase is a phase in which?

a) A transaction may obtain locks, but does not release any

b) A transaction may obtain locks, and releases a few or all of them
c) A transaction may release locks, but does not obtain any new locks
d) A transaction may release locks, and does obtain new locks
Answer: a
Explanation: None.

14. The shrinking phase is a phase in which?

a) A transaction may obtain locks, but does not release any

b) A transaction may obtain locks, and releases a few or all of them
c) A transaction may release locks, but does not obtain any new locks
d) A transaction may release locks, and does obtain new locks
Answer: c
Explanation: None.

15. Which of the following concurrency control protocols ensure both conflict serializability and freedom from dead
lock?

a) I only
b) II only
c) Both I and II
d) Neither I nor II
Answer: b
Explanation: None.

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1. The number of resources requested by a process ____________

a) must always be less than the total number of resources available in the system
b) must always be equal to the total number of resources available in the system
c) must not exceed the total number of resources available in the system
d) must exceed the total number of resources available in the system
Answer: c
Explanation: None.

2. The request and release of resources are ___________

a) command line statements

b) interrupts
c) system calls
d) special programs
Answer: c
Explanation: None.
3. What are Multithreaded programs?

a) lesser prone to deadlocks

b) more prone to deadlocks
c) not at all prone to deadlocks
d) none of the mentioned
Answer: b
Explanation: Multiple threads can compete for shared resources.

4. For a deadlock to arise, which of the following conditions must hold simultaneously?

a) Mutual exclusion
b) No preemption
c) Hold and wait
d) All of the mentioned
Answer: d
Explanation: None.

5. For Mutual exclusion to prevail in the system ____________

a) at least one resource must be held in a non sharable mode

b) the processor must be a uniprocessor rather than a multiprocessor
c) there must be at least one resource in a sharable mode
d) all of the mentioned
Answer: a
Explanation: If another process requests that resource (non – shareable resource), the requesting process must be del
ayed until the resource has been released.

6. For a Hold and wait condition to prevail ____________

a) A process must be not be holding a resource, but waiting for one to be freed, and then request to acquire it
b) A process must be holding at least one resource and waiting to acquire additional resources that are being held by
other processes
c) A process must hold at least one resource and not be waiting to acquire additional resources
d) None of the mentioned
Answer: b
Explanation: None.

7. Deadlock prevention is a set of methods ____________

a) to ensure that at least one of the necessary conditions cannot hold

b) to ensure that all of the necessary conditions do not hold
c) to decide if the requested resources for a process have to be given or not
d) to recover from a deadlock
Answer: a
Explanation: None.

8. For non sharable resources like a printer, mutual exclusion ____________

a) must exist
b) must not exist
c) may exist
d) none of the mentioned
Answer: a
Explanation: A printer cannot be simultaneously shared by several processes.

9. For sharable resources, mutual exclusion ____________

a) is required
b) is not required
c) may be or may not be required
d) none of the mentioned
Answer: b
Explanation: They do not require mutually exclusive access, and hence cannot be involved in a deadlock.

10. To ensure that the hold and wait condition never occurs in the system, it must be ensured that ____________

a) whenever a resource is requested by a process, it is not holding any other resources

b) each process must request and be allocated all its resources before it begins its execution
c) a process can request resources only when it has none
d) all of the mentioned
Answer: d
Explanation: c – A process may request some resources and use them. Before it can can request any additional resou
rces, however it must release all the resources that it is currently allocated.

11. The disadvantage of a process being allocated all its resources before beginning its execution is ____________

a) Low CPU utilization

b) Low resource utilization
c) Very high resource utilization
d) None of the mentioned
Answer: b
Explanation: None.

12. To ensure no preemption, if a process is holding some resources and requests another resource that cannot be im
mediately allocated to it ____________

a) then the process waits for the resources be allocated to it

b) the process keeps sending requests until the resource is allocated to it
c) the process resumes execution without the resource being allocated to it
d) then all resources currently being held are preempted
Answer: d
Explanation: None.

13. One way to ensure that the circular wait condition never holds is to ____________

a) impose a total ordering of all resource types and to determine whether one precedes another in the ordering
b) to never let a process acquire resources that are held by other processes
c) to let a process wait for only one resource at a time
d) all of the mentioned
Answer: a
Explanation: None.

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1. Each request requires that the system consider the _____________ to decide whether the current request can be sa
tisfied or must wait to avoid a future possible deadlock.

a) resources currently available

b) processes that have previously been in the system
c) resources currently allocated to each process
d) future requests and releases of each process
Answer: a
Explanation: None.

2. Given a priori information about the ________ number of resources of each type that maybe requested for each pr
ocess, it is possible to construct an algorithm that ensures that the system will never enter a deadlock state.

a) minimum
b) average
c) maximum
d) approximate
Answer: c
Explanation: None.

3. A deadlock avoidance algorithm dynamically examines the __________ to ensure that a circular wait condition ca
n never exist.

a) resource allocation state

b) system storage state
c) operating system
d) resources
Answer: a
Explanation: Resource allocation states are used to maintain the availability of the already and current available reso
urces.

4. A state is safe, if ____________

a) the system does not crash due to deadlock occurrence

b) the system can allocate resources to each process in some order and still avoid a deadlock
c) the state keeps the system protected and safe
d) all of the mentioned
Answer: b
Explanation: None.

5. A system is in a safe state only if there exists a ____________

a) safe allocation
b) safe resource
c) safe sequence
d) all of the mentioned
Answer: c
Explanation: None.

6. All unsafe states are ____________

a) deadlocks
b) not deadlocks
c) fatal
d) none of the mentioned
Answer: b
Explanation: None.

7. A system has 12 magnetic tape drives and 3 processes : P0, P1, and P2. Process P0 requires 10 tape drives, P1 req
uires 4 and P2 requires 9 tape drives.

a) P0, P1, P2
b) P1, P2, P0
c) P2, P0, P1
d) P1, P0, P2
Answer: d
Explanation: None.

10

a) then the system will not be in a safe state

b) then the system will be in a safe state
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.

a) with multiple instances of each resource type

b) with a single instance of each resource type
c) single & multiple instances of each resource type
d) none of the mentioned
Answer: a
Explanation: None.

8. If no cycle exists in the resource allocation graph ____________

a) less efficient
b) more efficient
c) equal
d) none of the mentioned
Answer: a
Explanation: None.

9. The resource allocation graph is not applicable to a resource allocation system ____________

a) Available
b) Need
c) Allocation
d) All of the mentioned
Answer: d
Explanation: None.

10. The Banker’s algorithm is _____________ than the resource allocation graph algorithm.

a) Allocation – Available
b) Max – Available
c) Max – Allocation
d) Allocation – Max
Answer: c
Explanation: None.

11. The data structures available in the Banker’s algorithm are ____________

a) an unsafe state
b) a safe state
c) a protected state
d) a deadlock
Answer: b
Explanation: None.

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1. The wait-for graph is a deadlock detection algorithm that is applicable when ____________

a) all resources have a single instance

b) all resources have multiple instances
c) all resources have a single 7 multiple instances
d) all of the mentioned
Answer: a
Explanation: None.

2. An edge from process Pi to Pj in a wait for graph indicates that ____________

a) Pi is waiting for Pj to release a resource that Pi needs

b) Pj is waiting for Pi to release a resource that Pj needs
c) Pi is waiting for Pj to leave the system
d) Pj is waiting for Pi to leave the system
Answer: a
Explanation: None.

3. If the wait for graph contains a cycle ____________

a) then a deadlock does not exist

b) then a deadlock exists
c) then the system is in a safe state
d) either deadlock exists or system is in a safe state
Answer: b
Explanation: None.

4. If deadlocks occur frequently, the detection algorithm must be invoked ________

a) rarely
b) frequently
c) rarely & frequently
d) none of the mentioned
Answer: b
Explanation: None.

5. What is the disadvantage of invoking the detection algorithm for every request?
a) overhead of the detection algorithm due to consumption of memory
b) excessive time consumed in the request to be allocated memory
c) considerable overhead in computation time
d) all of the mentioned
Answer: c
Explanation: None.

6. A deadlock eventually cripples system throughput and will cause the CPU utilization to ______

a) increase
b) drop
c) stay still
d) none of the mentioned
Answer: b
Explanation: None.

7. Every time a request for allocation cannot be granted immediately, the detection algorithm is invoked. This will h
elp identify ____________

a) the set of processes that have been deadlocked

b) the set of processes in the deadlock queue
c) the specific process that caused the deadlock
d) all of the mentioned
Answer: a
Explanation: None.

8. A computer system has 6 tape drives, with ‘n’ processes competing for them. Each process may need 3 tape drive
s. The maximum value of ‘n’ for which the system is guaranteed to be deadlock free is?

a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: None.

9. A system has 3 processes sharing 4 resources. If each process needs a maximum of 2 units then, deadlock ______
______

a) can never occur

b) may occur
c) has to occur
d) none of the mentioned
Answer: a
Explanation: None.

10. ‘m’ processes share ‘n’ resources of the same type. The maximum need of each process doesn’t exceed ‘n’ and t
he sum of all their maximum needs is always less than m+n. In this setup, deadlock ____________

a) can never occur

b) may occur
c) has to occur
d) none of the mentioned
Answer: a
Explanation: None.

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1. A deadlock can be broken by ____________

a) abort one or more processes to break the circular wait

b) abort all the process in the system
c) preempt all resources from all processes
d) none of the mentioned
Answer: a
Explanation: None.

2. The two ways of aborting processes and eliminating deadlocks are ____________

a) Abort all deadlocked processes

b) Abort all processes
c) Abort one process at a time until the deadlock cycle is eliminated
d) All of the mentioned
Answer: c
Explanation: None.

3. Those processes should be aborted on occurrence of a deadlock, the termination of which?

a) is more time consuming

b) incurs minimum cost
c) safety is not hampered
d) all of the mentioned
Answer: b
Explanation: None.

4. The process to be aborted is chosen on the basis of the following factors?

a) priority of the process

b) process is interactive or batch
c) how long the process has computed
d) all of the mentioned
Answer: d
Explanation: None.

5. Cost factors for process termination include ____________

a) Number of resources the deadlock process is not holding

b) CPU utilization at the time of deadlock
c) Amount of time a deadlocked process has thus far consumed during its execution
d) All of the mentioned
Answer: c
Explanation: None.

6. If we preempt a resource from a process, the process cannot continue with its normal execution and it must be ___
_________

a) aborted
b) rolled back
c) terminated
d) queued
Answer: b
Explanation: None.

7. To _______ to a safe state, the system needs to keep more information about the states of processes.

a) abort the process

b) roll back the process
c) queue the process
d) none of the mentioned
Answer: b
Explanation: None.

8. If the resources are always preempted from the same process __________ can occur.

a) deadlock
b) system crash
c) aging
d) starvation
Answer: d
Explanation: None.

9. What is the solution to starvation?

a) the number of rollbacks must be included in the cost factor

b) the number of resources must be included in resource preemption
c) resource preemption be done instead
d) all of the mentioned
Answer: a
Explanation: None.

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1. What is Address Binding?

a) going to an address in memory

b) locating an address with the help of another address
c) binding two addresses together to form a new address in a different memory space
d) a mapping from one address space to another
Answer: d
Explanation: None.

2. Binding of instructions and data to memory addresses can be done at ____________

a) Compile time
b) Load time
c) Execution time
d) All of the mentioned
Answer: d
Explanation: None.
3. If the process can be moved during its execution from one memory segment to another, then binding must be ___
_________

a) delayed until run time

b) preponed to compile time
c) preponed to load time
d) none of the mentioned
Answer: a
Explanation: None.

4. What is Dynamic loading?

a) loading multiple routines dynamically

b) loading a routine only when it is called
c) loading multiple routines randomly
d) none of the mentioned
Answer: b
Explanation: None.

5. What is the advantage of dynamic loading?

a) A used routine is used multiple times

b) An unused routine is never loaded
c) CPU utilization increases
d) All of the mentioned
Answer: b
Explanation: None.

6. The idea of overlays is to ____________

a) data that are needed at any given time

b) enable a process to be larger than the amount of memory allocated to it
c) keep in memory only those instructions
d) all of the mentioned
Answer: d
Explanation: None.

7. The ___________ must design and program the overlay structure.

a) programmer
b) system architect
c) system designer
d) none of the mentioned
Answer: a
Explanation: None.

8. The ___________ swaps processes in and out of the memory.

a) Memory manager
b) CPU
c) CPU manager
d) User
Answer: a
Explanation: None.
9. If a higher priority process arrives and wants service, the memory manager can swap out the lower priority proces
s to execute the higher priority process. When the higher priority process finishes, the lower priority process is swap
ped back in and continues execution. This variant of swapping is sometimes called?

a) priority swapping
b) pull out, push in
c) roll out, roll in
d) none of the mentioned
Answer: c
Explanation: None.

10. If binding is done at assembly or load time, then the process _____ be moved to different locations after being s
wapped out and in again.

a) can
b) must
c) can never
d) may
Answer: c
Explanation: None.

11. In a system that does not support swapping ____________

a) the compiler normally binds symbolic addresses (variables) to relocatable addresses

b) the compiler normally binds symbolic addresses to physical addresses
c) the loader binds relocatable addresses to physical addresses
d) binding of symbolic addresses to physical addresses normally takes place during execution
Answer: a
Explanation: None.

12. Which of the following is TRUE?

a) Overlays are used to increase the size of physical memory

b) Overlays are used to increase the logical address space
c) When overlays are used, the size of a process is not limited to the size of the physical memory
d) Overlays are used whenever the physical address space is smaller than the logical address space
Answer: c
Explanation: None.

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1. The address generated by the CPU is referred to as ____________

a) Physical address
b) Logical address
c) Neither physical nor logical
d) None of the mentioned
Answer: b
Explanation: None.

2. The address loaded into the memory address register of the memory is referred to as ____________
a) Physical address
b) Logical address
c) Neither physical nor logical
d) None of the mentioned
Answer: a
Explanation: None.

3. The run time mapping from virtual to physical addresses is done by a hardware device called the ____________

a) Virtual to physical mapper

b) Memory management unit
c) Memory mapping unit
d) None of the mentioned
Answer: b
Explanation: None.

4. The base register is also known as the ____________

a) basic register
b) regular register
c) relocation register
d) delocation register
Answer: c
Explanation: None.

5. The size of a process is limited to the size of ____________

a) physical memory
b) external storage
c) secondary storage
d) none of the mentioned
Answer: a
Explanation: None.

6. If execution time binding is being used, then a process ______ be swapped to a different memory space.

a) has to be
b) can never
c) must
d) may
Answer: d
Explanation: None.

7. Swapping requires a _________

a) motherboard
b) keyboard
c) monitor
d) backing store
Answer: d
Explanation: None.

8. The backing store is generally a ____________

a) fast disk
b) disk large enough to accommodate copies of all memory images for all users
c) disk to provide direct access to the memory images
d) all of the mentioned
Answer: d
Explanation: None.

9. The ________ consists of all processes whose memory images are in the backing store or in memory and are read
y to run.

a) wait queue
b) ready queue
c) cpu
d) secondary storage
Answer: b
Explanation: None.

10. The _________ time in a swap out of a running process and swap in of a new process into the memory is very hi
gh.

a) context – switch
b) waiting
c) execution
d) all of the mentioned
Answer: a
Explanation: None.

11. The major part of swap time is _______ time.

a) waiting
b) transfer
c) execution
d) none of the mentioned
Answer: b
Explanation: None.

12. Swapping _______ be done when a process has pending I/O, or has to execute I/O operations only into operating
system buffers.

a) must
b) can
c) must never
d) maybe
Answer: c
Explanation: None.

13. Swap space is allocated ____________

a) as a chunk of disk
b) separate from a file system
c) into a file system
d) all of the mentioned
Answer: a
Explanation: None.
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1. The main memory accommodates ____________

a) operating system
b) cpu
c) user processes
d) all of the mentioned
Answer: a
Explanation: None.

2. What is the operating system?

a) in the low memory

b) in the high memory
c) either low or high memory (depending on the location of interrupt vector)
d) none of the mentioned
Answer: c
Explanation: None.

3. In contiguous memory allocation ____________

a) each process is contained in a single contiguous section of memory

b) all processes are contained in a single contiguous section of memory
c) the memory space is contiguous
d) none of the mentioned
Answer: a
Explanation: None.

4. The relocation register helps in ____________

a) providing more address space to processes

b) a different address space to processes
c) to protect the address spaces of processes
d) none of the mentioned
Answer: c
Explanation: None.

5. With relocation and limit registers, each logical address must be _______ the limit register.

a) less than
b) equal to
c) greater than
d) none of the mentioned
Answer: a
Explanation: None.

6. The operating system and the other processes are protected from being modified by an already running process be
cause ____________

a) they are in different memory spaces

b) they are in different logical addresses
c) they have a protection algorithm
d) every address generated by the CPU is being checked against the relocation and limit registers
Answer: d
Explanation: None.

7. Transient operating system code is code that ____________

a) is not easily accessible

b) comes and goes as needed
c) stays in the memory always
d) never enters the memory space
Answer: b
Explanation: None.

8. Using transient code, _______ the size of the operating system during program execution.

a) increases
b) decreases
c) changes
d) maintains
Answer: c
Explanation: None.

9. When memory is divided into several fixed sized partitions, each partition may contain ________

a) exactly one process

b) at least one process
c) multiple processes at once
d) none of the mentioned
Answer: a
Explanation: None.

10. In fixed size partition, the degree of multiprogramming is bounded by ___________

a) the number of partitions

b) the CPU utilization
c) the memory size
d) all of the mentioned
Answer: a
Explanation: None

11. The first fit, best fit and worst fit are strategies to select a ______

a) process from a queue to put in memory

b) processor to run the next process
c) free hole from a set of available holes
d) all of the mentioned
Answer: c
Explanation: None.

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1. In internal fragmentation, memory is internal to a partition and ____________

a) is being used
b) is not being used
c) is always used
d) none of the mentioned
Answer: b
Explanation: None.

2. A solution to the problem of external fragmentation is ____________

a) compaction
b) larger memory space
c) smaller memory space
d) none of the mentioned
Answer: a
Explanation: None.

3. Another solution to the problem of external fragmentation problem is to ____________

a) permit the logical address space of a process to be noncontiguous

b) permit smaller processes to be allocated memory at last
c) permit larger processes to be allocated memory at last
d) all of the mentioned
Answer: a
Explanation: None.

4. If relocation is static and is done at assembly or load time, compaction _________

a) cannot be done
b) must be done
c) must not be done
d) can be done
Answer: a
Explanation: None.

5. The disadvantage of moving all process to one end of memory and all holes to the other direction, producing one l
arge hole of available memory is ____________

a) the cost incurred

b) the memory used
c) the CPU used
d) all of the mentioned
Answer: a
Explanation: None.

6. __________ is generally faster than _________ and _________

a) first fit, best fit, worst fit

b) best fit, first fit, worst fit
c) worst fit, best fit, first fit
d) none of the mentioned
Answer: a
Explanation: None.
7. External fragmentation exists when?

a) enough total memory exists to satisfy a request but it is not contiguous

b) the total memory is insufficient to satisfy a request
c) a request cannot be satisfied even when the total memory is free
d) none of the mentioned
Answer: a
Explanation: None.

8. External fragmentation will not occur when?

a) first fit is used

b) best fit is used
c) worst fit is used
d) no matter which algorithm is used, it will always occur
Answer: d
Explanation: None.

9. Sometimes the overhead of keeping track of a hole might be ____________

a) larger than the memory

b) larger than the hole itself
c) very small
d) all of the mentioned
Answer: b
Explanation: None.

10. When the memory allocated to a process is slightly larger than the process, then ____________

a) internal fragmentation occurs

b) external fragmentation occurs
c) both internal and external fragmentation occurs
d) neither internal nor external fragmentation occurs
Answer: a
Explanation: None.

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1. Physical memory is broken into fixed-sized blocks called ________

a) frames
b) pages
c) backing store
d) none of the mentioned
Answer: a
Explanation: None.

2. Logical memory is broken into blocks of the same size called _________

a) frames
b) pages
c) backing store
d) none of the mentioned
Answer: b
Explanation: None.

3. Every address generated by the CPU is divided into two parts. They are ____________

a) frame bit & page number

b) page number & page offset
c) page offset & frame bit
d) frame offset & page offset
Answer: b
Explanation: None.

4. The __________ is used as an index into the page table.

a) frame bit
b) page number
c) page offset
d) frame offset
Answer: b
Explanation: None.

5. The _____ table contains the base address of each page in physical memory.

a) process
b) memory
c) page
d) frame
Answer: c
Explanation: None.

6. The size of a page is typically ____________

a) varied
b) power of 2
c) power of 4
d) none of the mentioned
Answer: b
Explanation: None.

7. If the size of logical address space is 2 to the power of m, and a page size is 2 to the power of n addressing units, t
hen the high order _____ bits of a logical address designate the page number, and the ____ low order bits designate t
he page offset.

a) m, n
b) n, m
c) m – n, m
d) m – n, n
Answer: d
Explanation: None.

8. With paging there is no ________ fragmentation.

a) internal
b) external
c) either type of
d) none of the mentioned
Answer: b
Explanation: None.

9. The operating system maintains a ______ table that keeps track of how many frames have been allocated, how ma
ny are there, and how many are available.

a) page
b) mapping
c) frame
d) memory
Answer: c
Explanation: None.

10. Paging increases the ______ time.

a) waiting
b) execution
c) context – switch
d) all of the mentioned
Answer: c
Explanation: None.

11. Smaller page tables are implemented as a set of _______

a) queues
b) stacks
c) counters
d) registers
Answer: d
Explanation: None.

12. The page table registers should be built with _______

a) very low speed logic

b) very high speed logic
c) a large memory space
d) none of the mentioned
Answer: b
Explanation: None.

13. For larger page tables, they are kept in main memory and a __________ points to the page table.

a) page table base register

b) page table base pointer
c) page table register pointer
d) page table base
Answer: a
Explanation: None.

14. For every process there is a __________

a) page table
b) copy of page table
c) pointer to page table
d) all of the mentioned
Answer: a
Explanation: None.

15. Time taken in memory access through PTBR is ____________

a) extended by a factor of 3
b) extended by a factor of 2
c) slowed by a factor of 3
d) slowed by a factor of 2
Answer: d
Explanation: None.

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1. Each entry in a translation lookaside buffer (TL

b) consists of ____________

a) key
b) value
c) bit value
d) constant
Answer: a
Explanation: None.

2. If a page number is not found in the TLB, then it is known as a ____________

a) TLB miss
b) Buffer miss
c) TLB hit
d) All of the mentioned
Answer: a
Explanation: None.

3. An ______ uniquely identifies processes and is used to provide address space protection for that process.

a) address space locator

b) address space identifier
c) address process identifier
d) none of the mentioned
Answer: b
Explanation: None.

4. The percentage of times a page number is found in the TLB is known as ____________

a) miss ratio
b) hit ratio
c) miss percent
d) none of the mentioned
Answer: b
Explanation: None.

5. Memory protection in a paged environment is accomplished by ____________

a) protection algorithm with each page

b) restricted access rights to users
c) restriction on page visibility
d) protection bit with each page
Answer: d
Explanation: None.

6. When the valid – invalid bit is set to valid, it means that the associated page ____________

a) is in the TLB
b) has data in it
c) is in the process’s logical address space
d) is the system’s physical address space
Answer: c
Explanation: None.

7. Illegal addresses are trapped using the _____ bit.

a) error
b) protection
c) valid – invalid
d) access
Answer: c
Explanation: None.

8. When there is a large logical address space, the best way of paging would be ____________

a) not to page
b) a two level paging algorithm
c) the page table itself
d) all of the mentioned
Answer: b
Explanation: None.

9. In a paged memory, the page hit ratio is 0.35. The required to access a page in secondary memory is equal to 100
ns. The time required to access a page in primary memory is 10 ns. The average time required to access a page is?

a) 3.0 ns
b) 68.0 ns
c) 68.5 ns
d) 78.5 ns
Answer: c
Explanation: None.

10. To obtain better memory utilization, dynamic loading is used. With dynamic loading, a routine is not loaded unti
l it is called. For implementing dynamic loading ____________

a) special support from hardware is required

b) special support from operating system is essential
c) special support from both hardware and operating system is essential
d) user programs can implement dynamic loading without any special support from hardware or operating system
Answer: d
Explanation: None.

11. In paged memory systems, if the page size is increased, then the internal fragmentation generally ____________

a) becomes less
b) becomes more
c) remains constant
d) none of the mentioned
Answer: b
Explanation: None.

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1. In segmentation, each address is specified by ____________

a) a segment number & offset

b) an offset & value
c) a value & segment number
d) a key & value
Answer: a
Explanation: None.

2. In paging the user provides only ________ which is partitioned by the hardware into ________ and ______

a) one address, page number, offset

b) one offset, page number, address
c) page number, offset, address
d) none of the mentioned
Answer: a
Explanation: None.

3. Each entry in a segment table has a ____________

a) segment base
b) segment peak
c) segment value
d) none of the mentioned
Answer: a
Explanation: None.

4. The segment base contains the ____________

a) starting logical address of the process

b) starting physical address of the segment in memory
c) segment length
d) none of the mentioned
Answer: b
Explanation: None.

5. The segment limit contains the ____________

a) starting logical address of the process
b) starting physical address of the segment in memory
c) segment length
d) none of the mentioned
Answer: c
Explanation: None.

6. The offset ‘d’ of the logical address must be ____________

a) greater than segment limit

b) between 0 and segment limit
c) between 0 and the segment number
d) greater than the segment number
Answer: b
Explanation: None.

7. If the offset is legal ____________

a) it is used as a physical memory address itself

b) it is subtracted from the segment base to produce the physical memory address
c) it is added to the segment base to produce the physical memory address
d) none of the mentioned
Answer: a
Explanation: None.

8. When the entries in the segment tables of two different processes point to the same physical location __________
__

a) the segments are invalid

b) the processes get blocked
c) segments are shared
d) all of the mentioned
Answer: c
Explanation: None.

9. The protection bit is 0/1 based on ____________

a) write only
b) read only
c) read – write
d) none of the mentioned
Answer: c
Explanation: None.

10. If there are 32 segments, each of size 1Kb, then the logical address should have ____________

a) 13 bits
b) 14 bits
c) 15 bits
d) 16 bits
Answer: a
Explanation: To specify a particular segment, 5 bits are required. To select a particular byte after selecting a page, 1
0 more bits are required. Hence 15 bits are required.
11. Consider a computer with 8 Mbytes of main memory and a 128K cache. The cache block size is 4 K. It uses a di
rect mapping scheme for cache management. How many different main memory blocks can map onto a given physic
al cache block?

a) 2048
b) 256
c) 64
d) 8
Answer: c
Explanation: None.

12. A multilevel page table is preferred in comparison to a single level page table for translating virtual address to ph
ysical address because ____________

a) it reduces the memory access time to read or write a memory location

b) it helps to reduce the size of page table needed to implement the virtual address space of a process
c) it is required by the translation lookaside buffer
d) it helps to reduce the number of page faults in page replacement algorithms
Answer: b
Explanation: None.

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1. If one or more devices use a common set of wires to communicate with the computer system, the connection is cal
led ______

a) CPU
b) Monitor
c) Wirefull
d) Bus
Answer: d
Explanation: None.

2. A ____ a set of wires and a rigidly defined protocol that specifies a set of messages that can be sent on the wires.

a) port
b) node
c) bus
d) none of the mentioned
Answer: c
Explanation: None.

3. When device A has a cable that plugs into device B, and device B has a cable that plugs into device C and device
C plugs into a port on the computer, this arrangement is called a _________

a) port
b) daisy chain
c) bus
d) cable
Answer: b
Explanation: None.

4. The _________ present a uniform device-access interface to the I/O subsystem, much as system calls provide a st
andard interface between the application and the operating system.

a) Devices
b) Buses
c) Device drivers
d) I/O systems
Answer: c
Explanation: None.

5. A ________ is a collection of electronics that can operate a port, a bus, or a device.

a) controller
b) driver
c) host
d) bus
Answer: a
Explanation: None.

6. An I/O port typically consists of four registers status, control, ________ and ________ registers.

a) system in, system out

b) data in, data out
c) flow in, flow out
d) input, output
Answer: b
Explanation: None.

7. The ______ register is read by the host to get input.

a) flow in
b) flow out
c) data in
d) data out
Answer: c
Explanation: None.

8. The ______ register is written by the host to send output.

a) status
b) control
c) data in
d) data out
Answer: d
Explanation: None.

9. The hardware mechanism that allows a device to notify the CPU is called _______

a) polling
b) interrupt
c) driver
d) controlling
Answer: b
Explanation: None.
10. The CPU hardware has a wire called __________ that the CPU senses after executing every instruction.

a) interrupt request line

b) interrupt bus
c) interrupt receive line
d) interrupt sense line
Answer: a
Explanation: None.

11. The _________ determines the cause of the interrupt, performs the necessary processing and executes a return fr
om the interrupt instruction to return the CPU to the execution state prior to the interrupt.

a) interrupt request line

b) device driver
c) interrupt handler
d) all of the mentioned
Answer: c
Explanation: None.

12. In general the two interrupt request lines are ____________

a) maskable & non maskable interrupts

b) blocked & non maskable interrupts
c) maskable & blocked interrupts
d) none of the mentioned
Answer: a
Explanation: None.

13. The _________ are reserved for events such as unrecoverable memory errors.

a) non maskable interrupts

b) blocked interrupts
c) maskable interrupts
d) none of the mentioned
Answer: a
Explanation: None.

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1. The ________ can be turned off by the CPU before the execution of critical instruction sequences that must not b
e interrupted.

a) nonmaskable interrupt
b) blocked interrupt
c) maskable interrupt
d) none of the mentioned
Answer: c
Explanation: None.

2. The __________ is used by device controllers to request service.

a) nonmaskable interrupt
b) blocked interrupt
c) maskable interrupt
d) none of the mentioned
Answer: c
Explanation: None.

3. The interrupt vector contains ____________

a) the interrupts
b) the memory addresses of specialized interrupt handlers
c) the identifiers of interrupts
d) the device addresses
Answer: b
Explanation: None.

4. Division by zero, accessing a protected or non existent memory address, or attempting to execute a privileged inst
ruction from user mode are all categorized as ________

a) errors
b) exceptions
c) interrupt handlers
d) all of the mentioned
Answer: b
Explanation: None.

5. For large data transfers, _________ is used.

a) dma
b) programmed I/O
c) controller register
d) none of the mentioned
Answer: a
Explanation: None.

6. A character stream device transfers ____________

a) bytes one by one

b) block of bytes as a unit
c) with unpredictable response times
d) none of the mentioned
Answer: a
Explanation: None.

7. A block device transfers ____________

a) bytes one by one

b) block of bytes as a unit
c) with unpredictable response times
d) none of the mentioned
Answer: b
Explanation: None.

8. What is a dedicated device?

a) opposite to a sharable device

b) same as a sharable device
c) can be used concurrently by several processes
d) none of the mentioned
Answer: a
Explanation: None.

9. A keyboard is an example of a device that is accessed through a __________ interface.

a) block stream
b) set of blocks
c) character stream
d) none of the mentioned
Answer: c
Explanation: None.

10. In polling ____________

a) busy – wait cycles wait for I/O from device

b) interrupt handler receives interrupts
c) interrupt-request line is triggered by I/O device
d) all of the mentioned
Answer: a
Explanation: None.

11. A non blocking system call _________________

a) halts the execution of the application for an extended time

b) does not halt the execution of the application
c) does not block the interrupts
d) none of the mentioned
Answer: b
Explanation: None.

12. An asynchronous call ____________

a) returns immediately, without waiting for the I/O to complete

b) does not return immediately and waits for the I/O to complete
c) consumes a lot of time
d) is too slow
Answer: a
Explanation: None.

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1. Buffering is done to ____________

a) cope with device speed mismatch

b) cope with device transfer size mismatch
c) maintain copy semantics
d) all of the mentioned
Answer: d
Explanation: None.
2. Caching is ________ spooling.

a) same as
b) not the same as
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.

3. Caching ____________

a) holds a copy of the data

b) is fast memory
c) holds the only copy of the data
d) holds output for a device
Answer: a
Explanation: None.

4. Spooling ____________

a) holds a copy of the data

b) is fast memory
c) holds the only copy of the data
d) holds output for a device
Answer: c
Explanation: None.

5. The ________ keeps state information about the use of I/O components.

a) CPU
b) OS
c) kernel
d) shell
Answer: c
Explanation: None.

6. The kernel data structures include ____________

a) process table
b) open file table
c) close file table
d) all of the mentioned
Answer: b
Explanation: None.

7. Windows NT uses a __________ implementation for I/O.

a) message – passing
b) draft – passing
c) secondary memory
d) cache
Answer: a
Explanation: None.
8. A ________ is a full duplex connection between a device driver and a user level process.

a) Bus
b) I/O operation
c) Stream
d) Flow
Answer: c
Explanation: None.

9. I/O is a _________ in system performance.

a) major factor
b) minor factor
c) does not matter
d) none of the mentioned
Answer: a
Explanation: None.

10. If the number of cycles spent busy – waiting is not excessive, then ____________

a) interrupt driven I/O is more efficient than programmed I/O

b) programmed I/O is more efficient than interrupt driven I/O
c) both programmed and interrupt driven I/O are equally efficient
d) none of the mentioned
Answer: b
Explanation: None.

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1. What is the disadvantage of real addressing mode?

a) there is a lot of cost involved

b) time consumption overhead
c) absence of memory protection between processes
d) restricted access to memory locations by processes
Answer: c
Explanation: None.

2. Preemptive, priority based scheduling guarantees ____________

a) hard real time functionality

b) soft real time functionality
c) protection of memory
d) none of the mentioned
Answer: b
Explanation: None.

3. Real time systems must have ____________

a) preemptive kernels
b) non preemptive kernels
c) preemptive kernels or non preemptive kernels
d) neither preemptive nor non preemptive kernels
Answer: a
Explanation: None.

4. What is Event latency?

a) the amount of time an event takes to occur from when the system started
b) the amount of time from the event occurrence till the system stops
c) the amount of time from event occurrence till the event crashes
d) the amount of time that elapses from when an event occurs to when it is serviced.
Answer: d
Explanation: None.

5. Interrupt latency refers to the period of time ____________

a) from the occurrence of an event to the arrival of an interrupt

b) from the occurrence of an event to the servicing of an interrupt
c) from arrival of an interrupt to the start of the interrupt service routine
d) none of the mentioned
Answer: c
Explanation: None.

6. Real time systems need to __________ the interrupt latency.

a) minimize
b) maximize
c) not bother about
d) none of the mentioned
Answer: a
Explanation: None.

7. The amount of time required for the scheduling dispatcher to stop one process and start another is known as ____
__________

a) event latency
b) interrupt latency
c) dispatch latency
d) context switch
Answer: c
Explanation: None.

8. The most effective technique to keep dispatch latency low is to ____________

a) provide non preemptive kernels

b) provide preemptive kernels
c) make it user programmed
d) run less number of processes at a time
Answer: b
Explanation: None.

9. Priority inversion is solved by use of _____________

a) priority inheritance protocol

b) two phase lock protocol
c) time protocol
d) all of the mentioned
Answer: a
Explanation: None.

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1. In a real time system the computer results ____________

a) must be produced within a specific deadline period

b) may be produced at any time
c) may be correct
d) all of the mentioned
Answer: a
Explanation: None.

2. In a safety critical system, incorrect operation ____________

a) does not affect much

b) causes minor problems
c) causes major and serious problems
d) none of the mentioned
Answer: c
Explanation: None.

3. Antilock brake systems, flight management systems, pacemakers are examples of ____________

a) safety critical system

b) hard real time system
c) soft real time system
d) safety critical system and hard real time system
Answer: d
Explanation: None.

4. In a ______ real time system, it is guaranteed that critical real time tasks will be completed within their deadlines.

a) soft
b) hard
c) critical
d) none of the mentioned
Answer: b
Explanation: None.

5. Some of the properties of real time systems include ____________

a) single purpose
b) inexpensively mass produced
c) small size
d) all of the mentioned
Answer: d
Explanation: None.

6. The amount of memory in a real time system is generally ____________

a) less compared to PCs
b) high compared to PCs
c) same as in PCs
d) they do not have any memory
Answer: a
Explanation: None.

7. What is the priority of a real time task?

a) must degrade over time

b) must not degrade over time
c) may degrade over time
d) none of the mentioned
Answer: b
Explanation: None.

8. Memory management units ____________

a) increase the cost of the system

b) increase the power consumption of the system
c) increase the time required to complete an operation
d) all of the mentioned
Answer: d
Explanation: None.

9. The technique in which the CPU generates physical addresses directly is known as ____________

a) relocation register method

b) real addressing
c) virtual addressing
d) none of the mentioned
Answer: b
Explanation: None.

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1. Earliest deadline first algorithm assigns priorities according to ____________

a) periods
b) deadlines
c) burst times
d) none of the mentioned
Answer: b
Explanation: None.

2. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. The tota
l CPU utilization is ____________

a) 0.90
b) 0.74
c) 0.94
d) 0.80
Answer: c
Explanation: None.

3. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35., the prio
rities of P1 and P2 are?

a) remain the same throughout

b) keep varying from time to time
c) may or may not be change
d) none of the mentioned
Answer: b
Explanation: None.

4. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35., can the
two processes be scheduled using the EDF algorithm without missing their respective deadlines?

a) Yes
b) No
c) Maybe
d) None of the mentioned
Answer: a
Explanation: None.

5. Using EDF algorithm practically, it is impossible to achieve 100 percent utilization due to __________

a) the cost of context switching

b) interrupt handling
c) power consumption
d) all of the mentioned
Answer: a
Explanation: None.

6. T shares of time are allocated among all processes out of N shares in __________ scheduling algorithm.

a) rate monotonic
b) proportional share
c) earliest deadline first
d) none of the mentioned
Answer: b
Explanation: None.

7. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B i
s assigned 15 shares and C is assigned 20 shares.

a) 20
b) 15
c) 50
d) none of the mentioned
Answer: c
Explanation: None.

8. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B
is assigned 15 shares and C is assigned 20 shares.
a) 20
b) 15
c) 50
d) none of the mentioned
Answer: b
Explanation: None.

9. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B
is assigned 15 shares and C is assigned 20 shares.

a) 20
b) 15
c) 50
d) none of the mentioned
Answer: a
Explanation: None.

10. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares,
B is assigned 15 shares and C is assigned 20 shares.

a) allocate 30 shares to it
b) deny entry to D in the system
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.

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1. To schedule the processes, they are considered _________

a) infinitely long
b) periodic
c) heavy weight
d) light weight
Answer: b
Explanation: None.

2. If the period of a process is ‘p’, then what is the rate of the task?

a) p2
b) 2*p
c) 1/p
d) p
Answer: c
Explanation: None.

3. The scheduler admits a process using __________

a) two phase locking protocol

b) admission control algorithm
c) busy wait polling
d) none of the mentioned
Answer: c
Explanation: None.

4. The ____________ scheduling algorithm schedules periodic tasks using a static priority policy with preemption.

a) earliest deadline first

b) rate monotonic
c) first cum first served
d) priority
Answer: b
Explanation: None.

5. Rate monotonic scheduling assumes that the __________

a) processing time of a periodic process is same for each CPU burst

b) processing time of a periodic process is different for each CPU burst
c) periods of all processes is the same
d) none of the mentioned
Answer: a
Explanation: None.

6. In rate monotonic scheduling, a process with a shorter period is assigned __________

a) a higher priority
b) a lower priority
c) higher & lower priority
d) none of the mentioned
Answer: a
Explanation: None.

7. There are two processes P1 and P2, whose periods are 50 and 100 respectively. P1 is assigned higher priority than
P2. The processing times are t1 = 20 for P1 and t2 = 35 for P2. Is it possible to schedule these tasks so that each me
ets its deadline using Rate monotonic scheduling?

a) yes
b) no
c) maybe
d) none of the mentioned
Answer: a
Explanation: None.

8. If a set of processes cannot be scheduled by rate monotonic scheduling algorithm, then __________

a) they can be scheduled by EDF algorithm

b) they cannot be scheduled by EDF algorithm
c) they cannot be scheduled by any other algorithm
d) none of the mentioned
Answer: c
Explanation: None.

9. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. The tota
l CPU utilization is?

a) 0.90
b) 0.74
c) 0.94
d) 0.80
Answer: c
Explanation: None.

10. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. Can th
e processes be scheduled without missing the deadlines?

a) Yes
b) No
c) Maybe
d) None of the mentioned
Answer: b
Explanation: None.

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1. The major difference between a multimedia file and a regular file is ___________

a) the size
b) the attributes
c) the ownership
d) the rate at which the file must be accessed
Answer: d
Explanation: Multimedia files must be accessed at a specific rate whereas accessing regular files requires no special
timings.

2. Video is represented as a series of images formally known as ___________

a) pics
b) shots
c) frames
d) snaps
Answer: c
Explanation: None.

3. The faster the frames are displayed, ___________

a) the rougher the video appears

b) the smoother the video appears
c) it gets blurry
d) none of the mentioned
Answer: b
Explanation: None.

4. The characteristic of the eye to retain the image for a short time after it has been presented is known as ________
___

a) persistence of vision
b) learning power
c) memory mapped input
d) none of the mentioned
Answer: a
Explanation: None.

5. When will Local playback be used?

a) the multimedia data are delivered from a local file system

b) a computer next to you is playing something
c) a multimedia file is being played on a system in the local network
d) none of the mentioned
Answer: a
Explanation: None.

6. Multimedia files stored on a remote server are delivered to a client across the network using a technique known as
___________

a) download
b) streaming
c) flowing
d) leaking
Answer: b
Explanation: None.

7. What are the two types of streaming techniques?

a) progressive download & real time streaming

b) regular download & real time streaming
c) real time & virtual time streaming
d) virtual time streaming
Answer: a
Explanation: None.

8. A media file containing audio or video is downloaded and stored on the client’s local file system in ___________

a) progressive download
b) regular download
c) real time streaming
d) virtual time streaming
Answer: a
Explanation: As the file is being downloaded, the client is able to play back the media file without having to wait for
the file to be downloaded in its entirety.

9. Progressive download is most useful for ___________

a) short video clips

b) long video clips
c) extremely long and high quality videos
d) none of the mentioned
Answer: a
Explanation: None.

10. The media file is streamed to the client but is only played and not stored by the client in ___________

a) progressive download
b) regular download
c) real time streaming
d) virtual time streaming
Answer: c
Explanation: None.

11. Real time streaming is most useful for ___________

a) short video clips

b) long video clips
c) extremely short and low quality videos
d) none of the mentioned
Answer: b
Explanation: None.

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1. The ability to move around within a media stream is known as ___________

a) buffering
b) random access
c) access
d) sequential access
Answer: b
Explanation: None.

2. What are the two types of real time streaming?

a) live & on demand streaming

b) dead & static streaming
c) static & on demand streaming
d) on demand streaming
Answer: a
Explanation: None.

3. Random access is not allowed in ___________

a) live streaming
b) dead streaming
c) static streaming
d) on demand streaming
Answer: a
Explanation: None.

4. The streaming that takes place as the event is occurring is ___________

a) live streaming
b) dead streaming
c) static streaming
d) on demand streaming
Answer: d
Explanation: None.
5. For a computer to deliver continuous media it must guarantee the specific rate and timing requirements, also kno
wn as ___________

a) deadline
b) quality of service
c) period
d) burst time
Answer: b
Explanation: None.

6. For QOS to be implemented properly ___________

a) file systems must be efficient to meet the rate requirements of continuous media
b) network protocols must support bandwidth requirements while minimizing delay and jitter
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: None.

7. What will happen once a file is compressed?

a) it has a better quality

b) it takes up less space for storage
c) it cannot be delivered to the client more quickly
d) none of the mentioned
Answer: b
Explanation: None.

8. Compression ratio is the ratio of ___________

a) the original file size to the size of the compressed file

b) the number of pixels in a frame of the original size to those in a frame of the compressed file
c) compressed file size to the original file size
d) none of the mentioned
Answer: a
Explanation: None.

9. Lossy and lossless are classifications of ___________

a) multimedia storage systems

b) files
c) compression algorithms
d) all of the mentioned
Answer: c
Explanation: None.

10. Lossy techniques provide ___________ when compared to lossless techniques.

a) lower compression ratios

b) much higher compression ratios
c) similar compression ratios
d) none of the mentioned
Answer: b
Explanation: None.
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1. What is the full form of MPEG?

a) Motion Pictures Engineering Group

b) Motion Picture Engineers Group
c) Motion Picture Experts Group
d) None of the mentioned
Answer: c
Explanation: None.

2. What is MPEG compression?

a) stores the compression values of each frame

b) stores the differences between successive frames
c) stores multiple frames’ values together
d) none of the mentioned
Answer: b
Explanation: None.

3. What are the levels in QoS?

a) Best effort service

b) Soft QoS
c) Hard QoS
d) All of the mentioned
Answer: d
Explanation: None.

4. The level that treats different types of traffics in different ways, giving certain traffic streams higher priority than
other streams and with best efforts, but no guarantees are made ___________

a) Best effort service

b) Soft QoS
c) Worst effort service
d) Hard QoS
Answer: b
Explanation: None.

5. The quality of service requirements are guaranteed in ___________

a) Best effort service

b) Soft QoS
c) Worst effort service
d) Hard QoS
Answer: d
Explanation: None.

6. What are the factors that define QoS?

a) Throughput
b) Jitter
c) Delay
d) All of the mentioned
Answer: d
Explanation: None.

7. Delay and Jitter ___________

a) mean the same thing

b) are two completely different things
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.

8. What is the Delay?

a) the time from when a request is first submitted to when the desired result is produced
b) the delay that occurs during playback of the stream
c) how the errors are handled during the transmission and processing of continuous media
d) none of the mentioned
Answer: a
Explanation: None.

9. What is Admission control?

a) the delay that occurs during playback of the stream

b) the practice of admitting a request for service only if the server has sufficient resources to satisfy the request
c) how the errors are handled during the transmission and processing of continuous media
d) none of the mentioned
Answer: b
Explanation: None.

10. An admission control scheme assigns a __________ to each type of resource.

a) processor
b) memory location
c) resource manager
d) all of the mentioned
Answer: c
Explanation: None.

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1. A scheduling algorithm can use either ___________ priority or ________ priority.

a) static, still
b) static, dynamic
c) live, dead
d) none of the mentioned
Answer: b
Explanation: None.

2. The priority of a process will ______________ if the scheduler assigns it a static priority.
a) change
b) remain unchanged
c) depends on the operating system
d) none of the mentioned
Answer: b
Explanation: None.

3. As disks have relatively low transfer rates and relatively high latency rates, disk schedulers must reduce latency ti
mes to ___________

a) ensure high bandwidth

b) ensure low bandwidth
c) make sure data is transferred
d) reduce data transfer speeds
Answer: a
Explanation: None.

4. Servicing requests strictly according to deadline using EDF may result in ___________

a) lower seek times

b) lower bandwidth
c) higher seek time
d) higher bandwidth
Answer: c
Explanation: None.

5. The hybrid algorithm that combines EDF with SCAN algorithm is known as ___________

a) EDS
b) SDF
c) SCAN-EDF
d) None of the mentioned
Answer: c
Explanation: None.

6. If several requests have different deadlines that are relatively close together, then using the SCAN – EDF algorith
m ___________

a) the SCAN ordering will service the requests in that batch

b) the EDF ordering will service the requests in that batch
c) the FCFS ordering will service the requests in that batch
d) none of the mentioned
Answer: a
Explanation: None.

7. Multimedia systems require _________ scheduling to ensure critical tasks will be serviced within timing deadline
s.

a) soft real time

b) hard real time
c) normal
d) none of the mentioned
Answer: b
Explanation: None.

8. The EDF scheduler uses ________ to order requests according to their deadlines.

a) stack
b) disks
c) queue
d) none of the mentioned
Answer: c
Explanation: None.

9. In SCAN – EDF, requests with the same deadlines are ordered according to ___________

a) SCAN policy
b) EDF policy
c) FCFS policy
d) FIFO policy
Answer: a
Explanation: None.

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1. The three general methods for delivering content from a server to a client across a network are ___________

a) unicasting
b) multicasting
c) broadcasting
d) all of the mentioned
Answer: d
Explanation: None.

2. Unicasting delivers the content to ___________

a) a single client
b) all clients, regardless whether they want the content or not
c) a group of receivers who indicate they wish to receive the content
d) none of the mentioned
Answer: a
Explanation: None.

3. Broadcasting delivers the content to ___________

a) a single client
b) all clients, regardless whether they want the content or not
c) a group of receivers who indicate they wish to receive the content
d) none of the mentioned
Answer: b
Explanation: None.

4. Multicasting delivers the content to ___________

a) a single client
b) all clients, regardless whether they want the content or not
c) a group of receivers who indicate they wish to receive the content
d) none of the mentioned
Answer: c
Explanation: None.

5. RTSP stands for ___________

a) Real Time Streaming Policy

b) Real Time Streaming Protocol
c) Real Time Systems Protocol
d) Read Time Streaming Policy
Answer: b
Explanation: None.

6. HTTP is __________

a) a stateful protocol
b) a stateless protocol
c) a protocol that maintains the status of its connection with the client
d) a stateless protocol that does not maintain the status of its connection with the client
Answer: d
Explanation: None.

7. RTSP includes which of the following states?

a) SETUP
b) PLAY
c) PAUSE
d) All of the mentioned
Answer: d
Explanation: None.

8. In the SETUP state ___________

a) the server is setup

b) the client is setup
c) the server allocates resources for the client session
d) the client sends requests to the server
Answer: c
Explanation: None.

9. In the TEARDOWN state ___________

a) the server breaks down the connection and releases the resources allocated for the session
b) the client breaks down the connection and releases the resources allocated for the session
c) the system crashes
d) none of the mentioned
Answer: a
Explanation: None.

10. RTP stands for ___________

a) real time protocol

b) real time transmission control protocol
c) real time transmission protocol
d) real time transport protocol
Answer: d
Explanation: None.

11. The problem with unicast delivery is that the ___________

a) memory allocation is difficult

b) server must establish a separate unicast session for each client
c) the routers must support unicasting
d) the clients must be close to the server
Answer: b
Explanation: None.

12. The difficulty with multicasting from a practical point of view is ___________

a) memory allocation is difficult

b) server must establish a separate unicast session for each client
c) the routers must support multicasting
d) none of the mentioned
Answer: c
Explanation: None.

13. To let a client have random access to a media stream with ___________

a) the protocol used must not be stateless

b) the server must support download
c) the stream should give access rights to the client
d) all of the mentioned
Answer: a
Explanation: None.

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1. Which of the following are forms of malicious attack?

a) Theft of information
b) Modification of data
c) Wiping of information
d) All of the mentioned
Answer: d
Explanation: None.

2. What are the common security threats?

a) File Shredding
b) File sharing and permission
c) File corrupting
d) File integrity
Answer: b
Explanation: Sharing and associated permissions are usual exploits which can compromise the system.

3. From the following, which is not a common file permission?

a) Write
b) Execute
c) Stop
d) Read
Answer: c
Explanation: None.

4. Which of the following is a good practice?

a) Give full permission for remote transferring

b) Grant read only permission
c) Grant limited permission to specified account
d) Give both read and write permission but not execute
Answer: c
Explanation: Limited access is a key method to circumvent unauthorized access and exploits.

5. What is not a good practice for user administration?

a) Isolating a system after a compromise

b) Perform random auditing procedures
c) Granting privileges on a per host basis
d) Using telnet and FTP for remote access
Answer: d
Explanation: Telnet and FTP are not encrypted and can be compromised.

6. Which of the following is the least secure method of authentication?

a) Key card
b) fingerprint
c) retina pattern
d) Password
Answer: d
Explanation: Passwords can be compromised more easily than to replicate a physical thing like key card, fingerprint
or retina.

7. Which of the following is a strong password?

a) 19thAugust88
b) Delhi88
c) P@assw0rd
d) !augustdelhi
Answer: c
Explanation: It has a combination of Alphabet both capital and small along with number and special character. Thus
always use complex password with a combination of all these.

8. Why is one time password safe?

a) It is easy to generated
b) It cannot be shared
c) It is different for every access
d) It is a complex encrypted password
Answer: c
Explanation: One time password is safe since it is generated per access and thus cannot be brute forced or deduced.
9. What does Light Directory Access Protocol (LDAP) doesn’t store?

a) Users
b) Address
c) Passwords
d) Security Keys
Answer: b
Explanation: None.

10. What is characteristic of RADIUS system?

a) It is essential for centralized encryption and authentication

b) It works on Network layer to deny access to unauthorized people
c) It provides centralized authentication mechanism via network devices
d) It’s a strong File access system
Answer: c
Explanation: None.

11. Which happens first authorization or authentication?

a) Authorization
b) Authentication
c) Authorization & Authentication are same
d) None of the mentioned
Answer: a
Explanation: None.

12. What are the characteristics of Authorization?

a) RADIUS and RSA

b) 3 way handshaking with syn and fin
c) Multilayered protection for securing resources
d) Deals with privileges and rights
Answer: d
Explanation: None.

13. What forces the user to change password at first login?

a) Default behavior of OS
b) Part of AES encryption practice
c) Devices being accessed forces the user
d) Account administrator
Answer: d
Explanation: Its administrator’s job to ensure that password of the user remains private and is known only to user. B
ut while making a new user account he assigns a random general password to give it to user. Thus even administrato
r cannot access a particular users account.

14. What is not a best practice for password policy?

a) Deciding maximum age of password

b) Restriction on password reuse and history
c) Password encryption
d) Having change password every 2 years
Answer: d
Explanation: Old passwords are more vulnerable to being misplaced or compromised. Passwords should be changed
periodically to enhance security.

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1. What is the breach of integrity?

a) This type of violation involves unauthorized reading of data

b) This violation involves unauthorized modification of data
c) This violation involves unauthorized destruction of data
d) This violation involves unauthorized use of resources
Answer: b
Explanation: None.

2. What is breach of confidentiality?

a) This type of violation involves unauthorized reading of data

b) This violation involves unauthorized modification of data
c) This violation involves unauthorized destruction of data
d) This violation involves unauthorized use of resources
Answer: a
Explanation: None.

3. What is theft of service?

a) This type of violation involves unauthorized reading of data

b) This violation involves unauthorized modification of data
c) This violation involves unauthorized destruction of data
d) This violation involves unauthorized use of resources
Answer: d
Explanation: None.

4. What is breach of availability?

a) This type of violation involves unauthorized reading of data

b) This violation involves unauthorized modification of data
c) This violation involves unauthorized destruction of data
d) This violation involves unauthorized use of resources
Answer: c
Explanation: None.

5. What is Trojan horse?

a) It is a useful way to encrypt password

b) It is a user which steals valuable information
c) It is a rogue program which tricks users
d) It’s a brute force attack algorithm
Answer: c
Explanation: None.

6. What is trap door?

a) IT is trap door in WarGames
b) It is a hole in software left by designer
c) It is a Trojan horse
d) It is a virus which traps and locks user terminal
Answer: b
Explanation: None.

7. Which mechanism is used by worm process?

a) Trap door
b) Fake process
c) Spawn Process
d) VAX process
Answer: c
Explanation: None.

8. Which of the following is not a characteristic of a virus?

a) Virus destroy and modify user data

b) Virus is a standalone program
c) Virus is a code embedded in a legitimate program
d) Virus cannot be detected
Answer: d
Explanation: Virus can be detected by having an antivirus program.

9. What is known as masquerading?

a) When one participant in communication pretends to be someone else

b) When attacker modifies data in communication
c) When attack is of fraudulent repeat of a valid data
d) When attack gains access to remote systems
Answer: a
Explanation: None.

10. Who unleashed famous worm attack in 1988 which effected UNIX systems and caused losses in millions?

a) Robert Morris
b) Bob Milano
c) Mark zuckerberg
d) Bill Gates
Answer: a
Explanation: None.

11. What is port scanning?

a) It is a software used to scan system for attack

b) It is a software application designed to probe a server or host for open ports
c) It is software used to scan system for introducing attacks by brute force
d) None of the mentioned
Answer: b
Explanation: None.

12. Which is not a port scan type?

a) TCP scanning
b) SYN scanning
c) UDP scanning
d) SYSTEM Scanning
Answer: d
Explanation: None.

13. Which is not a valid port scan type?

a) ACK scanning
b) Window scanning
c) IGMP scan
d) FIN scanning
Answer: c
Explanation: None.

14. What are zombie systems?

a) Are specific system which are designed to attack by manufacturer

b) They are network of known hacking group
c) These systems are previously compromised independent systems
d) None of the mentioned
Answer: c
Explanation: None.

15. What is known as a DOS attack?

a) It is attacked to block traffic of network

b) It is attacked to harm contents stored in HDD by worm spawn processes
c) It is an attempt to make a machine or network resource unavailable
d) None of the mentioned
Answer: c
Explanation: None.

16. With regard to DOS attack what is not true from below options?

a) We can stop DOS attack completely

b) By upgrading OS vulnerability we can stop DOS attack to some extent
c) DOS attack has to be stopped at network level
d) Such attack can last for hours
Answer: a
Explanation: None.

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1. What is not an important part of security protection?

a) Large amount of RAM to support antivirus

b) Strong passwords
c) Audit log periodically
d) Scan for unauthorized programs in system directories
Answer: a
Explanation: RAM has no effect on security of a system. System’s protection remains unchanged in increasing or de
creasing amount of RAM.

2. What is used to protect network from outside internet access?

a) A trusted antivirus
b) 24 hours scanning for virus
c) Firewall to separate trusted and untrusted network
d) Deny users access to websites which can potentially cause security leak
Answer: c
Explanation: Firewall create a protective barrier to secure internal network. An antivirus can only detect harmful vir
uses but cannot stop illegal access by remote attacker.

3. What is the best practice in the firewall domain environment?

a) Create two domain trusted and untrusted domain

b) Create strong policy in firewall to support different types of users
c) Create a Demilitarized zone
d) Create two DMZ zones with one untrusted domain
Answer: c
Explanation: All live servers or workstations are kept in a separate zone than inside and outside to enhance protectio
n.

4. Which direction access cannot happen using DMZ zone by default?

a) Company computer to DMZ

b) Internet to DMZ
c) Internet to company computer
d) Company computer to internet
Answer: c
Explanation: Connection from internet is never allowed to directly access internal PCs but is routed through DMZ z
one to prevent attacks.

5. What are the two features of a tripwire file system?

a) It is a tool to monitor file systems

b) It is used to automatically take corrective action
c) It is used to secure UNIX system
d) None of the mentioned
Answer: a
Explanation: None.

6. How do viruses avoid basic pattern match of antivirus?

a) They are encrypted

b) They act with special permissions
c) They modify themselves
d) None of the mentioned
Answer: c
Explanation: None.

7. How does an antivirus of today identify viruses?

a) Previously known patterns

b) It can detect unknown patterns
c) It can take high priority to increase scanning speed
d) None of the mentioned
Answer: a
Explanation: None.

8. What is known as a sandbox?

a) It is a program which can be molded to do the desired task

b) It is a program that is controlled or emulated section of OS
c) It is a special mode of antivirus
d) None of the mentioned
Answer: b
Explanation: None.

9. What is are two safe computing practices?

a) Not to open software from unknown vendors

b) Open and execute programs in admin level/root
c) Open and execute programs in presence of antivirus
d) None of the mentioned
Answer: a
Explanation: Disgruntled employees have in past infected the master copies of software programs to do economic ha
rm to the company.

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1. What are the different ways to intrude?

a) Buffer overflows
b) Unexpected combinations and unhandled input
c) Race conditions
d) All of the mentioned
Answer: d
Explanation: None.

2. What are the major components of the intrusion detection system?

a) Analysis Engine
b) Event provider
c) Alert Database
d) All of the mentioned
Answer: d
Explanation: None.

3. What are the different ways to classify an IDS?

a) anomaly detection
b) signature based misuse
c) stack based
d) all of the mentioned
Answer: d
Explanation: None.
4. What are the different ways to classify an IDS?

a) Zone based
b) Host & Network based
c) Network & Zone based
d) Level based
Answer: b
Explanation: None.

5. What are the characteristics of anomaly based IDS?

a) It models the normal usage of network as a noise characterization

b) It doesn’t detect novel attacks
c) Anything distinct from the noise is not assumed to be intrusion activity
d) It detects based on signature
Answer: a
Explanation: None.

6. What is the major drawback of anomaly detection IDS?

a) These are very slow at detection

b) It generates many false alarms
c) It doesn’t detect novel attacks
d) None of the mentioned
Answer: b
Explanation: None.

7. What are the characteristics of signature based IDS?

a) Most are based on simple pattern matching algorithms

b) It is programmed to interpret a certain series of packets
c) It models the normal usage of network as a noise characterization
d) Anything distinct from the noise is assumed to be intrusion activity
Answer: a
Explanation: None.

8. What are the drawbacks of signature based IDS?

a) They are unable to detect novel attacks

b) They suffer from false alarms
c) They have to be programmed again for every new pattern to be detected
d) All of the mentioned
Answer: d
Explanation: None.

9. What are the characteristics of Host based IDS?

a) The host operating system logs in the audit information

b) Logs includes logins,file opens and program executions
c) Logs are analysed to detect tails of intrusion
d) All of the mentioned
Answer: d
Explanation: None.
10. What are the drawbacks of the host based IDS?

a) Unselective logging of messages may increase the audit burdens

b) Selective logging runs the risk of missed attacks
c) They are very fast to detect
d) They have to be programmed for new patterns
Answer: a
Explanation: None.

11. What are the strengths of the host based IDS?

a) Attack verification
b) System specific activity
c) No additional hardware required
d) All of the mentioned
Answer: d
Explanation: None.

12. What are characteristics of stack based IDS?

a) They are integrated closely with the TCP/IP stack and watch packets
b) The host operating system logs in the audit information
c) It is programmed to interpret a certain series of packets
d) It models the normal usage of network as a noise characterization
Answer: a
Explanation: None.

13. What are characteristics of Network based IDS?

a) They look for attack signatures in network traffic

b) Filter decides which traffic will not be discarded or passed
c) It is programmed to interpret a certain series of packet
d) It models the normal usage of network as a noise characterization
Answer: a
Explanation: None.

14. What are strengths of Network based IDS?

a) Cost of ownership reduced

b) Malicious intent detection
c) Real time detection and response
d) All of the mentioned
Answer: d
Explanation: None.

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1. What is the preferred way of encryption?

a) pre shared secret key

b) using key distribution center (KD
c)
c) public key-encryption
d) symmetric key
Answer: c
Explanation: Pre Shared key can be compromised and either party can be suspected. Likewise KDC or symmetric ke
y can have breach which are undesirable. Public and private key encryption is a known industry standard.

2. What is not a role of encryption?

a) It is used to protect data from unauthorized access during transmission

b) It is used to ensure user authentication
c) It is used to ensure data integrity
d) It is used to ensure data corruption doesn’t happens
Answer: d
Explanation: Encryption doesn’t have error correction or detection facility thus cannot be used to safeguard from dat
a corruption.

3. What is cipher-block chaining?

a) Data is logically ‘ANDed’ with previous block

b) Data is logically ‘ORed’ with previous block
c) Data is logically ‘XORed’ with previous block
d) None of the mentioned
Answer: c
Explanation: None.

4. What is not an encryption standard?

a) AES
b) TES
c) Triple DES
d) DES
Answer: b
Explanation: None.

5. Which of the following is not a stream cipher?

a) Two fish
b) RC5
c) RC4
d) TBONE
Answer: d
Explanation: None.

6. What is a Hash Function?

a) It creates a small flexible block of data

b) It creates a small,fixed block of data
c) It creates a encrypted block of data
d) None of the mentioned
Answer: b
Explanation: None.

7. MD5 produces __________ bits hash data.

a) 128
b) 150
c) 160
d) 112
Answer: a
Explanation: None.

8. SHA-1 produces __________ bit of hash.

a) 128
b) 160
c) 150
d) 112
Answer: b
Explanation: None.

9. Which two of the following are authentication algorithms?

a) MAC
b) AES
c) DAS
d) Digital-signature
Answer: a
Explanation: None.

10. What is the role of Key Distribution Center?

a) It is used to distribute keys to everyone in world

b) It intended to reduce the risks inherent in exchanging keys
c) All of the mentioned
d) None of the mentioned
Answer: b
Explanation: None.

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1. A thread is also called ___________

a) Light Weight Process(LWP)

b) Heavy Weight Process(HWP)
c) Process
d) None of the mentioned
Answer: a
Explanation: None.

2. A thread shares its resources(like data section, code section, open files, signals) with ___________

a) other process similar to the one that the thread belongs to

b) other threads that belong to similar processes
c) other threads that belong to the same process
d) all of the mentioned
Answer: c
Explanation: None.
3. A heavy weight process ___________

a) has multiple threads of execution

b) has a single thread of execution
c) can have multiple or a single thread for execution
d) none of the mentioned
Answer: b
Explanation: None.

4. A process having multiple threads of control implies ___________

a) it can do more than one task at a time

b) it can do only one task at a time, but much faster
c) it has to use only one thread per process
d) none of the mentioned
Answer: a
Explanation: None.

5. Multithreading an interactive program will increase responsiveness to the user by ___________

a) continuing to run even if a part of it is blocked

b) waiting for one part to finish before the other begins
c) asking the user to decide the order of multithreading
d) none of the mentioned
Answer: a
Explanation: None.

6. Resource sharing helps ___________

a) share the memory and resources of the process to which the threads belong
b) an application have several different threads of activity all within the same address space
c) reduce the address space that a process could potentially use
d) all of the mentioned
Answer: d
Explanation: None.

7. Multithreading on a multi – CPU machine ___________

a) decreases concurrency
b) increases concurrency
c) doesn’t affect the concurrency
d) can increase or decrease the concurrency
Answer: b
Explanation: None.

8. The kernel is _______ of user threads.

a) a part of
b) the creator of
c) unaware of
d) aware of
Answer: c
Explanation: None.
9. If the kernel is single threaded, then any user level thread performing a blocking system call will ___________

a) cause the entire process to run along with the other threads
b) cause the thread to block with the other threads running
c) cause the entire process to block even if the other threads are available to run
d) none of the mentioned
Answer: c
Explanation: None.

10. Because the kernel thread management is done by the Operating System itself ___________

a) kernel threads are faster to create than user threads

b) kernel threads are slower to create than user threads
c) kernel threads are easier to manage as well as create then user threads
d) none of the mentioned
Answer: b
Explanation: None.

11. If a kernel thread performs a blocking system call, ____________

a) the kernel can schedule another thread in the application for execution
b) the kernel cannot schedule another thread in the same application for execution
c) the kernel must schedule another thread of a different application for execution
d) the kernel must schedule another thread of the same application on a different processor
Answer: a
Explanation: None.

12. Which of the following is FALSE?

a) Context switch time is longer for kernel level threads than for user level threads
b) User level threads do not need any hardware support
c) Related kernel level threads can be scheduled on different processors in a multiprocessor system
d) Blocking one kernel level thread blocks all other related threads
Answer: d
Explanation: None.

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1. The model in which one kernel thread is mapped to many user-level threads is called ___________

a) Many to One model

b) One to Many model
c) Many to Many model
d) One to One model
Answer: a
Explanation: None.

2. The model in which one user-level thread is mapped to many kernel level threads is called ___________

a) Many to One model

b) One to Many model
c) Many to Many model
d) One to One model
Answer: b
Explanation: None.

3. In the Many to One model, if a thread makes a blocking system call ___________

a) the entire process will be blocked

b) a part of the process will stay blocked, with the rest running
c) the entire process will run
d) none of the mentioned
Answer: a
Explanation: None.

4. In the Many to One model, multiple threads are unable to run in parallel on multiprocessors because of ________
___

a) only one thread can access the kernel at a time

b) many user threads have access to just one kernel thread
c) there is only one kernel thread
d) none of the mentioned
Answer: a
Explanation: None.

5. The One to One model allows ___________

a) increased concurrency
b) decreased concurrency
c) increased or decreased concurrency
d) concurrency equivalent to other models
Answer: a
Explanation: None.

6. In the One to One model when a thread makes a blocking system call ___________

a) other threads are strictly prohibited from running

b) other threads are allowed to run
c) other threads only from other processes are allowed to run
d) none of the mentioned
Answer: b
Explanation: None.

7. Which of the following is the drawback of the One to One Model?

a) increased concurrency provided by this model

b) decreased concurrency provided by this model
c) creating so many threads at once can crash the system
d) creating a user thread requires creating the corresponding kernel thread
Answer: d
Explanation: None.

8. When is the Many to One model at an advantage?

a) When the program does not need multithreading

b) When the program has to be multi-threaded
c) When there is a single processor
d) None of the mentioned
Answer: a
Explanation: None.

9. In the Many to Many model true concurrency cannot be gained because ___________

a) the kernel can schedule only one thread at a time

b) there are too many threads to handle
c) it is hard to map threads with each other
d) none of the mentioned
Answer: a
Explanation: None.

10. In the Many to Many models when a thread performs a blocking system call ___________

a) other threads are strictly prohibited from running

b) other threads are allowed to run
c) other threads only from other processes are allowed to run
d) none of the mentioned
Answer: b
Explanation: None.

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1. Signals that occur at the same time, are presented to the process ____________

a) one at a time, in a particular order

b) one at a time, in no particular order
c) all at a time
d) none of the mentioned
Answer: b
Explanation: None.

2. Which of the following is not TRUE?

a) Processes may send each other signals

b) Kernel may send signals internally
c) A field is updated in the signal table when the signal is sent
d) Each signal is maintained by a single bit
Answer: c
Explanation: A field is updated in the process table when the signal is sent.

1. Virtual memory allows ____________

a) execution of a process that may not be completely in memory

b) a program to be smaller than the physical memory
c) a program to be larger than the secondary storage
d) execution of a process without being in physical memory
Answer: a
Explanation: None.
2. The instruction being executed, must be in ____________

a) physical memory
b) logical memory
c) physical & logical memory
d) none of the mentioned
Answer: a
Explanation: None.

3. Error handler codes, to handle unusual errors are ____________

a) almost never executed

b) executed very often
c) executed periodically
d) none of the mentioned
Answer: a
Explanation: None.

4. The ability to execute a program that is only partially in memory has benefits like ____________

a) The amount of physical memory cannot put a constraint on the program

b) Programs for an extremely large virtual space can be created
c) Throughput increases
d) All of the mentioned
Answer: d
Explanation: None.

5. In virtual memory. the programmer __________ of overlays.

a) has to take care

b) does not have to take care
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.

6. Virtual memory is normally implemented by ________

a) demand paging
b) buses
c) virtualization
d) all of the mentioned
Answer: a
Explanation: None.

7. Segment replacement algorithms are more complex than page replacement algorithms because ____________

a) Segments are better than pages

b) Pages are better than segments
c) Segments have variable sizes
d) Segments have fixed sizes
Answer: c
Explanation: None.
8. A swapper manipulates ___________ whereas the pager is concerned with individual _______ of a process.

a) the entire process, parts

b) all the pages of a process, segments
c) the entire process, pages
d) none of the mentioned
Answer: c
Explanation: None.

9. Using a pager ____________

a) increases the swap time

b) decreases the swap time
c) decreases the swap time & amount of physical memory needed
d) increases the amount of physical memory needed
Answer: c
Explanation: None.

10. The valid – invalid bit, in this case, when valid indicates?

a) the page is not legal

b) the page is illegal
c) the page is in memory
d) the page is not in memory
Answer: c
Explanation: None.

11. A page fault occurs when?

a) a page gives inconsistent data

b) a page cannot be accessed due to its absence from memory
c) a page is invisible
d) all of the mentioned
Answer: b
Explanation: None.

12. When a page fault occurs, the state of the interrupted process is ____________

a) disrupted
b) invalid
c) saved
d) none of the mentioned
Answer: c
Explanation: None.

13. When a process begins execution with no pages in memory?

a) process execution becomes impossible

b) a page fault occurs for every page brought into memory
c) process causes system crash
d) none of the mentioned
Answer: b
Explanation: None.
14. If the memory access time is denoted by ‘ma’ and ‘p’ is the probability of a page fault (0 <= p <= 1). Then the ef
fective access time for a demand paged memory is ____________

a) p x ma + (1-p) x page fault time

b) ma + page fault time
c) (1-p) x ma + p x page fault time
d) none of the mentioned
Answer: c
Explanation: None.

15. When the page fault rate is low ____________

a) the turnaround time increases

b) the effective access time increases
c) the effective access time decreases
d) turnaround time & effective access time increases
Answer: c
Explanation: None.

16. Locality of reference implies that the page reference being made by a process ____________

a) will always be to the page used in the previous page reference

b) is likely to be one of the pages used in the last few page references
c) will always be one of the pages existing in memory
d) will always lead to page faults
Answer: b
Explanation: None.

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1. Which of the following page replacement algorithms suffers from Belady’s Anomaly?

a) Optimal replacement
b) LRU
c) FIFO
d) Both optimal replacement and FIFO
Answer: c
Explanation: None.

2. A process refers to 5 pages, A, B, C, D, E in the order : A, B, C, D, A, B, E, A, B, C, D, E. If the page replacemen

t algorithm is FIFO, the number of page transfers with an empty internal store of 3 frames is?

a) 8
b) 10
c) 9
d) 7
Answer: c
Explanation: None.

3. In question 2, if the number of page frames is increased to 4, then the number of page transfers ____________

a) decreases
b) increases
c) remains the same
d) none of the mentioned
Answer: b
Explanation: None.

4. A memory page containing a heavily used variable that was initialized very early and is in constant use is remove
d, then the page replacement algorithm used is ____________

a) LRU
b) LFU
c) FIFO
d) None of the mentioned
Answer: c
Explanation: None.

5. A virtual memory system uses First In First Out (FIFO) page replacement policy and allocates a fixed number of f
rames to a process. Consider the following statements.

a) Both P and Q are true, and Q is the reason for P

b) Both P and Q are true, but Q is not the reason for P
c) P is false but Q is true
d) Both P and Q are false
Answer: c
Explanation: None.

6. Users _______ that their processes are running on a paged system.

a) are aware
b) are unaware
c) may unaware
d) none of the mentioned
Answer: b
Explanation: None.

7. If no frames are free, _____ page transfer(s) is/are required.

a) one
b) two
c) three
d) four
Answer: b
Explanation: None.

8. When a page is selected for replacement, and its modify bit is set ____________

a) the page is clean

b) the page has been modified since it was read in from the disk
c) the page is dirty
d) the page has been modified since it was read in from the disk & page is dirty
Answer: d
Explanation: None.

9. The aim of creating page replacement algorithms is to ____________

a) replace pages faster
b) increase the page fault rate
c) decrease the page fault rate
d) to allocate multiple pages to processes
Answer: c
Explanation: None.

10. A FIFO replacement algorithm associates with each page the _______

a) time it was brought into memory

b) size of the page in memory
c) page after and before it
d) all of the mentioned
Answer: a
Explanation: None.

11. What is the Optimal page – replacement algorithm?

a) Replace the page that has not been used for a long time
b) Replace the page that has been used for a long time
c) Replace the page that will not be used for a long time
d) None of the mentioned
Answer: c
Explanation: None.

12. Optimal page – replacement algorithm is difficult to implement, because ____________

a) it requires a lot of information

b) it requires future knowledge of the reference string
c) it is too complex
d) it is extremely expensive
Answer: b
Explanation: None.

13. LRU page – replacement algorithm associates with each page the ______

a) time it was brought into memory

b) the time of that page’s last use
c) page after and before it
d) all of the mentioned
Answer: b
Explanation: None.

14. For 3 page frames, the following is the reference string:

a) 10
b) 15
c) 11
d) 12
Answer: d
Explanation: None.

15. What are the two methods of the LRU page replacement policy that can be implemented in hardware?
a) Counters
b) RAM & Registers
c) Stack & Counters
d) Registers
Answer: c
Explanation: None.

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1. When using counters to implement LRU, we replace the page with the ____________

a) smallest time value

b) largest time value
c) greatest size
d) none of the mentioned
Answer: a
Explanation: Whenever a reference to a page is made, the contents of the clock register are copied into the time-of-u
se field in the page-table entry for that page. In this way, we always have the time of the last reference to each page.

2. In the stack implementation of the LRU algorithm, a stack can be maintained in a manner ____________

a) whenever a page is used, it is removed from the stack and put on bottom
b) the bottom of the stack is the LRU page
c) the top of the stack contains the LRU page and all new pages are added to the top
d) none of the mentioned
Answer: b
Explanation: None.

3. There is a set of page replacement algorithms that can never exhibit Belady’s Anomaly, called ____________

a) queue algorithms
b) stack algorithms
c) string algorithms
d) none of the mentioned
Answer: b
Explanation: None.

4. Applying the LRU page replacement to the following reference string.

a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: None.

5. Increasing the RAM of a computer typically improves performance because ____________

a) Virtual memory increases

b) Larger RAMs are faster
c) Fewer page faults occur
d) None of the mentioned
Answer: c
Explanation: None.

6. The essential content(s) in each entry of a page table is/are ____________

a) Virtual page number

b) Page frame number
c) Both virtual page number and page frame number
d) Access right information
Answer: b
Explanation: None.

7. The minimum number of page frames that must be allocated to a running process in a virtual memory environmen
t is determined by ____________

a) the instruction set architecture

b) page size
c) physical memory size
d) number of processes in memory
Answer: a
Explanation: None.

8. What is the reason for using the LFU page replacement algorithm?

a) an actively used page should have a large reference count

b) a less used page has more chances to be used again
c) it is extremely efficient and optimal
d) all of the mentioned
Answer: a
Explanation: None.

9. What is the reason for using the MFU page replacement algorithm?

a) an actively used page should have a large reference count

b) a less used page has more chances to be used again
c) it is extremely efficient and optimal
d) all of the mentioned
Answer: b
Explanation: None.

10. The implementation of the LFU and the MFU algorithm is very uncommon because ____________

a) they are too complicated

b) they are optimal
c) they are expensive
d) all of the mentioned
Answer: c
Explanation: None.

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1. The minimum number of frames to be allocated to a process is decided by the ____________

a) the amount of available physical memory
b) operating System
c) instruction set architecture
d) none of the mentioned
Answer: c
Explanation: None.

2. When a page fault occurs before an executing instruction is complete if ____________

a) the instruction must be restarted

b) the instruction must be ignored
c) the instruction must be completed ignoring the page fault
d) none of the mentioned
Answer: a
Explanation: None.

3. Consider a machine in which all memory reference instructions have only one memory address, for them we need
at least _____ frame(s).

a) one
b) two
c) three
d) none of the mentioned
Answer: b
Explanation: At least one frame for the instruction and one for the memory reference.

4. The maximum number of frames per process is defined by ____________

a) the amount of available physical memory

b) operating System
c) instruction set architecture
d) none of the mentioned
Answer: a
Explanation: None.

5. The algorithm in which we split m frames among n processes, to give everyone an equal share, m/n frames is kno
wn as ____________

a) proportional allocation algorithm

b) equal allocation algorithm
c) split allocation algorithm
d) none of the mentioned
Answer: b
Explanation: None.

6. The algorithm in which we allocate memory to each process according to its size is known as ____________

a) proportional allocation algorithm

b) equal allocation algorithm
c) split allocation algorithm
d) none of the mentioned
Answer: a
Explanation: None.
7. With either equal or proportional algorithm, a high priority process is treated ___________ a low priority process.

a) greater than
b) same as
c) lesser than
d) none of the mentioned
Answer: b
Explanation: None.

8. _________ replacement allows a process to select a replacement frame from the set of all frames, even if the fram
e is currently allocated to some other process.

a) Local
b) Universal
c) Global
d) Public
Answer: c
Explanation: None.

9. _________ replacement allows each process to only select from its own set of allocated frames.

a) Local
b) Universal
c) Global
d) Public
Answer: a
Explanation: None.

10. One problem with the global replacement algorithm is that ____________

a) it is very expensive
b) many frames can be allocated to a process
c) only a few frames can be allocated to a process
d) a process cannot control its own page – fault rate
Answer: d
Explanation: None.

11. ________ replacement generally results in greater system throughput.

a) Local
b) Global
c) Universal
d) Public
Answer: b
Explanation: None.

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1. A process is thrashing if ____________

a) it spends a lot of time executing, rather than paging

b) it spends a lot of time paging than executing
c) it has no memory allocated to it
d) none of the mentioned
Answer: b
Explanation: None.

2. Thrashing _______ the CPU utilization.

a) increases
b) keeps constant
c) decreases
d) none of the mentioned
Answer: c
Explanation: None.

3. What is a locality?

a) a set of pages that are actively used together

b) a space in memory
c) an area near a set of processes
d) none of the mentioned
Answer: a
Explanation: None.

4. When a subroutine is called ____________

a) it defines a new locality

b) it is in the same locality from where it was called
c) it does not define a new locality
d) none of the mentioned
Answer: a
Explanation: None.

5. A program is generally composed of several different localities, which _____ overlap.

a) may
b) must
c) do not
d) must not
Answer: a
Explanation: None.

6. In the working set model, for:

a) {1, 2, 4, 5, 6}
b) {2, 1, 6, 7, 3}
c) {1, 6, 5, 7, 2}
d) {1, 2, 3, 4, 5}
Answer: c
Explanation: None.

7. The accuracy of the working set depends on the selection of ____________

a) working set model

b) working set size
c) memory size
d) number of pages in memory
Answer: b
Explanation: None.

8. If working set window is too small ____________

a) it will not encompass entire locality

b) it may overlap several localities
c) it will cause memory problems
d) none of the mentioned
Answer: a
Explanation: None.

9. If working set window is too large ____________

a) it will not encompass entire locality

b) it may overlap several localities
c) it will cause memory problems
d) none of the mentioned
Answer: b
Explanation: None.

10. If the sum of the working – set sizes increases, exceeding the total number of available frames ____________

a) then the process crashes

b) the memory overflows
c) the system crashes
d) the operating system selects a process to suspend
Answer: d
Explanation: None.

11. Consider the following page reference string.

a) 10
b) 14
c) 8
d) 11
Answer: a
Explanation: None.

12. Consider the following page reference string.

a) 10
b) 14
c) 8
d) 11
Answer: c
Explanation: None.

13. Consider the following page reference string.

a) 16
b) 15
c) 14
d) 11
Answer: a
Explanation: None.

14. Consider the following page reference string.

a) 16
b) 15
c) 14
d) 11
Answer: c
Explanation: None.

15. Consider the following page reference string.

a) 16
b) 15
c) 14
d) 11
Answer: d
Explanation: None.

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1. Data cannot be written to secondary storage unless written within a ______

a) file
b) swap space
c) directory
d) text format
Answer: a
Explanation: None.

2. File attributes consist of ____________

a) name
b) type
c) identifier
d) all of the mentioned
Answer: d
Explanation: None.

3. The information about all files is kept in ____________

a) swap space
b) operating system
c) seperate directory structure
d) none of the mentioned
Answer: c
Explanation: None.

4. A file is a/an _______ data type.

a) abstract
b) primitive
c) public
d) private
Answer: a
Explanation: None.

5. The operating system keeps a small table containing information about all open files called ____________

a) system table
b) open-file table
c) file table
d) directory table
Answer: b
Explanation: None.

6. In UNIX, what will the open system call return?

a) pointer to the entry in the open file table

b) pointer to the entry in the system wide table
c) a file to the process calling it
d) none of the mentioned
Answer: a
Explanation: None.

7. System wide table in UNIX contains process independent information such as ____________

a) location of file on disk

b) access dates
c) file size
d) all of the mentioned
Answer: d
Explanation: None.

8. The open file table has a/an _______ associated with each file.

a) file content
b) file permission
c) open count
d) close count
Answer: c
Explanation: open count indicates the number of processes that have the file open.

9. Which of the following are the two parts of the file name?

a) name & identifier

b) identifier & type
c) extension & name
d) type & extension
Answer: c
Explanation: None.
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1. The UNIX sytem uses a/an ________ stored at the beginning of a some files to indicate roughly the type of file.

a) identifier
b) extension
c) virtual number
d) magic number
Answer: d
Explanation: None.

2. The larger the block size, the ______ the internal fragmentation.

a) greater
b) lesser
c) same
d) none of the mentioned
Answer: a
Explanation: None.

3. In the sequential access method, information in the file is processed ____________

a) one disk after the other, record access doesnt matter

b) one record after the other
c) one text document after the other
d) none of the mentioned
Answer: b
Explanation: None.

4. Sequential access method ______ on random access devices.

a) works well
b) doesnt work well
c) maybe works well and doesnt work well
d) none of the mentioned
Answer: a
Explanation: None.

5. The direct access method is based on a ______ model of a file, as _____ allow random access to any file block.

a) magnetic tape, magnetic tapes

b) tape, tapes
c) disk, disks
d) all of the mentioned
Answer: c
Explanation: None.

6. For a direct access file ____________

a) there are restrictions on the order of reading and writing

b) there are no restrictions on the order of reading and writing
c) access is restricted permission wise
d) access is not restricted permission wise
Answer: b
Explanation: None.

7. A relative block number is an index relative to ____________

a) the beginning of the file

b) the end of the file
c) the last written position in file
d) none of the mentioned
Answer: a
Explanation: None.

8. The index contains ____________

a) names of all contents of file

b) pointers to each page
c) pointers to the various blocks
d) all of the mentioned
Answer: c
Explanation: None.

9. For large files, when the index itself becomes too large to be kept in memory?

a) index is called
b) an index is created for the index file
c) secondary index files are created
d) all of the mentioned
Answer: b
Explanation: None.

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1. To organise file systems on disk _______________

a) they are split into one or more partitions

b) information about files is added to each partition
c) they are made on different storage spaces
d) all of the mentioned
Answer: b
Explanation: None.

2. The directory can be viewed as a _________ that translates file names into their directory entries.

a) symbol table
b) partition
c) swap space
d) cache
Answer: a
Explanation: None.

3. What will happen in the single level directory?

a) All files are contained in different directories all at the same level
b) All files are contained in the same directory
c) Depends on the operating system
d) None of the mentioned
Answer: b
Explanation: None.

4. What will happen in the single level directory?

a) all directories must have unique names

b) all files must have unique names
c) all files must have unique owners
d) all of the mentioned
Answer: b
Explanation: None.

5. What will happen in the two level directory structure?

a) each user has his/her own user file directory

b) the system doesn’t its own master file directory
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: None.

6. When a user job starts in a two level directory system, or a user logs in _____________

a) the users user file directory is searched

b) the system’s master file directory is not searched
c) the master file directory is indexed by user name or account number, and each entry points to the UFD for that use
r
d) all of the mentioned
Answer: c
Explanation: None.

7. When a user refers to a particular file?

a) system MFD is searched

b) his own UFD is not searched
c) both MFD and UFD are searched
d) every directory is searched
Answer: c
Explanation: None.

8. What is the disadvantage of the two level directory structure?

a) it does not solve the name collision problem

b) it solves the name collision problem
c) it does not isolate users from one another
d) it isolates users from one another
Answer: d
Explanation: None.

9. In the tree structured directories _____________

a) the tree has the stem directory

b) the tree has the leaf directory
c) the tree has the root directory
d) all of the mentioned
Answer: c
Explanation: None.

10. The current directory contains, most of the files that are _____________

a) of current interest to the user

b) stored currently in the system
c) not used in the system
d) not of current interest to the system
Answer: a
Explanation: None.

11. Which of the following are the types of Path names?

a) absolute & relative

b) local & global
c) global & relative
d) relative & local
Answer: a
Explanation: None.

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1. An absolute path name begins at the _____________

a) leaf
b) stem
c) current directory
d) root
Answer: d
Explanation: None.

2. A relative path name begins at the _____________

a) leaf
b) stem
c) current directory
d) root
Answer: c
Explanation: None.

3. In a tree structure, when deleting a directory that is not empty?

a) The contents of the directory are safe

b) The contents of the directory are also deleted
c) contents of the directory are not deleted
d) none of the mentioned
Answer: b
Explanation: None.
4. When two users keep a subdirectory in their own directories, the structure being referred to is _____________

a) tree structure
b) cyclic graph directory structure
c) two level directory structure
d) acyclic graph directory
Answer: d
Explanation: None.

5. A tree structure ______ the sharing of files and directories.

a) allows
b) may restrict
c) restricts
d) none of the mentioned
Answer: c
Explanation: None.

6. With a shared file _____________

a) actual file exists

b) there are two copies of the file
c) the changes made by one person are not reflected to the other
d) the changes made by one person are reflected to the other
Answer: d
Explanation: None.

7. In UNIX, what is a link?

a) a directory entry
b) a pointer to another file or subdirectory
c) implemented as an absolute or relative path name
d) all of the mentioned
Answer: d
Explanation: None.

8. The operating system _______ the links when traversing directory trees, to preserve the acyclic structure of the sy
stem.

a) considers
b) ignores
c) deletes
d) none of the mentioned
Answer: b
Explanation: None.

9. The deletion of a link ________ the original file.

a) deletes
b) affects
c) does not affect
d) none of the mentioned
Answer: c
Explanation: None.
10. When keeping a list of all the links/references to a file, and the list is empty, implies that _____________

a) the file has no copies

b) the file is deleted
c) the file is hidden
d) none of the mentioned
Answer: b
Explanation: None.

11. When a cycle exists, the reference count maybe non zero, even when it is no longer possible to refer to a director
y or file, due to _______

a) the possibility of one hidden reference

b) the possibility of two hidden references
c) the possibility of self referencing
d) none of the mentioned
Answer: c
Explanation: None.

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1. What is the mount point?

a) an empty directory at which the mounted file system will be attached

b) a location where every time file systems are mounted
c) is the time when the mounting is done
d) none of the mentioned
Answer: a
Explanation: None.

2. When a file system is mounted over a directory that is not empty then _____________

a) the system may not allow the mount

b) the system must allow the mount
c) the system may allow the mount and the directory’s existing files will then be made obscure
d) all of the mentioned
Answer: c
Explanation: None.

3. In UNIX, exactly which operations can be executed by group members and other users is definable by _________
____

a) the group’s head

b) the file’s owner
c) the file’s permissions
d) all of the mentioned
Answer: b
Explanation: None.

4. A process _____ lower the priority of another process if both are owned by the same owner.

a) must
b) can
c) cannot
d) none of the mentioned
Answer: b
Explanation: None.

5. In distributed file system ________________ directories are visible from the local machine.

a) protected
b) local
c) private
d) remote
Answer: d
Explanation: None.

6. In the world wide web, a ____ is needed to gain access to the remote files, and separate operations are used to tran
sfer files.

a) laptop
b) plugin
c) browser
d) player
Answer: c
Explanation: None.

7. Anonymous access allows a user to transfer files _____________

a) without having an account on the remote system

b) only if he accesses the system with a guest account
c) only if he has an account on the remote system
d) none of the mentioned
Answer: a
Explanation: The world wide web uses anonymous file exchange almost exclusively.

8. The machine containing the files is the _______ and the machine wanting to access the files is the ______

a) master, slave
b) memory, user
c) server, client
d) none of the mentioned
Answer: c
Explanation: None.

9. Distributed naming services/Distributed information systems have been devised to _____________

a) provide information about all the systems

b) provide unified access to the information needed for remote computing
c) provide unique names to all systems in a network
d) all of the mentioned
Answer: b
Explanation: None.

10. Domain name system provides _____________

a) host-name-to-network-address translations for the entire internet
b) network-address-to-host-name translations for the entire internet
c) binary to hex translations for the entire internet
d) all of the mentioned
Answer: a
Explanation: None.

11. To recover from failures in the network operations _____________ information may be maintained.

a) ip address
b) state
c) stateless
d) operating system
Answer: b
Explanation: None.

12. The series of accesses between the open and close operations is a _____________

a) transaction
b) procedure
c) program
d) file session
Answer: d
Explanation: None.

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1. Reliability of files can be increased by _____________

a) keeping the files safely in the memory

b) making a different partition for the files
c) by keeping them in external storage
d) by keeping duplicate copies of the file
Answer: d
Explanation: None.

2. Protection is only provided at the _____ level.

a) lower
b) central
c) higher
d) none of the mentioned
Answer: a
Explanation: None.

3. What is the main problem with access control lists?

a) their maintenance
b) their length
c) their permissions
d) all of the mentioned
Answer: b
Explanation: None.
4. Many systems recognize three classifications of users in connection with each file (to condense the access control
list).

a) Owner
b) Group
c) Universe
d) All of the mentioned
Answer: d
Explanation: None.

5. All users in a group get _______ access to a file.

a) different
b) similar
c) same
d) none of the mentioned
Answer: b
Explanation: None.

6. Universe consists of _____________

a) all users that aren’t included in the group or owners

b) all users that are not owners
c) all users in the system
d) none of the mentioned
Answer: c
Explanation: None.

7. In UNIX, groups can be created and modified by?

a) superuser
b) any user
c) a programmer only
d) the people in the group only
Answer: a
Explanation: None.

8. To control access the three bits used in UNIX are represented by _____________

a) r
b) w
c) x
d) all of the mentioned
Answer: d
Explanation: None.

9. If each access to a file is controlled by a password, then what is the disadvantage?

a) user will need to remember a lot of passwords

b) it is not reliable
c) it is not efficient
d) all of the mentioned
Answer: a
Explanation: None.

10. What will happen in a multi level directory structure?

a) the same previous techniques will be used as in the other structures

b) a mechanism for directory protection will have to applied
c) the subdirectories do not need protection once the directory is protected
d) none of the mentioned
Answer: b
Explanation: None.

11. In UNIX, the directory protection is handled _________ to the file protection.

a) different
b) similar
c) it is not handled at all
d) none of the mentioned
Answer: b
Explanation: None.

12. Disks are segmented into one or more partitions, each containing a file system or ______

a) left ‘raw’
b) made into swap space
c) made into backup space
d) left ‘ripe’
Answer: a
Explanation: None.

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1. The three major methods of allocating disk space that are in wide use are _____________

a) contiguous
b) linked
c) indexed
d) all of the mentioned
Answer: d
Explanation: None.

2. In contiguous allocation _____________

a) each file must occupy a set of contiguous blocks on the disk

b) each file is a linked list of disk blocks
c) all the pointers to scattered blocks are placed together in one location
d) none of the mentioned
Answer: a
Explanation: None.

3. In linked allocation _____________

a) each file must occupy a set of contiguous blocks on the disk

b) each file is a linked list of disk blocks
c) all the pointers to scattered blocks are placed together in one location
d) none of the mentioned
Answer: b
Explanation: None.

4. In indexed allocation _____________

a) each file must occupy a set of contiguous blocks on the disk

b) each file is a linked list of disk blocks
c) all the pointers to scattered blocks are placed together in one location
d) none of the mentioned
Answer: c
Explanation: None.

5. On systems where there are multiple operating system, the decision to load a particular one is done by _________
____

a) boot loader
b) bootstrap
c) process control block
d) file control block
Answer: a
Explanation: None.

6. The VFS (virtual file system) activates file system specific operations to handle local requests according to their _
______

a) size
b) commands
c) timings
d) file system types
Answer: d
Explanation: None.

7. What is the real disadvantage of a linear list of directory entries?

a) size of the linear list in memory

b) linear search to find a file
c) it is not reliable
d) all of the mentioned
Answer: b
Explanation: None.

8. Contiguous allocation of a file is defined by _____________

a) disk address of the first block & length

b) length & size of the block
c) size of the block
d) total size of the file
Answer: a
Explanation: None.

9. One difficulty of contiguous allocation is _____________

a) finding space for a new file
b) inefficient
c) costly
d) time taking
Answer: a
Explanation: None.

10. _______ and ________ are the most common strategies used to select a free hole from the set of available holes.

a) First fit, Best fit

b) Worst fit, First fit
c) Best fit, Worst fit
d) None of the mentioned
Answer: a
Explanation: None.

11. The first fit and best fit algorithms suffer from _____________

a) internal fragmentation
b) external fragmentation
c) starvation
d) all of the mentioned
Answer: b
Explanation: None.

12. To solve the problem of external fragmentation ________ needs to be done periodically.

a) compaction
b) check
c) formatting
d) replacing memory
Answer: a
Explanation: None.

13. If too little space is allocated to a file _____________

a) the file will not work

b) there will not be any space for the data, as the FCB takes it all
c) the file cannot be extended
d) the file cannot be opened
Answer: c
Explanation: None.

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1. A device driver can be thought of like a translator. Its input consists of _____ commands and output consists of _
______ instructions.

a) high level, low level

b) low level, high level
c) complex, simple
d) low level, complex
Answer: a
Explanation: None.

2. The file organization module knows about _____________

a) files
b) logical blocks of files
c) physical blocks of files
d) all of the mentioned
Answer: d
Explanation: None.

3. Metadata includes _____________

a) all of the file system structure

b) contents of files
c) both file system structure and contents of files
d) none of the mentioned
Answer: c
Explanation: None.

4. For each file there exists a ___________ that contains information about the file, including ownership, permission
s and location of the file contents.

a) metadata
b) file control block
c) process control block
d) all of the mentioned
Answer: b
Explanation: None.

5. For processes to request access to file contents, they need _____________

a) to run a seperate program

b) special interrupts
c) to implement the open and close system calls
d) none of the mentioned
Answer: c
Explanation: None.

6. During compaction time, other normal system operations _______ be permitted.

a) can
b) cannot
c) is
d) none of the mentioned
Answer: b
Explanation: None.

7. When in contiguous allocation the space cannot be extended easily?

a) the contents of the file have to be copied to a new space, a larger hole
b) the file gets destroyed
c) the file will get formatted and lost all its data
d) none of the mentioned
Answer: a
Explanation: None.

8. In the linked allocation, the directory contains a pointer to which block?

a) I only
b) II only
c) Both I and II
d) Neither I nor II
Answer: c
Explanation: None.

9. There is no __________ with linked allocation.

a) internal fragmentation
b) external fragmentation
c) starvation
d) all of the mentioned
Answer: b
Explanation: None.

10. What is the major disadvantage with a linked allocation?

a) internal fragmentation
b) external fragmentation
c) there is no sequential access
d) there is only sequential access
Answer: d
Explanation: None.

11. What if a pointer is lost or damaged in a linked allocation?

a) the entire file could get damaged

b) only a part of the file would be affected
c) there would not be any problems
d) none of the mentioned
Answer: a
Explanation: None.

12. FAT stands for _____________

a) File Attribute Transport

b) File Allocation Table
c) Fork At Time
d) None of the mentioned
Answer: b
Explanation: None.

13. By using FAT, random access time is __________

a) the same
b) increased
c) decreased
d) not affected
Answer: c
Explanation: None.

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1. A better way of contiguous allocation to extend the file size is _____________

a) adding an extent (another chunk of contiguous space)

b) adding an index table to the first contiguous block
c) adding pointers into the first contiguous block
d) none of the mentioned
Answer: a
Explanation: None.

2. If the extents are too large, then what is the problem that comes in?

a) internal fragmentation
b) external fragmentation
c) starvation
d) all of the mentioned
Answer: a
Explanation: None.

3. The FAT is used much as a _________

a) stack
b) linked list
c) data
d) pointer
Answer: b
Explanation: None.

4. A section of disk at the beginning of each partition is set aside to contain the table in _____________

a) fat
b) linked allocation
c) hashed allocation
d) indexed allocation
Answer: a
Explanation: None.

5. Contiguous allocation has two problems _________ and _________ that linked allocation solves.

a) external – fragmentation & size – declaration

b) internal – fragmentation & external – fragmentation
c) size – declaration & internal – fragmentation
d) memory – allocation & size – declaration
Answer: a
Explanation: None.

6. Each _______ has its own index block.

a) partition
b) address
c) file
d) all of the mentioned
Answer: c
Explanation: None.

7. Indexed allocation _________ direct access.

a) supports
b) does not support
c) is not related to
d) none of the mentioned
Answer: a
Explanation: None.

8. The pointer overhead of indexed allocation is generally _________ the pointer overhead of linked allocation.

a) less than
b) equal to
c) greater than
d) keeps varying with
Answer: c
Explanation: None.

9. For any type of access, contiguous allocation requires ______ access to get a disk block.

a) only one
b) at least two
c) exactly two
d) none of the mentioned
Answer: a
Explanation: We can easily keep the initial address of the file in memory and calculate immediately the disk address
of the ith block and read it directly.

10. Consider a disk where blocks 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 17, 18, 25, 26 and 27 are free and the rest of the bloc
ks are allocated. Then the free space bitmap would be _____________

a) 10000110000001110011111100011111…
b) 110000110000001110011111100011111…
c) 01111001111110001100000011100000…
d) 001111001111110001100000011100000…
Answer: d
Explanation: None.

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1. _______ tend to represent a major bottleneck in system performance.

a) CPUs
b) Disks
c) Programs
d) I/O
Answer: b
Explanation: None.

2. In UNIX, even an ’empty’ disk has a percentage of its space lost to ______

a) programs
b) inodes
c) virtual memory
d) stacks
Answer: b
Explanation: None.

3. By preallocating the inodes and spreading them across the volume, we ___________ the system performance.

a) improve
b) decrease
c) maintain
d) do not affect
Answer: a
Explanation: None.

4. ____________ writes occur in the order in which the disk subsystem receives them, and the writes are not buffere
d.

a) Asynchronous
b) Regular
c) Synchronous
d) Irregular
Answer: c
Explanation: None.

5. In ___________ writes, the data is stored in the cache.

a) Asynchronous
b) Regular
c) Synchronous
d) Irregular
Answer: a
Explanation: None.

6. A file being read or written sequentially should not have its pages replaced in LRU order, because ____________
_

a) it is very costly
b) the most recently used page will be used last
c) it is not efficient
d) all of the mentioned
Answer: b
Explanation: None.

7. In the optimized technique for sequential access ___________ removes a page from the buffer as soon as the next
page is requested.

a) write ahead
b) read ahead
c) free-behind
d) add-front
Answer: c
Explanation: None.

8. With _______ a requested page and several subsequent pages are read and cached.

a) write ahead
b) read ahead
c) free-behind
d) add-front
Answer: b
Explanation: None.

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1. Some directory information is kept in main memory or cache to ___________

a) fill up the cache

b) increase free space in secondary storage
c) decrease free space in secondary storage
d) speed up access
Answer: d
Explanation: None.

2. A systems program such as fsck in ______ is a consistency checker.

a) UNIX
b) Windows
c) Macintosh
d) Solaris
Answer: a
Explanation: None.

3. A consistency checker __________________ and tries to fix any inconsistencies it finds.

a) compares the data in the secondary storage with the data in the cache
b) compares the data in the directory structure with the data blocks on disk
c) compares the system generated output and user required output
d) all of the mentioned
Answer: b
Explanation: None.

4. Each set of operations for performing a specific task is a _________

a) program
b) code
c) transaction
d) all of the mentioned
Answer: c
Explanation: None.

5. Once the changes are written to the log, they are considered to be ________
a) committed
b) aborted
c) completed
d) none of the mentioned
Answer: a
Explanation: None.

6. When an entire committed transaction is completed, ___________

a) it is stored in the memory

b) it is removed from the log file
c) it is redone
d) none of the mentioned
Answer: b
Explanation: None.

7. What is a circular buffer?

a) writes to the end of its space and then continues at the beginning
b) overwrites older values as it goes
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: None.

8. All the changes that were done from a transaction that did not commit before the system crashed, have to be ____
_____

a) saved
b) saved and the transaction redone
c) undone
d) none of the mentioned
Answer: c
Explanation: None.

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1. A machine in Network file system (NFS) can be ________

a) client
b) server
c) both client and server
d) neither client nor server
Answer: c
Explanation: None.

2. A _________ directory is mounted over a directory of a _______ file system.

a) local, remote
b) remote, local
c) local, local
d) none of the mentioned
Answer: d
Explanation: None.

3. The _________ becomes the name of the root of the newly mounted directory.

a) root of the previous directory

b) local directory
c) remote directory itself
d) none of the mentioned
Answer: b
Explanation: None.

4. ___________ mounts, is when a file system can be mounted over another file system, that is remotely mounted, n
ot local.

a) recursive
b) cascading
c) trivial
d) none of the mentioned
Answer: b
Explanation: None.

5. The mount mechanism ________ a transitive property.

a) exhibits
b) does not exhibit
c) may exhibit
d) none of the mentioned
Answer: b
Explanation: Mounting a remote file system does not give the client access to other file systems that were, by chance
, mounted over the former file system.

6. A mount operation includes the _____________

a) name of the network

b) name of the remote directory to be mounted
c) name of the server machine storing it
d) all of the mentioned
Answer: b
Explanation: None.

7. The mount request is mapped to the corresponding __________ and is forwarded to the mount server running on t
he specific server machine.

a) IPC
b) System
c) CPU
d) RPC
Answer: b
Explanation: None.

8. The server maintains a/an ________ that specifies local file systems that it exports for mounting, along with name
s of machines that are permitted to mount them.
a) export list
b) import list
c) sending list
d) receiving list
Answer: a
Explanation: None.

9. In UNIX, the file handle consists of a __________ and __________

a) file-system identifier & an inode number

b) an inode number & FAT
c) a FAT & an inode number
d) a file pointer & FAT
Answer: a
Explanation: None.

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1. The NFS servers ____________

a) are stateless
b) save the current state of the request
c) maybe stateless
d) none of the mentioned
Answer: a
Explanation: None.

2. Every NFS request has a _________ allowing the server to determine if a request is duplicated or if any are missi
ng.

a) name
b) transaction
c) sequence number
d) all of the mentioned
Answer: c
Explanation: None.

3. A server crash and recovery will __________ to a client.

a) be visible
b) affect
c) be invisible
d) harm
Answer: c
Explanation: All blocks that the server is managing for the client will be intact.

4. The server must write all NFS data ___________

a) synchronously
b) asynchronously
c) index-wise
d) none of the mentioned
Answer: a
Explanation: None.

5. A single NFS write procedure ____________

a) can be atomic
b) is atomic
c) is non atomic
d) none of the mentioned
Answer: b
Explanation: None.

6. The NFS protocol __________ concurrency control mechanisms.

a) provides
b) does not provide
c) may provide
d) none of the mentioned
Answer: b
Explanation: None.

7. _______________ in NFS involves the parsing of a path name into separate directory entries – or components.

a) Path parse
b) Path name parse
c) Path name translation
d) Path name parsing
Answer: c
Explanation: None.

8. For every pair of component and directory vnode after path name translation ____________

a) a single NFS lookup call is used sequentially

b) a single NFS lookup call is used beginning from the last component
c) at least two NFS lookup calls per component are performed
d) a separate NFS lookup call is performed
Answer: d
Explanation: None.

9. When a client has a cascading mount _______ server(s) is/are involved in a path name traversal.

a) at least one
b) more than one
c) more than two
d) more than three
Answer: b
Explanation: None.

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1. In _______ information is recorded magnetically on platters.

a) magnetic disks
b) electrical disks
c) assemblies
d) cylinders
Answer: a
Explanation: None.

2. The heads of the magnetic disk are attached to a _____ that moves all the heads as a unit.

a) spindle
b) disk arm
c) track
d) none of the mentioned
Answer: b
Explanation: None.

3. The set of tracks that are at one arm position make up a ___________

a) magnetic disks
b) electrical disks
c) assemblies
d) cylinders
Answer: d
Explanation: None.

4. The time taken to move the disk arm to the desired cylinder is called the ____________

a) positioning time
b) random access time
c) seek time
d) rotational latency
Answer: c
Explanation: None.

5. The time taken for the desired sector to rotate to the disk head is called ____________

a) positioning time
b) random access time
c) seek time
d) rotational latency
Answer: d
Explanation: None.

6. When the head damages the magnetic surface, it is known as _________

a) disk crash
b) head crash
c) magnetic damage
d) all of the mentioned
Answer: b
Explanation: None.

7. A floppy disk is designed to rotate ___________ as compared to a hard disk drive.

a) faster
b) slower
c) at the same speed
d) none of the mentioned
Answer: b
Explanation: None.

8. What is the host controller?

a) controller built at the end of each disk

b) controller at the computer end of the bus
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: None.

9. ______ controller sends the command placed into it, via messages to the _____ controller.

a) host, host
b) disk, disk
c) host, disk
d) disk, host
Answer: c
Explanation: None.

10. What is the disk bandwidth?

a) the total number of bytes transferred

b) total time between the first request for service and the completion on the last transfer
c) the total number of bytes transferred divided by the total time between the first request for service and the comple
tion on the last transfer
d) none of the mentioned
Answer: c
Explanation: None.

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1. Whenever a process needs I/O to or from a disk it issues a ______________

a) system call to the CPU

b) system call to the operating system
c) a special procedure
d) all of the mentioned
Answer: b
Explanation: None.

2. If a process needs I/O to or from a disk, and if the drive or controller is busy then ____________

a) the request will be placed in the queue of pending requests for that drive
b) the request will not be processed and will be ignored completely
c) the request will be not be placed
d) none of the mentioned
Answer: a
Explanation: None.
3. Consider a disk queue with requests for I/O to blocks on cylinders.

a) 600
b) 620
c) 630
d) 640
Answer: d
Explanation: None.

4. Consider a disk queue with requests for I/O to blocks on cylinders.

a) 224
b) 236
c) 245
d) 240
Answer: b
Explanation: None.

5. Random access in magnetic tapes is _________ compared to magnetic disks.

a) fast
b) very fast
c) slow
d) very slow
Answer: d
Explanation: None.

6. Magnetic tape drives can write data at a speed ________ disk drives.

a) much lesser than

b) comparable to
c) much faster than
d) none of the mentioned
Answer: b
Explanation: None.

7. On media that use constant linear velocity (CLV), the _____________ is uniform.

a) density of bits on the disk

b) density of bits per sector
c) the density of bits per track
d) none of the mentioned
Answer: c
Explanation: The farther a track is from the center of the disk.

8. SSTF algorithm, like SJF __________ of some requests.

a) may cause starvation

b) will cause starvation
c) does not cause starvation
d) causes aging
Answer: a
Explanation: None.
9. In the ______ algorithm, the disk arm starts at one end of the disk and moves toward the other end, servicing requ
ests till the other end of the disk. At the other end, the direction is reversed and servicing continues.

a) LOOK
b) SCAN
c) C-SCAN
d) C-LOOK
Answer: b
Explanation: None.

10. In the _______ algorithm, the disk head moves from one end to the other, servicing requests along the way. Whe
n the head reaches the other end, it immediately returns to the beginning of the disk without servicing any requests o
n the return trip.

a) LOOK
b) SCAN
c) C-SCAN
d) C-LOOK
Answer: c
Explanation: None.

11. In the ______ algorithm, the disk arm goes as far as the final request in each direction, then reverses direction im
mediately without going to the end of the disk.

a) LOOK
b) SCAN
c) C-SCAN
d) C-LOOK
Answer: a
Explanation: None.

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1. The process of dividing a disk into sectors that the disk controller can read and write, before a disk can store data i
s known as ____________

a) partitioning
b) swap space creation
c) low-level formatting
d) none of the mentioned
Answer: c
Explanation: None.

2. The data structure for a sector typically contains ____________

a) header
b) data area
c) trailer
d) all of the mentioned
Answer: d
Explanation: None.
3. The header and trailer of a sector contain information used by the disk controller such as _________ and _______
__

a) main section & disk identifier

b) error correcting codes (EC
c) & sector number
c) sector number & main section
d) disk identifier & sector number
Answer: b
Explanation: None.

4. The two steps the operating system takes to use a disk to hold its files are _______ and ________

a) partitioning & logical formatting

b) swap space creation & caching
c) caching & logical formatting
d) logical formatting & swap space creation
Answer: a
Explanation: None.

5. The _______ program initializes all aspects of the system, from CPU registers to device controllers and the conte
nts of main memory, and then starts the operating system.

a) main
b) bootloader
c) bootstrap
d) rom
Answer: c
Explanation: None.

6. For most computers, the bootstrap is stored in ________

a) RAM
b) ROM
c) Cache
d) Tertiary storage
Answer: b
Explanation: None.

7. A disk that has a boot partition is called a _________

a) start disk
b) end disk
c) boot disk
d) all of the mentioned
Answer: c
Explanation: None.

8. Defective sectors on disks are often known as __________

a) good blocks
b) destroyed blocks
c) bad blocks
d) none of the mentioned
Answer: c
Explanation: None.

9. In SCSI disks used in high end PCs, the controller maintains a list of _________ on the disk. The disk is initialize
d during ________ formatting which sets aside spare sectors not visible to the operating system.

a) destroyed blocks, high level formatting

b) bad blocks, partitioning
c) bad blocks, low level formatting
d) destroyed blocks, partitioning
Answer: c
Explanation: None.

10. The scheme used in the above question is known as _______ or ________

a) sector sparing & forwarding

b) forwarding & sector utilization
c) backwarding & forwarding
d) sector utilization & backwarding
Answer: a
Explanation: None.

11. An unrecoverable error is known as _________

a) hard error
b) tough error
c) soft error
d) none of the mentioned
Answer: a
Explanation: None.

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1. Virtual memory uses disk space as an extension of _________

a) secondary storage
b) main memory
c) tertiary storage
d) none of the mentioned
Answer: b
Explanation: None.

2. Using swap space significantly _________ system performance.

a) increases
b) decreases
c) maintains
d) does not affect
Answer: b
Explanation: Disk access is much slower than memory access.

3. Linux __________ the use of multiple swap spaces.

a) allows
b) does not allow
c) may allow
d) none of the mentioned
Answer: a
Explanation: Putting these swap spaces on separate disks reduces the load places on the I/O system.

4. A single swap space ______ reside in two places.

a) can
b) cannot
c) must not
d) none of the mentioned
Answer: a
Explanation: None.

5. If the swap space is simply a large file, within the file system, ____________ used to create it, name it and allocat
e its space.

a) special routines must be

b) normal file system routines can be
c) normal file system routines cannot be
d) swap space storage manager is
Answer: b
Explanation: None.

6. For swap space created in a separate disk partition where no file system or directory structure is placed, ________
_____ used to allocate and deallocate the blocks.

a) special routines must be

b) normal file system routines can be
c) normal file system routines cannot be
d) swap space storage manager is
Answer: d
Explanation: None.

7. When a fixed amount of swap space is created during disk partitioning, more swap space can be added only by?

a) only I
b) only II
c) both I and II
d) neither I nor II
Answer: c
Explanation: None.

8. In UNIX, two per process ________ are used by the kernel to track swap space use.

a) process tables
b) swap maps
c) memory maps
d) partition maps
Answer: b
Explanation: None.
9. It is __________ to reread a page from the file system than to write it to swap space and then to reread it from the
re.

a) useless
b) less efficient
c) more efficient
d) none of the mentioned
Answer: c
Explanation: None.

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1. A microcontroller at-least should consist of:

a) RAM, ROM, I/O ports and timers

b) CPU, RAM, I/O ports and timers
c) CPU, RAM, ROM, I/O ports and timers
d) CPU, ROM, I/O ports and timers
Answer: c
Explanation: A microcontroller at-least consists of a processor as its CPU with RAM, ROM, I/O ports and timers. It
may contain some additional peripherals like ADC, PWM, etc.

2. Unlike microprocessors, microcontrollers make use of batteries because they have:

a) high power dissipation

b) low power consumption
c) low voltage consumption
d) low current consumption
Answer: b
Explanation: Micro Controllers are made by using the concept of VLSI technology. So here, CMOS based logic gate
s are coupled together by this technique that consumes low power.

3. What is the order decided by a processor or the CPU of a controller to execute an instruction?

a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
Answer: d
Explanation: First instruction is fetched from Program Memory. After fetching, instruction is decoded to generate co
ntrol signals to perform the intended task. After decoding, instruction is executed and the complete intended task of t
hat particular instruction.

4. If we say microcontroller is 8-bit then here 8-bit denotes size of:

a) Data Bus
b) ALU
c) Control Bus
d) Address Bus
Answer: b
Explanation: If we say a microcontroller is 8-bit it means that it is capable of processing 8-bit data at a time. Data pr
ocessing is the task of ALU and if ALU is able to process 8-bit data then the data bus should be 8-bit wide. In most
books it tells that size of data bus but to be precise it is the size of ALU because in Harvard Architecture there are tw
o sets of data bus which can be of same size but it is not mandatory.

5. How are the performance and the computer capability affected by increasing its internal bus width?

a) it increases and turns better

b) it decreases
c) remains the same
d) internal bus width doesn’t affect the performance in any way
Answer: a
Explanation: As the bus width increases, the number of bits carried by bus at a time increases as a result of which th
e total performance and computer capability increases.
6. Abbreviate CISC and RISC.

a) Complete Instruction Set Computer, Reduced Instruction Set Computer

b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
Answer: b
Explanation: CISC means Complete Instruction Set Computer because in this a microcontroller has an instruction se
t that supports many addressing modes for the arithmetic and logical instructions, data transfer and memory accesses
instructions. RISC means Reduced Instruction Set Computer because here a microcontroller has an instruction set t
hat supports fewer addressing modes for the arithmetic and logical instructions and for data transfer instructions.

7. Give the names of the buses present in a controller for transferring data from one place to another?

a) data bus, address bus

b) data bus
c) data bus, address bus, control bus
d) address bus
Answer: c
Explanation: There are 3 buses present in a microcontroller they are data bus (for carrying data from one place to an
other), address bus (for carrying the address to which the data will flow) and the control bus (which tells the controll
er to execute which type of work at that address may be it read or write operation).

8. What is the file extension that is loaded in a microcontroller for executing any instruction?

a) .doc
b) .c
c) .txt
d) .hex
Answer: d
Explanation: Microcontrollers are loaded with .hex extension as they understand the language of 0’s and 1’s only.

9. What is the most appropriate criterion for choosing the right microcontroller of our choice?

a) speed
b) availability
c) ease with the product
d) all of the mentioned
Answer: d
Explanation: For choosing the right microcontroller for our product we must consider its speed so that the instructio
ns may be executed in the least possible time. It also depends on the availability so that the particular product may b
e available in our neighboring regions or market in our need. It also depends on the compatibility with the product s
o that the best results may be obtained.

10. Why microcontrollers are not called general purpose computers?

a) because they have built in RAM and ROM

b) because they design to perform dedicated task
c) because they are cheap
d) because they consume low power
Answer: b
Explanation: Microcontrollers are designed to perform dedicated tasks. While designing general purpose computers
end use is not known to designers.
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1. How many types of architectures are available, for designing a device that is able to work on its own?

a) 3
b) 2
c) 1
d) 4
Answer: b
Explanation: There are basically two main types of architectures present, they are Von Neumann and Harvard archit
ectures.

2. Which architecture is followed by general purpose microprocessors?

a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: b
Explanation: General purpose microprocessors make use of Von Neumann architecture as here a simpler design is of
fered.

3. Which architecture involves both the volatile and the non volatile memory?

a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: In Harvard architecture, both the volatile and the non volatile memories are involved. This is done to in
crease its efficiency as both the memories are being used over here.

4. Which architecture provides separate buses for program and data memory?

a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: Harvard Architecture provides separated buses for data and program memory to fetch program and dat
a simultaneously. By doing this access time is reduced and hence performance is increased.

5. Which microcontroller doesn’t match with its architecture below?

a) Microchip PIC- Harvard

b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
Answer: b
Explanation: MSP430 supports Von Neumann architecture.

6. Harvard architecture has _____________

a) dedicated buses for data and program memory
b) pipeline technique
c) complex architecture
d) all of the mentioned
Answer: d
Explanation: Harvard Architecture has dedicated buses for data and program memory and pipeline technique becaus
e of this architecture is complex.

7. Which out of the following supports Harvard architecture?

a) ARM7
b) Pentium
c) SHARC
d) All of the mentioned
Answer: c
Explanation: SHARC supports harvard architecture for signal processing in DSP.

8. Why most of the DSPs use Harvard architecture?

a) they provide greater bandwidth

b) they provide more predictable bandwidth
c) they provide greater bandwidth & also more predictable bandwidth
d) none of the mentioned
Answer: c
Explanation: Most of the DSPs use harvard architecture because they provide a wider predictable bandwidth.

9. Which of the following supports CISC as well as Harvard architecture?

a) ARM7
b) ARM9
c) SHARC
d) None of the mentioned
Answer: c
Explanation: SHARC supports both the CISC and the Harvard architecture.

10. Which of the two architecture saves memory?

a) Harvard
b) Von Neumann
c) Harvard & Von Neumann
d) None of the mentioned
Answer: b
Explanation: As only one memory is present in the Von Neumann architecture so it saves a lot of memory.

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1. 8051 microcontrollers are manufactured by which of the following companies?

a) Atmel
b) Philips
c) Intel
d) All of the mentioned
Answer: d
Explanation: 8051 microcontrollers are manufactured by Intel, Atmel, Philips/Signetics, Infineon, Dallas Semi/Maxi
m.

2. AT89C2051 has RAM of:

a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Answer: a
Explanation: It has 128 bytes of RAM in it.

3. 8051 series has how many 16 bit registers?

a) 2
b) 3
c) 1
d) 0
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.

4. When 8051 wakes up then 0x00 is loaded to which register?

a) PSW
b) SP
c) PC
d) None of the mentioned
Answer: c
Explanation: When 8051 wakes up, Program Counter (P
c) loaded with 0000H. Because of this in 8051 first opcode is stored in ROM address at 0000H.

5. When the microcontroller executes some arithmetic operations, then the flag bits of which register are affected?

a) PSW
b) SP
c) DPTR
d) PC
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity, register bank se
lect bits etc which are affected during such operations.

6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction

a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are set to 1. In t
he result, the number of 1’s present are even so parity flag is set to zero.

7. How are the bits of the register PSW affected if we select Bank2 of 8051?

a) PSW.5=0 and PSW.4=1

b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and RS0=0 wh
ich are fourth and third bit of the register respectively.

8. If we push data onto the stack then the stack pointer

a) increases with every push

b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push of element.

9. On power up, the 8051 uses which RAM locations for register R0- R7

a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.

10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?

a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.

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1. “DJNZ R0, label” is ________ byte instruction.

a) 2
b) 3
c) 1
d) Can’t be determined
Answer: a
Explanation: DJNZ is 2-byte instruction. This means jump can be of -128 to +127 locations with respect to PC. Here
-128 means upward or backward jump and +127 means downward or forward jump.

2. JZ, JNZ, instructions checked content of _______ register.

a) DPTR
b) B
c) A
d) PSW
Answer: c
Explanation: JZ and JNZ instructions checked the content of A register and if condition was satisfied or true then ju
mp to target address.

3. Calculate the jump code for again and here if code starts at 0000H

a) F3,02
b) F9,01
c) E9,01
d) E3,02
Answer: c
Explanation: Loop address is calculated by subtracting destination address and the address next to the source address
.

4. When the call instruction is executed the topmost element of stack comes out to be

a) the address where stack pointer starts

b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
Answer: b
Explanation: The topmost element of the stack is the address of the instruction next to the call instruction so that wh
en RET is executed then PC is filled with that address and so the pointer moves to the main program and continue w
ith its routine task.

5. LCALL instruction takes

a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
Answer: c
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte instruction.

6. Are PUSH and POP instructions are a type of CALL instructions?

a) yes
b) no
c) none of the mentioned
d) cant be determined
Answer: b
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH instructions the poi
nter does not move to any location specified by its address which is the fundamental of CALL instruction, so it is no
t a type of CALL instruction.

7. What is the time taken by one machine cycle if crystal frequency is 20MHz?

a) 1.085 micro seconds

b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
Answer: b
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal frequency) /12

8. Find the number of times the following loop will be executed

a) 100
b) 200
c) 20000
d) 2000
Answer: c
Explanation: It will be executed 200*100 times.

9. What is the meaning of the instruction MOV A,05H?

a) data 05H is stored in the accumulator

b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
d) none of the mentioned
Answer: c
Explanation: If we need to store the address in the accumulator, then directly the address is moved to it unlikely of u
sing # used for storing data in any register.

10. Do the two instructions mean the same?

a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
Answer: b
Explanation: In the first statement, when the decrements approach zero then the jump moves back and in the second
statement, when the result after decrements is not zero, then it jumps back.

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1. To initialize any port as an output port what value is to be given to it?

a) 0xFF
b) 0x00
c) 0x01
d) A port is by default an output port
Answer: d
Explanation: In 8051, a port is initialized by default in its output mode no need to pass any value to it.

2. Which out of the four ports of 8051 needs a pull-up resistor for using it is as an input or an output port?

a) PORT 0
b) PORT 1
c) PORT 2
d) PORT 3
Answer: a
Explanation: These pins are the open drain pins of the controller which means it needs a pull-up resistor for using it
as an input or an output ports.

3. Which of the ports act as the 16 bit address lines for transferring data through it?

a) PORT 0 and PORT 1

b) PORT 1 and PORT 2
c) PORT 0 and PORT 2
d) PORT 1 and PORT 3
Answer: c
Explanation: PORT 0 and PORT 2 are used as the 16 bit address lines where PORT0 act as lower bit address lines a
nd PORT 2 as higher bit address lines.

4. Which of the following registers are not bit addressable?

a) SCON
b) PCON
c) A
d) PSW
Answer: b
Explanation: PCON register is not a bit addressable register.

5. Which instruction is used to check the status of a single bit?

a) MOV A,P0
b) ADD A,#05H
c) JNB PO.0, label
d) CLR P0.05H
Answer: b
Explanation: JNB which stands for Jump if no bit checks the status of the bit P0.0 and jumps if the bit is 0.

6. Which addressing mode is used in pushing or popping any element on or from the stack?

a) immediate
b) direct
c) indirect
d) register
Answer: c
Explanation: If we want to push or pop any element on or from the stack then direct addressing mode has to be used
in it, as the other way is not accepted.

7. Which operator is the most important while assigning any instruction as register indirect instruction?

a) $
b) #
c) @
d) &
Answer: b
Explanation: In register, indirect mode data is copied at that location where R0 or R1 are present, so @ operator is u
sed ex. MOV @R0,A

8. What is the advantage of register indirect addressing mode?

a) it makes use of registers R0 and R1

b) it uses the data dynamically
c) it makes use of operator @
d) it is easy
Answer: b
Explanation: Register indirect addressing mode is useful if a series of data is to be assigned to that address, with the
help of this quality the number of instructions decreases as a result of which performance increases.
9. Which of the following comes under the indexed addressing mode?

a) MOVX A, @DPTR
b) MOVC @A+DPTR,A
c) MOV A,R0
d) MOV @R0,A
Answer: b
Explanation: Indexed addressing mode stands for that instruction where the bits of the accumulator is also indexed w
ith the 16 bit registers.

PSST! You better watch out, something's buggy above.

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1. When we add two numbers the destination address must always be.

a) some immediate data

b) any register
c) accumulator
d) memory
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator. Example- ADD A,R0;
ADD A, @R1; ADD A,@ DPTR

2. DAA command adds 6 to the nibble if:

a) CY and AC are necessarily 1

b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.

3. If SUBB A,R4 is executed, then actually what operation is being applied?

a) R4+A
b) R4-A
c) A-R4
d) R4+A
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of the register or some
immediate value. So A-R4 is being executed.

4. A valid division instruction always makes:

a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.

5. In 8 bit signed number operations, OV flag is set to 1 if:

a) a carry is generated from D7 bit

b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to 1.

6. In unsigned number addition, the status of which bit is important?

a) OV
b) CY
c) AC
d) PSW
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is important and in signed num
ber operation the status of OV flag is important.

7. Which instructions have no effect on the flags of PSW?

a) ANL
b) ORL
c) XRL
d) All of the mentioned
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the data copy instructions,
so all these instructions don’t affect the bits of the flag.

8. ANL instruction is used _______

a) to AND the contents of the two registers

b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to mask the status of
the bits of the register.

9. CJNE instruction makes _______

a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are gr