• Contents:
CMOS Inverter
CMOS NAND Gate
CMOS NOR Gate
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CMOS Inverter
It consists of two MOSFETs in series in such a way that a p-
channel device has its source connected to +VDD(a positive
voltage) and the n-channel has its source connected to ground.
The gates of the two devices connected together as the
common input and the drains are connected together as the
common output.
When input is HIGH, the gate of Q1(p-channel) is at 0 V
relative to the source of Q1 i.e. Vgs1=0 V. Thus Q1 is OFF. On
the other hand, the gate of Q2(n-channel) is at +VDD relative to
its source i.e. Vgs2=+VDD. Thus Q2 is ON. This will produce
VOUT=0 V.
When input is LOW, the gate of Q1(p-channel) is at negative
potential relative to its source while Q2 has Vgs=0 V.Thus,Q1 is
ON and Q2 is OFF. This produces output voltage approximately
+VDD.
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A Q1 Q2 Output
0 ON OFF 1
1 OFF ON 0
Truth Table
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Contd…
Different symbols used for the p-channel and n-
channel transistors to reflect their logical behaviour.
The n-channel transistor (Q2) is switched ‘ON’ when a
HIGH voltage is applied at the input.
The p-channel transistor (Q1) has the opposite
behaviour, it is switched ON when a LOW voltage is
applied at the input.
It is indicated by placing bubble in the symbol
Kongunadu College of Engineering & Technology CMOS 4
CMOS NAND Gate
It consists of two p-channel MOSFETs,Q1 and
Q2,connected in parallel and two n-channel MOSFETs,Q3
and Q4 are connected in series.
When Q1 and Q2 are both ON. Since the gate-to-source
voltages of Q3 and Q4(n-channel MOSFETs) are both 0 V,
those MOSFETs are OFF.
The output is therefore connected to +VDD(HIGH)
through Q1 and Q2 and is disconnected from ground and
the equivalent switching circuit when A=0 and B=+VDD.
In this case,Q1 is on because VGS1=-VDD and Q4 is ON
because VGS4=+VDD.
MOSFETs Q2 and Q3 are off because gate-to-source
voltages are 0 V.
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Contd…
Since Q1 is ON and Q3 is OFF, the output is connected to
+VDD and it is connected from ground.
When A=+VDD and B=0 V, the situation is similar(not
shown);the output is connected to +VDD through Q2 and
it is disconnected from ground because Q4 is OFF.
Finally, when both inputs are high(A=B=+VDD),
MOSFTETs Q1 and Q2 are both OFF and Q3 and Q4 are
both ON.
Thus, the output is connected to the ground through Q3
and Q4 and it is disconnected from +VDD.
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Truth Table of NAND Gate
A B Q1 Q2 Q3 Q4 Output
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0
Kongunadu College of Engineering & Technology CMOS 8
CMOS NOR Gate
Here, p-channel MOSFETs Q1 and Q2 are connected in
series and n-channel MOSFETs Q3 and Q4 are connected
in parallel.
Like NAND circuit, this circuit can be analysed by
realizing that a LOW at any input turns ON its
corresponding p-channel MOSFET and turns OFF its
corresponding n-channel MOSFET and vice versa for a
HIGH input.
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Truth Table of NOR Gate
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Advantages
Consumes less power.
Can be operated at high voltages, resulting in improved
noise immunity.
Fan-out is more.
Better noise margin.
Disadvantages
Susceptible to static charge.
Switching speed low
Greater propagation delay
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Conclusion
The CMOS circuit is discussed for mode of operations such as
inverter, NAND and NOR gates.
References:
Mandal, “Digital Electronics Principles & Application,
McGraw Hill Edu, 2013.
William Keitz, Digital Electronics-A Practical Approach with
VHDL, Pearson, 2013.
Thomas L.Floyd, ‘Digital Fundamentals’, 11th edition, Pearson
Education, 2015.
Charles H.Roth, Jr, Lizy Lizy Kurian John, ‘Digital System
Design using VHDL, Cengage,2013.
D.P.Kothari,J.S.Dhillon, ‘Digital circuits and Design’,Pearson
Education, 2016.
A.P.Godse., Dr.D.A.Godse, ‘Digital Logic Circuits’ , Technical
Publications Third Edition 2016
Other Web Sources
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