Advanced UVM
How TLM Works
Tom Fitzpatrick
Strategic Verification Architect
How TLM Works
TLM is all about communication through method calls
• A TLM port specifies the “API” to be used class my_env extends uvm_env;
• A TLM export supplies the implementation of class initiator extends uvm_component;
the methods uvm_put_port #(tr) pport;
virtual task run();
Connections are between … class tr extends
pport.put(tr1); uvm_transaction;
ports/exports, not components … …
endtask
Transactions are objects endclass Port
Ports & exports are parameterized virtual function void connect();
initiator.pport.connect(target.pxport);
by the transaction type being endfunction
Export
communicated class target2
target extends
extendsuvm_component;
target;
uvm_put_imp #(tr,target)
uvm_put_imp #(tr,target) pxport;
pxport;
virtual task put(tr);
…
endtask
endclass
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Hierarchical Connections
Port-to-Export
class my_env extends uvm_env;
class p1 extends uvm_component;
uvm_put_port #(tr) pport;
pport
endclass
virtual function void connect();
pxport
endfunction
class p2 extends uvm_component;
uvm_put_export #(tr) pxport;
endclass
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Hierarchical Connections
Port-to-Export
class my_env extends uvm_env;
port.connect(export);
class p1 extends uvm_component;
uvm_put_port #(tr) pport;
pport
endclass
virtual function void connect();
p1.pport.connect(p2.pxport); pxport
endfunction
class p2 extends uvm_component;
uvm_put_export #(tr) pxport;
endclass
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Hierarchical Connections
Port-to-Export
class my_env extends uvm_env;
port.connect(export);
class p1 extends uvm_component;
Port-to-Port uvm_put_port #(tr) pport;
virtual function void connect();
C1 pport
endfunction
pport
endclass
virtual function void connect();
p1.pport.connect(p2.pxport);
endfunction
class p2 extends uvm_component;
uvm_put_export #(tr) pxport;
endclass
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Hierarchical Connections
Port-to-Export
class my_env extends uvm_env;
port.connect(export);
class p1 extends uvm_component;
Port-to-Port uvm_put_port #(tr) pport;
child.port.connect(parent_port); virtual function void connect();
C1 pport
c1.pport.connect(pport);
endfunction
pport
endclass
virtual function void connect();
p1.pport.connect(p2.pxport);
endfunction
class p2 extends uvm_component;
uvm_put_export #(tr) pxport;
endclass
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Hierarchical Connections
Port-to-Export
class my_env extends uvm_env;
port.connect(export);
class p1 extends uvm_component;
Port-to-Port uvm_put_port #(tr) pport;
child.port.connect(parent_port); virtual function void connect();
C1
Export-to-Export c1.pport.connect(pport);
endfunction
endclass
virtual function void connect();
p1.pport.connect(p2.pxport); pxport
endfunction
class p2 extends uvm_component; pxport
uvm_put_export #(tr) pxport;
virtual function void connect(); C2
endfunction
endclass
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Hierarchical Connections
Port-to-Export
class my_env extends uvm_env;
port.connect(export);
class p1 extends uvm_component;
Port-to-Port uvm_put_port #(tr) pport;
child.port.connect(parent_port); virtual function void connect();
C1
Export-to-Export c1.pport.connect(pport);
endfunction
parent_export.connect(child.export); endclass
virtual function void connect();
p1.pport.connect(p2.pxport); pxport
endfunction
class p2 extends uvm_component; pxport
uvm_put_export #(tr) pxport;
virtual function void connect(); C2
pxport.connect(c2.pxport);
endfunction
endclass
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Hierarchical Connections
Port-to-Export
class my_env extends uvm_env;
port.connect(export);
class
classC1
p1 extends uvm_component;
Port-to-Port uvm_put_port#(tr)
uvm_put_port #(tr)pport;
pport;
child.port.connect(parent_port); task run_phase(uvm_phase
virtual phase);
function void connect();
pport.put(t);
c1.pport.connect(pport); C1
Export-to-Export
endtask
endfunction
parent_export.connect(child.export); endclass
endclass
Last Export is actually an ‘imp’ virtual function void connect();
p1.pport.connect(p2.pxport);
endfunction
class p2 extends uvm_component;
class C2X extendsuvm_component;
C2 extends C2;
uvm_put_export #(tr) pxport;
uvm_put_imp#(tr, C2X) pxport;
C2) pxport;
virtual function void connect();
task put(tr t);
pxport.connect(c2.pxport); C2
…
endfunction
endtask
endclass
endclass
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Analysis Communication
Analysis ports support
class my_env extends uvm_env;
1:many connections class mon extends uvm_component;
• All write() functions called in zero time uvm_analysis_port #(tr) aport;
virtual task run();
Used by coverage collectors and …
scoreboards aport.write(tr1);
… Analysis
• uvm_subscriber has built-in analysis_export endtask Port
endclass
virtual function void connect();
mon.aport.connect(cov.analysis_export);
endfunction
class cov extends uvm_subscriber #(tr);
virtual function void write(tr);
…
endfunction
endclass
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Analysis of Multiple Streams
Choice 1: Use imp suffixes defined via macro
• Declare macros outside of component
`uvm_analysis_imp_decl(_BEFORE)
• Instantiate suffixed imps `uvm_analysis_imp_decl(_AFTER)
• Implement write_SUFFIX methods
class score extends uvm_component;
Write methods are functions `uvm_component_utils(score);
• Can’t synchronize between streams
uvm_analysis_imp_BEFORE #(tr, score) before_export;
uvm_analysis_imp_AFTER #(tr, score) after_export;
virtual function void write_BEFORE(tr);
…
endfunction
class cov extends uvm_subscriber #(tr);
virtual
virtual function void write_AFTER(tr);
function void write(tr);
……
endfunction
endfunction
endclass
endclass
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Analysis of Multiple Streams
Choice 2: Use embedded fifos
• Declare analysis exports
class score2 extends uvm_component;
• Connect exports to fifos `uvm_component_utils(score2);
Run_phase must actively pull from fifos
uvm_analysis_export #(tr) b4_export;
uvm_analysis_export #(tr) after_export;
uvm_tlm_analysis_fifo #(tr) b4_fifo,after_fifo;
function void connect_phase( uvm_phase phase );
b4_export.connect(b4_fifo.analysis_export);
after_export.connect(after_fifo.analysis_export);
endfunction
task run_phase(uvm_phase phase);
b4_fifo.get(t1);
aftr_fifo.get(t2);
…
endclass
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TLM2 in UVM
TLM2 based on a generic_payload transaction base class
• TLM2 uses sockets, which contain both a port and an export
• Pass-by-reference
• The generic payload can be extended to model any kind of transaction
Connections are between sockets, just like ports/exports
• Initiator socket connects to target socket
class my_env extends uvm_env;
Socket
class initiator extends uvm_component; class target extends uvm_component;
endclass endclass
virtual function void connect();
initiator.sock.connect(target.sock);
endfunction
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TLM2 in UVM – Blocking Transport
Completes the entire transaction within a single method call
• Uses the b_transport() task
class my_env extends uvm_env;
class initiator extends uvm_component; class target extends uvm_component;
uvm_tlm_b_initiator_socket#(apb_rw) sock; uvm_tlm_b_target_socket #(target, apb_rw) sock;
Socket
virtual task run_phase(uvm_phase phase); task b_transport(apb_rw rw, uvm_tlm_time delay);
… …
sock.b_transport(rw, delay) endtask
…
endtask
endclass endclass
virtual function void connect();
initiator.sock.connect(target.sock);
endfunction
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TLM2 in UVM – Nonblocking Transport
Bidirectional communication
• Uses the nb_transport_fw() and nb_transport_bw() functions
• Initiator implements nb_transport_bw(); Target implements nb_transport_fw()
class my_env extends uvm_env;
class initiator extends uvm_component; class target extends uvm_component;
uvm_tlm_nb_initiator_socket#(initiator, apb_rw uvm_tlm_nb_target_socket #(target, apb_rw,
tlm_phase) sock; tlm_phase) sock;
function uvm_tlm_sync_e b_transport_bw( function uvm_tlm_sync_e b_transport_fw(
Socket
apb_rw rw, ref tlm_phase ph, apb_rw rw, ref tlm_phase ph,
uvm_tlm_time delay); uvm_tlm_time delay);
… …
endfunction endfunction
endclass endclass
virtual function void connect();
initiator.sock.connect(target.sock);
endfunction
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TLM2 in UVM – Nonblocking Transport
Bidirectional communication
• Uses the nb_transport_fw() and nb_transport_bw() functions
• Initiator implements nb_transport_bw(); Target implements nb_transport_fw()
class my_env extends uvm_env;
class initiator extends uvm_component; class target extends uvm_component;
Socket
Pass
through
Socket
virtual function void connect();
initiator.sock.connect(target.sock);
endfunction
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TLM2 in UVM – Generic Payload
All elements are rand and protected
Must use predefined virtual accessor methods
Defined to be either READ, WRITE or IGNORE command
OK
uvm_tlm_generic_payload INCOMPLETE
bit [63:0] m_address GENERIC_ERROR
uvm_tlm_command_e m_command ADDRESS_ERROR
byte m_data[] COMMAND_ERROR
int unsigned m_length BURST_ERROR
uvm_tlm_response_status_e m_response_status; BYTE_ENABLE_ERROR
bit m_dmi
byte m_byte_enable[]
int unsigned m_byte_enable_length
int unsigned m_streaming_width
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TLM Summary
Every port must eventually connect to
an implementation (imp)
You’ll mostly only use two port/export connections
From To
analysis monitor.ap subscriber.analysis_export
sequencer/driver driver.seq_item_port sequencer.seq_item_export
All TLM connections go from ‘origin’ to ‘destination’
• port.connect(export);
• child_port.connect(parent_port);
• parent_export.connect(child_export); // or imp
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Advanced UVM
How TLM Works
Tom Fitzpatrick
Strategic Verification Architect
