A PROJECT REPORT
ON
CHIP DESIGN FOR TURBO ENCODER MODULE FOR IN-VEHICLE SYSTEM
Submitted to Jawaharlal Nehru Technological University Anantapur for the partial
fulfillment of the requirement for the award of the degree of
Bachelor of Technology
In
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by
MOGHAL FAYAZ BEIG 17FH1A0461
SOMPALLI VENKATA SWAMY 17FH1A0476
BESTHA SUNIL 17FH1A0443
M. ABDUL MUIZ 17FH1A0456
SANAMURI MADHUSUDHAN RAO 17FH1A0471
T HARI PRASAD REDDY 16FH1A0465
Under The Esteemed Guidance of
MOHAMMAD ZUBAIR M.Tech
Assistant Professor, ECE Department
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Dr. K.V. SUBBA REDDY INSTITUTE OF TECHNOLOGY
(Affiliated to JNTUA, Anantapuramu, Approved by AICTE)
DUPADU, KURNOOL (Dist), AP-518218
2017-2021
Dr. K.V. SUBBA REDDY INSTITUTE OF TECHNOLOGY
(Affiliated to JNTUA, Anantapuramu, Approved by AICTE)
DUPADU, KURNOOL (Dist.), AP-518218
CERTIFICATE
This is to certify that the project work on “CHIP DESIGN FOR TURBO ENCODER
MODULE FOR IN-VEHICLE SYSTEM” is a bonafide work done by
MOGHAL FAYAZBEIG(17FH1A0461), SOMPALLI VENKATA SWAMY (17FH1A0476),
BESTHA SUNIL(17FH1A0443), M.ABDUL MUIZ(17FH1A0456), S.MADHUSUDHAN
RAO(17FH1A0471), T. HARI PRASAD REDDY(16FH1A0465) in partial fulfillment of the
requirement for the award of the degree of “Bachelor of Technology in Electronics and
Communication Engineering” JNTUA, Anantapuramu during 2017-2021.
PROJECT GUIDE HEAD OF THE DEPARTMENT
MOHAMMAD ZUBAIR Smt. M.V. SRUTHI
M .Tech Ph.D., M. Tech,
Asst. Professor, Assoc. Professor
Department of ECE, Department of ECE
Dr. K.V.S.R. Institute of technology. Dr. K.V.S.R. Institute of technology.
Place: DUPADU EXTERNAL EXAMINER
Date:
ACKNOWLEDGEMENT
At the outset I sincerely thanks to our guide MOHAMMAD ZUBAIR, M.Tech
Assistant Professor in Dept. of Electronics and Communication Engineering at Dr.KVSRIT,
for his kind cooperation and encouragement for the successful completion of Seminar and
providing the necessary facilities.
I am most obliged and grateful to DR. M.V SRUTHI, Head of the Department of
Electronics and Communication of Dr. KVSRIT for giving me guidance in completing this
Seminar successfully.
It is my privilege and pleasure to express my profound sense of gratitude and
indebtedness to Dr. S G GOVINDARAJULU, Professor in Department of Electronics and
Communication, Dr. KVSRIT, for his guidance, cogent discussion, constructive criticisms, and
encouragement throughout this dissertation work.
I would like to express my very great appreciation to T. VIJAY KUMAR, Associate
Professor in Department of Electronics and Communication, Dr.KVSRIT for her valuable and
constructive suggestions during the planning and development of this research work.
I am grateful to Dr. L.THIMMAIAH, Principal, Dr.KVSRIT, for his sagacious
guidance, scholarly and the inspiration offered in an amiable and pleasant manner in helping
me for completing this seminar successfully.
We would like to thank our college management, the chairman Dr.K.V.SUBBA
REDDY Garu, Mrs. K.VIJAYALAKSHMAMMA garu who had inspired a lot through her
speeches. She has given meaning to our Technological studies and told us to survive in this
competitive world. We wish to express our thanks to all staff members and our friends who
have rendered their whole-hearted support at all times for the successful completion of his
seminar within the limited time.
Finally, I acknowledge with gratitude the unflagging support and patience of my
PARENTS for their guidance and encouragement during this dissertation work.
PROJECT MEMBERS
M. FAYAZ BEIG 17FH1A0461
S. VENKATA SWAMY 17FH1A0476
B. SUNIL 17FH1A0443
M. ABDUL MUIZ 17FH1A0456
S. MADHUSUDHAN RAO 17FH1A0471
T. HARI PRASAD REDDY 16FH1A0465
CONTENTS
CHAPTER NAME PAGE NO
LIST OF FIGURES I
ABSTRACT II
CHAPTER 1
INTODUCTION 01-05
1.1 OVERVIEW 01
1.2 AIM AND OBJECTIVE 03
1.3 PURPOSE OF STUDY 03
1.4 REASEARCH QUESTIONS 04
1.5 RESEARCH CONTEXT 04
1.6 RESARCH METHOD 05
CHAPTER 2
LITERATURE REVIEW 06-08
2.1 OVERVIEW 06
2.2 ERRORS OCCURRED DURING THE CODING IN COMMUNICATION PROCESS 07
CHAPTER 3
RESEARCH ON PROPOSED SOLUTION 09-23
3.1 OVERVIEW 09
3.2 LANGUAGE USED FOR TURBO ALGORITHM 09
3.3 IMPORTANCE OF VHDL OVER OTHER LANGUAGES 11
3.4 TOOLS USED TO ALONG WITH THE VHDL 14
3.5 BUILDING TURBO ALGORITHM 16
3.6 BUILDING OF VHDL 17
3.7 SYNTHESIZABLE CONSTRUCTS AND VHDL TEMPLATES 18
3.8 HOW TURBO ALGORITHM IS IMPLEMENTED THROUGH VHDL 18
3.8.1 THE TURBO DECODER ARCHITECTURE 19
3.8.2 THE SMU CONTROL UNIT 20
3.9 SUMMARY 22
CHAPTER 4
ANALYSIS ON RESEARCH 24-41
4.1 INTRODUCTION 24
4.2 TURBO ENCODER MODULE 25
4.3 FPGA DESIGN FOR THE TURBO ENCODER MODULE FPGA 29
A: SIMULATION AND VERIFICATION 31
4.4 PROPOSED SOLUTION FOR THE PROBLEM: TURBO ALGORITHM 32
4.5 HIDDEN MARKOV MODEL AND TURBO DECODER 33
4.5.1 HIDDEN MARKOV MODEL 33
4.5.2 TURBO DECODER 34
4.6 BLOCK DIAGRAM OF TURBO ALGORITHM 35
4.7 DESCRIPTION OF TURBO ALGORITHM 38
4.8 ADVANTAGES OF TURBO ALGORITHM 39
B. HARDWARE IMPLEMENTATION 40
CHAPTER 5
PROPOSED METHOD 42-48
5.1 INTRODUCTION 42
5.2 LITERATURE SURVEY 43
5.3 NEW TURBO ENCODING AND DECODING METHOD 44
A. OVERALL STRUCTURE OF TURBO NoC 44
B. TURBO ENCODER 45
C. TURBO DECODER 46
CHAPTER 6
IMPLEMENTATION 49-56
CHAPTER 7
SIMULATION RESULTS 57-59
CHAPTER 8
CONCLUSION 60-61
8.1 RECOMMANDATIONS 60
8.2 FEATURE SCOPE 61
BIBILOGRAPHY 62-64
LIST OF FIGURES
FIGURE NO NAME OF THE FIGURE PAGE NO
3.1 DESIGN FLOW OF VHDL 12
4.1 THE IVS BLOCK DIAGRAM 24
4.2 THE STRUCTURE OF THE TURBO ENCODER 25
4.3 THE OUTPUT BUFFER OF TURBO ENCODER 26
4.4 THE PSEUDO CODE FOR SERIAL COMPUTATION OF 30
THE TURBO ENCODER
4.5 THE PSEUDO CODE FOR PARALLEL COMPUTATION 31
OF THE TURBO ENCODER
4.6 THE HIDDEN MARCOV MODEL 34
4.7 THE BASIC BLOCK DIAGRAM OF TURBO DECODER 36
4.8 SHOWS THE TURBO ALGORITHM TRELLIS 37
4.9 THE TRELLIS DIAGRAM OF TURBO ALGORITHM 38
4.10 SHOWS THE STATE OF THE TRELLIS DIAGRAM 39
OF THE TURBO ALGORITHM
4.11 THE LOGIC UTILIZATION OF THE TURBO ENCODER 40
WITH SERIAL COMPETITION
4.12 THE LOGIC UTILIZATION OF THE TURBO ENCODER 40
WITH PARALLEL COMPETITION
4.13 THE LOGIC UTILIZATION OF THE TURBO ENCODER 41
SERIAL VS PARALLEL COMPUTATION
5.1 THE IVS BLOCK DIAGRAM 43
5.2 STRUCTURE OF TURBO NoC 44
5.3 BLOCK DIAGRAM OF ENCODING SCHEME 45
5.4 DATA ENCODING EXAMPLE 46
5.5 BLOCK DIAGRAM OF DECODING SCHEME 47
5.6 DATA DECODING EXAMPLE 47
7.1 WB ENCODER 57
7.2 WB DECODER 57
7.3 SB ENCODER 57
7.4 SB DECODER 58
7.5 DESIGN SUMMARY 58
7.6 TIME SUMMARY 59
I
ABSTRACT
This design and implementation of the Turbo encoder to be an embedded module in the in-
vehicle system (IVS) chip. Field programmable gate array (FPGA) is employed to develop the
Turbo encoder module. As a high-performance on-chip communication method, the Turbo
technique has recently been applied to networks on chip (NoCs). We propose a new standard-
basis (SB) and Walsh basis (WB) based encoding/decoding methods to leverage the
performance and cost of Turbo NoCs in area, power assumption, and network throughput. In
the transmitter module, source data from different venders are separately encoded with an
orthogonal code of a standard basis and these coded data are mixed by an XOR operation.
Then, the sums of data can be transmitted to their destinations through the on-chip
communication infrastructure. In the receiver module, a sequence of chips is retrieved by
taking an AND operation between the sums of data and the corresponding orthogonal code.
After a simple accumulation of these chips, original data can be reconstructed. We implement
our encoding/decoding method and apply it to a Turbo NoC with a star topology.
II
